Array substrate, display panel and display apparatus

Abstract

Provided are an array substrate, a display panel and a display apparatus. The array substrate comprises a base substrate, a thin film transistor, a pixel electrode, a common electrode, a conductive pattern and a plurality of gate lines, the thin film transistor being located on the base substrate, the thin film transistor comprising a source electrode, a drain electrode and a gate electrode, and the pixel electrode being electrically connected to the drain electrode; the common electrode is configured to form an electric field with the pixel electrode; the conductive pattern and the common electrode are located on different layers; the gate lines are electrically connected to the gate electrode of the thin film transistor; the conductive pattern is electrically connected to the common electrode, and the orthographic projections of the gate lines on the base substrate at least partially overlap the orthographic projection of the conductive pattern on the base substrate. By means of providing the conductive pattern electrically connected to the common electrode, and enabling the conductive pattern and the gate lines to overlap each other in the direction perpendicular to the base substrate, the embodiments of the present disclosure enable good uniformity of common electrode signals during diffusion, and help to ensure a relatively large pixel aperture ratio, thereby facilitating display.

Description

Array substrate, display panel, and display device

[0001] This application claims priority to Chinese Patent Application No. 202310786210.7 filed on June 29, 2023, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to an array substrate, a display panel, and a display device. Background Art

[0003] With the advancement of technology, the demand for image quality among self-media and film and television professionals is increasing. For example, in 2017, broadcasters transitioned from 1080P to 4K UHD television production and transmission, and mobile apps are gradually gaining access to 4K UHD video streams. Simultaneously, camera technology is constantly improving, with some cameras now capable of 6K / 8K video recording. Currently, medium and large-sized display products are trending towards higher resolutions. How to achieve higher resolutions while maintaining good display performance while meeting product size requirements is a constant challenge for display R&D professionals.

[0004] Summary of the Invention

[0005] At least one embodiment of the present disclosure provides an array substrate, a display panel, and a display device.

[0006] At least one embodiment of the present disclosure provides an array substrate, comprising a base substrate, a thin film transistor, a pixel electrode, a common electrode, a conductive pattern and a plurality of gate lines, wherein the thin film transistor is located on the base substrate, and the thin film transistor includes a source, a drain and a gate; the pixel electrode is electrically connected to the drain; the common electrode is configured to form an electric field with the pixel electrode; the conductive pattern and the common electrode are located in different layers; the plurality of gate lines extend along a first direction, and the plurality of gate lines are spaced apart along a second direction, and the gate lines are electrically connected to the gates of the thin film transistors, the first direction and the second direction are both parallel to the base substrate, and the first direction intersects with the second direction, wherein the conductive pattern is electrically connected to the common electrode, and the orthographic projection of the gate line on the base substrate at least partially overlaps with the orthographic projection of the conductive pattern on the base substrate.

[0007] For example, according to at least one embodiment of the present disclosure, an array substrate is provided, which further includes an active pattern, wherein the active pattern is respectively connected to the source and the drain of the thin film transistor and at least partially overlaps with the gate, wherein the orthographic projection of the active pattern on the base substrate overlaps at most partially with the orthographic projection of the conductive pattern on the base substrate.

[0008] For example, in the array substrate provided according to at least one embodiment of the present disclosure, there is a gap between the orthographic projection of the active pattern on the base substrate and the orthographic projection of the conductive pattern on the base substrate.

[0009] For example, according to at least one embodiment of the present disclosure, in the array substrate provided, the conductive pattern includes a plurality of conductive pattern units, and at least part of the orthographic projection of the conductive pattern units on the base substrate surrounds the orthographic projection of the active pattern on the base substrate.

[0010] For example, in the array substrate provided by at least one embodiment of the present disclosure, the orthographic projection of at least part of the conductive pattern unit on the base substrate is in the shape of a closed ring, or an open ring.

[0011] For example, according to the array substrate provided by at least one embodiment of the present disclosure, in the first direction, at least parts of adjacent conductive pattern units are connected to each other.

[0012] For example, according to the array substrate provided by at least one embodiment of the present disclosure, the conductive pattern further includes a plurality of connecting portions, the connecting portions extend along the second direction, and both ends of the connecting portions are respectively connected to two adjacent conductive pattern units in the second direction.

[0013] For example, according to the array substrate provided by at least one embodiment of the present disclosure, the array substrate also includes a plurality of data lines, the data lines extending along the second direction, and the data lines are electrically connected to the source, wherein the orthographic projection of the connecting portion on the base substrate falls within the orthographic projection of the portion of the data line located between the two conductive pattern units connected by the connecting portion on the base substrate.

[0014] For example, in the array substrate provided according to at least one embodiment of the present disclosure, the width of the conductive pattern is greater than or equal to 3 μm.

[0015] For example, in the array substrate provided according to at least one embodiment of the present disclosure, in a direction perpendicular to the base substrate, the conductive pattern is located on a side of the common electrode away from the base substrate.

[0016] For example, according to the array substrate provided in at least one embodiment of the present disclosure, in a direction perpendicular to the base substrate, the common electrode is closer to the base substrate than the pixel electrode, and the conductive pattern is located between the common electrode and the pixel electrode.

[0017] For example, in the array substrate provided according to at least one embodiment of the present disclosure, in a direction perpendicular to the base substrate, the common electrode is farther away from the base substrate than the pixel electrode.

[0018] At least one embodiment of the present disclosure further provides a display panel, comprising the array substrate described in any of the above embodiments and an opposing substrate, wherein the opposing substrate is arranged opposite to the array substrate to form a box.

[0019] For example, according to the array substrate provided in at least one embodiment of the present disclosure, the array substrate also includes a shading pattern, and the orthographic projection of the conductive pattern on the base substrate, the orthographic projection of the data line on the base substrate, and the orthographic projection of the gate line on the base substrate all fall within the orthographic projection of the shading pattern on the base substrate.

[0020] For example, according to the array substrate provided by at least one embodiment of the present disclosure, the shading pattern includes a plurality of openings, at least part of the pixel electrode is located in the opening, the array substrate also includes a flat layer, the flat layer is located on the side of the pixel electrode close to the conductive pattern, the drain is electrically connected to the pixel electrode through a via hole passing through the flat layer, and the orthographic projection of the via hole on the base substrate does not overlap with the orthographic projection of the conductive pattern unit on the base substrate.

[0021] For example, in the array substrate provided according to at least one embodiment of the present disclosure, the minimum distance between the orthographic projection of the via hole on the base substrate and the orthographic projection of the conductive pattern unit on the base substrate is greater than or equal to 3.25 μm.

[0022] For example, according to the array substrate provided by at least one embodiment of the present disclosure, in the second direction, the distance that the edge of the orthographic projection of the shading pattern on the base substrate exceeds the edge of the orthographic projection of the gate line on the base substrate is greater than or equal to 0.5 μm.

[0023] For example, according to the array substrate provided by at least one embodiment of the present disclosure, the minimum distance between the edge of the orthographic projection of the data line on the base substrate and the edge of the orthographic projection of the light shielding pattern on the base substrate is greater than or equal to 0.5 μm.

[0024] For example, according to at least one embodiment of the present disclosure, the array substrate is provided, wherein the display panel further includes a plurality of supporting structures, and the supporting structures are located between the array substrate and the base substrate to support the cell thickness.

[0025] For example, in a display panel provided according to at least one embodiment of the present disclosure, the array substrate includes a top insulating layer, the top insulating layer is located on a side of the conductive pattern away from the base substrate, the top insulating layer includes a first insulating portion and a second insulating portion connected to each other, the first insulating portion covers the conductive pattern, the orthographic projection of the second insulating portion on the base substrate does not overlap with at least part of the orthographic projection of the conductive pattern on the base substrate, in a direction perpendicular to the base substrate, the positions where the first insulating portion and the second insulating portion are connected to each other have a step difference, the surface of the first insulating portion away from the conductive pattern is farther away from the base substrate than the surface of the second insulating portion away from the conductive pattern, and the orthographic projection of the support structure on the base substrate falls within the orthographic projection of the second insulating portion on the base substrate.

[0026] For example, in the display panel provided according to at least one embodiment of the present disclosure, at least a portion of the orthographic projection of the conductive pattern on the base substrate surrounds the orthographic projection of the support structure on the base substrate.

[0027] For example, in the display panel provided according to at least one embodiment of the present disclosure, in the second direction, portions of the conductive pattern located on both sides of the same support structure in the second direction are connected to each other.

[0028] For example, in the display panel provided according to at least one embodiment of the present disclosure, in the first direction, at least portions of the conductive pattern located between two adjacent support structures are disconnected from each other.

[0029] For example, according to the display panel provided by at least one embodiment of the present disclosure, in the second direction, the orthographic projection areas of the portions of the conductive pattern located on both sides of the same supporting structure on the base substrate are different.

[0030] For example, according to the display panel provided by at least one embodiment of the present disclosure, the array substrate has a first alignment layer, the opposing substrate has a second alignment layer, the multiple supporting structures are arranged on the opposing substrate, and the first alignment layer has a recess in the area surrounded by at least part of the conductive pattern to limit the position of the supporting structure.

[0031] For example, in the display panel provided according to at least one embodiment of the present disclosure, the orthographic projection of the support structure on the base substrate at least partially overlaps with the orthographic projection of the recess on the base substrate.

[0032] For example, in the display panel provided according to at least one embodiment of the present disclosure, the orthographic projection of the supporting structure on the base substrate falls within the orthographic projection of the recess on the base substrate.

[0033] At least one embodiment of the present disclosure further provides a display device, comprising the display panel described in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0035] FIG1 is a schematic diagram of a partial structure of an array substrate provided by at least one embodiment of the present disclosure.

[0036] FIG. 2 is a schematic cross-sectional view of the array substrate taken along line AA′ in FIG. 1 .

[0037] FIG3 is a schematic cross-sectional view of the array substrate taken along line BB′ in FIG1 .

[0038] FIG. 4 is a schematic cross-sectional view of the array substrate taken along line CC′ in FIG. 1 .

[0039] FIG5 is a schematic cross-sectional view of the array substrate taken along line DD′ in FIG1 .

[0040] FIG. 6 is a schematic cross-sectional view of the array substrate taken along line EE′ in FIG. 1 .

[0041] FIG7 is a schematic diagram of a partial structure of another array substrate provided by at least one embodiment of the present disclosure.

[0042] FIG8 is a schematic structural diagram of a display panel.

[0043] FIG9 is a schematic structural diagram of a display panel provided by at least one embodiment of the present disclosure.

[0044] FIG10 is a partial cross-sectional view of the display panel in FIG9 .

[0045] FIG11 is a schematic diagram of a partial structure of the conductive pattern in FIG10 .

[0046] FIG12 is a schematic diagram of a partial structure of another conductive pattern.

[0047] FIG13 is a schematic diagram of a partial structure of another conductive pattern.

[0048] FIG14 is a schematic diagram of a partial structure of another conductive pattern.

[0049] FIG15 is a schematic diagram of a partial structure of another conductive pattern.

[0050] FIG16 is a partial cross-sectional schematic diagram of another display panel provided by an embodiment of the present disclosure.

[0051] FIG17 is a schematic diagram of a partial structure of another conductive pattern.

[0052] FIG18 is a schematic diagram of a partial structure of another conductive pattern.

[0053] FIG19 is a schematic diagram of a partial structure of another conductive pattern.

[0054] FIG20 is a schematic diagram of a partial structure of another conductive pattern.

[0055] FIG21 is a schematic diagram showing the connection between the display area and the peripheral area of ​​the display panel provided by an embodiment of the present disclosure.

[0056] FIG. 22 is a schematic diagram of a partial structure of the display area in FIG. 21 .

[0057] FIG23 is an enlarged view of a local area in FIG22 .

[0058] FIG. 24 is a schematic cross-sectional view of the array substrate taken along line M1 - M1 ′ in FIG. 21 .

[0059] FIG. 25 is a schematic cross-sectional view of the array substrate taken along line M2 - M2 ′ in FIG. 21 .

[0060] FIG. 26 is a schematic cross-sectional view of the array substrate taken along line M3 - M3 ′ in FIG. 21 .

[0061] FIG. 27 is a schematic cross-sectional view of the array substrate taken along line M4 - M4 ′ in FIG. 21 .

[0062] FIG. 28 is a schematic cross-sectional view of the array substrate taken along line M5 - M5 ′ in FIG. 21 . DETAILED DESCRIPTION

[0063] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0064] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are simply used to distinguish different components. The words "include" or "comprising" and similar terms mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0065] The features "perpendicular," "parallel," and "identical" used in the embodiments of the present disclosure include the features "perpendicular," "parallel," and "identical" in the strict sense, as well as "approximately perpendicular," "approximately parallel," and "approximately identical" that include certain errors, taking into account the errors associated with the measurement of specific quantities (i.e., the limitations of the measurement system), and represent within the acceptable deviation range for the specific value determined by ordinary technicians in this field. The "center" in the embodiments of the present disclosure can include a position strictly at the geometric center and a position approximately at the center of a small area around the geometric center.

[0066] With the rapid development of imaging technology, there is a market demand for display products with larger sizes and higher resolutions. At the same time, with the rapid transmission of information through the Internet, users are becoming more and more familiar with the display industry and paying more attention to their own visual experience.

[0067] However, during research, the inventors of the present disclosure discovered that for medium and large-sized display products (e.g., liquid crystal display products), the display panel generally includes an array substrate and an opposing substrate arranged relative to each other, and the array substrate may be provided with pixel electrodes and common electrodes. An electric field can be formed between the pixel electrode and the common electrode to drive the liquid crystal molecules located between the array substrate and the opposing substrate to rotate, thereby achieving display. When the uniformity of the signal diffusion of the common electrode is poor, crosstalk and other display defects may occur. For example, for medium and large-sized high-resolution products, due to the limitation of the square resistance of the common electrode, the signal uniformity of the common electrode is poor. When the product is running (e.g., when reloading the screen), there may be crosstalk problems when using Excel documents, affecting the user's visual experience when working in Excel. Of course, the above-mentioned crosstalk problem is not limited to scenarios when using Excel documents. For example, the aspect ratio of the display screen of the above-mentioned medium and large-sized display products can be 16:9, for example, the size of the display screen can be 597.6mm×336.15mm, but is not limited to this.

[0068] Therefore, it is urgent to reduce the square resistance of the common electrode in the array substrate to improve the uniformity of signal transmission. At the same time, the technical solution for reducing the square resistance of the common electrode should also have a small impact on the pixel aperture ratio of the product to facilitate display.

[0069] At least one embodiment of the present disclosure provides an array substrate, a display panel, and a display device.

[0070] At least one embodiment of the present disclosure provides an array substrate including a base substrate, a thin film transistor, a pixel electrode, a common electrode, a conductive pattern and a plurality of gate lines, wherein the thin film transistor is located on the base substrate, and the thin film transistor includes a source electrode, a drain electrode and a gate electrode; the pixel electrode is electrically connected to the drain electrode; the common electrode is configured to form an electric field with the pixel electrode; the conductive pattern and the common electrode are located in different layers; the gate line extends along a first direction, and the plurality of gate lines are spaced apart along a second direction, the gate line is electrically connected to the gate electrode of the thin film transistor, the first direction and the second direction are both parallel to the base substrate, and the first direction intersects with the second direction, the conductive pattern is electrically connected to the common electrode, and the orthographic projection of the gate line on the base substrate at least partially overlaps with the orthographic projection of the conductive pattern on the base substrate.

[0071] The array substrate provided in the embodiment of the present disclosure can effectively reduce the square resistance of the common electrode and improve the uniformity of the common electrode signal during diffusion by adding a conductive pattern electrically connected to the common electrode, thereby reducing the probability of crosstalk in the display product and improving the display effect; at the same time, by at least partially overlapping the orthographic projection of the gate line on the base substrate with the orthographic projection of the conductive pattern on the base substrate, the layout area occupied by the conductive pattern can be reduced, and the pixel aperture ratio can be increased to facilitate display.

[0072] The array substrate, display panel, and display device provided by the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0073] FIG1 is a schematic diagram of a partial structure of an array substrate provided by at least one embodiment of the present disclosure; FIG2 is a schematic diagram of a cross-section of the array substrate taken along line AA′ in FIG1 .

[0074] As shown in Figures 1 and 2, the array substrate 10 includes a base substrate 100, a thin film transistor 200, a pixel electrode 300, and a common electrode 400. The thin film transistor 200 is located on the base substrate 100 and includes a source electrode 201, a drain electrode 202, and a gate electrode 203. The pixel electrode 300 is electrically connected to the drain electrode 202 of the thin film transistor 200, and the common electrode 400 is configured to form an electric field with the pixel electrode 300. For example, a liquid crystal layer (not shown) may be provided on one side of the array substrate 10. The electric field formed between the pixel electrode 300 and the common electrode 400 can drive the liquid crystal molecules to deflect for display.

[0075] As shown in Figures 1 and 2, the array substrate 10 further includes a conductive pattern 500, which is electrically connected to the common electrode 400 and is located on a different layer from the common electrode 400. For example, as shown in Figure 2, the conductive pattern 500 and the common electrode 400 may be in direct contact to facilitate electrical signal transmission between the two, but the present invention is not limited thereto. For example, in some embodiments, an insulating layer may be provided between the conductive pattern 500 and the common electrode 400, and the insulating layer may have a via hole so that the common electrode 400 and the conductive pattern 500 are electrically connected through the via hole. The embodiments of the present disclosure are not limited to this.

[0076] As shown in Figures 1 and 2, the array substrate 10 further includes a plurality of gate lines 600. The gate lines 600 extend along a first direction X and are spaced apart along a second direction Y. The gate lines 600 are electrically connected to the gate electrode 203 of the thin film transistor 200 to control the conduction between the source electrode 201 and the drain electrode 202 of the thin film transistor 200. The orthographic projection of the gate line 600 on the base substrate 100 at least partially overlaps with the orthographic projection of the conductive pattern 500 on the base substrate 100.

[0077] For example, an opposing substrate may be provided on the opposite side of the array substrate 10 as shown in FIG1 (for example, see FIG8-FIG9 ). The opposing substrate includes a shading pattern 800, and the shading pattern 800 has an opening 810, and the pixel electrode 300 is located in the opening 810. For example, the opening of the shading pattern 800 may define a pixel area to control the pixel light-emitting area. The portion of the shading pattern 800 other than the opening 810 may block the structure in the array substrate 10 to reduce the risk of light leakage and the like. For example, the shading pattern 800 may cover various signal lines in the array substrate 10, such as, for example, a gate line 600, a conductive pattern 500, a data line, etc., but is not limited thereto. Therefore, when the orthographic projection of the conductive pattern 500 on the base substrate 100 at least partially overlaps with the orthographic projection of the gate line 600 on the base substrate 100, the effect of the provision of the conductive pattern 500 on the pixel aperture ratio can be minimized. For example, after provision of the conductive pattern 500, the pixel aperture ratio of the array substrate 10 can be substantially unchanged, thereby facilitating display. That is, the orthographic projection of the conductive pattern 500 on the base substrate 100 at least partially overlaps with the orthographic projection of the gate line 600 on the base substrate 100, so that the pixel aperture ratio is not reduced due to the provision of the conductive pattern 500.

[0078] 1 and 2 , the first direction X and the second direction Y are both parallel to the base substrate 100 , and the first direction X intersects the second direction Y. For example, the first direction X may be perpendicular to the second direction Y.

[0079] As shown in Figures 1 and 2, the array substrate 10 provided in the embodiment of the present disclosure can effectively reduce the square resistance of the common electrode 400 and improve the uniformity of the common electrode 400 signal diffusion by adding a conductive pattern 500 electrically connected to the common electrode 400, thereby reducing the probability of crosstalk in the display product and improving the display effect; at the same time, by at least partially overlapping the orthographic projection of the gate line 600 on the base substrate 100 with the orthographic projection of the conductive pattern 500 on the base substrate 10, the layout area occupied by the conductive pattern 500 can be reduced, and the pixel aperture ratio can be made larger, which is conducive to display.

[0080] For example, as shown in FIG1 , in the second direction Y, the edge of the orthographic projection of the conductive pattern 500 on the base substrate 100 may extend beyond the edge of the orthographic projection of the gate line 600 on the base substrate 100, for example, by a distance greater than or equal to 0.5 μm. For example, a portion of the orthographic projection of the gate line 600 on the base substrate 100 is covered by the orthographic projection of the conductive pattern 500 on the base substrate 100. For example, in the first direction X, the orthographic projection of the portion of the conductive pattern 500 located between two adjacent thin film transistors 200 and extending along the first direction X on the base substrate 100 covers at least a portion of the gate line 600.

[0081] For example, as shown in FIG1 , in the second direction Y, the size of the portion where the orthographic projection of the conductive pattern 500 on the base substrate 100 overlaps the orthographic projection of the gate line 600 on the base substrate 100 is 30% to 90% of the size of the gate line 600, and may be, for example, at least one of 30% to 70%, 40% to 60%, 450% to 75%, and 50% to 60%, but is not limited thereto. For example, in order to reduce the size of the conductive pattern 500 in the second direction Y, the overlapping area between the conductive pattern 500 and the gate line 600 may be increased as much as possible, thereby facilitating obtaining a larger pixel aperture ratio for display.

[0082] For example, as shown in FIG1 , the array substrate 10 further includes an active pattern 250. The active pattern 250 is connected to the source electrode 201 and the drain electrode 202 of the thin film transistor 200, respectively, and at least partially overlaps with the gate electrode 203. For example, in the first direction X, the source electrode 201 and the drain electrode 202 are respectively disposed on either side of the active pattern 250. For example, the source electrode 201 and the drain electrode 202 may be located on the same layer, and an insulating layer may be disposed between the same layer and the active pattern 250. The source electrode 201 and the drain electrode 202 may be connected to the active pattern 250 via vias penetrating the insulating layer, but the present invention is not limited thereto.

[0083] For example, in an embodiment of the present disclosure, the active pattern 250 is made of a semiconductor material, such as amorphous silicon, low temperature polysilicon, or an oxide semiconductor material, but is not limited thereto.

[0084] For example, as shown in FIG1 , the orthographic projection of the active pattern 250 on the base substrate 100 overlaps at least partially with the orthographic projection of the conductive pattern 500 on the base substrate 100. That is, the orthographic projection of the active pattern 250 on the base substrate 100 does not overlap at least partially, or does not overlap at all. For example, the conductive pattern 500 may include a plurality of hollow portions 501, and at least a portion of the orthographic projection of the active pattern 250 on the base substrate 100 may be located within the region enclosed by the orthographic projections of the hollow portions 501 on the base substrate 100. Thus, along a direction perpendicular to the base substrate 10 (a third direction Z), the active pattern 250 is not completely covered by the conductive pattern 500, so that at least a portion of the active pattern 250 is exposed through the hollow portions 501.

[0085] Such a configuration can prevent the active pattern 250 or at least part of the structure connected to the active pattern 250 from being covered by the conductive pattern 500, thereby facilitating observation of the working state of the thin film transistor 200 (for example, observation can be performed through a microscope) and facilitating inspection and maintenance when a failure occurs in the thin film transistor 200.

[0086] In the embodiment of the present disclosure, the third direction Z is perpendicular to the first direction X and perpendicular to the second direction Y.

[0087] For example, as shown in FIG1 , there is a gap between the orthographic projection of the active pattern 250 on the base substrate 100 and the orthographic projection of the conductive pattern 500 on the base substrate 100. For example, the orthographic projection of the active pattern 250 on the base substrate 100 may be completely located within the area enclosed by the orthographic projection of the hollow portion 501 of the conductive pattern 500 on the base substrate, so as to facilitate observation of the operating state of the thin film transistor 200.

[0088] For example, as shown in FIG1 , the conductive pattern 500 includes a plurality of conductive pattern units 510 . The orthographic projections of the conductive pattern units 510 on the base substrate 100 at least partially surround the orthographic projections of the active pattern 250 on the base substrate 100 . For example, the plurality of conductive pattern units 510 may correspond one-to-one to a plurality of thin-film transistors 200 , and the number of conductive pattern units 510 in the array substrate 10 may be equal to the number of thin-film transistors 200 , but is not limited thereto. For example, at least a portion of the orthographic projections of the thin-film transistors 200 on the base substrate 100 may not be covered by the orthographic projections of the conductive pattern 500 on the base substrate 100 to facilitate observation of their operating state.

[0089] For example, as shown in FIG1 , the orthographic projection of at least a portion of the conductive pattern unit 510 on the base substrate 100 is a closed ring. For example, the ring is not limited to a circular ring and can be, for example, a polygon, an ellipse, a triangle, etc., and the embodiments of the present disclosure are not limited thereto. For example, the orthographic projection of at least a portion of the conductive pattern unit 510 on the base substrate 100 can be an octagonal ring, but is not limited thereto.

[0090] For example, as shown in FIG1 , the orthographic projection of at least a portion of the conductive pattern unit 510 on the base substrate 100 may also be an open ring, for example, a ring with a gap, such as a semicircle, so that a portion of the conductive pattern unit 510 is arranged around the thin film transistor 200 .

[0091] For example, as shown in FIG. 1 , in the first direction X, at least parts of adjacent conductive pattern units 510 are connected to each other, thereby reducing the overall square resistance of the conductive pattern 500 and facilitating uniformity of the signal transmitted by the common electrode 400 .

[0092] For example, as shown in FIG1 , the conductive pattern 500 further includes a plurality of connection portions, for example, the plurality of connection portions may be the first connection portion 520 shown in FIG1 . For example, the first connection portion 520 extends along the second direction Y, and the two ends of the first connection portion 520 are respectively connected to two adjacent conductive pattern units 510 in the second direction Y, thereby further reducing the overall square resistance of the conductive pattern 500, so as to facilitate uniformity of the signal transmitted by the common electrode 400. For example, the conductive pattern 500 may be an overall "mesh" structure, so that the signal transmitted by the common electrode 400 can be transmitted in all directions, which is conducive to uniformity of the signal, but is not limited thereto. For example, a pixel electrode 300 is provided between two adjacent first connection portions 520, and the greater the distance between the two adjacent first connection portions 520 in the first direction X, the more conducive it is to increase the pixel aperture ratio.

[0093] FIG3 is a schematic cross-sectional view of the array substrate taken along line BB′ in FIG1 .

[0094] For example, as shown in Figures 1 and 3, the array substrate 10 further includes a plurality of data lines 700. The data lines 700 extend along the second direction Y and are electrically connected to the source electrodes 201 of the thin film transistors 200. The orthographic projection of the first connecting portion 520 on the base substrate 100 falls within the orthographic projection of the portion of the data line 700 located between the two conductive pattern units 510 connected to the first connecting portion 520 on the base substrate 100.

[0095] For example, as shown in Figures 1 and 3, in the second direction Y, the data line 700 and the first connection portion 520 between two adjacent conductive pattern units 510 have basically the same trend, and the width of the first connection portion 520 is basically the same as the width of the data line 700, thereby reducing the impact of the first connection portion 520 on the pixel aperture ratio.

[0096] For example, as shown in Figures 1 and 3, the minimum distance L1 between the edge of the orthographic projection of the data line 700 on the substrate 100 and the edge of the orthographic projection of the conductive pattern 500 on the substrate 100 is greater than or equal to 0.5 μm. For example, the width of the orthographic projection of the conductive pattern 500 on the substrate 100 is smaller than the width of the orthographic projection of the data line 700 on the substrate 100, thereby facilitating an increase in the pixel aperture ratio. For example, the minimum distance L1 may be at least one of 0.5 μm to 0.9 μm, 0.5 μm to 0.8 μm, 0.6 μm to 0.7 μm, and 0.55 μm to 0.75 μm, but is not limited thereto.

[0097] For example, as shown in Figure 1, the orthographic projection of the conductive pattern 500 on the base substrate 100, the orthographic projection of the data line 700 on the base substrate 100, and the orthographic projection of the gate line 600 on the base substrate 100 all fall within the orthographic projection of the shading pattern 800 on the base substrate 100 to reduce interference with pixel display.

[0098] For example, as shown in Figure 1, the distance L2 between the edge of the positive projection of the shading pattern 800 on the base substrate 100 and the edge of the positive projection of the gate line 600 on the base substrate 100 is greater than or equal to 0.5μm, for example, it can be at least one of 0.5μm to 0.9μm, 0.5μm to 0.8μm, 0.6μm to 0.7μm and 0.55μm to 0.75μm, but is not limited to this.

[0099] For example, as shown in FIG1 , the width L3 of the conductive pattern 500 is greater than or equal to 3 μm, and may be, for example, at least one of 3.1 μm to 3.5 μm, 3.2 μm to 3.6 μm, 3.3 μm to 3.7 μm, and 3.4 μm to 3.8 μm, thereby reducing the overall square resistance of the conductive pattern 500 to facilitate the uniformity of the signal transmitted by the common electrode 400 while making the pixel aperture ratio larger.

[0100] For example, as shown in Figures 1 and 2, the array substrate 10 further includes a planar layer 910, which is located on a side of the pixel electrode 300 close to the conductive pattern 500. The drain electrode 202 is electrically connected to the pixel electrode 300 via a via 950 that penetrates the planar layer 910. For example, as shown in Figure 1, the orthographic projection of the via 950 on the base substrate 100 does not overlap with the orthographic projection of the conductive pattern unit 510 on the base substrate 100. For example, the orthographic projection of the via 950 on the base substrate 100 is located within the area enclosed by the orthographic projection of the conductive pattern unit 510 on the base substrate 100, for example, it can be located in the above-mentioned hollow portion 501. This arrangement facilitates detection of the connection between the drain electrode 202 and the pixel electrode 300 at the via 950.

[0101] For example, as shown in FIG1 , the minimum distance L4 between the orthographic projection of the via hole 950 on the base substrate 100 and the orthographic projection of the conductive pattern unit 510 on the base substrate 100 is greater than or equal to 3.25 μm to reduce the impact of the conductive pattern 510 on the connection condition at the via hole 950. For example, the minimum distance L4 may be at least one of 3.25 μm to 3.50 μm, 3.35 μm to 3.65 μm, 3.45 μm to 3.75 μm, and 3.55 μm to 3.85 μm, but is not limited thereto.

[0102] For example, as shown in Figures 1 and 2, in a direction perpendicular to the base substrate 100, that is, in the third direction Z shown in Figure 2, a first insulating layer 911 is provided on the base substrate 100, and the drain electrode 202 and the source electrode 201 of the thin film transistor 200 are provided on the same layer and are both located on the first insulating layer 911. A planarization layer 910 is provided on the drain electrode 202. A common electrode 400 is provided on the planarization layer 910. For example, the common electrode 400 can be made of a transparent material such as, but not limited to, ITO (Indium Tin Oxide).

[0103] For example, as shown in Figures 1 and 2, the conductive pattern 500 is located on a side of the common electrode 400 away from the base substrate 100. For example, a second insulating layer 922 is further provided between the conductive pattern 500 and the pixel electrode 300. For example, in the third direction Z, the common electrode 400 is closer to the base substrate 100 than the pixel electrode 300, and the conductive pattern 500 is located between the common electrode 400 and the pixel electrode 300, but the present invention is not limited thereto. For example, the pixel electrode 300 can be made of a transparent conductive material, for example, the pixel electrode 300 can be made of the same material as the common electrode 400, but the present invention is not limited thereto.

[0104] For example, as shown in Figures 1 and 3, the data line 700 can be located in the same layer as the drain electrode 202 and the source electrode 201 of the thin film transistor 200, and all of them are located on the first insulating layer 911, so as to facilitate the connection between the data line 700 and the source electrode 201. For example, the data line 700, the source electrode 201, and the drain electrode 202 can be made of the same conductive material and formed by the same process, but the present invention is not limited thereto.

[0105] FIG. 4 is a schematic cross-sectional view of the array substrate taken along line CC′ in FIG. 1 .

[0106] For example, as shown in Figures 1 and 4, at the position cut by line CC', the first insulating layer 911, the data line 700, the planar layer 910, the common electrode 400, and the conductive pattern 500 are sequentially stacked on the base substrate 100. The second insulating layer 922 is disposed on the conductive pattern 500, and the thickness of the second insulating layer 922 is substantially uniform.

[0107] FIG5 is a schematic cross-sectional view of the array substrate taken along line DD′ in FIG1 .

[0108] For example, as shown in Figures 1 and 5, at the position intercepted by line D-D', the gate line 600, the first insulating layer 911, the planar layer 910, the common electrode 400, the conductive pattern 500, and the second insulating layer 922 are sequentially arranged. The orthographic projection of the gate line 600 on the base substrate 100 and the orthographic projection of the conductive pattern 500 on the base substrate 100 at least partially overlap to reduce the impact of the conductive pattern 500 on the pixel aperture ratio. For example, in some embodiments of the present disclosure, the width of the conductive pattern 500 can be substantially equal to the width of the gate line 600, but is not limited thereto.

[0109] FIG. 6 is a schematic cross-sectional view of the array substrate taken along line EE′ in FIG. 1 .

[0110] For example, as shown in Figures 1 and 6, at a position cut by line EE', the first insulating layer 911, the planar layer 910, the common electrode 400, the conductive pattern 500, and the second insulating layer 922 are sequentially disposed on the base substrate 100. For example, at this position, the orthographic projection of the conductive pattern 500 on the base substrate 100 falls within the orthographic projection of the common electrode 400 on the base substrate 100, but the present invention is not limited thereto.

[0111] For example, as shown in Figure 1, in the array substrate 10, the film layer where the gate line 600 is located can be a first metal layer, the film layer where the data line 700 (as shown in Figure 4), the source 201 and the drain 202 are located can be a second metal layer, and the film layer where the conductive pattern 500 is located can be a third metal layer, but is not limited thereto.

[0112] For example, in some embodiments of the present disclosure, in a direction perpendicular to the base substrate, the relative positions of the common electrode and the pixel electrode can be flexibly adjusted according to design requirements, as long as an electric field that drives the liquid crystal to deflect can be formed between the two.

[0113] FIG7 is a schematic diagram of a partial structure of another array substrate provided by at least one embodiment of the present disclosure.

[0114] For example, in some embodiments, in the array substrate 11 provided by the position cut by line AA' in FIG1 , the structure of the array substrate 11 at the corresponding position is shown in FIG7 , that is, the common electrode 400 can be further away from the base substrate 100 than the pixel electrode 300. The difference between the array substrate 11 shown in FIG7 and the array substrate 10 lies in the relative positional relationship between the common electrode 400 and the pixel electrode 300. For the remaining structures, refer to the relevant descriptions of the above embodiments and are not repeated here.

[0115] For example, as shown in FIG7 , in the third direction Z, the first insulating layer 931, the drain electrode 202, and the planar layer 910 are sequentially arranged. The pixel electrode 300 is arranged on the planar layer 910, and the second insulating layer 932 is arranged on the pixel electrode 300. The common electrode 400 and the conductive pattern 500 are sequentially arranged on the second insulating layer 932, and the third insulating layer 933 is arranged on the conductive pattern 500. For example, an electric field can be formed between the pixel electrode 300 and the common electrode 400 to drive the liquid crystal to deflect. For example, the pixel electrode 300 can be made of the same material as the common electrode 400, such as ITO, but is not limited thereto. Compared to the array substrate shown in FIG6 , the conductive pattern 500 in the array substrate 11 is further away from the base substrate 100. Such an arrangement, for example, facilitates flexible arrangement of the structure of the conductive pattern 500 to adapt to more design requirements.

[0116] FIG8 is a schematic structural diagram of a display panel.

[0117] Typically, as shown in FIG8 , an array substrate 10 and an opposing substrate 20 are provided in a display product of medium or large size and high resolution, and the opposing substrate 20 is arranged opposite to the array substrate 10. For example, a plurality of supporting structures 15 may be provided on the opposing substrate 20 to support the array substrate 10 and the opposing substrate 20. For example, a layer of the array substrate 10 facing the opposing substrate 20 is usually an insulating layer, which can protect the array substrate 10. For example, the insulating layer can also be an alignment layer to enable the liquid crystal to be arranged uniformly and stably. However, since the supporting structure 15 is in direct contact with the above-mentioned insulating layer or alignment layer, it is easy for the supporting structure 15 to shift during the process of setting the opposing substrate 20 and the array substrate 10 into a box, thereby scratching the surface of the above-mentioned insulating layer or the surface of the alignment layer, which can easily lead to display defects such as mura.

[0118] FIG9 is a schematic structural diagram of a display panel provided by at least one embodiment of the present disclosure.

[0119] Therefore, as shown in FIG9 , an embodiment of the present disclosure further provides a display panel 1000. The display panel 1000 includes the array substrate 10 and the counter substrate 20 described in any of the above embodiments, wherein the counter substrate 20 is disposed opposite the array substrate 10 to form a cell. The display panel 1000 also includes a plurality of support structures 210, which are located between the array substrate 10 and the counter substrate 20 to support the cell thickness. For example, the array substrate in the following embodiments is described using the array substrate 10 shown in FIG1 , but is not limited thereto.

[0120] For example, as shown in Figure 9, a liquid crystal layer 30 is provided within the cell. The liquid crystal layer 30 includes a plurality of liquid crystal molecules 301. In some embodiments, a filter layer may be provided on the side of the counter substrate 20 facing the array substrate 10 to achieve color display. For example, the filter layer may include a plurality of filter units, each of which may correspond to a display electrode. For example, the plurality of filter units may include, but are not limited to, a plurality of red filter units, a plurality of green filter units, and a plurality of blue filter units.

[0121] For example, as shown in FIG9 , the array substrate 10 includes a top insulating layer 900 , which is located on the side of the conductive pattern 500 away from the base substrate 100 . For example, the top insulating layer 900 may be the film layer of the array substrate 10 closest to the counter substrate 20 . FIG9 also shows the conductive pattern 500 , which is located on the side of the top insulating layer 900 close to the base substrate 100 . As can be seen from FIG9 , the conductive pattern 500 is not laid out in a single layer, but rather has a pattern with a characteristic shape. For clarity, some film layers are omitted from the array substrate in FIG9 .

[0122] For example, as shown in Figures 4 and 9, because the conductive pattern 500 is closer to the base substrate 100 than the top insulating layer 900, and the thickness of the top insulating layer 900 is relatively uniform, the top insulating layer 900 can include a first insulating portion 901 and a second insulating portion 902 that are connected to each other. As shown in Figure 4, the first insulating portion 901 covers the conductive pattern 500, while the orthographic projection of the second insulating portion 902 on the base substrate 100 does not overlap with at least a portion of the orthographic projection of the conductive pattern 500 on the base substrate 100.

[0123] For example, the first insulating layer 901 completely covers the conductive pattern 500 , so that the orthographic projection of the conductive pattern 500 on the base substrate 100 falls within the orthographic projection of the first insulating layer 901 on the base substrate 100 .

[0124] For example, as shown in FIG9 and FIG4 , the first insulating portion 901 and the second insulating portion 902 have a step H at their connection locations in the third direction Z. The surface of the first insulating portion 901 away from the conductive pattern 500 is further away from the base substrate 100 than the surface of the second insulating portion 902 away from the conductive pattern 500. The orthographic projection of the support structure 210 on the base substrate 100 falls within the orthographic projection of the second insulating portion 902 on the base substrate 100. For example, the step H between the first insulating portion 901 and the second insulating portion 902 can be substantially equal to the thickness of the conductive pattern 500. For example, the step H can be 0.3 μm to 1 μm, for example, at least one of 0.3 μm to 0.5 μm, 0.5 μm to 0.8 μm, 0.6 μm to 0.9 μm, and 0.3 μm to 0.7 μm, but is not limited thereto.

[0125] With such an arrangement, as shown in Figures 9 and 4, the second insulating portion 902 can be recessed relative to the first insulating portion 901, and the support structure 210 can be located on the second insulating portion 902, so that the first insulating portion 901 can be used to limit the support structure 210 to limit the support structure 210 from sliding on the surface of the second insulating portion 902, thereby reducing the risk of the support structure 210 scratching the top insulating layer 900, and further reducing the risk of display defects such as Mura.

[0126] For example, as shown in FIG9 , the top insulating layer 900 in the above embodiment may be the first alignment layer 110, and the counter substrate 20 further includes a second alignment layer 220. The second alignment layer 220 may be the film layer of the counter substrate 20 closest to the array substrate 10, and may face the first alignment layer 110 in the third direction Z. For example, the first alignment layer 110 and the second alignment layer 220 may jointly control the alignment state of the liquid crystal molecules 301, thereby facilitating orderly arrangement of the liquid crystal molecules 301.

[0127] For example, as shown in FIG9 , a plurality of support structures 210 are disposed on the counter substrate 20, and the first alignment layer 110 has recesses 205 within an area enclosed by at least a portion of the conductive pattern 500 to define the positions of the support structures 210. For example, the orthographic projections of the support structures 210 on the base substrate 100 at least partially overlap with the orthographic projections of the recesses 205 on the base substrate 100. For example, the orthographic projections of the support structures 210 on the base substrate 100 can be made to fall within the orthographic projections of the recesses 205 on the base substrate 100. This allows the first alignment layer 110 to effectively limit the movement of the support structures 210 in a direction parallel to the base substrate 100 while controlling the alignment of the liquid crystal molecules 301, thereby reducing the risk of the support structures 210 scratching the first alignment layer 110.

[0128] It should be noted that in the embodiments of the present disclosure, as shown in FIG9 , the metal structure 500 may not be in direct contact with the film layer of the array substrate 10 closest to the counter substrate 20 (e.g., the top insulating layer or the first alignment layer 110 in the above-described embodiments). For example, multiple other film layers may be provided on the side of the metal structure 500 away from the base substrate 100, as long as the film layer of the array substrate 10 closest to the counter substrate 20 has a recess and the risk of the support structure 210 scratching the film layer of the array substrate 10 closest to the counter substrate 20 is reduced.

[0129] FIG10 is a partial cross-sectional view of the display panel in FIG9 .

[0130] For example, as shown in FIG10 , at least a portion of the orthographic projection of the conductive pattern 500 on the base substrate 100 surrounds the orthographic projection of the support structure 210 on the base substrate 100. For example, the orthographic projection of the support structure 210 on the base substrate 100 can be any one of a polygon (e.g., an octagon), a circle, and an ellipse, and the embodiments of the present disclosure are not limited to this. For example, the orthographic projection of the conductive pattern unit 510 (see FIG1 ) in the conductive pattern 500 on the base substrate 100 can be a closed ring, so that the support structure 210 can be located in the ring. For example, in some embodiments of the present disclosure, the orthographic projection of the portion of the conductive pattern 500 surrounding the support structure 210 on the base substrate 100 can also be an open ring, and this is not limited.

[0131] For example, as shown in Figures 4 and 10, when the support structure 210 is at least partially surrounded by the conductive pattern 500, the partial conductive pattern 500 limits the support structure 210 from moving in a direction parallel to the base substrate 100, thereby reducing the risk of the support structure 210 scratching the surface of the array substrate 10 (for example, the first alignment layer 110 in the array substrate 10).

[0132] FIG11 is a schematic diagram of a partial structure of the conductive pattern in FIG10 .

[0133] For example, as shown in FIG11 , in the second direction Y, the portions of the conductive pattern 500 located on either side of the same support structure 210 in the second direction Y are connected to each other. For example, the conductive pattern 500 may include a second connecting portion 530. The portions of the conductive pattern 500 located on either side of the same support structure 210 in the second direction Y extend primarily in the first direction X, and the two portions are connected by the second connecting portion 530. This allows the orthographic projection of the portion of the conductive pattern 500 surrounding the same support structure 210 on the substrate to form a closed ring. In this arrangement, the support structure 210 is circumferentially constrained by the conductive pattern 500, thereby effectively reducing the risk of movement of the support structure 210 in a direction parallel to the substrate 100.

[0134] FIG12 is a schematic diagram of a partial structure of another conductive pattern.

[0135] For example, the conductive pattern shown in FIG12 has a different shape from the conductive pattern in FIG11 . For other features, reference may be made to the relevant descriptions in the above embodiments and will not be repeated here.

[0136] For example, as shown in Figures 10 and 12 , in the second direction Y, the portions of the conductive pattern in Figure 12 located on both sides of the same support structure 210 include two opposing corners, corresponding to the support structure 210 having a partially protruding structure, but the present invention is not limited thereto. For example, when the support structure 210 has various shapes according to design requirements, the shape and structure of the conductive pattern 500 can also be flexibly adjusted accordingly to better restrict the movement of the support structure 210 in a direction parallel to the substrate.

[0137] FIG13 is a schematic diagram of a partial structure of another conductive pattern.

[0138] For example, the conductive pattern shown in FIG13 has a different shape from the conductive pattern in FIG11 . For other features, reference may be made to the relevant descriptions in the above embodiments and will not be repeated here.

[0139] For example, as shown in FIG13 , at least the portion of the conductive pattern 500 located between two adjacent support structures 210 in the first direction X is disconnected from each other. For example, as shown in FIG10 and FIG13 , the conductive pattern 500 may include a first conductive pattern portion 541 and a second conductive pattern portion 542 located on opposite sides of the same support structure 210 in the second direction Y, respectively, with the first conductive pattern portion 541 and the second conductive pattern portion 542 being disconnected from each other. For example, in the first direction X, the two first conductive pattern portions 541 located on the same side of two adjacent support structures 210 are connected to each other, while the two second conductive pattern portions 542 located on the same side of the two adjacent support structures 210 are disconnected from each other. For example, in this arrangement, the portion of the support structure 210 not surrounded by the conductive pattern 500 is less likely to slide. With this arrangement, the movement of the support structure 210 can be limited by the first conductive pattern portion 541 and the second conductive pattern portion 542.

[0140] FIG14 is a schematic diagram of a partial structure of another conductive pattern.

[0141] For example, the conductive pattern shown in FIG14 has a different shape from the conductive pattern in FIG13 . For other features, reference may be made to the relevant descriptions in the above embodiments and will not be repeated here.

[0142] For example, as shown in FIG14 , at least the portion of the conductive pattern 500 located between two adjacent support structures 210 in the first direction X is disconnected from each other. For example, as shown in FIG10 and FIG14 , the conductive pattern 500 may include a first conductive pattern portion 551 and a second conductive pattern portion 552 located on opposite sides of the same support structure 210 in the second direction Y. The first conductive pattern portion 551 and the second conductive pattern portion 552 are disconnected from each other, and the second conductive pattern portion 552 includes a first sub-conductive pattern portion 5521 and a second sub-conductive pattern portion 5522 spaced apart from each other. For example, in the first direction X, the two first conductive pattern portions 541 located on the same side of two adjacent support structures 210 are connected to each other, while the two second conductive pattern portions 542 located on the same side of the two adjacent support structures 210 are disconnected from each other. The first sub-conductive pattern portion 5521 and the second sub-conductive pattern portion 5522 surrounding the same support structure 210 form an orthographic projection on the substrate in the shape of a figure eight, thereby limiting the movement of the support structure 210.

[0143] FIG15 is a schematic diagram of a partial structure of another conductive pattern.

[0144] For example, as shown in Figures 10 and 15 , to better define the movement of the support structure 210 according to design requirements, the structure of the conductive pattern 500 is not limited to that shown in the above embodiments. For example, in the second direction Y, the portions of the conductive pattern 500 located on opposite sides of the same support structure 210 may have different orthographic projection areas on the substrate 100. For example, in some embodiments, the conductive pattern 500 may be provided only on one side of the support structure 210 to reduce movement of the support structure 210 toward the support structure 210 closer to that side, but the present invention is not limited thereto.

[0145] FIG16 is a partial cross-sectional schematic diagram of another display panel provided by an embodiment of the present disclosure.

[0146] For example, as shown in FIG16 , a display panel 1001 includes a plurality of pixel electrodes 300 and a plurality of support structures 210. The plurality of pixel electrodes 300 are arranged in an array along a first direction X and a second direction Y. The plurality of support structures 210 are arranged in an array along the first direction X and the second direction Y. There is a gap between the orthographic projections of the pixel electrodes 300 on the substrate and the orthographic projections of the support structures 210 on the substrate. For example, the orthographic projections of the support structures 210 on the substrate are substantially circular, and the orthographic projection area of ​​the support structures 210 on the substrate is smaller than the orthographic projection area of ​​the pixel electrodes 300 on the substrate.

[0147] For example, as shown in Figure 16, the display panel 1001 also includes a conductive pattern 500, and at least part of the conductive pattern 500 surrounds the support structure 210. For example, the conductive pattern 500 includes a plurality of conductive pattern units 510, and the support structure 210 is located in the area surrounded by the conductive pattern units 510. In the first direction X, the portions of the conductive pattern 500 surrounding two adjacent support structures 210 are connected to each other. In the second direction Y, the portions of the conductive pattern 500 located on both sides of the same pixel electrode 300 are connected to each other. For example, the conductive pattern 500 can be made into an integrated structure, which is beneficial to reducing the square resistance of the conductive pattern 500, so as to facilitate the diffusion of signals in all directions. At the same time, the support structure 210 can be slid in a direction parallel to the base substrate to reduce scratches on the array substrate in the display panel 1001, which is beneficial to reducing the occurrence of crosstalk and display defects such as mura.

[0148] FIG17 is a schematic diagram of a partial structure of another conductive pattern; FIG18 is a schematic diagram of a partial structure of another conductive pattern; FIG19 is a schematic diagram of a partial structure of another conductive pattern; and FIG20 is a schematic diagram of a partial structure of another conductive pattern.

[0149] For example, as shown in FIG17 , the conductive pattern 500 may include a first conductive pattern portion 5011 and a second conductive pattern portion 5012, which are spaced apart in a second direction Y. The first conductive pattern portion 5011 extends along a first direction X, and the extension direction of the first conductive pattern portion 5011 is substantially straight, while the extension direction of the second conductive pattern portion 5012 is curved. The orthographic projection of the second conductive pattern portion 5012 on the substrate at least partially overlaps with the orthographic projection of the gate line 600 on the substrate. For example, the orthographic projection of the portion of the second conductive pattern portion 5012 extending along the first direction X on the substrate falls within the orthographic projection of the gate line 600 on the substrate, thereby saving layout space and facilitating an increase in pixel aperture ratio. For example, the second conductive pattern portion 5012 includes a straight line segment extending along the first direction X between adjacent data lines, and the orthographic projection of the straight line segment on the substrate falls within the orthographic projection of the gate line 600 on the substrate.

[0150] For example, as shown in FIG18 , the conductive pattern 500 includes a first conductive pattern portion 5013 and a second conductive pattern portion 5014. The first conductive pattern portion 5013 and the second conductive pattern portion 5014 both extend in a curved direction, and are connected by a second connecting portion 530. The display panel includes a first gate line 6001 and a second gate line 6002. The first gate line 6001 and the second gate line 6002 both extend along a first direction X. The orthographic projection of the first conductive pattern portion 5013 on the substrate at least partially overlaps with the orthographic projection of the first gate line 6001 on the substrate, and the orthographic projection of the second conductive pattern portion 5014 on the substrate at least partially overlaps with the orthographic projection of the second gate line 6002 on the substrate. The display panel includes a first pixel electrode 3001 and a second pixel electrode 3002 adjacent to each other in the first direction X, and a third pixel electrode 3003 and a fourth pixel electrode 3004 adjacent to each other in the first direction X. The first pixel electrode 3001 and the third pixel electrode 3003 are located in different rows in the second direction Y. For example, the drain electrode 202 adjacent to the gate electrode 203 connected to the first gate line 6001 is connected to the first pixel electrode 3001 through a via hole. For example, the drain electrode 202 adjacent to the gate electrode 203 connected to the second gate line 6002 is connected to the third pixel electrode 3003 through a via hole.

[0151] For example, as shown in Figure 19, the conductive pattern 500 includes a plurality of openings 50010. For example, the conductive pattern 500 includes a plurality of conductive pattern units 510, and the positive projection of the conductive pattern unit 510 on the substrate is an open ring. At least part of the pixel electrode 300 is located in the ring area, so that the distance between adjacent pixel electrodes 300 in the second direction Y can be reduced to increase the pixel opening.

[0152] For example, as shown in FIG20 , the conductive pattern 500 may include a first conductive pattern portion 5015 and a second conductive pattern portion 5016, the first conductive pattern portion 5015 and the second conductive pattern portion 5016 being spaced apart in a second direction Y, and connected by a second connecting portion 530. The first conductive pattern portion 5015 and the second conductive pattern portion 5016 both extend in a curved direction. The display panel includes a first gate line 6003 and a second gate line 6004, both extending along a first direction X. The orthographic projection of the first conductive pattern portion 5015 on the substrate at least partially overlaps with the orthographic projection of the first gate line 6003 on the substrate, and the orthographic projection of the second conductive pattern portion 5016 on the substrate at least partially overlaps with the orthographic projection of the second gate line 6004 on the substrate. For example, the pixel electrode 300 can be connected to the drain of the thin film transistor through the via 950, and at least a portion of the pixel electrode 300 can be connected to the common electrode line through the via 960 (for the arrangement of the common electrode line, please refer to the relevant description of Figures 22 and 23 in the following embodiments). For example, there is a gap between the orthographic projection of the via 950 on the base substrate and the orthographic projection of the via 960 on the base substrate to reduce the risk of poor signal.

[0153] Figure 21 is a schematic diagram of the connection between the display area and the peripheral area of ​​the display panel provided by an embodiment of the present disclosure; Figure 22 is a schematic diagram of a local structure of the display area in Figure 21; and Figure 23 is an enlarged view of the local area in Figure 22.

[0154] For example, as shown in FIG. 21 , the display panel includes a display area 1010 and a peripheral area 1020 . The peripheral area 1020 is located on at least one side of the display area 1010 . For example, the peripheral area 1020 may be disposed around the display area 1010 , but is not limited thereto.

[0155] For example, as shown in FIG22 , when viewed from the array substrate side of the display panel, a plurality of sub-pixels are provided in the display area 1010, and the plurality of sub-pixels are arranged in an array along a first direction X and a second direction Y to form a plurality of pixel rows and a plurality of pixel columns. For example, the plurality of sub-pixels include a first sub-pixel 310, a second sub-pixel 320, and a third sub-pixel 330. For example, the first sub-pixel 310, the second sub-pixel 320, and the third sub-pixel 330 may each be a sub-pixel emitting a different color. For example, one of the first sub-pixel 310 and the second sub-pixel 320 may be a red sub-pixel emitting red light, the other may be a blue sub-pixel emitting blue light, and the third sub-pixel 330 may be a green sub-pixel emitting green light. For example, the first sub-pixel 310 is a blue sub-pixel, and the second sub-pixel 320 is a red sub-pixel. Of course, the colors of the first sub-pixel 310, the second sub-pixel 320, and the third sub-pixel 330 may be interchangeable. Of course, the disclosed embodiments are not limited to this, and the size of the light-emitting area of ​​each color sub-pixel may be set according to actual product requirements.

[0156] For example, as shown in Figures 22 and 23, a conductive pattern 500 and the source 201, drain 202 and gate 203 of the thin film transistor 200 are arranged between two adjacent rows of sub-pixels, and part of the structure of the thin film transistor 200 is not covered by the conductive pattern 500 to facilitate the detection of the working status of the thin film transistor 200.

[0157] For example, compared to the conductive pattern 500 shown in FIG11 , the number of second connection portions 530 in the conductive pattern 500 in FIG23 can be reduced according to design requirements. For example, in the second direction Y, a second connection portion 530 is provided between two adjacent third sub-pixels 330, and a second connection portion 530 may not be provided between two adjacent second sub-pixels 320 to better adapt to the layout space. For example, in some embodiments, in the second direction Y, a second connection portion 530 may be provided only between two adjacent first sub-pixels 310, and no second connection portion 530 may be provided between two adjacent third sub-pixels 330, but the present invention is not limited thereto. For example, in some embodiments, the number and position of the second connection portions 530 can be flexibly adjusted according to the layout space.

[0158] For example, as shown in Figures 21 and 23, the display panel further includes a common electrode line 5000, and the common electrode line 5000 extends along the first direction X. For example, the common electrode line 5000 can be located on the same layer as the gate line 600. For example, the conductive pattern 500 can be located on a side of the common electrode line 5000 away from the base substrate, and the common electrode line 5000 can be electrically connected to the conductive pattern 500, thereby further reducing the square resistance of the common electrode 400 (as shown in Figure 4) and improving the uniformity of the signal diffusion of the common electrode 400.

[0159] For example, as shown in FIG. 23 , the orthographic projection of the common electrode line 5000 on the base substrate does not overlap with the gate line 600 to reduce signal interference.

[0160] Figure 24 is a schematic cross-sectional view of the array substrate in Figure 21 taken along line M1-M1'; Figure 25 is a schematic cross-sectional view of the array substrate in Figure 21 taken along line M2-M2'; Figure 26 is a schematic cross-sectional view of the array substrate in Figure 21 taken along line M3-M3'; Figure 27 is a schematic cross-sectional view of the array substrate in Figure 21 taken along line M4-M4'; Figure 28 is a schematic cross-sectional view of the array substrate in Figure 21 taken along line M5-M5'.

[0161] For example, as shown in FIG. 21 , a portion of the signal lines in the display area 1010 are connected to the peripheral area 1020 , so that a driving signal can be applied from the peripheral area 1020 to the display area 1010 .

[0162] For example, as shown in Figures 21 and 24, at the position intercepted by line M1-M1', the first insulating layer 911, the flat layer 910, the connector 1400 located on the same layer as the common electrode 400, the connector 1500 located on the same layer as the conductive pattern 500, the second insulating layer 922, and the connector 1300 located on the same layer as the pixel electrode 300 are stacked in sequence on the base substrate 100.

[0163] For example, as shown in Figures 21 and 25, at the position intercepted by line M2-M2', a hollowed-out area of ​​the third metal layer (i.e., the film layer where the conductive pattern 500 is located) is located. A connector 1601 located on the same layer as the gate line 600, a first insulating layer 911, a connector 1700 located on the same layer as the data line 700, a planar layer 910, a connector 1401 located on the same layer as the common electrode 400, a second insulating layer 922, and a connector 1301 located on the same layer as the pixel electrode 300 are sequentially stacked on the base substrate 100. For example, in the second direction Y, other connectors located on the same layer are spaced apart on both sides of the connector 1601. For example, the connector 1601 can transmit a scan signal from the peripheral area 1020 to the display area 1010 to control the on / off switching of the thin film transistor 200 in the display area 1010.

[0164] For example, as shown in Figures 21 and 26, the position intercepted by line M3-M3' is located at the edge of the hollowed-out region of the third metal layer. At this position, the structure of the connector 1401 and the structure below it, which are located on the same layer as the common electrode 400, is substantially the same as the structure shown in Figure 24. A connector 1501, which is located on the same layer as the conductive pattern 500, is disposed on the connector 1401. The second insulating layer 922 and the connector 1301, which is located on the same layer as the pixel electrode 300, are disposed on the conductive pattern 500.

[0165] For example, as shown in Figures 21 and 27, at the position intercepted by line M4-M4', the connector 1602 located on the same layer as the gate line 600, the first insulating layer 911, the connector 1701 located on the same layer as the data line 700 (as shown in Figure 4), the flat layer 910, the connector 1401 located on the same layer as the common electrode 400, and the connector 1502 located on the same layer as the conductive pattern 500 are arranged in sequence, the second insulating layer 922 is located on the connector 1502, and the connector 1302 located on the same layer as the pixel electrode 300 is located on the second insulating layer 922 and is connected to the connector 1502 through the via N1.

[0166] For example, as shown in Figures 21 and 28, at the position intercepted by line M5-M5', a connector 1603 located on the same layer as the gate line 600, a first insulating layer 911, a connector 1702 located on the same layer as the data line 700 (as shown in Figure 4), and a planar layer 910 are sequentially arranged, a second insulating layer 922 is located on the planar layer 910, and a connector 1303 located on the same layer as the pixel electrode 300 is located on the second insulating layer 922. The connector 1303 is connected to the connector 1702 through a via N2, and the connector 1303 is connected to the connector 1603 through a via N3.

[0167] In the embodiments of the present disclosure, the source 201 and drain 202 of the thin film transistor 200 are interchangeable. Of course, one of the source 201 and drain 202 of the thin film transistor 200 can also be referred to as a first electrode, and the other of the source 201 and drain 202 of the thin film transistor 200 can also be referred to as a second electrode. The gate 203 of the thin film transistor 200 can also be referred to as a control electrode.

[0168] In the embodiment of the present disclosure, both the pixel electrode 300 and the common electrode 400 may be referred to as display electrodes. For example, one of the pixel electrode 300 and the common electrode 400 may be referred to as a first display electrode, and the other of the pixel electrode 300 and the common electrode 400 may be referred to as a second display electrode.

[0169] For example, the array substrate provided by the embodiment of the present disclosure may be manufactured using an oxide back channel etch (Oxide Back Channel Etch) technique.

[0170] For example, in the embodiment of the present disclosure, the support structure 15 may also be referred to as a spacer.

[0171] The embodiments of the present disclosure are described using the example of the pixel electrode 300 being located on the side of the common electrode 400 away from the base substrate, that is, the pixel electrode 300 is formed after the common electrode 400, but are not limited thereto. The positions of the pixel electrode 300 and the common electrode 400 can be adjusted as needed. For example, in some embodiments, the common electrode 400 is located on the side of the pixel electrode 300 away from the base substrate. In the embodiments of the present disclosure, one of the common electrode 400 and the pixel electrode 300 away from the base substrate has a slit to facilitate the formation of an electric field between the common electrode 400 and the pixel electrode 300.

[0172] The embodiments of the present disclosure take the conductive pattern 500 as being located above the common electrode 400, i.e., the conductive pattern 500 is formed after the common electrode 400, but the present invention is not limited thereto. In other embodiments, the conductive pattern 500 may be formed first, and then the common electrode 400 may be formed, i.e., the common electrode 400 is located above the conductive pattern 500.

[0173] In the embodiments of the present disclosure, components located on the same layer may be formed from the same film layer through the same patterning process. For example, components located on the same layer may be located on a surface of the same component away from the base substrate.

[0174] It should be noted that, for the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or intervening elements may be present.

[0175] In the embodiments of the present disclosure, the patterning or patterning process may include only photolithography, or may include photolithography and etching steps, or may include other processes such as printing and inkjet printing to form a predetermined pattern. A photolithography process includes film formation, exposure, and development, and utilizes photoresist, a mask, and an exposure machine to form a pattern. The appropriate patterning process may be selected based on the structure to be formed in the embodiments of the present disclosure.

[0176] In the embodiments of the present disclosure, components located at different layers are formed from different film layers through different patterning processes.

[0177] At least one embodiment of the present disclosure further provides a display device, and the display device includes the display panel described in any of the above embodiments. Therefore, the display device includes the above display panel, and therefore, the technical effects of the above display panel can also be reflected on the display device, which will not be repeated here.

[0178] There are a few points to note:

[0179] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to general designs.

[0180] (2) In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0181] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure, which is determined by the appended claims.

Claims

1. An array substrate, comprising: substrate substrate; A thin film transistor, located on the substrate, comprising a source electrode, a drain electrode and a gate electrode; a pixel electrode, electrically connected to the drain electrode; a common electrode configured to form an electric field with the pixel electrode; A conductive pattern located at a different layer from the common electrode; a plurality of gate lines, the plurality of gate lines extending along a first direction, the plurality of gate lines being spaced apart along a second direction, the gate lines being electrically connected to the gate of the thin film transistor, the first direction and the second direction both being parallel to the substrate, and the first direction intersecting the second direction, The conductive pattern is electrically connected to the common electrode, and an orthographic projection of the gate line on the base substrate at least partially overlaps with an orthographic projection of the conductive pattern on the base substrate.

2. The array substrate according to claim 1, further comprising an active pattern connected to the source electrode and the drain electrode of the thin film transistor respectively and at least partially overlapping the gate electrode, in, An orthographic projection of the active pattern on the base substrate overlaps at least partially with an orthographic projection of the conductive pattern on the base substrate.

3. The array substrate according to claim 2, wherein: An orthographic projection of the active pattern on the base substrate has a space between an orthographic projection of the conductive pattern on the base substrate.

4. The array substrate according to claim 2 or 3, wherein: The conductive pattern includes a plurality of conductive pattern units, and at least a portion of an orthographic projection of the conductive pattern units on the base substrate surrounds an orthographic projection of the active pattern on the base substrate.

5. The array substrate according to claim 4, wherein: The orthographic projection of at least part of the conductive pattern unit on the base substrate is in the shape of a closed ring or an open ring.

6. The array substrate according to claim 4, wherein: In the first direction, at least parts of adjacent conductive pattern units are connected to each other.

7. The array substrate according to any one of claims 4 to 6, wherein: The conductive pattern further includes a plurality of connecting portions, wherein the connecting portions extend along the second direction, and two ends of the connecting portions are respectively connected to two adjacent conductive pattern units in the second direction.

8. The array substrate according to claim 7, further comprising a plurality of data lines, the data lines extending along the second direction and the data lines being electrically connected to the source electrode, in, The orthographic projection of the connecting portion on the base substrate falls within the orthographic projection of a portion of the data line located between the two conductive pattern units connected by the connecting portion on the base substrate.

9. The array substrate according to any one of claims 1 to 8, wherein: The width of the conductive pattern is greater than or equal to 3 μm.

10. The array substrate according to any one of claims 1 to 9, wherein: In a direction perpendicular to the base substrate, the conductive pattern is located on a side of the common electrode away from the base substrate.

11. The array substrate according to claim 10, wherein: In a direction perpendicular to the base substrate, the common electrode is closer to the base substrate than the pixel electrode, and the conductive pattern is located between the common electrode and the pixel electrode.

12. The array substrate according to claim 10, wherein: In a direction perpendicular to the base substrate, the common electrode is farther away from the base substrate than the pixel electrode.

13. A display panel, comprising: The array substrate according to any one of claims 1 to 12; The counter substrate is arranged opposite to the array substrate to form a box.

14. According to the display panel of claim 13, the opposing substrate comprises a shading pattern, and the orthographic projection of the conductive pattern on the base substrate, the orthographic projection of the data line on the base substrate, and the orthographic projection of the gate line on the base substrate all fall into the orthographic projection of the shading pattern on the base substrate.

15. The display panel according to claim 14, wherein: The light shielding pattern includes a plurality of openings, and at least a portion of the pixel electrode is located in the openings. The array substrate also includes a flat layer, which is located on a side of the pixel electrode close to the conductive pattern. The drain is electrically connected to the pixel electrode through a via hole penetrating the flat layer. The orthographic projection of the via hole on the base substrate does not overlap with the orthographic projection of the conductive pattern unit on the base substrate. 16 . The display panel according to claim 15 , wherein a minimum distance between an orthographic projection of the via hole on the base substrate and an orthographic projection of the conductive pattern unit on the base substrate is greater than or equal to 3.25 μm.

17. The display panel according to any one of claims 14 to 16, wherein: In the second direction, The distance that the edge of the orthographic projection of the light shielding pattern on the base substrate exceeds the edge of the orthographic projection of the gate line on the base substrate is greater than or equal to 0.5 μm.

18. The display panel according to any one of claims 14 to 17, wherein: A minimum distance between an edge of an orthographic projection of the data line on the base substrate and an edge of an orthographic projection of the light shielding pattern on the base substrate is greater than or equal to 0.5 μm.

19. The display panel according to claim 13, wherein: The display panel further includes a plurality of supporting structures, and the supporting structures are located between the array substrate and the base substrate to support the cell thickness.

20. The display panel according to claim 19, wherein: The array substrate comprises a top insulating layer, wherein the top insulating layer is located on a side of the conductive pattern away from the base substrate. The top insulating layer includes a first insulating portion and a second insulating portion connected to each other, the first insulating portion covers the conductive pattern, and an orthographic projection of the second insulating portion on the base substrate does not overlap with at least a portion of an orthographic projection of the conductive pattern on the base substrate. In a direction perpendicular to the base substrate, the positions where the first insulating part and the second insulating part are connected to each other have a step difference, the surface of the first insulating part away from the conductive pattern is farther away from the base substrate than the surface of the second insulating part away from the conductive pattern, and the orthographic projection of the support structure on the base substrate falls into the orthographic projection of the second insulating part on the base substrate.

21. The display panel according to claim 19 or 20, wherein: At least a portion of an orthographic projection of the conductive pattern on the base substrate surrounds an orthographic projection of the support structure on the base substrate.

22. The display panel according to claim 19, wherein: In the second direction, portions of the conductive pattern located on both sides of the same support structure in the second direction are connected to each other.

23. The display panel according to claim 19, wherein: In the first direction, at least parts of the conductive pattern located between two adjacent support structures are disconnected from each other.

24. The display panel according to claim 19, wherein: In the second direction, the orthographic projection areas of the portions of the conductive pattern located on two sides of the same support structure on the base substrate are different.

25. The display panel according to any one of claims 19 to 24, wherein: The array substrate has a first alignment layer, the opposing substrate has a second alignment layer, the plurality of support structures are arranged on the opposing substrate, and the first alignment layer has a recess in an area at least partially surrounded by the conductive pattern to define the position of the support structure.

26. The display panel according to claim 25, wherein: An orthographic projection of the support structure on the base substrate at least partially overlaps with an orthographic projection of the recess on the base substrate.

27. The display panel according to claim 25, wherein: The orthographic projection of the support structure on the substrate falls into the orthographic projection of the recess on the substrate.

28. A display device comprising the display panel according to any one of claims 13 to 27.

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