Thin-film transistors and electronic devices with vertical structure

Abstract

The application provides a vertical structure thin film transistor and electronic device; the vertical structure thin film transistor can realize a polysilicon thin film transistor with a minimum channel length by stacking a first doped part, a channel part and a second doped part; and the second doped part is arranged in a via of an insulating layer, the second doped part is connected to the channel part through the via and partially contacts the channel part, the contact area of the second doped part and the channel part is reduced, the ions diffused to the channel area are reduced, the device stability of the thin film transistor is improved, the projection area of the thin film transistor is reduced, the aperture ratio of the display panel is improved, and the development of high-resolution and high-refresh-rate products and even the realization of the function of part of chips are facilitated.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a vertically structured thin-film transistor and electronic device. Background Technology

[0002] With the development of display technology, existing display devices need to reduce the size and area of ​​thin-film transistors (TFTs) to achieve narrow bezels, high aperture ratios, high brightness, and high resolution. However, polycrystalline silicon TFTs have relatively low mobility. To improve the mobility of TFTs, the channel length needs to be reduced, which means increasing the area occupied by the active layer. Furthermore, the channel length is limited by process constraints, resulting in a limited reduction in the miniaturization of TFTs. This makes it impossible for display devices to simultaneously achieve both high mobility and small size. To address this issue, existing display devices have designed a vertical TFT structure. By using the thickness of the active layer as the channel length, this design is not limited by process constraints and can achieve TFTs with extremely small channel lengths. However, during the fabrication of vertical TFT structures, because the ohmic contact regions are located on the top and bottom sides of the channel region, ions from the ohmic contact regions easily diffuse into the channel, leading to decreased device stability.

[0003] Therefore, existing vertical thin-film transistors have the technical problem of poor stability due to the easy diffusion of ions from the ohmic contact region into the channel. Summary of the Invention

[0004] This application provides a vertically structured thin-film transistor and electronic device to alleviate the technical problem that ions in the ohmic contact region of existing vertically structured thin-film transistors easily diffuse into the channel, resulting in poor stability of the thin-film transistor.

[0005] This application provides a vertically structured thin-film transistor, which includes:

[0006] Insulating substrate;

[0007] An active layer is disposed on one side of the insulating substrate, and the active layer includes a first doped portion, a channel portion and a second doped portion disposed in a stacked manner;

[0008] An insulating layer is disposed on the side of the channel portion away from the first doped portion, and the insulating layer includes vias;

[0009] The second doped portion is disposed within the via, and the second doped portion is connected to and partially in contact with the channel portion through the via.

[0010] In some embodiments, the vertically structured thin-film transistor further includes a source-drain layer disposed on the side of the insulating layer away from the active layer. The source-drain layer includes a first electrode and a second electrode. The via includes a first via and a second via. The first electrode is electrically connected to the first doped portion through the first via. The second doped portion is disposed in the second via, and the second electrode is in contact with the second doped portion.

[0011] In some embodiments, the material of the first doped portion includes N-type doped polycrystalline silicon, and the material of the second doped portion includes N-type doped amorphous silicon.

[0012] In some embodiments, the dopant concentration of the first doped portion on the side closer to the insulating substrate is greater than the dopant concentration of the first doped portion on the side closer to the channel portion.

[0013] In some embodiments, the first doped portion includes a first heavily doped portion and a first lightly doped portion, wherein the dopant concentration of the first heavily doped portion is greater than the dopant concentration of the first lightly doped portion, and the first lightly doped portion is disposed between the first heavily doped portion and the channel portion.

[0014] In some embodiments, the first lightly doped portion includes a third via, the first electrode is electrically connected to the first heavily doped portion through the first via and the third via, and the first electrode is electrically connected to the first lightly doped portion through the first via and the third via.

[0015] In some embodiments, the width of the first heavily doped portion is greater than the width of the first lightly doped portion, and the first electrode is electrically connected to the first heavily doped portion through the first via.

[0016] In some embodiments, the material of the first doped portion includes N-type doped amorphous silicon.

[0017] In some embodiments, the dopant concentration of the second doped portion on the side near the source / drain layer is greater than the dopant concentration of the second doped portion on the side near the channel portion.

[0018] In some embodiments, the second doped portion includes a second heavily doped portion and a second lightly doped portion, the doping ion concentration of the second heavily doped portion is greater than the doping ion concentration of the second lightly doped portion, the second lightly doped portion is disposed between the second heavily doped portion and the channel portion, and the second lightly doped portion is in contact with the side portion of the second heavily doped portion.

[0019] In some embodiments, the ratio of the thickness of the second heavily doped portion to the thickness of the second lightly doped portion is greater than or equal to 5.

[0020] In some embodiments, the second electrode extends into the second via, and the second heavily doped portion contacts the side of the second electrode.

[0021] In some embodiments, the second doped portion includes a first portion disposed in the insulating layer away from the channel portion and a second portion located within the second via, wherein the first portion is connected to the second portion.

[0022] In some embodiments, the aperture of the second via ranges from 2 micrometers to 4 micrometers.

[0023] In some embodiments, the width of the first doped portion is greater than the width of the channel portion.

[0024] In some embodiments, the thin-film transistor with the vertical structure further includes a gate located on the sidewall of the insulating layer, the orthogonal projection of the gate onto the sidewall of the insulating layer covering the channel portion.

[0025] In some embodiments, the vertically structured thin-film transistor further includes:

[0026] A light-shielding layer is disposed between the insulating substrate and the active layer, wherein the orthogonal projection of the light-shielding layer on the insulating substrate at least covers the orthogonal projection of the second doped portion on the insulating substrate.

[0027] In some embodiments, the gate is connected to the light-shielding layer.

[0028] Meanwhile, this application provides an electronic device including a thin-film transistor with a vertical structure as described in any of the above embodiments.

[0029] Beneficial Effects: This application provides a vertically structured thin-film transistor and electronic device. The vertically structured thin-film transistor includes an insulating substrate, an active layer, and an insulating layer. The active layer is disposed on one side of the insulating substrate and includes a first doped portion, a channel portion, and a second doped portion stacked together. The insulating layer is disposed on the side of the channel portion away from the first doped portion and includes a via. The second doped portion is disposed within the via and is connected to and partially in contact with the channel portion through the via. By stacking the first doped portion, the channel portion, and the second doped portion, this application can realize a polycrystalline silicon thin-film transistor with an extremely small channel length. By disposing the second doped portion within the via of the insulating layer, and connecting and partially contacting the channel portion through the via, the contact area between the second doped portion and the channel portion can be reduced. This reduces the number of ions diffusing into the channel region, improves the device stability of the thin-film transistor, and reduces the projected area of ​​the thin-film transistor, increasing the aperture ratio of the display panel. This is beneficial for developing high-resolution and high-refresh-rate products and even realizing some chip functions. Attached Figure Description

[0030] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0031] Figure 1 This is a schematic diagram of the structure of an existing display device.

[0032] Figure 2 This is a first schematic diagram of a vertically structured thin-film transistor provided in an embodiment of this application.

[0033] Figure 3 for Figure 2 A1-A2 cross-sectional view of the vertical structure of the thin-film transistor.

[0034] Figure 4 This is a second schematic diagram of a vertically structured thin-film transistor provided in an embodiment of this application.

[0035] Figure 5 This is a third schematic diagram of a vertically structured thin-film transistor provided in an embodiment of this application.

[0036] Figure 6 This is a first schematic diagram of the vertical thin-film transistor corresponding to each step in the fabrication method of the vertical thin-film transistor provided in the embodiments of this application.

[0037] Figure 7 This is a second schematic diagram of the vertical thin-film transistor corresponding to each step in the fabrication method of the vertical thin-film transistor provided in the embodiments of this application.

[0038] Figure 8 This is a third schematic diagram of the vertical thin-film transistor corresponding to each step in the fabrication method of the vertical thin-film transistor provided in the embodiments of this application. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0040] like Figure 1 As shown, a conventional display device includes a substrate 11, a light-shielding layer 12, a buffer layer 13, an active layer 14, a gate insulating layer 15, a gate layer 16, an interlayer insulating layer 17, a source / drain layer 18, a planarization layer 19, a first electrode layer 22, a passivation layer 21, and a second electrode layer 23. Figure 1As can be seen, the active layer 14 includes an ohmic contact region 141 and a channel region 142. The ohmic contact region 141 includes a heavily doped region 141a and a lightly doped region 141b. Each region of the active layer is arranged horizontally, occupying a large area. Furthermore, due to limitations in exposure and etching precision, the channel length of the active layer is relatively small, resulting in low mobility of the thin-film transistor 10. To improve the mobility of thin-film transistors, existing display devices design vertically structured thin-film transistors, where the channel length of the active layer is equal to the thickness of the active layer, enabling the realization of thin-film transistors with extremely small channel lengths. However, during the fabrication of vertically structured thin-film transistors, because the ohmic contact regions are located on the upper and lower sides of the channel region, ions from the ohmic contact regions easily diffuse into the channel, causing a decrease in device stability. Therefore, existing vertically structured thin-film transistors suffer from the technical problem of poor stability due to the easy diffusion of ions from the ohmic contact regions into the channel.

[0041] This application provides a vertically structured thin-film transistor and electronic device to address the aforementioned technical problems.

[0042] like Figure 2 , Figure 3 As shown, this application embodiment provides a vertically structured thin-film transistor 3, which includes:

[0043] Insulating substrate 31;

[0044] An active layer 34 is disposed on one side of the insulating substrate 31. The active layer 34 includes a first doped portion 341, a channel portion 342, and a second doped portion 343 stacked together.

[0045] An insulating layer 35 is disposed on the side of the channel portion 342 away from the first doped portion 341, and the insulating layer 35 includes a via 37;

[0046] The second doped portion 343 is disposed within the via 37, and the second doped portion 343 is connected to and partially in contact with the channel portion 342 through the via 37.

[0047] This application provides a vertically structured thin-film transistor (TFT). By stacking a first doped portion, a channel portion, and a second doped portion, a polycrystalline silicon TFT with an extremely small channel length can be realized. By placing the second doped portion within a via in the insulating layer, allowing the second doped portion to connect and partially contact the channel portion through the via, the contact area between the second doped portion and the channel portion can be reduced. This reduces the number of ions diffusing into the channel region, improves the device stability of the TFT, and reduces the projected area of ​​the TFT, thereby increasing the aperture ratio of the display panel. This is beneficial for developing high-resolution and high-refresh-rate products and even realizing some chip functions.

[0048] It should be noted that, Figure 3 for Figure 2 A cross-sectional view of the vertical structure of the thin-film transistor in the diagram along line A1-A2. Figure 3 In this process, because the second doped portion is located within the via, therefore, in Figure 3 The vias are not shown in the diagram; the location of the via is indicated by the number 37.

[0049] In one embodiment, such as Figure 3 As shown, the vertically structured thin-film transistor 3 further includes a source-drain layer 38, which is disposed on the side of the insulating layer 35 away from the active layer 34. The source-drain layer 38 includes a first electrode 381 and a second electrode 382. The via 37 includes a first via 371 and a second via 372. The first electrode 381 is electrically connected to the first doped portion 341 through the first via 371. The second doped portion 343 is disposed in the second via 372, and the second electrode 382 is in contact with the second doped portion 343.

[0050] In this embodiment, by placing the second doped portion within a via to reduce the contact area between the second doped portion and the channel, thereby reducing the number of ions diffusing into the channel, to achieve normal operation of the thin-film transistor, when connecting the second doped portion to the second electrode of the source / drain layer, the second electrode can be directly placed on the second via, allowing direct contact between the second electrode and the second doped portion for electrical connection, eliminating the need for a via to connect to the second doped portion. For the first doped portion, since it is located below the channel, a first via can be formed by etching the insulating layer, allowing the source / drain layer to connect to the first doped portion through the first via of the insulating layer, thus achieving connection between the source / drain layer and the active layer. Signal input through the first and second electrodes enables normal operation of the thin-film transistor. Furthermore, in this structure, the second electrode is directly connected to the second doped portion, eliminating the need for additional vias connecting the second doped portion and the second electrode, reducing process steps.

[0051] This invention addresses the technical problem that poor polysilicon crystallization within vias leads to poor thin-film transistor (TFT) performance. In one embodiment, the first doped portion is made of N-type doped polysilicon, and the second doped portion is made of N-type doped amorphous silicon. By using N-type doped polysilicon for the first doped portion, better conductivity between the first doped portion and the first electrode is achieved. Conversely, using N-type doped amorphous silicon for the second doped portion avoids the performance degradation caused by poor polysilicon crystallization when the second doped portion is located within the via, thereby improving TFT performance.

[0052] To address the issue of increased leakage current due to smaller channel size in the active layer, one embodiment involves a higher dopant concentration on the side of the first doped portion closer to the insulating substrate compared to the side closer to the channel. By ensuring a higher dopant concentration on the side of the first doped portion closer to the insulating substrate compared to the side closer to the channel, the first doped portion exhibits a stacked structure with a heavily doped bottom layer and a lightly doped top layer. Electrons must pass through both the heavily doped and lightly doped regions during movement, thus reducing the leakage current of the thin-film transistor.

[0053] In one embodiment, such as Figure 4 As shown, the first doped portion 341 includes a first heavily doped portion 341a and a first lightly doped portion 341b. The dopant concentration of the first heavily doped portion 341a is greater than that of the first lightly doped portion 341b. The first lightly doped portion 341b is disposed between the first heavily doped portion 341a and the channel portion 342. By making the first doped portion include a first heavily doped portion and a first lightly doped portion, and making the dopant concentration of the first heavily doped portion greater than that of the first lightly doped portion, a stacked structure of the first heavily doped portion and the first lightly doped portion can be formed. This forces electrons to pass through the first heavily doped portion and the first lightly doped portion when moving, reducing the leakage current of the thin-film transistor.

[0054] In one embodiment, such as Figure 4 As shown, the first lightly doped portion 341b includes a third via 373. The first electrode 381 is electrically connected to the first heavily doped portion 341a through the first via 371 and the third via 373, and the first electrode 381 is also electrically connected to the first lightly doped portion 341b through the first via 371 and the third via 373. By forming a third via in the first lightly doped portion, the first electrode can be connected to the first heavily doped portion through the first via and the third via, allowing electrons to move along the first heavily doped portion to the first lightly doped portion, thereby reducing the leakage current of the thin-film transistor and improving its performance.

[0055] Specifically, the first electrode is electrically connected to the first lightly doped part through the first via and the third via, and at the same time, the first electrode is electrically connected to the first heavily doped part through the first via and the third via. Since the impedance of the first heavily doped part is less than that of the first lightly doped part, the electrons will still flow from the first heavily doped part to the first lightly doped part, thus enabling the thin-film transistor to conduct, reducing the leakage current of the thin-film transistor, and improving the performance of the thin-film transistor.

[0056] Specifically, by forming a third via on the first lightly doped portion, and by integrating the first and third vias, the insulating layer and the first lightly doped portion can be etched and formed in the same process when forming the first and third vias, thereby reducing the number of process steps in the thin-film transistor and improving the fabrication efficiency of the thin-film transistor.

[0057] To address the problem that the connection between the first electrode and the first lightly doped portion may cause electrons to move from the first lightly doped portion, resulting in leakage current and poor performance of the thin-film transistor device, in one embodiment, such as... Figure 5 As shown, the width L1 of the first heavily doped portion 341a is greater than the width L2 of the first lightly doped portion 341b. The first electrode 381 is electrically connected to the first heavily doped portion 341a through the first via 371. By making the width of the first heavily doped portion greater than the width of the first lightly doped portion, the first electrode can be directly connected to the first heavily doped portion through the first via, avoiding an increase in leakage current of the thin-film transistor caused by the connection between the first electrode and the first lightly doped portion. This allows electrons to pass through both the first lightly doped portion and the first heavily doped portion, thereby reducing the leakage current of the thin-film transistor and improving the performance of the thin-film transistor device.

[0058] Specifically, such as Figure 5 As shown, in the region where the first heavily doped portion 341a extends beyond the first lightly doped portion 341b, the first electrode 381 is electrically connected to the first heavily doped portion 341a through the first via 371. That is, when the first electrode is set, if the first electrode is electrically connected to the first heavily doped portion in the region where the first heavily doped portion extends beyond the first lightly doped portion, the first electrode and the first lightly doped portion will not come into contact, thus avoiding an increase in the leakage current of the thin-film transistor and improving the performance of the thin-film transistor.

[0059] To address the challenge of forming a structure with high doping concentration at the bottom layer and low doping concentration at the surface layer along the thickness direction in polycrystalline silicon, one embodiment uses N-type doped amorphous silicon as the material for the first doped layer. By employing N-type doped amorphous silicon as the material for the first doped layer, the first doped layer can be formed by chemical vapor deposition during the formation of the first lightly doped layer and the second lightly doped layer. Then, by controlling the proportion of phosphine, a structure with high doping concentration at the bottom layer and low doping concentration at the surface layer is formed. This allows electrons to pass sequentially through the first heavily doped layer and the first lightly doped layer, reducing leakage current and improving the performance of the thin-film transistor.

[0060] In one embodiment, the dopant ion concentration ratio of the first heavily doped portion to the first lightly doped portion is 10:1.

[0061] To address the issue of increased leakage current due to smaller channel size in the active layer, one embodiment involves a higher dopant concentration in the second doped portion near the source / drain layer compared to the side near the channel. By ensuring a higher dopant concentration near the source / drain layer compared to the side near the channel, the second doped portion exhibits a stacked structure with a lightly doped bottom layer and a heavily doped top layer. Electrons must pass through both the heavily doped and lightly doped regions during movement, thus reducing the leakage current of the thin-film transistor.

[0062] In one embodiment, such as Figure 4 As shown, the second doped portion 343 includes a second heavily doped portion 343a and a second lightly doped portion 343b. The dopant concentration of the second heavily doped portion 343a is greater than that of the second lightly doped portion 343b. The second lightly doped portion 343b is disposed between the second heavily doped portion 343a and the channel portion 342, and the second lightly doped portion 343b is in contact with the side portion of the second heavily doped portion 343a. By making the second doped portion include a second heavily doped portion and a second lightly doped portion, with the second heavily doped portion electrically connected to the first electrode and the second lightly doped portion located between the second heavily doped portion and the channel portion, a stacked structure of the second heavily doped portion and the second lightly doped portion can be formed. This forces electrons to pass through both the second heavily doped portion and the second lightly doped portion when moving, reducing the leakage current of the thin-film transistor. Furthermore, by making the side portion of the second lightly doped portion contact the side portion of the second heavily doped portion, the contact area between the second lightly doped portion and the second heavily doped portion is increased, improving the performance of the thin-film transistor.

[0063] In one embodiment, such as Figure 4 As shown, the ratio of the thickness h1 of the second heavily doped portion 343a to the thickness h2 of the second lightly doped portion 343b is greater than or equal to 5. By making the ratio of the thickness of the second heavily doped portion to the thickness of the second lightly doped portion greater than or equal to 5, the thickness of the second heavily doped portion is made larger, so that the active layer can be turned on when realizing the function of the thin-film transistor, enabling the thin-film transistor to work normally.

[0064] Specifically, the distance between the bottom and top of the first heavily doped region is taken as the thickness of the first heavily doped region, and the distance between the bottom of the first heavily doped region and the bottom of the first lightly doped region is taken as the thickness of the first lightly doped region.

[0065] In one embodiment, such as Figure 4As shown, the second electrode 382 extends into the second via 372, and the second heavily doped portion 343a contacts the side of the second electrode 382. By extending the second electrode into the second via, the contact area between the second heavily doped portion and the second electrode is increased, thereby improving the conductivity of the second electrode and the second heavily doped portion, avoiding poor contact between the second heavily doped portion and the second electrode, and improving the performance of the thin-film transistor.

[0066] In one embodiment, the dopant ion concentration ratio of the second heavily doped portion to the second lightly doped portion is 10:1.

[0067] Specifically, the above embodiments are described with the example of the first doped portion including a first lightly doped portion and a first heavily doped portion, and the second doped portion including a second lightly doped portion and a second heavily doped portion. However, the embodiments of this application are not limited to this. When the first doped portion includes a first lightly doped portion and a first heavily doped portion, the second doped portion may also include a second lightly doped portion and a second heavily doped portion. For the design of the first lightly doped portion, the first heavily doped portion, the second lightly doped portion and the second heavily doped portion, please refer to the above embodiments, which will not be repeated here.

[0068] In one embodiment, the second doped portion includes a first portion disposed on the insulating layer away from the channel portion and a second portion located within the second via, the first portion and the second portion being connected. When connecting the second electrode to the second doped portion, the second doped portion can also be disposed outside the second via, with the second doped portion including the first portion on the insulating layer and the second portion located within the second via. This allows the second electrode to contact the first portion, achieving connection between the second electrode and the second doped portion, and increases the contact area between the second doped portion and the second electrode, preventing poor contact, increasing the area of ​​the second doped portion, and improving the performance of the thin-film transistor.

[0069] Specifically, when forming the second doped portion, amorphous silicon can be deposited into the via, allowing the amorphous silicon to extend from the insulating layer into the via. The amorphous silicon can then be etched to form the first portion and the second portion, enabling the first portion to be connected to the second electrode and thus enabling the thin-film transistor to operate normally.

[0070] In one embodiment, such as Figure 3 As shown, the aperture d of the second via 372 ranges from 2 micrometers to 4 micrometers. If the aperture of the second via is too large, ions will diffuse into the channel portion; if the aperture is too small, the second doped portion will have poor contact with the channel portion and the second electrode. By making the aperture range of the second via 2 micrometers to 4 micrometers, the second doped portion in the second via can have good contact with the channel portion and the second electrode, and the second via will not be too large, thus preventing ion diffusion into the channel portion.

[0071] Specifically, such as Figure 3 As shown, when the cross-section of the second via is an inverted trapezoid, the width of the lower base of the inverted trapezoid is used as the diameter of the second via.

[0072] In one embodiment, the width of the first doped portion is greater than the width of the channel portion. By making the width of the first doped portion greater than the width of the channel portion, when the first electrode is connected to the first doped portion, the first electrode can be connected to the portion of the first doped portion that extends beyond the channel portion, thereby realizing the connection between the first electrode and the first doped portion.

[0073] In one embodiment, such as Figure 3 As shown, the vertically structured thin-film transistor 3 also includes a gate 36 located on the sidewall of the insulating layer 35. The orthogonal projection of the gate 36 onto the sidewall of the insulating layer 35 covers the channel portion 342. By placing the gate on the sidewall of the insulating layer, the gate is prevented from affecting the setting of the second doped portion. Furthermore, the orthogonal projection of the gate onto the sidewall of the insulating layer covers the channel portion, allowing the gate to control the channel portion and realize the normal function of the thin-film transistor.

[0074] This addresses the technical problem that the performance of the active layer deteriorates when exposed to light. In one embodiment, such as... Figure 3 As shown, the vertically structured thin-film transistor 3 further includes:

[0075] A light-shielding layer 32 is disposed between the insulating substrate 31 and the active layer 34. The orthographic projection of the light-shielding layer 32 on the insulating substrate 31 at least covers the orthographic projection of the second doped portion 343 on the insulating substrate 31. By ensuring that the orthographic projection of the light-shielding layer on the insulating substrate at least covers the orthographic projection of the second doped portion on the insulating substrate, the light-shielding layer can prevent external light from shining into the channel portion, thus preventing the active layer from being exposed to light and causing performance degradation.

[0076] To address the issue of insufficient control capability when the gate is positioned on the insulating layer side, in one embodiment, the gate is connected to the light-shielding layer. By connecting the gate to the light-shielding layer, semi-enclosure of the active layer can be achieved, improving the gate's control capability.

[0077] In one embodiment, the material of the light-shielding layer includes molybdenum, titanium, tungsten, or a stack thereof.

[0078] In one embodiment, such as Figure 3 As shown, the vertically structured thin-film transistor 3 also includes a buffer layer 33.

[0079] In one embodiment, the material of the buffer layer includes silicon oxide, silicon nitride, silicon oxynitride, or a stack thereof.

[0080] In one embodiment, the insulating layer 35 includes a gate insulating layer 351 and an interlayer insulating layer 352.

[0081] In one embodiment, the material of the gate insulating layer includes silicon oxide, silicon nitride, silicon oxynitride, or a stack thereof.

[0082] In one embodiment, the thickness of the gate insulating layer ranges from 30 nanometers to 200 nanometers.

[0083] In one embodiment, the material of the gate layer includes molybdenum, titanium, tungsten, or a stack thereof.

[0084] In one embodiment, the thickness of the gate layer ranges from 0.1 micrometers to 1 micrometer.

[0085] In one embodiment, the interlayer insulating layer is made of a stack of silicon oxide and silicon nitride.

[0086] In one embodiment, the source and drain layers are made of molybdenum, titanium, tungsten, aluminum, copper, or a stack thereof.

[0087] Meanwhile, this application provides a method for fabricating a vertically oriented thin-film transistor, which is fabricated as described in any of the above embodiments. The method for fabricating the vertically oriented thin-film transistor includes:

[0088] An insulating substrate is provided, and a light-shielding layer is formed on the insulating substrate; the structure of the vertical thin-film transistor corresponding to this step is as follows. Figure 6 As shown in (a) in the middle;

[0089] Specifically, metal can be deposited on an insulating substrate and then exposed and etched to form a light-shielding layer.

[0090] A buffer layer and a first doped layer are deposited on the light-shielding layer; the structure of the corresponding vertical thin-film transistor is as follows. Figure 6 As shown in (b);

[0091] Specifically, when forming the first doped part on the buffer layer, amorphous silicon can be deposited by chemical vapor deposition, hydrogen silicide and hydrogen gas are introduced during film formation, and then the amorphous silicon is transformed into polycrystalline silicon by laser annealing. Then, the polycrystalline silicon is patterned by exposure and etching, and finally phosphorus ion doping is performed by ion implantation to obtain the first doped part.

[0092] Specifically, the thickness of the first doped portion ranges from 10 nanometers to 100 nanometers.

[0093] Specifically, when the first doped region includes a first lightly doped region and a first heavily doped region, amorphous silicon can be deposited on a buffer layer by chemical vapor deposition. During the film formation process, hydrogen silicide, hydrogen, and phosphine are sequentially introduced. The film formation process requires two steps: a large flow rate of phosphine in the first step and a small flow rate in the second step. The first doped region is then formed by exposure and etching.

[0094] Specifically, since phosphorus ions are present during the amorphous silicon film formation process, no additional ion implantation is required.

[0095] Specifically, the thickness of the first doped portion ranges from 10 nanometers to 300 nanometers.

[0096] A channel portion is formed on the first doped portion; the structure of the vertical thin-film transistor corresponding to this step is as follows: Figure 6 As shown in (c);

[0097] Specifically, an amorphous silicon layer is deposited on the first doped portion, and the amorphous silicon is transformed into polycrystalline silicon by laser annealing. Then, the polycrystalline silicon is patterned to form the channel portion by exposure and etching.

[0098] Specifically, the thickness of the channel ranges from 10 nanometers to 100 nanometers.

[0099] A gate insulating layer and a gate layer are formed on the channel portion; the structure of the corresponding vertical thin-film transistor is as follows: Figure 6 As shown in (d);

[0100] An interlayer insulating layer is formed on the gate insulating layer, and the interlayer insulating layer is etched to obtain a second via; the structure of the vertical thin-film transistor corresponding to this step is as follows. Figure 7 As shown in (a) in the middle;

[0101] A second doped portion is formed within the second via; the structure of the corresponding vertical thin-film transistor is as follows: Figure 7 As shown in (b);

[0102] Specifically, when forming the second doped portion on the buffer layer, amorphous silicon can be deposited by chemical vapor deposition, with hydrogen silicide, hydrogen gas, and phosphine introduced during the deposition process. Then, the amorphous silicon is patterned by exposure and etching to obtain the second doped portion. Since phosphorus ions are present during the amorphous silicon film deposition process, no additional ion implantation is required.

[0103] Specifically, when the second doped region includes a second lightly doped region and a second heavily doped region, amorphous silicon can be deposited on a buffer layer using chemical vapor deposition. During film formation, hydrogen silicide, hydrogen, and phosphine are sequentially introduced, requiring a two-step film formation process. In the first step, the phosphine flow rate is high, and in the second step, the phosphine flow rate is low. Then, the second doped region is formed through exposure and etching. Since phosphorus ions are present during the amorphous silicon film formation process, no additional ion implantation is required.

[0104] Specifically, the thickness of the second doped portion ranges from 300 nanometers to 1000 nanometers.

[0105] The first via is obtained by etching the interlayer insulating layer; the structure of the corresponding vertical thin-film transistor is as follows. Figure 8 As shown;

[0106] A source / drain layer is formed on the interlayer insulating layer; the structure of the corresponding vertical thin-film transistor is as follows: Figure 3 As shown.

[0107] This application provides a method for fabricating a vertically structured thin-film transistor (TFT). The TFT fabricated using this method achieves a polycrystalline silicon TFT with an extremely small channel length by stacking a first doped portion, a channel portion, and a second doped portion. Furthermore, by placing the second doped portion within a via in the insulating layer, allowing it to connect and partially contact the channel portion through the via, the contact area between the second doped portion and the channel portion is reduced. This reduces the number of ions diffusing into the channel region, improves the device stability of the TFT, and reduces the projected area of ​​the TFT, thereby increasing the aperture ratio of the display panel. This is beneficial for developing high-resolution and high-refresh-rate products and even realizing some chip functions.

[0108] Meanwhile, this application provides an electronic device including a thin-film transistor with a vertical structure as described in any of the above embodiments.

[0109] As can be seen from the above embodiments:

[0110] This application provides a vertically structured thin-film transistor and electronic device. The vertically structured thin-film transistor includes an insulating substrate, an active layer, and an insulating layer. The active layer is disposed on one side of the insulating substrate and includes a first doped portion, a channel portion, and a second doped portion stacked together. The insulating layer is disposed on the side of the channel portion away from the first doped portion and includes a via. The second doped portion is disposed within the via and is connected to and partially in contact with the channel portion through the via. By stacking the first doped portion, the channel portion, and the second doped portion, this application can realize a polycrystalline silicon thin-film transistor with an extremely small channel length. By disposing the second doped portion within the via of the insulating layer, and connecting and partially contacting the channel portion through the via, the contact area between the second doped portion and the channel portion can be reduced, thus reducing ions diffusing into the channel region, improving the device stability of the thin-film transistor, and reducing the projected area of ​​the thin-film transistor, thereby increasing the aperture ratio of the display panel. This is beneficial for developing high-resolution and high-refresh-rate products, and even realizing some chip functions.

[0111] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0112] The foregoing has provided a detailed description of a vertically structured thin-film transistor and electronic device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A vertically oriented thin-film transistor, characterized in that, include: Insulating substrate; An active layer is disposed on one side of the insulating substrate, and the active layer includes a first doped portion, a channel portion and a second doped portion disposed in a stacked manner; An insulating layer is disposed on the side of the channel portion away from the first doped portion, and the insulating layer includes vias; The second doped portion is disposed within the via, and the second doped portion is connected to and partially in contact with the channel portion through the via; The projection of the via on the insulating substrate overlaps with the projection of the channel on the insulating substrate, the projection of the second doped portion on the insulating substrate overlaps with the projection of the channel on the insulating substrate, and the second doped portion and the channel portion are in contact on the surface of the channel portion; the contact area between the second doped portion and the channel portion is smaller than the surface area of ​​the channel portion.

2. The thin-film transistor with a vertical structure as described in claim 1, characterized in that, The vertical thin-film transistor further includes a source-drain layer disposed on the side of the insulating layer away from the active layer. The source-drain layer includes a first electrode and a second electrode. The via includes a first via and a second via. The first electrode is electrically connected to the first doped portion through the first via. The second doped portion is disposed in the second via. The second electrode is in contact with the second doped portion.

3. The thin-film transistor with a vertical structure as described in claim 2, characterized in that, The material of the first doped portion includes N-type doped polycrystalline silicon, and the material of the second doped portion includes N-type doped amorphous silicon.

4. The thin-film transistor with a vertical structure as described in claim 2, characterized in that, The dopant concentration of the first doped portion on the side closer to the insulating substrate is greater than the dopant concentration of the first doped portion on the side closer to the channel portion.

5. The thin-film transistor with a vertical structure as described in claim 2, characterized in that, The first doped portion includes a first heavily doped portion and a first lightly doped portion. The dopant concentration of the first heavily doped portion is greater than the dopant concentration of the first lightly doped portion. The first lightly doped portion is disposed between the first heavily doped portion and the channel portion.

6. The thin-film transistor with a vertical structure as described in claim 5, characterized in that, The first lightly doped portion includes a third via, the first electrode is electrically connected to the first heavily doped portion through the first via and the third via, and the first electrode is electrically connected to the first lightly doped portion through the first via and the third via.

7. The thin-film transistor with a vertical structure as described in claim 5, characterized in that, The width of the first heavily doped portion is greater than the width of the first lightly doped portion, and the first electrode is electrically connected to the first heavily doped portion through the first via.

8. The thin-film transistor with a vertical structure as described in claim 5, characterized in that, The material of the first doped portion includes N-type doped amorphous silicon.

9. The thin-film transistor with a vertical structure as described in claim 2, characterized in that, The dopant concentration of the second doped portion on the side closer to the source / drain layer is greater than the dopant concentration of the second doped portion on the side closer to the channel portion.

10. The thin-film transistor with a vertical structure as described in claim 2, characterized in that, The second doped portion includes a second heavily doped portion and a second lightly doped portion. The dopant concentration of the second heavily doped portion is greater than that of the second lightly doped portion. The second lightly doped portion is disposed between the second heavily doped portion and the channel portion, and the second lightly doped portion is in contact with the side portion of the second heavily doped portion.

11. The thin-film transistor with a vertical structure as described in claim 10, characterized in that, The ratio of the thickness of the second heavily doped portion to the thickness of the second lightly doped portion is greater than or equal to 5.

12. The thin-film transistor with a vertical structure as described in claim 10, characterized in that, The second electrode extends into the second via, and the second heavily doped portion contacts the side of the second electrode.

13. The thin-film transistor with a vertical structure as described in claim 2, characterized in that, The second doped portion includes a first portion disposed in the insulating layer away from the channel portion and a second portion located within the second via, wherein the first portion is connected to the second portion.

14. The thin-film transistor with a vertical structure as described in claim 2, characterized in that, The aperture of the second via ranges from 2 micrometers to 4 micrometers.

15. The thin-film transistor with a vertical structure as described in claim 1, characterized in that, The width of the first doped portion is greater than the width of the channel portion.

16. The thin-film transistor with a vertical structure as described in claim 1, characterized in that, The vertically structured thin-film transistor also includes a gate located on the sidewall of the insulating layer, the orthogonal projection of the gate onto the sidewall of the insulating layer covering the channel portion.

17. The thin-film transistor with a vertical structure as described in claim 16, characterized in that, The vertically structured thin-film transistor also includes: A light-shielding layer is disposed between the insulating substrate and the active layer, wherein the orthogonal projection of the light-shielding layer on the insulating substrate at least covers the orthogonal projection of the second doped portion on the insulating substrate.

18. The thin-film transistor with a vertical structure as described in claim 17, characterized in that, The gate is connected to the light-shielding layer.

19. An electronic device, characterized in that, The electronic device includes a thin-film transistor with a vertical structure as described in any one of claims 1 to 18.

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