Large panel level fan-out packaging method and large panel level fan-out packaging structure

Abstract

A large panel level fan-out packaging method and a large panel level fan-out packaging structure. The large panel level fan-out packaging method comprises: providing a temporary carrier (1) and a plurality of dies (3), pasting the plurality of dies (3) onto the temporary carrier (1), and cutting same into blocks to form cut frame dies (A); carrying out surface treatment on the dies (3) on each cut frame die (A), and arranging and tiling the plurality of cut frame dies (A); manufacturing a frame (4), and attaching the frame (4) to the tiled temporary carrier (1), wherein the frame (4) covers the gap between two adjacent tiled cut frame dies (A), and the plurality of dies (3) are all exposed out of the frame (4); carrying out plastic package on the plurality of dies (3), and separating the temporary carrier (1) to obtain a die plastic package; and electrically leading out I / O ports of the plurality of dies (3) from both sides of the die plastic package.

Description

Large-board-level fan-out packaging method and large-board-level fan-out packaging structure

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 28, 2023, with application number 202310786144.3. The entire contents of the above application are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of integrated circuit packaging, for example, to a large-board-level fan-out packaging method and a large-board-level fan-out packaging structure. Background Art

[0003] At present, large-scale fan-out packaging usually uses a printed circuit board (PCB) as the substrate (redistribution layer first (RDL-First) process), attaches the chip on the PCB and then plastic-encapsulates it, and then leads out the input / output (I / O) through a single-sided circuit build-up layer; or uses a detachable temporary carrier as the substrate, adopts a die-first process, first attaches the chip on the detachable temporary carrier and then plastic-encapsulates it, and then detaches the temporary carrier and leads out the chip's I / O through an RDL build-up layer.

[0004] During the packaging process, regardless of whether the chip only has I / O on a single side or both sides require I / O, or whether multiple layers of circuits are required, the processes in related technologies have shortcomings such as board warping, long single-sided RDL build-up processes, and a high risk of fragmentation when separating the temporary carrier or during subsequent tape-out. These shortcomings significantly reduce production efficiency, lower yields, and increase costs.

[0005] Summary of the Invention

[0006] The present application provides a large-board-level fan-out packaging method and a large-board-level fan-out packaging structure manufactured by the method. Based on the Die-First process, it improves board warping, shortens the production process, and avoids the generation of fragments during the wafer production process. After separating the temporary carrier board, it is no longer necessary to apply tape or film to fix or improve the strength of the plastic package body, thereby achieving the purpose of small warping, no fragments, no residual glue, fewer steps, improved production efficiency and yield, and reduced costs.

[0007] This application adopts the following technical solutions:

[0008] A large-board-level fan-out packaging method is provided, comprising the following steps:

[0009] Providing a temporary carrier and a plurality of chips, attaching the plurality of chips to the temporary carrier and dicing the chips to form a plurality of cut-frame chips;

[0010] Performing surface treatment on each chip on the cut frame, and then arranging and assembling the plurality of cut frame chips;

[0011] Making a frame according to the layout, and then attaching the frame to the temporary carrier after the frame is assembled, the frame covers the gap between two adjacent cut-frame chips after the frame is assembled, and the multiple chips are exposed on the frame;

[0012] Performing a plastic packaging process on the plurality of chips, and then separating the temporary carrier to obtain a chip plastic packaging body;

[0013] The I / O ports of the multiple chips are electrically led out from both sides of the chip plastic package.

[0014] As an optional solution for the large-scale fan-out packaging method, providing a temporary carrier and a plurality of chips, attaching the plurality of chips to the temporary carrier and dicing the chips to form a plurality of cut-frame chips, includes:

[0015] Providing a temporary carrier plate, and pressing bonding glue on one side of the temporary carrier plate along the thickness direction;

[0016] Providing a plurality of chips, and attaching the plurality of chips to the surface of the bonding adhesive away from the temporary carrier;

[0017] The temporary carrier board with the multiple chips attached thereto is cut into multiple framed chips.

[0018] As an optional solution for the large-board-level fan-out packaging method, the frame is a semi-transparent BT board that does not contain copper.

[0019] As an optional solution for the large-board fan-out packaging method, the I / O ports of the multiple chips are electrically led out from both sides of the chip plastic package, including:

[0020] Performing a hole-opening process on the chip plastic package to form a plurality of first through holes and blind holes for exposing the I / O ports of the plurality of chips, wherein the first through holes penetrate the chip plastic package;

[0021] Fabricating first conductive pillars in the plurality of first through holes and the plurality of blind holes, and fabricating first redistribution layers electrically connected to the first conductive pillars on opposite sides of the chip plastic package to lead out I / O ports of the plurality of chips;

[0022] A nickel-palladium-gold layer is prepared on the surface of the first redistribution layer.

[0023] As another optional solution for the large-board fan-out packaging method, the I / O ports of the plurality of chips are electrically led out from both sides of the chip plastic package, including:

[0024] Performing a hole-opening process on the chip plastic package to form a plurality of first through holes and blind holes for exposing the I / O ports of the plurality of chips, wherein the first through holes penetrate the chip plastic package;

[0025] Fabricating first conductive pillars in the plurality of first through holes and the plurality of blind holes, and fabricating first redistribution layers electrically connected to the first conductive pillars on two opposite sides of the chip plastic package;

[0026] Pressing dielectric layers on opposite side surfaces of the chip plastic package and the surface of the first redistribution layer respectively;

[0027] Opening two opposite surfaces of the dielectric layer to form a plurality of second through holes, wherein the pad area of ​​the first redistribution layer on each side is exposed through the second through holes on the dielectric layer on the same side;

[0028] Fabricating second conductive pillars electrically connected to the pad areas of the first redistribution layer in the plurality of second through holes, and fabricating second redistribution layers electrically connected to the second conductive pillars on opposite sides of the dielectric layer to lead out the I / O ports of the plurality of chips;

[0029] A nickel-palladium-gold layer is prepared on the surface of the second redistribution layer.

[0030] On the other hand, the present application provides a large-board-level fan-out packaging structure, comprising:

[0031] A chip plastic package body, comprising a plastic package layer, a frame encapsulated in the plastic package layer, and multiple groups of chips, wherein two adjacent groups of chips are separated by the frame, and one side of the multiple groups of chips and the frame are flush with one side of the plastic package layer;

[0032] a plurality of first conductive pillars, wherein some of the plurality of first conductive pillars pass through the chip plastic package, and the remaining portions are respectively located in a plurality of blind holes in the plastic package layer corresponding to the I / O ports of the plurality of groups of chips;

[0033] A first redistribution layer is formed on two opposite surfaces of the chip plastic package, and the first redistribution layer is electrically connected to the plurality of first conductive pillars and the I / O ports of the plurality of chips;

[0034] A nickel-palladium-gold layer is formed on the surface of the first redistribution layer.

[0035] In another aspect, the present application provides another large-board-level fan-out packaging structure, comprising:

[0036] A chip plastic package body, comprising a plastic package layer, a frame encapsulated in the plastic package layer, and multiple groups of chips, wherein two adjacent groups of chips are separated by the frame, and one side of the multiple groups of chips and the frame are flush with one side of the plastic package layer;

[0037] a plurality of first conductive pillars, wherein some of the plurality of first conductive pillars pass through the chip plastic package, and the remaining portions are respectively located in a plurality of blind holes in the plastic package layer corresponding to the I / O ports of the plurality of groups of chips;

[0038] A first redistribution layer is formed on two opposite surfaces of the chip plastic package, and the first redistribution layer is electrically connected to the plurality of first conductive pillars and the I / O ports of the plurality of chips;

[0039] A dielectric layer is formed on two opposite surfaces of the chip plastic package and a surface of the first redistribution layer;

[0040] a plurality of second conductive pillars, the plurality of second conductive pillars being formed in the second through holes of the dielectric layer and electrically connected to the first redistribution layer on the same side;

[0041] a second redistribution layer formed on two opposite sides of the dielectric layer and electrically connected to the plurality of second conductive pillars;

[0042] A nickel-palladium-gold layer is formed on the surface of the second redistribution layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a flow chart of the large-board-level fan-out packaging method described in Example 1 of the present application.

[0044] FIG2 is a schematic cross-sectional view of the temporary carrier described in Example 1 of the present application.

[0045] FIG3 is a cross-sectional schematic diagram of the bonding adhesive described in Example 1 of the present application attached to a temporary carrier.

[0046] FIG4 is a cross-sectional schematic diagram of the chip described in Example 1 of the present application attached to a temporary carrier.

[0047] FIG5 is a schematic cross-sectional view of the temporary carrier with the chip attached thereto after cutting as described in Example 1 of the present application.

[0048] FIG6 is a cross-sectional view of the cut-frame chips after being assembled into a frame as described in Example 1 of the present application.

[0049] FIG7 is a schematic cross-sectional view of the frame described in Example 1 of the present application.

[0050] FIG8 is a cross-sectional schematic diagram of the frame described in Example 1 of the present application attached to a temporary carrier board after the frame is assembled.

[0051] FIG9 is a schematic cross-sectional view after plastic packaging as described in Example 1 of the present application.

[0052] Figure 10 is a cross-sectional schematic diagram after the temporary carrier plate described in Example 1 of the present application is removed.

[0053] FIG11 is a partial cross-sectional schematic diagram of the chip plastic package after a hole is opened as described in Example 1 of the present application.

[0054] FIG12 is a partial cross-sectional schematic diagram after the first conductive pillar and the first redistribution layer are manufactured as described in Example 1 of the present application.

[0055] FIG13 is a partial cross-sectional schematic diagram of the dielectric layer after compression as described in Example 1 of the present application.

[0056] FIG14 is a partial cross-sectional schematic diagram of the dielectric layer after the holes are opened as described in Example 1 of the present application.

[0057] FIG15 is a partial cross-sectional schematic diagram after the second conductive pillar and the second redistribution layer are manufactured as described in Example 1 of the present application.

[0058] Figure 16 is a partial cross-sectional schematic diagram of the second redistribution layer after surface treatment described in Example 1 of the present application.

[0059] Figure 17 is a physical picture of the large-board-level fan-out packaging structure described in Example 1 of the present application.

[0060] Figure 18 is a partial cross-sectional schematic diagram of the first redistribution layer after surface treatment described in Example 2 of the present application. DETAILED DESCRIPTION

[0061] The technical solution of this application is described below through specific implementation methods.

[0062] Unless otherwise specified, various raw materials in this application can be purchased commercially or prepared according to conventional methods in this technical field.

[0063] Example 1

[0064] As shown in FIG1 , the large-board fan-out packaging method of this embodiment is as follows:

[0065] 1. Select a bismaleimide triazine resin (BT) board as a temporary carrier board 1 ( FIG. 2 ) and remove dust from the surface of the temporary carrier board 1 ;

[0066] 2. As shown in Figure 3, press bonding glue 2 onto the temporary carrier 1, controlling the pressure, temperature, and speed during pressing to avoid bubbles and wrinkles;

[0067] 3. As shown in FIG4 , multiple groups of chips 3 are attached to the surface of the bonding adhesive 2 away from the temporary carrier 1;

[0068] 4. As shown in FIG5 , the temporary carrier 1 after bonding is cut according to the chip group to form a plurality of cut-frame chips A, and the chip 3 on each cut-frame chip A constitutes a chip group;

[0069] 5. Perform surface treatment on chip 3 on the cut frame chip A;

[0070] The chip's pad is metal aluminum. In the embodiment of the present application, a layer of other metal can be added to the surface of the metal aluminum pad to change the material properties of the outermost layer of the pad; or the entire chip can be activated by plasma gas (including but not limited to argon, nitrogen, and oxygen) to increase its wettability and other effects, which is beneficial to the combination of the chip with other materials, such as plastic packaging materials.

[0071] 6. Arrange and frame multiple framed chips A, as shown in Figure 6;

[0072] 7. According to the layout requirements, a translucent BT board (without copper) is selected to make a hollow structure frame 4 as shown in FIG7 . The thickness of the frame 4 is selected according to the product requirements.

[0073] 8. Lay the frame 4 on the temporary carrier 1 after framing. As shown in FIG8 , the frame is fixed to the temporary carrier 1 by the bonding glue 2 on the temporary carrier 1. After lamination, remove bubbles. Each group of chips 3 is located in a hollow area of ​​the frame 4.

[0074] The tapeout process (carrier board production) eliminates the need for adhesive tape or film, preventing residual adhesive from affecting the product and improving product yield. The double-sided symmetrical design of the redistribution layer effectively reduces warping and significantly improves production efficiency.

[0075] 9. Use electromagnetic compatibility (EMC) plastic packaging material to plastic-encapsulate the chip 3 and the frame 4, as shown in FIG9 ;

[0076] 10. After the plastic encapsulation material is cured to form a plastic encapsulation layer 5, the temporary carrier 1 is separated and the bonding adhesive 2 is removed to obtain a chip plastic encapsulation body, as shown in FIG10 ;

[0077] The embodiment of the present application can select the corresponding plastic packaging material according to the product requirements. After plastic packaging, the temporary carrier and bonding glue can be removed by debonding. The corresponding debonding scheme can be adopted according to the characteristics of the bonding glue. Plastic packaging and debonding are both existing technologies in this field and will not be described in detail.

[0078] 11. Laser drilling is performed on the chip plastic package to form a plurality of first through holes 51 and a plurality of blind holes 52 for exposing the I / O ports of the chip 3, as shown in FIG11 ;

[0079] Laser can be used to punch holes in the chip plastic package (specifically, the plastic layer formed after the plastic package material is cured). According to the product blind hole and through hole requirements, corresponding laser drilling parameters are used, and the details are not repeated here.

[0080] 12. As shown in FIG12 , first conductive pillars 61 are formed in the first through holes 51 and blind holes 52 by electroplating, and first redistribution layers 62 are formed on two opposite sides of the chip plastic package.

[0081] The electroplating parameters can be set according to product requirements, and electroplating can be performed on both sides of the chip plastic package at the same time.

[0082] Before step 12, a seed layer can be formed by sputtering in the blind holes and through holes and on the surface of the chip plastic package, and then the first redistribution layer is formed to improve the bonding force between the first redistribution layer and the chip plastic package and improve the stability of the circuit structure.

[0083] 13. Press a dielectric layer 7 on the two opposite surfaces of the chip plastic package and the surface of the first redistribution layer 62, as shown in FIG13 ;

[0084] 14. Laser drilling the dielectric layer 7 to form a plurality of second through holes 71 that partially expose the first redistribution layer 62. As shown in FIG14 , the pad area of ​​the first redistribution layer 62 on each side is exposed through the second through holes 71 on the dielectric layer 7 on the same side.

[0085] 15. Then, a second conductive pillar 81 is formed in the second through hole 71 by electroplating, and a second redistribution layer 82 is simultaneously formed on two opposite surfaces of the dielectric layer 7. As shown in FIG15 , the second conductive pillar 81 is electrically connected to the pad area of ​​the first redistribution layer 62, and the second conductive pillar 81 is electrically connected to the second redistribution layer 82.

[0086] Before this step, a seed layer may be prepared first as needed, and then a second redistribution layer may be produced, which will not be described in detail.

[0087] 16. Surface treatment is performed on the second redistribution layer 82 on the opposite sides of the dielectric layer 7, i.e. nickel palladium gold is deposited on the surface of the second redistribution layer 82 to obtain a nickel palladium gold layer 9, thereby obtaining a large-board-level fan-out packaging structure as shown in FIG16 , and the actual picture is shown in FIG17 .

[0088] In this step, the second redistribution layer is surface treated, that is, a protective layer, namely a nickel palladium gold layer, is prepared on the second redistribution layer by nickel palladium gold. On the one hand, the nickel palladium gold layer can protect the second redistribution layer, and on the other hand, it is conducive to surface mount technology (SMT) or wire bonding.

[0089] As shown in FIG16 , the large-board-level fan-out packaging structure of this embodiment includes:

[0090] The chip plastic package includes a plastic layer 5, a frame 4 encapsulated in the plastic layer 5, and multiple groups of chips 3. Two adjacent groups of chips 3 are separated by the frame 4. One side of the chip 3 and the frame 4 are flush with one side of the plastic layer 5.

[0091] The frame is embedded in the plastic layer to increase the rigidity of the product, avoid fragmentation, and improve product yield.

[0092] A plurality of first conductive pillars 61, wherein some of the plurality of first conductive pillars 61 penetrate the chip plastic package, and the remaining portions are respectively located in a plurality of blind holes 52 of the plastic package layer 5 corresponding to the I / O ports of the plurality of groups of chips 3;

[0093] A first redistribution layer 62 is located on two opposite sides of the chip plastic package, and the first redistribution layer 62 is electrically connected to the first conductive pillar 61 and the I / O port of the chip 3;

[0094] a dielectric layer 7 located on two opposite surfaces of the chip plastic package and covering the first redistribution layer 62;

[0095] A plurality of second conductive pillars 81 are formed in the second through holes 71 of the dielectric layer 7 and electrically connected to the first redistribution layer 62 on the same side;

[0096] a second redistribution layer 82 located on two opposite sides of the dielectric layer 7 , wherein the second redistribution layer 82 is electrically connected to the second conductive pillar 81 ;

[0097] The nickel-palladium-gold layer 9 is located on the surface of the second redistribution layer 82 .

[0098] This solution adopts a multi-layer redistribution layer structural design to improve line strength.

[0099] This application creates a hollowed-out frame based on a layout design. The frame is then attached to a temporary carrier board after framing, ensuring that the frame just covers the gap between the temporary carrier boards of two adjacent framed chips. This prevents the plastic encapsulation compound from leaking out, thereby improving product yield. After encapsulation, the temporary carrier board is removed and circuits are created to electrically connect the chip's I / O ports, resulting in a large-board fan-out packaging structure. Furthermore, embedding the frame in the plastic encapsulation compound effectively increases product rigidity, prevents fragmentation, and thus improves product yield.

[0100] Example 2

[0101] This embodiment is basically the same as the above-mentioned embodiment 1 (refer to Figures 1-12 of embodiment 1), with the difference being that the redistribution layer is a double-sided single-layer structure.

[0102] The large-board fan-out packaging method of this embodiment is as follows:

[0103] 1. Select FR4 as the temporary carrier board 1 (refer to Figure 2) and remove dust from the surface of the temporary carrier board 1;

[0104] In this application, the temporary carrier board can be a BT board or a glass fiber epoxy resin copper clad FR4 board. Before pressing the bonding glue, the temporary carrier board needs to be dust-free. When pressing the bonding glue, the pressure, temperature, and speed during pressing need to be controlled to avoid bubbles and wrinkles.

[0105] 2. Press the bonding adhesive 2 onto the temporary carrier 1 (see Figure 3), controlling the pressure, temperature, and speed during pressing to avoid bubbles and wrinkles;

[0106] 3. Attach multiple groups of chips 3 on the bonding glue 2 away from the temporary carrier 1 (see Figure 4);

[0107] 4. Cut the temporary carrier 1 after bonding according to the chip group to form multiple cut-frame chips A (see Figure 5). The chip 3 on each cut-frame chip A constitutes a chip group;

[0108] 5. Perform surface treatment on chip 3 on the cut frame chip A;

[0109] 6. Arrange and frame multiple framed chips A (refer to Figure 6);

[0110] 7. According to the layout requirements, select translucent BT board (without copper) to make the hollow structure frame 4 (refer to Figure 7). The thickness of the frame 4 is selected according to the product requirements;

[0111] 8. Lay the frame 4 on the temporary carrier 1 after framing (see Figure 8). The frame 4 is fixed to the temporary carrier 1 through the bonding glue 2 on the temporary carrier 1. After lamination, remove bubbles. Each group of chips 3 is located in a hollow area of ​​the frame 4.

[0112] 9. Use EMC plastic packaging material to plasticize the chip 3 and the frame 4 (refer to Figure 9);

[0113] 10. After the plastic encapsulation material is cured to form the plastic encapsulation layer 5, the temporary carrier 1 is separated and the bonding adhesive 2 is removed (see FIG. 10 ) to obtain the chip plastic encapsulation body;

[0114] 11. Laser drilling the chip plastic package to create a plurality of first through holes 51 and a plurality of blind holes 52 for exposing the I / O ports of the chip 3 (see FIG. 11 );

[0115] 12. Form first conductive pillars 61 in the first through-holes 51 and blind holes 52 by electroplating, and simultaneously form first redistribution layers 62 on two opposite sides of the chip plastic package (see FIG. 12 );

[0116] 13. Surface treatment is performed on the first redistribution layer 62 on opposite sides, that is, nickel palladium gold is deposited on the surface of the first redistribution layer 62 to obtain a nickel palladium gold layer 9, thereby obtaining a large-board-level fan-out packaging structure as shown in FIG18.

[0117] The first redistribution layer is surface treated, that is, a protective layer, namely a nickel-palladium-gold layer, is prepared on the first redistribution layer by nickel-palladium-gold plating. The nickel-palladium-gold layer can protect the first redistribution layer on the one hand, and is beneficial to SMT or wire bonding on the other hand.

[0118] In summary, the large-board-level fan-out packaging method of this embodiment includes:

[0119] S100, providing a temporary carrier and a plurality of chips, attaching the plurality of chips to the temporary carrier and dicing the chips to form a plurality of cut-frame chips;

[0120] S200, performing surface treatment on each chip on the cut frame, and then arranging and assembling the plurality of cut frame chips;

[0121] S300, making a frame according to the layout, and then attaching the frame to the temporary carrier after the frame is assembled, the frame covering the gap between two adjacent framed chips after the frame is assembled, and the multiple chips are exposed on the frame;

[0122] S400, performing a plastic packaging process on the plurality of chips, and then separating the temporary carrier to obtain a chip plastic packaging body;

[0123] S500: Electrically lead the input / output I / O ports of the plurality of chips from both sides of the chip plastic package.

[0124] As shown in FIG18 , the large-board-level fan-out packaging structure of this embodiment includes:

[0125] The chip plastic package includes a plastic layer 5, a frame 4 encapsulated in the plastic layer 5, and multiple groups of chips 3. Two adjacent groups of chips 3 are separated by the frame 4. One side of the chip 3 and the frame 4 are flush with one side of the plastic layer 5.

[0126] A plurality of first conductive pillars 61, wherein some of the plurality of first conductive pillars 61 penetrate the chip plastic package, and the remaining portions are respectively located in a plurality of blind holes 52 of the plastic package layer 5 corresponding to the I / O ports of the plurality of groups of chips 3;

[0127] A first redistribution layer 62 is located on two opposite surfaces of the chip plastic package, and the first redistribution layer 62 is electrically connected to the first conductive pillar 61 and the I / O port of the chip 3;

[0128] The NiPdAu layer 9 is located on the surface of the first redistribution layer 62 that is away from each other.

[0129] Beneficial effects of this application:

[0130] 1. After surface treatment of the chips on the cut frame chips, multiple cut frame chips are arranged and assembled according to the design. This application produces a hollow frame according to the layout design, and then affixes the frame to the temporary carrier after the assembly, and makes the frame just cover the gap between the temporary carriers of two adjacent cut frame chips, which can prevent the plastic encapsulation material from flowing out of the gap, thereby improving the product yield.

[0131] 2. The frame is embedded in the plastic packaging material, which can effectively improve the rigidity of the product and avoid fragmentation during the tape-out process, thereby improving the product yield.

[0132] 3. No tape or film is required during the tape-out process to avoid the impact of residual glue on the product.

[0133] 4. Circuits can be made on both sides at the same time, greatly improving production efficiency.

[0134] The above examples are only used to illustrate the detailed methods of the present application. The present application is not limited to the above detailed methods, that is, it does not mean that the present application must rely on the above detailed methods to be implemented. Those skilled in the art should understand that any improvements to the present application, equivalent replacement of the raw materials of the products of the present application, addition of auxiliary ingredients, selection of specific methods, etc., all fall within the scope of protection and disclosure of the present application.

Claims

1. A large-board fan-out packaging method, comprising: Providing a temporary carrier and a plurality of chips, attaching the plurality of chips to the temporary carrier and cutting them into pieces to form a plurality of cut-frame chips; Performing surface treatment on each chip on each framed chip, and then arranging and framing the plurality of framed chips; A frame is made according to the layout, and then the frame is attached to the temporary carrier after the frame is assembled, the frame covers the gap between two adjacent framed chips after the frame is assembled, and the multiple chips are exposed outside the frame; Performing plastic encapsulation on the plurality of chips, and then separating the temporary carrier to obtain a chip plastic encapsulation body; The input / output I / O ports of the multiple chips are electrically led out from both sides of the chip plastic package.

2. The method according to claim 1, wherein: The method of providing a temporary carrier and a plurality of chips, attaching the plurality of chips to the temporary carrier and cutting the chips into pieces to form a plurality of cut-frame chips comprises: Providing a temporary carrier, and pressing bonding glue on one side of the temporary carrier along the thickness direction thereof; Providing a plurality of chips, and attaching the plurality of chips to the surface of the bonding adhesive away from the temporary carrier; The temporary carrier board with multiple chips attached thereto is cut into multiple framed chips.

3. The method according to claim 1, wherein: The frame is a copper-free semi-transparent bismaleimide triazine resin BT board.

4. The method according to any one of claims 1 to 3, wherein: The I / O ports of the plurality of chips are electrically led out from both sides of the chip plastic package, comprising: Performing a hole-opening process on the chip plastic package to form a plurality of first through holes and blind holes for exposing the I / O ports of the plurality of chips, wherein the first through holes penetrate the chip plastic package; Making first conductive pillars in the plurality of first through holes and the plurality of blind holes, and making first redistribution layers electrically connected to the first conductive pillars on two opposite sides of the chip plastic package to lead out the I / O ports of the plurality of chips; A nickel-palladium-gold layer is prepared on the surface of the first redistribution layer.

5. The method according to any one of claims 1 to 3, wherein: The I / O ports of the plurality of chips are electrically led out from both sides of the chip plastic package, comprising: Performing a hole-opening process on the chip plastic package to form a plurality of first through holes and blind holes for exposing the I / O ports of the plurality of chips, wherein the first through holes penetrate the chip plastic package; Making first conductive pillars in the plurality of first through holes and the plurality of blind holes, and making first redistribution layers electrically connected to the first conductive pillars on two opposite sides of the chip plastic package; Pressing dielectric layers on opposite side surfaces of the chip plastic package and the surface of the first redistribution layer respectively; Performing hole processing on two opposite sides of the dielectric layer to form a plurality of second through holes, wherein the pad area of ​​the first redistribution layer on each side is exposed through the second through holes on the dielectric layer on the same side; Making second conductive pillars electrically connected to the pad area of ​​the first redistribution layer in the plurality of second through holes, and making second redistribution layers electrically connected to the second conductive pillars on opposite side surfaces of the dielectric layer to lead out the I / O ports of the plurality of chips; A nickel-palladium-gold layer is prepared on the surface of the second redistribution layer.

6. A large-board-level fan-out packaging structure, made by the large-board-level fan-out packaging method according to any one of claims 1 to 4, comprising: A chip plastic package body, comprising a plastic package layer, a frame encapsulated in the plastic package layer, and a plurality of groups of chips, wherein two adjacent groups of chips are separated by the frame, and one side of the plurality of groups of chips and the frame are flush with one side of the plastic package layer; A plurality of first conductive pillars, some of which penetrate through the chip plastic package, and the rest of which are respectively located in a plurality of blind holes of the plastic package layer corresponding to the I / O ports of the plurality of groups of chips; The first redistribution layer is formed on two opposite sides of the chip plastic package, and the first redistribution layer is electrically connected to the plurality of first conductive pillars and the I / O ports of the plurality of chips; A nickel-palladium-gold layer is formed on the surface of the first redistribution layer.

7. A large-board-level fan-out packaging structure, made by the large-board-level fan-out packaging method according to any one of claims 1 to 3 or 5, comprising: A chip plastic package body, comprising a plastic package layer, a frame encapsulated in the plastic package layer, and a plurality of groups of chips, wherein two adjacent groups of chips are separated by the frame, and one side of the plurality of groups of chips and the frame are flush with one side of the plastic package layer; A plurality of first conductive pillars, some of which penetrate through the chip plastic package, and the rest of which are respectively located in a plurality of blind holes of the plastic package layer corresponding to the I / O ports of the plurality of groups of chips; The first redistribution layer is formed on two opposite sides of the chip plastic package, and the first redistribution layer is electrically connected to the plurality of first conductive pillars and the I / O ports of the plurality of chips; A dielectric layer is formed on two opposite sides of the chip plastic package and on a surface of the first redistribution layer; A plurality of second conductive pillars are formed in the second through holes of the dielectric layer and being electrically connected to the first redistribution layer on the same side; A second redistribution layer, wherein the second redistribution layer is formed on two opposite side surfaces of the dielectric layer and the second redistribution layer is electrically connected to the plurality of second conductive pillars; A nickel-palladium-gold layer is formed on the surface of the second redistribution layer.

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