Display screen having display pixels comprising light-emitting sources

Abstract

The present disclosure relates to a display pixel (Pix2) comprising a light-emitting source, a light-emitting source driver circuit (45) for driving the light-emitting source, first and second conductive pads (P_Row, P_Col) connected to the driver circuit, a first transmission circuit (50, 52), and third and fourth conductive pads connected to the first transmission circuit. When the third conductive pad (P_STD_IN, P_DATA_ IN) is electrically connected to the outside of the display pixel, the first transmission circuit sends a first signal (STD, DATA), received on the third conductive pad, to the fourth conductive pad (P_STD_OUT, P_DATA_OUT), and sends a second signal (Comi, Dataj) to the driver circuit and to one of the first and second conductive pads.

Description

B22364PCT – IR00209    DESCRIPTION Display screen having display pixels comprising light-emitting sources This patent application claims priority from French patent application FR23 / 06910 which will be considered as an integral part of this description. Technical field

[0001] The present disclosure concerns a display screen having display pixels comprising light-emitting sources, for example light-emitting diodes. Background art

[0002] A pixel of an image corresponds to the unit element of the image displayed by a display screen. For the display of color images, the display screen generally comprises, for the display of each pixel of the image, at least three components, also called display sub-pixels, which each emit a light radiation, called image pixel color component substantially in a single color (for example, red, green, and blue). The superposition of the image pixel color components emitted by the three display sub-pixels provides the observer with the colored sensation corresponding to the pixel of the displayed image. In this case, the assembly formed by the three display sub-pixels used for the display of a pixel of an image is called display pixel of the display screen. Each display sub-pixel may comprise a light source, particularly a light-emitting diode.

[0003] The display pixels may be distributed in an array, each display pixel being located at the intersection of a row (also called line) and of a column of the array. Row electrodes are provided along the rows to connect each display pixel to a row driver circuit and column electrodes are provided along the columns to connect each display pixel toB22364PCT – IR00209    a column driver circuit. Generally, each row of display pixels is successively selected by a signal transmitted along the row electrodes, and the display pixels of the selected row are programmed to display the desired image pixels by signals transmitted along the column electrodes.

[0004] An active array is a screen drive architecture enabling to maintain all the display pixel rows active for the entire duration of an image, conversely to arrays said to be passive, where each row is only active for a time T = Tframe / M (where Tframe is the duration of the display of the whole image and M is the number of lines of the screen). This enables to increase the luminosity of the display screen. Further, it is possible to send low voltage or current levels on the array control lines, which enables to display bigger data flows.

[0005] The row driver circuit and the column driver circuit of the display screen are generally located on two sides of the array of display pixels. A drawback is that, given the space occupied by the row driver circuit and the column driver circuit, it may be difficult to provide a bezel-less screen. Moreover, for some applications, it is desirable to be able to manufacture a display screen by assembling several elementary display screens, or tiles. However, a display screen comprising a row driver circuit and a column driver circuit located on two sides of the array of display pixels cannot be used as an elementary display screen since, when assembling several such elementary display screens, the row driver circuits and the column driver circuits of the elementary display screens are located among the display pixels. Summary of InventionB22364PCT – IR00209

[0006] An object of an embodiment is to provide a display screen comprising display pixels overcoming all or part of the disadvantages of existing display screens comprising such display pixels.

[0007] Another object of an embodiment is that the display screen can be a bezel-less screen.

[0008] Another object of an embodiment is that the display screen can be used as an elementary display screen for the manufacture of a display screen by assembling several elementary display screens.

[0009] One embodiment provides a display screen comprising an array of display pixels arranged in rows and in columns. Each display pixel comprises at least one light-emitting source, and a light-emitting source driver circuit for driving said light-emitting source. The display pixels include first display pixels and second display pixels, at least some of the second display pixels being serially connected in a first succession. Each second display pixel of the first succession further comprises a first transmission circuit configured to: a) send first display data to the display pixels of the column of said second display pixel and to transmit second display data to the following second display pixel of the first succession; or b) send a first selection signal to the display pixels of the row of said second display pixel and to transmit a second selection signal to the following second display pixel of the first succession.

[0010] According to an embodiment, the first transmission circuit of each second display pixel is configured to implement either the features a) or the features b) according to the positions of the second display pixels in the displayB22364PCT – IR00209    screen. According to an embodiment, during operation, there is no decision made by the first transmission circuit, and, according to its configuration, the first transmission circuit will implement either the features a) or the features b). This configuration of the first transmission circuits can be made during the manufacturing of the display screen. The second display pixels can advantageously be used, in a display screen, as a column driver circuit for one column of the display screen or as a row driver circuit for one row of the display screen. A display screen comprising such second display pixels does not comprise a separate row driver circuit and / or a separate column driver circuit. More specifically, according to an embodiment, when the second display pixels are arranged in a row, the second display pixels of this row can advantageously be used, in the display screen, as a column driver circuit and the display screen does not comprise a separate column driver circuit but can comprise a separate row driver. Moreover, according to another embodiment, when the second display pixels are arranged in a column, the second display pixels of this column can advantageously be used, in the display screen, as a row driver circuit and the display screen does not comprise a separate row driver circuit but can comprise a separate column driver. Moreover, according to another embodiment, when the second display pixels are arranged in a row and in column, the second display pixels of this row can advantageously be used, in the display screen, as a column driver circuit and the display screen does not comprise a separate column driver circuit and the second display pixels of this column can advantageously be used, in the display screen, as a row driver circuit and the display screen does not comprise a separate row driver circuit. Therefore, according to an embodiment, a bezel-less screen can be manufactured since there is no need for an exclusiveB22364PCT – IR00209    space for the row driver circuit and the column driver circuit. Moreover, the display screen comprising such second display pixels can be used to manufacture a display screen having a tiled structure comprising several copies of the display screen comprising such second display pixels. As it is common for a display screen, since display pixels arranged in rows and in columns, for each row, the display pixels of the row are connected together by at least one electrode, and for each column, the display pixels of the column are connected together by at least one electrode.

[0011] According to an embodiment, each display pixel comprises first and second bonding electrically conductive pads connected to said light-emitting source driver circuit. Each second display pixels further comprises third and fourth bonding electrically conductive pads connected to said first transmission circuit. Said first transmission circuit is configured, when the third bonding electrically conductive pad is electrically connected to the outside of the display pixel, to send a first signal, received on the third bonding electrically conductive pad, to the fourth bonding electrically conductive pad, and to send a second signal to the light-emitting source driver circuit and to one of the first and second bonding electrically conductive pads, wherein the first signal corresponds to a first selection signal and wherein the second signal corresponds to a second selection signal; or wherein the first signal corresponds to first display data and wherein the second signal corresponds to second display data.

[0012] The number of conductive pads of each first display pixel is advantageously maintained the lowest. Moreover, the structure of the first display pixels and the second display pixels can be partly the same. According to an embodiment, itB22364PCT – IR00209    can be detected by the second display pixel that the third bonding electrically conductive pad is not electrically connected to the outside of the display pixel in case the third bonding electrically is left floating or is tied to a fixed level like the low reference potential Gnd.

[0013] According to an embodiment, for each first display pixel, the first bonding electrically conductive pad is intended to receive the second selection signal and the second bonding electrically conductive pad is intended to receive the second data signal. This implies a specific connection of the first display pixels in the display screen.

[0014] According to an embodiment, the display screen comprises, for each row, a first electrically conductive track connecting the first bonding electrically conductive pads of the first and second display pixels of said row, and, for each column, a second electrically conductive track connecting the second bonding electrically conductive pads of the first and second display pixels of said column.

[0015] According to an embodiment, in the first succession, the fourth bonding electrically conductive pad of one second display pixel of the first succession is connected to the third bonding electrically conductive pad of the following second display pixel of the first succession. There is no need for additional conductive tracks extending over the entire row or column for connecting the second display pixels.

[0016] According to an embodiment, for each second display pixel of the first succession, the light-emitting source driver circuit of the second display pixel is configured to receive the second signal sent by the first transmission circuit of the second display pixel to drive the light- emitting source and, for each second display pixel not in the first succession, the third bonding electrically conductiveB22364PCT – IR00209    pad of the second display pixel is not electrically connected to the outside of the second display pixel and the light- emitting source driver circuit of the second display pixel is configured to receive the second signal, received on the first bonding electrically conductive pad, to drive the light- emitting source. The connection of the second display pixel in the display screen advantageously automatically commands which signals are used by the light-emitting source driver circuit of the second display pixel.

[0017] According to an embodiment, each second display pixel further comprises a second transmission circuit, and fifth and sixth electrically bonding electrically conductive pads connected to said second transmission driver circuit. Said second transmission circuit is configured, when the fifth bonding electrically conductive pad is electrically connected to the outside of the display pixel, to send a third signal, received on the fifth bonding electrically conductive pad, to the sixth bonding electrically conductive pad, and to send a fourth signal to the light-emitting source driver circuit and to the other of the first and second bonding electrically conductive pads. The first signal corresponds to the first selection signal, the second signal corresponds to the second selection signal, the third signal corresponds to the first display data, and the fourth signal corresponds to the second display data. The first transmission circuit of each second display pixel of the first succession is configured to send the second selection signal to the display pixels of the row of said second display pixel and to transmit the first selection signal to the following second display pixel of the first succession. At least some of the second display pixels are serially connected in a second succession, and wherein the second transmission circuit of each second display pixel of the second succession is configured to send the secondB22364PCT – IR00209    display data to the display pixels of the column of said second display pixel and to transmit the first display data to the following second display pixel of the second succession. . According to an embodiment, it can be detected by the second display pixel that the fifth bonding electrically conductive pad is not electrically connected to the outside of the display pixel in case the fifth bonding electrically is left floating or is tied to a fixed level like the low reference potential.

[0018] The display screen can advantageously comprise only two types of display pixels, that is the first display pixels and the second display pixels. The second display pixel can advantageously be used, in a display screen, as a column driver circuit for one column of the display screen or as a row driver circuit for one row of the display screen.

[0019] According to an embodiment, in the second succession, the sixth bonding electrically conductive pad of one second display pixel of the second succession is connected to the fifth bonding electrically conductive pad of the following second display pixel of the second succession. There is no need for additional conductive tracks extending over the entire row or column for connecting the second display pixels.

[0020] According to an embodiment, for each second display pixel of the second succession, the light-emitting source driver circuit of the second display pixel is configured to receive the fourth signal sent by the second transmission circuit of the second display pixel to drive the light- emitting source and, for each second display pixel not in the second succession, the fifth bonding electrically conductive pad of the second display pixel is not electrically connected to the outside of the second display pixel and the light- emitting source driver circuit of the second display pixel isB22364PCT – IR00209    configured to receive the fourth signal, received on the first bonding electrically conductive pad, to drive the light- emitting source. The connection of the second display pixel in the display screen advantageously automatically commands which signals are used by the light-emitting source driver circuit of the second display pixel.

[0021] According to an embodiment, the display screen comprises a row and a column of the second display pixels, the other display pixels of the display screen being the first display pixels.

[0022] According to an embodiment, the first transmission circuit of each second display pixels comprises a driver electronic circuit and a demultiplexer. Said driver electronic circuit is configured to receive the first data signal and the first selection signal and configured to send the second data signal or the second selection signal to the demultiplexer. Said demultiplexer is configured to transmit the second data signal to the second electrically conductive pad or the second selection signal to the first electrically conductive pad according to a control signal. It is the value of the control signal of the multiplexer that commands the operation of the second display pixel as a row driver circuit or a column driver circuit.

[0023] According to an embodiment, the display screen comprises a row and a column of the second display pixels except for one display pixel that is one of the first display pixels, the other display pixels of the display screen being the other first display pixels.

[0024] According to an embodiment, the first transmission circuit of each second display pixel of the first succession is configured to send the second data signal to the display pixels of the column of said second display pixel and toB22364PCT – IR00209    transmit the first data signal to the following second display pixel of the first succession. The display pixels include third display pixels different from the second display pixels. The third display pixels are serially connected in a second succession. Each third display pixel comprises a third transmission circuit configured to send the second selection signal to the display pixels of the row of said third display pixel and to transmit the first selection signal to the following third display pixel of the second succession. Since the third display pixel can be different from the second display pixel, the structure of each third display pixel and second display pixel can advantageously be made simpler.

[0025] According to an embodiment, the display screen comprises a row of the second display pixels and a column of the third display pixels except for the display pixel at the intersection of said row and said column that is one of the first display pixels, the other display pixels of the display screen being the other first display pixels.

[0026] According to an embodiment, the display screen comprises a row of the second display pixels and a column of the third display pixels except for the display pixel of said row, or comprising a column of the third display pixels and a row of the second display pixels except for the display pixel of said column, the other display pixels of the display screen being the first display pixels.

[0027] According to an embodiment, the display screen comprises a row of the second display pixels except for one display pixel of said row that is a third display pixel and a column of the third display pixels except for one display pixel of said column that is a second display pixel, the other display pixels of the display screen being the first displayB22364PCT – IR00209    pixels except for one display pixel that is a second display pixel or a third display pixel.

[0028] According to an embodiment, each light-emitting source driver circuit comprises a storage circuit for storing at least one digital signal, the light-emitting source driver circuit being configured to drive said light-emitting source based on the stored digital signal, and to update said stored digital signal from the first data signal upon the detection of a pattern of the first selection signal.

[0029] According to an embodiment, said light-emitting source driver circuit is configured not to update said stored digital signal from the first data signal when the pattern of the first selection signal is not detected.

[0030] According to an embodiment, each display pixel comprises a stack of a first electronic circuit comprising the light-emitting source driver circuit and a second electronic circuit comprising the light-emitting source.

[0031] One embodiment provides a display pixel comprising: -at least one light-emitting source; -a light-emitting source driver circuit for driving said light-emitting source; -first and second bonding electrically conductive pads connected to said light-emitting source driver circuit; -a first transmission circuit; and -third and fourth bonding electrically conductive pads connected to said first transmission circuit, said first transmission circuit being configured, when the third bonding electrically conductive pad is electrically connected to the outside of the display pixel, to send a first signal, received on the third bonding electrically conductive pad, to the fourth bonding electrically conductive pad, and to send a second signal to the light-emitting source driver circuit andB22364PCT – IR00209    to one of the first and second bonding electrically conductive pads.

[0032] Such display pixel can advantageously be used, in a display screen, as a column driver circuit for one column of the display screen or as a row driver circuit for one row of the display screen. A display screen comprising such modified display pixels does not comprise a separate row driver circuit and / or a separate column driver circuit. Therefore, according to an embodiment, a bezel-less screen can be manufactured since there is no need for an exclusive space for the row driver circuit and the column driver circuit. Moreover, the display screen comprising such modified display pixels can be used to manufacture a display screen having a tiled structure comprising several copies of the display screen comprising such modified display pixels.

[0033] According to an embodiment, the light-emitting source driver circuit is configured to receive the second signal received on said one of the first and second bonding electrically conductive pads when the third bonding electrically conductive pad is not electrically connected to the outside of the display pixel.

[0034] According to an embodiment, the display pixel further comprises: -a second transmission circuit; and -fifth and sixth electrically bonding electrically conductive pads connected to said second transmission circuit, said second transmission circuit being configured, when the fifth bonding electrically conductive pad is electrically connected to the outside of the display pixel, to send a third signal, received on the fifth bonding electrically conductive pad, to the sixth bonding electrically conductive pad, and to send a fourth signal to the light-emitting source driver circuit andB22364PCT – IR00209    to the other of the first and second bonding electrically conductive pads.

[0035] The same display pixel can advantageously be used, in a display screen, as a column driver circuit for one column of the display screen or as a row driver circuit for one row of the display screen.

[0036] According to an embodiment, the light-emitting source driver circuit is configured to receive the fourth signal received on said other of the first and second bonding electrically conductive pads hen the fifth bonding electrically conductive pad is not electrically connected to the outside of the display pixel. Brief description of drawings

[0037] The foregoing features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0038] Figure 1 partially and schematically shows an example of a display screen;

[0039] Figure 2 partially and schematically shows another example of a display screen;

[0040] Figure 3 schematically shows the locations occupied by the driver circuits of the display screen of Figure 1;

[0041] Figure 4 is a schematic view of a display screen made by assembling several copies of the display screen of Figure 1 showing the locations occupied by the driver circuits of the display screen;

[0042] Figure 5 partially and schematically shows an embodiment of a display screen;B22364PCT – IR00209

[0043] Figure 6 is a very simplified cross-section view of a display pixel of a first type of the display screen of Figure 5;

[0044] Figure 7 shows a block diagram of an embodiment of the display pixel of the first type;

[0045] Figure 8 is a bottom view of the display pixel of Figure 7;

[0046] Figure 9 is a very simplified cross-section view of a display pixel of a second type of the display screen of Figure 5;

[0047] Figure 10 shows a block diagram of an embodiment of the display pixel of the second type;

[0048] Figure 11 is a bottom view of the display pixel of Figure 10;

[0049] Figure 12 is a schematic view of the display screen of Figure 5 showing the connection of electrodes and the display pixels;

[0050] Figure 13 partially and schematically shows another embodiment of a display screen;

[0051] Figure 14 shows a block diagram of an embodiment of a display pixel of a third type of the display screen of Figure 13;

[0052] Figure 15 is a bottom view of the display pixel of Figure 14;

[0053] Figure 16 is a schematic view of the display screen of Figure 13 showing the connection of electrodes and the display pixels;

[0054] Figure 17 partially and schematically shows another embodiment of a display screen;B22364PCT – IR00209

[0055] Figure 18 shows a block diagram of an embodiment of a display pixel of a fourth type of the display screen of Figure 17;

[0056] Figure 19 is a bottom view of the display pixel of Figure 18;

[0057] Figure 20 shows a block diagram of an embodiment of a display pixel of a fifth type of the display screen of Figure 17;

[0058] Figure 21 is a bottom view of the display pixel of Figure 20;

[0059] Figure 22 is a schematic view of the display screen of Figure 17 showing the connection of electrodes and the display pixels;

[0060] Figure 23 partially and schematically shows another embodiment of a display screen;

[0061] Figure 24 is a schematic view of the display screen of Figure 23 showing the connection of electrodes and the display pixels;

[0062] Figure 25 partially and schematically shows another embodiment of a display screen;

[0063] Figure 26 is a schematic view of the display screen of Figure 25 showing the connection of electrodes and the display pixels;

[0064] Figure 27 partially and schematically shows another embodiment of a display screen;

[0065] Figure 28 is a schematic view of the display screen of Figure 27 showing the connection of the electrodes and the display pixels; and

[0066] Figure 29 partially and schematically shows another embodiment of a display screen.B22364PCT – IR00209    Description of embodiments

[0067] Like features have been designated by like references in the various figures. In particular, the structural and / or functional features that are common among the various embodiments may have the same references and may dispose identical structural, dimensional and material properties. For the sake of clarity, only the steps and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail.

[0068] Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct connection without any intermediate elements other than conductors, and when reference is made to two elements coupled together, this signifies that these two elements can be connected or they can be coupled via one or more other elements. Further, a signal which alternates between a first constant state, for example, a low state, noted "0", and a second constant state, for example, a high state, noted "1", is called a "binary signal". The high and low states of different binary signals of a same electronic circuit may be different. In practice, the binary signals may correspond to voltages or to currents which may not be perfectly constant in the high or low state.

[0069] Unless specified otherwise, the expressions "around", "approximately", "substantially" and "in the order of" signify within 10%, and preferably within 5%. Further the expression "substantially constant" means which varies by less than 10% over time with respect to a reference value.

[0070] In the following specification, embodiments are disclosed for display pixels comprising light-emitting diodes. However, these embodiments can be implemented for display pixels comprising electroluminescent sources different fromB22364PCT – IR00209    light-emitting diodes, for example organic light-emitting diodes, field-induced polymer electroluminescent components, or laser diodes.

[0071] In the following specification, embodiments are disclosed for a color display screen comprising color display pixels, each display pixel comprising light-emitting diodes adapted to emit radiations of different colors. However, these embodiments also apply for a monochromatic display screen comprising monochromatic display pixels, each monochromatic display pixel comprising one light-emitting diode or only light-emitting diodes adapted to emit a radiation of a single color.

[0072] Figure 1 partially and schematically shows an example of a display screen 10. Display screen 10 comprises an array 12 of display pixels Pix1i,j, for example, arranged in M rows and in N columns, M being an integer varying from 1 to 8,000 and N being an integer varying from 1 to 16,000, i being an integer varying from 1 to M, and j being an integer varying from 1 to N. As an example, in Figure 1, M and N are equal to 3.

[0073] For each row, the display pixels Pix1i,jin the row are coupled to at least one row electrode E_Rowi. For each column, the display pixels Pix1i,jin the column are coupled to at least one column electrode E_Colj. Display screen 10 comprises a row driver circuit 14 coupled to row electrodes E_Rowiand adapted to delivering a selection and timing signal Comion each row electrode E_Rowi. Display screen 10 comprises a column driver circuit 16 coupled to column electrodes E_Coljand adapted to delivering a data signal Datajon each column electrode E_Colj. Row driver circuit 14 and column driver circuit 16 are controlled by a circuit 18, for example comprising a microprocessor, called timing controllerB22364PCT – IR00209    hereafter. According to an embodiment, selection and timing signal Comiis a binary signal and data signal Datajis a binary signal.

[0074] Moreover, each display pixel Pix1i,jis coupled to a source of a low reference potential Gnd, for example, the ground, via an electrode not shown in Figure 1, and to a source of a high reference potential Vcc, via an electrode not shown in Figure 1. The power supply voltage of the display screen corresponds to the voltage between high reference potential Vcc and low reference potential Gnd. The power supply voltage particularly depends on the arrangement of the light-emitting diodes and on the technology according to which the light-emitting diodes are manufactured. As an example, the power supply voltage may be in the order of from 3.5 V to 5.5 V.

[0075] Generally, each row of display pixels is successively selected, and the display pixels of the selected row are programmed to display the desired image pixels. In a known method for selecting display pixels, row driver circuit 14 is adapted to delivering selection and timing signals Comion row electrodes E_Rowito successively select each row of display pixels Pix1i,jand column driver circuit 16 is adapted to delivering data signals Datajon each column electrode E_Coljrepresentative of color digital data that are stored in the selected display pixels Pix1i,j.

[0076] In Figure 1, row driver circuit 14 is a multi-channel driver and column driver circuit 16 is a multi-channel driver.

[0077] Figure 2 partially and schematically shows a variation of display screen 10 in which row driver circuit 14 comprises several single-channel row driver circuits 141à 143and except that column driver circuit 16 comprises several single- channel column driver circuits 161à 163.B22364PCT – IR00209

[0078] Figure 3 schematically shows, for screen display 10 of Figure 1 or 2, the surfaces occupied by the array 12 of display pixels, row driver circuit 14, and column driver circuit 16. As it appears in Figure 3, row driver circuit 14 and column driver circuit 16 are generally located on two sides of the array 12 of display pixels. A drawback is that, given the space occupied by row driver circuit 14 and column driver circuit 16, it may be difficult to provide a bezel- less screen.

[0079] Figure 4 is a schematic view of a display screen 20 having a tiled structure, which means that it comprises an assembly of several copies of display screen 10. As it is shown in Figure 4, some of the row driver circuits 14 and the column driver circuits 16 are located among the arrays 12 of display pixels. Therefore, display screen 10 is not adapted for the manufacture of a display screen having a tiled structure.

[0080] The present invention consists in modifying some display pixels of the display screen so that they also collectively perform, in addition to the display of image pixels, the function usually performed by the row driver circuit and the column driver circuit. A display screen comprising such modified display pixels does not comprise a row driver circuit and a column driver circuit. Therefore, according to an embodiment, a bezel-less screen can be manufactured since there is no need for an exclusive space for the row driver circuit and the column driver circuit. Moreover, the display screen comprising such modified display pixels can be used to manufacture a display screen having a tiled structure comprising several copies of the display screen comprising such modified display pixels.B22364PCT – IR00209

[0081] Moreover, according to the present invention, the number of conductive tracks connecting timing controller 18 to the array of display pixels is reduced, preferably at most equal to six conductive tracks. This advantageously allows to reduce the number of bonding pads for the connection of the array of display pixels. Moreover, according to the present invention, the display screen neither comprises a row driver circuit nor a column driver circuit. This advantageously allows to reduce the number of chips connected to the array of display pixels.

[0082] Figure 5 partially and schematically shows an embodiment of a display screen 30. Display screen 30 comprises an array 32 of display pixels, for example, arranged in M rows and in N columns, i being an integer varying from 1 to M, and j being an integer varying from 1 to N. In the present embodiment, display screen 30 comprises display pixels Pix1 of a first type (Pixel) and display pixels Pix2 a second type (Pixel & Driver). The first column of array 32 comprises display pixels of the second type Pix2i,1, i varying from 1 to M, and the first row of array 32 comprises display pixels of the second type Pix21,j, j varying from 1 to N. The others display pixels of array 32 are of the first type. Therefore, array 32 comprises a sub-array of display pixels of the first type Pix1i,j, i being an integer varying from 2 to M, and j being an integer varying from 2 to N. Timing controller 18 is coupled to display pixel Pix21,1at the first row and at the first column. Timing controller 18 is configured to send four signals CLK_COL, DATA, CLK_ROW, STD to display pixel Pix21,1. According to an embodiment, each signal CLK_COL, DATA, CLK_ROW, STD is a binary signal.

[0083] In the present embodiment, each display pixel Pix1 of the first type only performs the function of displaying an image pixel. In the present embodiment, each display pixelB22364PCT – IR00209    Pix2 of the second type, in addition to performing the function of displaying an image pixel, includes a single row / column driver circuit that can operate as a single row driver circuit providing selection and timing signal Comito the row to which it belongs and / or as a single column driver circuit providing data signal Datajto the column to which it belongs according to the connection of the display pixel. According to an embodiment, selection and timing signal Comiis a binary signal and data signal Datajis a binary signal.

[0084] Figure 6 is a very simplified cross-section view of display pixel Pix1 of the first type. Display pixel Pix1 comprises a control circuit 34 covered with a display circuit 36. Control circuit 34 comprises a lower surface 38 and an upper surface 40 opposite to lower surface 38, surfaces 38 and 40 being preferably planar and parallel. Display circuit 36 comprises a lower surface 42 and an upper surface 44 opposite to lower surface 42, surfaces 42 and 44 being preferably planar and parallel. Surface 38 corresponds to the lower surface of display pixel Pix1 and Pix2 and surface 44 corresponds to the top surface of display pixel Pix1 and Pix2. Upper surface 40 of control circuit 34 is attached to lower surface 42 of display circuit 36.

[0085] Display circuit 36 comprises at least one light- emitting diode, preferably at least three light-emitting diodes LED_R, LED_G, LED_B. Control circuit 34 may correspond to an integrated circuit comprising electronic components, particularly insulated gate field effect transistors, also called MOS transistors, or thin film transistors, also called TFTs. Preferably, display circuit 36 only comprises light- emitting diodes LED_R, LED_G, LED_B and the conductive elements of these light-emitting diodes LED_R, LED_G, LED_B, and control circuit 34 comprises all the electronic components necessary to the control of the light-emitting diodes LED_R,B22364PCT – IR00209    LED_G, LED_B of display circuit 36. As a variant, display circuit 36 may also comprise other electronic components in addition to light-emitting diodes LED_R, LED_G, LED_B. Light- emitting diodes LED_R, LED_G, LED_B may be 2D light-emitting diodes, also called planar light-emitting diodes, comprising a stack of planar layers, or 3D light-emitting diodes, each comprising a three-dimensional semiconductor element covered with an active area.

[0086] According to an embodiment, display pixel Pix1 comprises at least three light-emitting diodes LED_R, LED_G, LED_B emitting light at first, second, and third wavelengths. According to an embodiment, the first wavelength corresponds to blue light and is within the range from 430 nm to 490 nm. According to an embodiment, the second wavelength corresponds to green light and is within the range from 510 nm to 570 nm. According to an embodiment, the third wavelength corresponds to red light and is within the range from 600 nm to 720 nm. As a variation, display pixel Pix1 and Pix2 can comprise only one light-emitting diode emitting light at the first, second, or third wavelength, or only two light-emitting diodes emitting light at two wavelengths among the first, second, and third wavelengths.

[0087] In Figure 6, light-emitting diodes LED_R, LED_G, LED_B are shown as being connected with a common anode. Control circuit 34 comprises, exposed on upper surface 40, a conductive pad R connected to the cathode of light-emitting diode LED_R, a conductive pad G connected to the cathode of light-emitting diode LED_G, a conductive pad B connected to the cathode of light-emitting diode LED_B and a conductive pad A connected to the anodes of light-emitting diodes LED_R, LED_G, LED_B. It may however be desirable to arrange light- emitting diodes LED_R, LED_G, LED_B according to another configuration. As an example, the light-emitting diodes mayB22364PCT – IR00209    be connected with a common cathode, or be connected independently from one another.

[0088] Control circuit 34 further comprises at least bonding conductive pads P_Gnd, P_Vcc, P_Col, P_Row on lower surface 38 in order to electrically connect display pixel Pix1 with the outside. Each bonding conductive pad P_Gnd, P_Vcc, P_Col, P_Row is intended to be connected to an electrode. The first conductive pad P_Gnd is coupled to the source of low reference potential Gnd. The second conductive pad P_Vcc is coupled to the source of high reference potential Vcc. The third conductive pad P_Row is coupled to row electrode E_Rowiand receives selection and timing signal Comi. The fourth conductive pad P_Col is coupled to column electrode E_Coljand receives data signal Dataj.

[0089] Figure 7 shows a block diagram of an embodiment of control circuit 34 of display pixel Pix1. Control circuit 34 of display pixel Pix1 comprises an electronic circuit 45 comprising a light-emitting diode driver circuit 46 that drives light-emitting diodes through conductive pads R, G, B and comprising a control and memory circuit 48 for driving light-emitting diode driver circuit 46. Control and memory circuit 48 receives selection and timing signal Comi, received at conductive pad P_Row, and Data signal Dataj,received at conductive pad P_Col. Control circuit 34 is powered through the high reference potential Vcc, received at conductive pad P_Vcc and the low reference potential Gnd, received at conductive pad P_Gnd.

[0090] Light-emitting diode driver circuit 46 may comprise three controllable current sources, each connected to one of the conductive pads R, G, and B. Each controllable current source may comprise a MOS transistor. In the present example, for each light-emitting diode, the anode of light-emittingB22364PCT – IR00209    diode receives high reference potential Vcc through conductive pad A and the cathode of each light-emitting diode is for example coupled to the terminal of respective controllable current source through conductive pads R, G, and B, the other terminal of controllable current source receiving low reference potential Gnd.

[0091] Control and memory circuit 48 may particularly comprise electronic components such as MOS transistors. According to an embodiment, control and memory circuit 48 comprises a storage circuit configured to store digital color signals based on received digital data. Digital color signals comprise each a number NB of bits and are representative of the image pixel color components to be displayed. Control and memory circuit 48 is configured to control light-emitting diode driver circuit 46 with signals obtained from digital color signals. According to an embodiment, light emitting diodes are controlled by pulse-width modulation, also called PWM (English acronym for Pulse Width Modulation). According to another embodiment, light emitting diodes are controlled by pulse-amplitude modulation, also called PAM (English acronym for Pulse Amplitude Modulation).

[0092] Figure 8 is a bottom view of control circuit 34 of display pixel Pix1. On lower surface 38, display pixel Pix1 comprises only four conductive pads P_Vcc, P_Gnd, P_Row, and P_Col. The number of conductive pads of display pixel Pix1 is advantageously maintained the lowest.

[0093] Figure 9 is a very simplified cross-section view of display pixel Pix2 of the second type. Display Pix2 comprises all the elements of display pixel Pix1 and further comprises additional bonding conductive pads P_CLK_ROW_IN, P_STD_IN, P_CLK_COL_IN, P_DATA_IN, P_CLK_ROW_OUT, P_STD_OUT, P_CLK_COL_OUT, P_DATA_OUT, and P_Vdd in order to electricallyB22364PCT – IR00209    connect display pixel Pix2 with the outside. According to the position of display pixel Pix2 in the array of display pixels, conductive pad P_Row can emit or receive selection and timing signal Comi. According to the position of display pixel Pix2 in the array of display pixels, conductive pad P_Col can emit or receive data signal Dataj.

[0094] Figure 10 shows a block diagram of an embodiment of control circuit 34 of display pixel Pix2. Control circuit 34 of display pixel Pix2 comprises electronic circuit 45 of control circuit 34 of display pixel Pix1, which is shown in dotted lines in Figure 10. Control circuit 34 of display pixel Pix2 further comprises a first transmission circuit 50, also called row driver circuit 50 hereafter, and a second transmission circuit 52, also called column driver circuit 52 hereafter. Control circuit 34 of display pixel Pix2 comprises, in addition to conductive pads P_Vcc, P_Gnd, P_Row, and P_Col, further conductive pads P_CLK_ROW_IN, P_STD_IN, P_CLK_COL_IN, P_DATA_IN, P_CLK_ROW_OUT, P_STD_OUT, P_CLK_COL_OUT, P_DATA_OUT, and P_Vdd.

[0095] Control circuit 34 receives, from conductive pad P_Vdd, a supply voltage Vdd inferior to supply voltage Vcc. Row driver circuit 50 receives signal CLK_ROW, received at pad P_CLK_ROW_IN, and receives signal STD, received at pad P_STD_IN. Row driver circuit 50 provides signal CLK_ROW at pad P_CLK_ROW_OUT and provides signal STD at pad P_STD_OUT. Row driver circuit 50 provides selection and timing signal Comiat pad P_Row and also to electronic circuit 45 through conductive path internal to control circuit 34. Column driver circuit 52 receives signal CLK_COL, received at pad P_CLK_COL_IN, and receives signal DATA, received at pad P_DATA_IN. Column driver circuit 52 provides signal CLK_COL at pad P_CLK_COL_OUT and provides signal DATA at pad P_DATA_OUT. Column driver circuit 52 provides data signalB22364PCT – IR00209    Datajat pad P_Col and also to electronic circuit 45 through conductive path internal to control circuit 34.

[0096] Figure 11 is a bottom view of control circuit 34 of display pixel Pix2. On lower surface 38, display pixel Pix2 comprises thirteen conductive pads P_Vcc, P_Gnd, P_Row, P_Col, P_CLK_ROW_IN, P_STD_IN, P_CLK_COL_IN, P_DATA_IN, P_CLK_ROW_OUT, P_STD_OUT, P_CLK_COL_OUT, P_DATA_OUT, and P_Vdd.

[0097] Figure 12 is a schematic view of display screen 30 of Figure 5 showing the connection of the electrodes and the display pixels.

[0098] For pixel Pix21,1of the first row and the first column, pads P_CLK_ROW_IN, P_STD_IN, P_CLK_COL_IN, and P_DATA_IN are coupled to timing controller 18, not shown in Figure 12. Pad P_CLK_ROW_IN of display pixel Pix21,1receives signal CLK_ROW from timing controller 18. Pad P_STD_IN of display pixel Pix21,1receives signal STD from timing controller 18. Pad P_CLK_COL_IN of display pixel Pix21,1receives signal CLK_COL from timing controller 18. Pad P_DATA_IN of display pixel Pix21,1receives signal DATA from timing controller 18.

[0099] For display pixels Pix2i,1of the first column, i varying from 2 to M, pads P_CLK_ROW_IN and P_STD_IN of display pixel Pix2i,1are coupled to pixel Pix2i-1,1. Pad P_CLK_ROW_IN of display pixel Pix2i,1is coupled, preferably connected, to pad P_CLK_ROW_OUT of display pixel Pix2i-1,1. Pad P_STD_IN of display pixel Pix2i,1is coupled, preferably connected, to pad P_STD_OUT of display pixel Pix2i-1,1. Pads P_COL_ROW_IN, P_DATA_IN, P_COL_ROW_OUT, and P_DATA_OUT of display pixel Pix2i,1are left floating or tied to a fixed level like the low reference potential Gnd. Moreover, pad P_Col of Pix2i,1is coupled to pad P_Col of Pix21,1by column electrode E_Col1.B22364PCT – IR00209

[0100] For display pixels Pix21,jof the first row, j varying from 2 to N, pads P_CLK_COL_IN and P_DATA_IN of display pixel Pix21,jare coupled to display pixel Pix21,j-1. Pad P_CLK_COL_IN of display pixel Pix21,jis coupled, preferably connected, to pad P_CLK_COL_OUT of display pixel Pix21,j-1. Pad P_DATA_IN of display pixel Pix21,jis coupled, preferably connected, to pad P_DATA_OUT of display pixel Pix21,j-1. Pads P_CLK_ROW_IN, P_STD_IN, P_CLK_ROW_OUT, and P_STD_OUT of display pixel Pix21,jare left floating or tied to a fixed level like the low reference potential Gnd. Moreover, pad P_Row of Pix21,jis coupled to pad P_Row of Pix21,1by row electrode E_Row1.

[0101] For all display pixels Pix1i,j, i varying from 2 to M and j varying from 2 to N, pad P_Col of display pixel Pix1i,jis coupled, preferably connected, to pad P_Col of display pixel Pix21,jby column electrode E_Colj, and pad P_Row of display pixel Pix1i,jis coupled, preferably connected, to pad P_Row of display pixel Pix2i,1by row electrode E_Rowi.

[0102] An embodiment of operation of display screen 30 will now be described. As an example, the display pixels on the row of rank i are selected when signal Comion electrode E_Rowicomprises a row selection pattern. A row selection pattern may correspond to signal Comithat is set at logical level "1" during a given duration or to signal Comithat comprises serial pulses. By default, each display pixel Pix2i,1of the first column provides signal Comiwithout the row selection pattern, for example by setting signal Comiat logical value "0" or without serial pulses. In order to select the display pixels of the row of rank i, timing controller 18 provides signal STD having the row selection pattern to display pixel Pix21,1. When display pixel Pix21,1receives signal STD having the row selection pattern, it sets signal Com1on pad P_Row having the row selection pattern in order to select the display pixels on the first row. Then, signal STD having theB22364PCT – IR00209    row selection pattern is sent to display pixel Pix22,1. Time difference between display pixel Pix21,1and display pixel Pix22,1is one row time, that is equal to the ratio between the frame time and the number of rows. Signal STD having the row selection pattern is then transmitted from display pixel Pix2i,1to display pixel Pix2i+1,1. When display pixel Pix2i,1receives signal STD having the row selection pattern, it sets signal Comion pad P_Row having the row selection pattern in order to select the display pixels on the row of rank i. The selected display pixel at row of rank i and column of rank j can therefore store display data Datajprovided by display pixel Pix21,j. Signal CLK_ROW is also transmitted from display pixel Pix2i,1to display pixel Pix2i+1,1and can be sent on pad P_Row by each display pixel Pix2i,1of a non-selected row to be used as a timing signal for the control of the light- emitting diodes by the display pixels.

[0103] For the display of image pixels on the row of rank i, display data are serially provided by timing controller 18 to display pixel Pix21,1, clocked by signal CLK_COL, starting from the display data regarding the display pixel DataNat the last column to the display data Data1regarding the display pixel at the first column. Display data DATA are serially transmitted from display pixel Pix21,jto display pixel Pix21,j+1, clocked by signal CLK_COL that is also transmitted from display pixel Pix21,jto display pixel Pix21,j+1, until the display data DataNregarding the display pixel at the last column reach display pixel Pix21,N. At that point, each display pixel Pix21,j, j varying from 1 to N, has received and stored display data Datajconcerning the column of rank j. Each display pixel Pix21,jprovides display data Datajto pad P_Col.

[0104] Figure 13 partially and schematically shows another embodiment of a display screen 60. Display screen 60 comprises an array 62 of display pixels, for example, arranged in MB22364PCT – IR00209    rows and in N columns, i being an integer varying from 1 to M, and j being an integer varying from 1 to N. In the present embodiment, display screen 60 comprises display pixels Pix1 of the first type (Pixel) and display pixels Pix3 of a third type (Pixel & Driver). Display pixels Pix3 of the third type can have the general structure shown in Figure 9 with a reduced number of conductive pads. The display pixel Pix11,1of the first column and the first row is a display pixel of the first type. The rest of the first column of array 62 comprises display pixels Pix3i,1of the third type, i varying from 2 to M. The rest of the first row of array 62 comprises display pixels Pix31,jof the third type, j varying from 2 to N. The others display pixels of array 62 are of the first type. Therefore, array 62 comprises a sub-array of display pixels of the first type Pix1i,j, i being an integer varying from 2 to M, and j being an integer varying from 2 to N. Timing controller 18 is configured to send six signals CLK_COL, DATA, CLK_ROW, STD, Data1, and Com1to the array 62 of display pixels. According to an embodiment, each signal CLK_COL, DATA, CLK_ROW, STD, Data1, and Com1is a binary signal.

[0105] In the present embodiment, each display pixel Pix3 of the third type, in addition to performing the function of displaying an image pixel, includes a driver circuit that can operate as a row driver circuit providing selection and timing signal Comior as a column driver circuit providing data signal Datajaccording to the programming of the display pixel.

[0106] Figure 14 shows a block diagram of an embodiment of control circuit 34 of display pixel Pix3. Control circuit 34 of display pixel Pix3 comprises electronic circuit 45 of control circuit 34 of display pixel Pix1, which is shown in dotted lines in Figure 14. Control circuit 34 of display pixel Pix3 comprises, in addition to bonding conductive pads P_Vcc, P_Gnd, P_Row, and P_Col, further bonding conductive padsB22364PCT – IR00209    P_CLK_IN, P_DATA_STD_IN, P_CLK_OUT, P_DATA_STD_OUT, and P_Vdd in order to electrically connect display pixel Pix3 with the outside. Control circuit 34 receives supply voltage Vdd from conductive pad P_Vdd.

[0107] Control circuit 34 of display pixel Pix3 further comprises a row / column driver circuit 64 coupled to pads P_CLK_IN, P_DATA_STD_IN, P_CLK_OUT, and P_DATA_STD_OUT. Row / column driver circuit 64 receives signals from pads P_CLK_IN and P_DATA_STD_IN and provides signals to pads P_CLK_OUT and P_DATA_STD_OUT. Control circuit 34 of display pixel Pix3 further comprises a demultiplexer 66 controlled by a signal provided by a node CTL. Demultiplexer 66 receives a signal from Row / column driver circuit 64 and provides this signal either to pad P_Row or to pad P_Col according to the voltage value of node CTL. Node CTL is linked either to node I_Vdd or node I_Gnd. Node I_Vdd is connected to pad P_Vdd and node I_Gnd is connected to pad P_Gnd. The link of node CTL either to node I_Vdd or node I_Gnd is made in a programming phase, in an assembly phase, or during production at wafer level. In an embodiment, node CTL is initially coupled to node I_Vdd by a first fuse track and to node I_Gnd by a second fuse track, and the first fuse track or the second fuse track is interrupted in the programming phase, for example by a laser, so that node CTL remains connected only either to node I_Vdd or to node I_Gnd. In another embodiment, the control circuit 34 of display pixel Pix3 further comprises a register that can be programmed in the programming phase and that control the voltage level of node CTL. In another embodiment, during the assembly phase of the display circuit 36 and the control circuit 34, node CTL is connected either to a metal pad of the display circuit 36 receiving supply voltage Vdd or to a metal pad of the display circuit 36 receiving low reference voltage Gnd.B22364PCT – IR00209

[0108] Figure 15 is a bottom view of control circuit 34 of display pixel Pix3. On lower surface 38, display pixel Pix3 comprises nine bonding conductive pads P_Vcc, P_Gnd, P_Row, P_Col, P_CLK_IN, P_DATA_STD_IN, P_CLK_OUT, P_DATA_STD_OUT, and P_Vdd in order to electrically connect display pixel Pix3 with the outside.

[0109] Figure 16 is a schematic view of display screen 60 of Figure 13 showing the connection of the electrodes and the display pixels.

[0110] Display pixels Pix3i,1of the first column, i varying from 2 to M, are programmed so that the demultiplexer 66 provides the signal sent by circuit 64 to pad P_Row. Display pixels Pix31,jof the first row, j varying from 2 to N, are programmed so that the demultiplexer 66 provides the signal sent by circuit 64 to pad P_Col.

[0111] Row electrode E_Row1receives signal Com1from timing controller 18. Column electrode E_Col1receives signal Data1from timing controller 18. For display pixel Pix32,1of the second row and the first column, pads P_CLK_IN, P_DATA_STD_IN are coupled to timing controller 18. Pad P_CLK_IN of display pixel Pix32,1receives signal CLK_ROW from timing controller 18. Pad P_DATA_STD_IN of display pixel Pix32,1receives signal STD from timing controller 18. For display pixel Pix31,2of the first row and the second column, pads P_CLK_IN, P_DATA_STD_IN are coupled to timing controller 18. Pad P_CLK_IN of display pixel Pix31,2receives signal CLK_COL from timing controller 18. Pad P_DATA_STD_IN of display pixel Pix31,2receives signal DATA from timing controller 18.

[0112] For display pixels Pix3i,1of the first column, i varying from 3 to M, pads P_CLK_IN and P_DATA_STD_IN of display pixel Pix3i,1are coupled to display pixel Pix3i-1,1. Pad P_CLK_IN of display pixel Pix3i,1is coupled, preferablyB22364PCT – IR00209    connected, to pad P_CLK_OUT of display pixel Pix3i-1,1. Pad P_DATA_STD_IN of display pixel Pix3i,1is coupled, preferably connected, to pad P_DATA_STD_OUT of display pixel Pix3i-1,1. For display pixels Pix31,jof the first row, j varying from 3 to N, pads P_CLK_IN and P_DATA_STD_IN of display pixel Pix31,jare coupled to display pixel Pix31,j-1. Pad P_CLK_IN of display pixel Pix31,jis coupled, preferably connected, to pad P_CLK_OUT of display pixel Pix31,j-1. Pad P_DATA_STD_IN of display pixel Pix31,jis coupled, preferably connected, to pad P_DATA_STD_OUT of display pixel Pix31,j-1. For all display pixels Pix1i,j, i varying from 2 to M and j varying from 2 to N, pad P_Col of display pixel Pix1i,jis coupled, preferably connected, to pad P_Col of display pixel Pix31,jby column electrode E_Colj, and pad P_Row of display pixel Pix1i,jis coupled, preferably connected, to pad P_Row of display pixel Pix2i,1. by row electrode E_Rowi. For display pixel Pix11,1of the first row and the first column, pad P_Row is coupled, preferably connected, to row electrode E_Row1, and pad P_Col is coupled, preferably connected, to column electrode E_Col1.

[0113] An embodiment of operation of display screen 60 will now be described. By default, each display pixel Pix3i,1of the first column provides signal Comiwithout the row selection pattern. In order to select the display pixels of the first row, timing controller 18 provides signal Com1having the row selection pattern to row electrode E_Row1. In order to select the display pixels of the row of rank i, i varying from 2 to M, timing controller 18 provides signal STD having the row selection pattern to display pixel Pix32,1. When display pixel Pix32,1receives signal STD having the row selection pattern, it sets signal Com2on pad P_Row having the row selection pattern in order to select the display pixels on the second row. Then, signal STD having the row selection pattern is sent to display pixel Pix33,1. Signal STDB22364PCT – IR00209    having the row selection pattern is then transmitted from display pixel Pix3i,1to display pixel Pix3i+1,1. When display pixel Pix3i,1receives signal STD having the row selection pattern, it sets signal Comion pad P_Row having the row selection pattern in order to select the display pixels on the row of rank i. The selected display pixel at row of rank i and column of rank j can therefore store display data Datajprovided by display pixel Pix21,jor Pix11,1for the first column. Signal CLK_ROW is also transmitted from display pixel Pix3i,1to display pixel Pix3i+1,1and can be sent on pad P_Row by each display pixel Pix3i,1of a non-selected row to be used as a timing signal for the control of the light-emitting diodes by the display pixels. For the first row, signal Com1can be used as a timing signal.

[0114] For the display of image pixels on the row of rank i, display data Data1are sent to column electrode E_Col1and display data DATA are serially provided by timing controller 18 to display pixel Pix31,2, clocked by signal CLK_COL, starting from the display data regarding the display pixel DataNat the last column to the display data Data2regarding the display pixel at the second column. Display data DATA are serially transmitted from display pixel Pix31,jto display pixel Pix31,j+1, clocked by signal CLK_COL that is also transmitted from display pixel Pix31,jto display pixel Pix31,j+1, until the display data DataNregarding the display pixel at the last column reach display pixel Pix31,N. At that point, each display pixel Pix31,j, j varying from 2 to N, has received and stored display data Datajconcerning the column of rank j. Each display pixel Pix31,j, j varying from 2 to N, provides display data Datajto pad P_Col.

[0115] Figure 17 partially and schematically shows another embodiment of a display screen 70. Display screen 70 comprises an array 72 of display pixels, for example, arranged in MB22364PCT – IR00209    rows and in N columns, i being an integer varying from 1 to M, and j being an integer varying from 1 to N. In the present embodiment, display screen 70 comprises display pixels Pix1 of the first type (Pixel), display pixels Pix4 of a fourth type (Pixel & Column), and display pixels Pix5 of a fifth type (Pixel & Row). Display pixels Pix4 of the fourth type and display pixels of the fifth type can have the general structure shown in Figure 9. The display pixel Pix11,1of the first column and the first row is a display pixel of the first type. The rest of the first row of array 72 comprises display pixels Pix41,jof the fourth type, j varying from 2 to N. The rest of the first column of array 72 comprises display pixels Pix5i,1of the fifth type, i varying from 2 to M. The others display pixels of array 72 are of the first type. Therefore, array 72 comprises a sub-array of display pixels Pix1i,j, i being an integer varying from 2 to M, and j being an integer varying from 2 to N. Timing controller 18 is configured to send six signals CLK_COL, DATA, CLK_ROW, STD, Data1, and Com1to the array 72 of display pixels. According to an embodiment, each signal CLK_COL, DATA, CLK_ROW, STD, Data1, and Com1is a binary signal.

[0116] In the present embodiment, each display pixel Pix4 of the fourth type, in addition to performing the function of displaying an image pixel, includes a driver circuit that can operate as a column driver circuit providing data signal Dataj. Moreover, each display pixel Pix5 of the fifth type, in addition to performing the function of displaying an image pixel, includes a driver circuit that can operate as a row driver circuit providing selection and timing signal Comi.

[0117] Figure 18 shows a block diagram of an embodiment of control circuit 34 of display pixel Pix4. Control circuit 34 of display pixel Pix4 comprises all the elements of control circuit 34 of display pixel Pix2 shown in Figure 2, exceptB22364PCT – IR00209    that the row driver circuit 50 is not present. Therefore, control circuit 34 of display pixel Pix4 comprises column driver circuit 52 receiving signal CLK_COL, received at pad P_CLK_COL_IN, receiving signal DATA, received at pad P_DATA_IN, providing signal CLK_COL at pad P_CLK_COL_OUT and providing signal DATA at pad P_DATA_OUT.

[0118] Figure 19 is a bottom view of control circuit 34 of display pixel Pix4. On lower surface 38, display pixel Pix4 comprises nine bonding conductive pads P_Vcc, P_Gnd, P_Row, P_Col, P_CLK_COL_IN, P_DATA_IN, P_CLK_COL_OUT, P_DATA_OUT, and P_Vdd in order to electrically connect display pixel Pix4 with the outside.

[0119] Figure 20 shows a block diagram of an embodiment of control circuit 34 of display pixel Pix5. Control circuit 34 of display pixel Pix5 comprises all the elements of control circuit 34 of display pixel Pix2 shown in Figure 2, except that the column driver circuit 52 is not present. Therefore, control circuit 34 of display pixel Pix5 comprises row driver circuit 50 receiving signal CLK_ROW, received at pad P_CLK_ROW_IN, receiving signal STD, received at pad P_STD_IN, providing signal CLK_ROW at pad P_CLK_ROW_OUT and providing signal STD at pad P_STD_OUT.

[0120] Figure 21 is a bottom view of control circuit 34 of display pixel Pix5. On lower surface 38, display pixel Pix5 comprises nine bonding conductive pads P_Vcc, P_Gnd, P_Row, P_Col, P_CLK_ROW_IN, P_STD_IN, P_CLK_ROW_OUT, P_STD_OUT, and P_Vdd in order to electrically connect display pixel Pix5 with the outside.

[0121] Figure 22 is a schematic view of display screen 70 of Figure 17 showing the connection of the electrodes and the display pixels.B22364PCT – IR00209

[0122] Row electrode E_Row1receives signal Com1from timing controller 18. Column electrode E_Col1receives signal Data1from timing controller 18. For display pixel Pix41,2of the first row and the second column, pads P_CLK_COL_IN, P_DATA_IN are coupled to timing controller 18. Pad P_CLK_COL_IN of display pixel Pix41,2receives signal CLK_COL from timing controller 18. Pad P_DATA_IN of display pixel Pix21,2receives signal DATA from timing controller 18. For display pixel Pix52,1of the second row and the first column, pads P_CLK_ROW_IN, P_STD_IN are coupled to timing controller 18. Pad P_CLK_ROW_IN of display pixel Pix52,1receives signal CLK_ROW from timing controller 18. Pad P_STD_IN of display pixel Pix52,1receives signal STD from timing controller 18. For display pixels Pix41,jof the first row, j varying from 3 to N, pads P_CLK_COL__IN and P_DATA_IN of display pixel Pix41,jare coupled to display pixel Pix41,j-1. Pad P_CLK_COL_IN of display pixel Pix41,jis coupled, preferably connected, to pad P_CLK_COL_OUT of display pixel Pix41,j-1. Pad P_DATA_IN of display pixel Pix41,jis coupled, preferably connected, to pad P_DATA_OUT of display pixel Pix41,j-1. For display pixels Pix5i,1of the first column, i varying from 3 to M, pads P_CLK_ROW_IN and P_STD_IN of display pixel Pix5i,1are coupled to display pixel Pix5i-1,1. Pad P_CLK_ROW_IN of display pixel Pix5i,1is coupled, preferably connected, to pad P_CLK_ROW_OUT of display pixel Pix5i-1,1. Pad P_STD_IN of display pixel Pix5i,1is coupled, preferably connected, to pad P_STD_OUT of display pixel Pix5i-1,1. For all display pixels Pix1i,j, i varying from 2 to M and j varying from 2 to N, pad P_Col of display pixel Pix1i,jis coupled, preferably connected, to pad P_Col of display pixel Pix41,jby column electrode E_Colj, and pad P_Row of display pixel Pix1i,jis coupled, preferably connected to pad P_Row of display pixel Pix5i,1by row electrode E_Rowi. For display pixel Pix11,1of the first row and the first column,B22364PCT – IR00209    pad P_Row is coupled, preferably connected, to row electrode E_Row1, and pad P_Col is coupled, preferably connected, to column electrode E_Col1.

[0123] An embodiment of operation of display screen 70 will now be described. By default, each display pixel Pix5i,1of the first column provides signal Comiwithout the row selection pattern. In order to select the display pixels of the first row, timing controller 18 provides signal Com1having the row selection pattern to row electrode E_Row1. In order to select the display pixels of the row of rank i, i varying from 2 to M, timing controller 18 provides signal STD having the row selection pattern to display pixel Pix52,1. When display pixel Pix52,1receives signal STD having the row selection pattern, it sets signal Com2on pad P_Row having the row selection pattern in order to select the display pixels on the second row. Then, signal STD having the row selection pattern is sent to display pixel Pix53,1. Signal STD having the row selection pattern is then transmitted from display pixel Pix5i,1to display pixel Pix5i+1,1. When display pixel Pix5i,1receives signal STD having the row selection pattern, it sets signal Comion pad P_Row having the row selection pattern in order to select the display pixels on the row of rank i. The selected display pixel at row of rank i and column of rank j can therefore store display data Datajprovided by display pixel Pix41,jor Pix11,1for the first column. Signal CLK_ROW is also transmitted from display pixel Pix5i,1to display pixel Pix5i+1,1and can be sent on pad P_Row by each display pixel Pix5i,1of a non-selected row to be used as a timing signal for the control of the light-emitting diodes by the display pixels. For the first row, signal Com1can be used as a timing signal.

[0124] For the display of image pixels on the row of rank i, display data Data1are sent to column electrode E_Col1andB22364PCT – IR00209    display data DATA are serially provided by timing controller 18 to display pixel Pix41,2, clocked by signal CLK_COL, starting from the display data regarding the display pixel DataNat the last column to the display data Data2regarding the display pixel at the second column. Display data DATA are serially transmitted from display pixel Pix41,jto display pixel Pix41,j+1, clocked by signal CLK_COL that is also transmitted from display pixel Pix41,jto display pixel Pix41,j+1, until the display data DataNregarding the display pixel at the last column reach display pixel Pix41,N. At that point, each display pixel Pix41,j, j varying from 2 to N, has received and stored display data Datajconcerning the column of rank j. Each display pixel Pix41,j, j varying from 2 to N, provides display data Datajto pad P_Col.

[0125] Figure 23 partially and schematically shows another embodiment of a display screen 80. Display screen 80 comprises an array 82 of display pixels, for example, arranged in M rows and in N columns, i being an integer varying from 1 to M, and j being an integer varying from 1 to N. In the present embodiment, display screen 80 comprises display pixels Pix1 of the first type (Pixel & Column), display pixels Pix4 of the fourth type (Pixel), and display pixels Pix5 of the fifth type (Pixel & Row). The first row of array 82 comprises display pixels Pix41,jof the fourth type, j varying from 1 to N. The rest of the first column of array 82 comprises display pixels Pix5i,1of the fifth type, i varying from 2 to M. The others display pixels of array 82 are of the first type. Therefore, array 82 comprises a sub-array of display pixels Pix1i,j, i being an integer varying from 2 to M, and j being an integer varying from 2 to N. Timing controller 18 is configured to send five signals CLK_COL, DATA, CLK_ROW, STD, and Com1to the array 82 of display pixels. According to anB22364PCT – IR00209    embodiment, each signal CLK_COL, DATA, CLK_ROW, STD, and Com1is a binary signal.

[0126] Figure 24 is a schematic view of display screen 80 of Figure 23 showing the connection of the electrodes and the display pixels.

[0127] For display pixel Pix41,1of the first row and the first column, pads P_CLK_COL_IN and P_DATA_IN are coupled to timing controller 18, not shown in Figure 24. Pad P_CLK_COL_IN of display pixel Pix41,1receives signal CLK_COL from timing controller 18. Pad P_DATA_IN of display pixel Pix41,1receives signal DATA from timing controller 18. For display pixels Pix41,jof the first row, j varying from 2 to N, pads P_CLK_COL_IN and P_DATA_IN of display pixel Pix41,jare coupled to display pixel Pix41,j-1. Pad P_CLK_COL_IN of display pixel Pix41,jis coupled, preferably connected, to pad P_CLK_COL_OUT of display pixel Pix41,j-1. Pad P_DATA_IN of display pixel Pix41,jis coupled, preferably connected, to pad P_DATA_OUT of display pixel Pix41,j-1.

[0128] For display pixel Pix52,1of the second row and the first column, pads P_CLK_ROW_IN and P_STD_IN are coupled to timing controller 18. Pad P_CLK_ROW_IN of display pixel Pix52,1receives signal CLK_ROW from timing controller 18. Pad P_STD_IN of display pixel Pix52,1receives signal STD from timing controller 18. For display pixels Pix5i,1of the first column, i varying from 3 to M, pads P_CLK_ROW_IN and P_STD_IN of display pixel Pix5i,1are coupled to display pixel Pix5i-1,1. Pad P_CLK_ROW_IN of display pixel Pix5i,1is coupled, preferably connected, to pad P_CLK_ROW_OUT of display pixel Pix5i-1,1. Pad P_STD_IN of display pixel Pix5i,1is coupled, preferably connected, to pad P_STD_OUT of display pixel Pix5i-1,1.B22364PCT – IR00209

[0129] For all display pixels Pix1i,j, i varying from 2 to M and j varying from 2 to N, pad P_Col of display pixel Pix1i,jis coupled, preferably connected, to pad P_Col of display pixel Pix41,jby column electrode E_Colj, and pad P_Row of display pixel Pix1i,jis coupled, preferably connected, to pad P_Row of display pixel Pix5i,1by row electrode E_Rowi.

[0130] An embodiment of operation of display screen 80 will now be described. By default, each display pixel Pix5i,1of the first column provides signal Comiwithout the row selection pattern. In order to select the display pixels of the first row, timing controller 18 provides signal Com1having the row selection pattern to row electrode E_Row1. In order to select the display pixels of the row of rank i, i varying from 2 to M, timing controller 18 provides signal STD having the row selection pattern to display pixel Pix52,1. When display pixel Pix52,1receives signal STD having the row selection pattern, it sets signal Com2on pad P_Row having the row selection pattern in order to select the display pixels on the second row. Then, signal STD having the row selection pattern is sent to display pixel Pix53,1. Signal STD having the row selection pattern is then transmitted from display pixel Pix5i,1to display pixel Pix5i+1,1. When display pixel Pix5i,1receives signal STD having the row selection pattern, it sets signal Comion pad P_Row having the row selection pattern in order to select the display pixels on the row of rank i. The selected display pixel at row of rank i and column of rank j can therefore store display data Datajprovided by display pixel Pix41,j. Signal CLK_ROW is also transmitted from display pixel Pix5i,1to display pixel Pix5i+1,1and can be sent on pad P_Row by each display pixel Pix5i,1of a non-selected row to be used as a timing signal for the control of the light-emitting diodes by the displayB22364PCT – IR00209    pixels. For the first row, signal Com1can be used as a timing signal.

[0131] For the display of image pixels on the row of rank i, display data DATA are serially provided by timing controller 18 to display pixel Pix41,1, clocked by signal CLK_COL, starting from the display data regarding the display pixel DataNat the last column to the display data Data1regarding the display pixel at the first column. Display data DATA are serially transmitted from display pixel Pix41,jto display pixel Pix41,j+1, clocked by signal CLK_COL that is also transmitted from display pixel Pix41,jto display pixel Pix41,j+1, until the display data DataNregarding the display pixel at the last column reach display pixel Pix41,N. At that point, each display pixel Pix41,j, j varying from 1 to N, has received and stored display data Datajconcerning the column of rank j. Each display pixel Pix41,j, j varying from 1 to N, provides display data Datajto pad P_Col.

[0132] Figure 25 partially and schematically shows another embodiment of a display screen 90. Display screen 90 comprises an array 92 of display pixels, for example, arranged in M rows and in N columns, i being an integer varying from 1 to M, and j being an integer varying from 1 to N. In the present embodiment, display screen 90 comprises display pixels Pix1 of the first type (Pixel), display pixels Pix4 of the fourth type (Pixel & Column), and display pixels Pix5 of the fifth type (Pixel & Row). The first column of array 92 comprises display pixels Pix5i,1of the fifth type, i varying from 1 to M. The rest of the first row of array 92 comprises display pixels Pix41,jof the fourth type, j varying from 2 to N. The others display pixels of array 92 are of the first type. Therefore, array 92 comprises a sub-array of display pixels Pix1i,j, i being an integer varying from 2 to M, and j being an integer varying from 2 to N. Timing controller 18 isB22364PCT – IR00209    configured to send five signals CLK_COL, DATA, CLK_ROW, STD, and Data1to the array 92 of display pixels. According to an embodiment, each signal CLK_COL, DATA, CLK_ROW, STD, and Data1is a binary signal.

[0133] Figure 26 is a schematic view of display screen 90 of Figure 25 showing the connection of the electrodes and the display pixels.

[0134] For display pixel Pix51,1of the first row and the first column, pads P_CLK_ROW_IN and P_STD_IN are coupled to timing controller 18, not shown in Figure 26. Pad P_CLK_ROW_IN of display pixel Pix51,1receives signal CLK_ROW from timing controller 18. Pad P_STD_IN of display pixel Pix51,1receives signal STD from timing controller 18. For display pixels Pix5i,1of the first column, i varying from 2 to M, pads P_CLK_ROW_IN and P_STD_IN of display pixel Pix5i,1are coupled to display pixel Pix5i-1,1. Pad P_CLK_ROW_IN of pixel Pix5i,1is coupled, preferably connected, to pad P_CLK_ROW_OUT of display pixel Pix5i-1,1. Pad P_STD_IN of display pixel Pix5i,1is coupled, preferably connected, to pad P_STD_OUT of display pixel Pix5i-1,1.

[0135] For display pixel Pix41,2of the first row and the second column, pads P_CLK_COL_IN and P_DATA_IN are coupled to timing controller 18. Pad P_CLK_COL_IN of display pixel Pix41,2receives signal CLK_COL from timing controller 18. Pad P_DATA_IN of display pixel Pix41,2receives signal DATA from timing controller 18. For display pixels Pix41,jof the first row, j varying from 3 to N, pads P_CLK_COL_IN and P_DATA_IN of display pixel Pix41,jare coupled to display pixel Pix41,j-1. Pad P_CLK_COL_IN of display pixel Pix41,jis coupled, preferably connected, to pad P_CLK_COL_OUT of display pixel Pix41,j-1. Pad P_DATA_IN of display pixel Pix41,jis coupled,B22364PCT – IR00209    preferably connected, to pad P_DATA_OUT of display pixel Pix41,j-1.

[0136] For all display pixels Pix1i,j, i varying from 2 to M and j varying from 2 to N, pad P_Col of display pixel Pix1i,jis coupled, preferably connected, to pad P_Col of display pixel Pix41,jby column electrode E_Colj, and pad P_Row of display pixel Pix1i,jis coupled, preferably connected to pad P_Row of display pixel Pix5i,1by row electrode E_Rowi.

[0137] An embodiment of operation of display screen 90 will now be described. By default, each display pixel Pix5i,1of the first column provides signal Comiwithout the row selection pattern. In order to select the display pixels of the row of rank i, i varying from 1 to M, timing controller 18 provides signal STD having the row selection pattern to display pixel Pix51,1. When display pixel Pix51,1receives signal STD having the row selection pattern, it sets signal Com1on pad P_Row having the row selection pattern in order to select the display pixels on the first row. Then, signal STD having the row selection pattern is sent to display pixel Pix52,1. Signal STD having the row selection pattern is then transmitted from display pixel Pix5i,1to display pixel Pix5i+1,1. When display pixel Pix5i,1receives signal STD having the row selection pattern, it sets signal Comion pad P_Row having the row selection pattern in order to select the display pixels on the row of rank i. The selected display pixel at row of rank i and column of rank j can therefore store display data Datajprovided on column electrode E_Colj. Signal CLK_ROW is also transmitted from display pixel Pix5i,1to display pixel Pix5i+1,1and can be sent on pad P_Row by each display pixel Pix5i,1of a non-selected row to be used as a timing signal for the control of the light-emitting diodes by the display pixels. For the first row, signal Com1can be used as a timing signal.B22364PCT – IR00209

[0138] For the display of image pixels on the row of rank i, display data Data1are sent to column electrode E_Col1and display data DATA are serially provided by timing controller 18 to display pixel Pix41,2, clocked by signal CLK_COL, starting from the display data regarding the display pixel DataNat the last column to the display data Data2regarding the display pixel at the second column. Display data DATA are serially transmitted from display pixel Pix41,jto display pixel Pix41,j+1, clocked by signal CLK_COL that is also transmitted from display pixel Pix41,jto display pixel Pix41,j+1, until the display data DataNregarding the display pixel at the last column reach display pixel Pix41,N. At that point, each display pixel Pix41,j, j varying from 2 to N, has received and stored display data Datajconcerning the column of rank j. Each display pixel Pix41,j, j varying from 2 to N, provides display data Datajto pad P_Col.

[0139] Figure 27 partially and schematically shows another embodiment of a display screen 100. Display screen 100 comprises an array 102 of display pixels, for example, arranged in M rows and in N columns, i being an integer varying from 1 to M, and j being an integer varying from 1 to N. In the present embodiment, display screen 100 comprises display pixels Pix1 of the first type (Pixel), display pixels Pix4 of the fourth type (Pixel & Column), and display pixels Pix5 of the fifth type (Pixel & Row). The display pixel Pix41,1at the first row and the first column is of the fourth type. The rest of the first column of array 102 comprises display pixels Pix5i,1of the fifth type, i varying from 2 to M. The display pixel Pix51,2at the first row and the second column is of the fifth type. The rest of the first row of array 102 comprises display pixels Pix41,jof the fourth type, j varying from 3 to N. The display pixel Pix42,2at the second row and the second column is of the fourth type. The others display pixels ofB22364PCT – IR00209    array 102 are of the first type. Timing controller 18 is configured to send four signals CLK_COL, DATA, CLK_ROW, and STD to array 102 of display pixels. According to an embodiment, each signal CLK_COL, DATA, CLK_ROW, and STD is a binary signal.

[0140] Figure 28 is a schematic view of display screen 100 of Figure 27 showing the connection of the electrodes and the display pixels.

[0141] For display pixel Pix41,1of the first row and the first column, pads P_CLK_COL_IN and P_DATA_IN are coupled to timing controller 18, not shown in Figure 28. Pad P_CLK_COL_IN of display pixel Pix41,1receives signal CLK_COL from timing controller 18. Pad P_DATA_IN of display pixel Pix41,1receives signal DATA from timing controller 18. For display pixel Pix42,2of the second row and the second column, pads P_CLK_COL_IN and P_DATA_IN are coupled to display pixel Pix41,1. Pad P_CLK_COL_IN of display pixel Pix42,2is coupled, preferably connected, to pad P_CLK_COL_OUT of display pixel Pix41,1. Pad P_DATA_IN of display pixel Pix42,2is coupled, preferably connected, to pad P_DATA_OUT of display pixel Pix41,1. For display pixel Pix41,3of the first row and the third column, pads P_CLK_COL_IN and P_DATA_IN are coupled to display pixel Pix42,2. Pad P_CLK_COL_IN of display pixel Pix41,3is coupled, preferably connected, to pad P_CLK_COL_OUT of display pixel Pix42,2. Pad P_DATA_IN of display pixel Pix41,3is coupled, preferably connected, to pad P_DATA_OUT of display pixel Pix42,2. For display pixels Pix41,jof the first row, j varying from 4 to N, pads P_CLK_COL_IN and P_DATA_IN of display pixel Pix41,jare coupled to display pixel Pix41,j-1. Pad P_CLK_COL_IN of display pixel Pix41,jis coupled, preferably connected, to pad P_CLK_COL_OUT of display pixel Pix41,j-1. Pad P_DATA_IN of display pixel Pix41,jis coupled, preferably connected, to pad P_DATA_OUT of display pixel Pix41,j-1.B22364PCT – IR00209

[0142] For display pixel Pix51,2of the first row and the second column, pads P_CLK_ROW_IN and P_STD_IN are coupled to timing controller 18. Pad P_CLK_ROW_IN of display pixel Pix51,2receives signal CLK_ROW from timing controller 18. Pad P_STD_IN of display pixel Pix51,2receives signal STD from timing controller 18. For display pixel Pix52,1of the second row and the first column, pads P_CLK_ROW_IN and P_STD_IN are coupled to display pixel Pix51,2. Pad P_CLK_ROW_IN of display pixel Pix52,1is coupled, preferably connected, to pad P_CLK_ROW_OUT of display pixel Pix51,2. Pad P_STD_IN of display pixel Pix52,1is coupled, preferably connected, to pad P_STD_OUT of display pixel Pix51,2. For display pixels Pix5i,1of the first column, i varying from 3 to M, pads P_CLK_ROW_IN and P_STD_IN of display pixel Pix5i,1are coupled to display pixel Pix5i-1,1. Pad P_CLK_ROW_IN of display pixel Pix5i,1is coupled, preferably connected, to pad P_CLK_ROW_OUT of display pixel Pix5i-1,1. Pad P_STD_IN of display pixel Pix5i,1is coupled, preferably connected, to pad P_STD_OUT of display pixel Pix5i-1,1.

[0143] For all display pixels Pix1i,j, i varying from 2 to M and j varying from 3 to N, pad P_Col of display pixel Pix1i,jis coupled, preferably connected, to pad P_Col of display pixel Pix41,jby column electrode E_Colj. For all display pixels of the second column Pix1i,2, i varying from 3 to M, pad P_Col of display pixel Pix1i,2is coupled, preferably connected, to pad P_Col of display pixel Pix52,2by column electrode E_Col2. For all display pixels Pix1i,j, i varying from 2 to M and j varying from 2 to N, i and j not being simultaneously equal to 2, pad P_Row of display pixel Pix1i,jis coupled, preferably connected to pad P_Row of display pixel Pix5i,1by row electrode E_Rowi.

[0144] An embodiment of operation of display screen 100 will now be described. By default, display pixel Pix51,2and eachB22364PCT – IR00209    display pixel Pix5i,1of the first column provides signal Comiwithout the row selection pattern. In order to select the display pixels of the row of rank i, i varying from 1 to M, timing controller 18 provides signal STD having the row selection pattern to display pixel Pix51,2. When display pixel Pix51,2receives signal STD having the row selection pattern, it sets signal Com1on pad P_Row having the row selection pattern in order to select the display pixels on the first row. Then, signal STD having the row selection pattern is sent to display pixel Pix52,1. Signal STD having the row selection pattern is then transmitted from display pixel Pix5i,1to display pixel Pix5i+1,1. When display pixel Pix5i,1receives signal STD having the row selection pattern, it sets signal Comion pad P_Row having the row selection pattern in order to select the display pixels on the row of rank i. The selected display pixel at row of rank i and column of rank j can therefore store display data Datajprovided on column electrode E_Colj. Signal CLK_ROW is also transmitted from display pixel Pix5i,1to display pixel Pix5i+1,1and can be sent on pad P_Row by each display pixel Pix5i,1of a non-selected row to be used as a timing signal for the control of the light-emitting diodes by the display pixels. For the first row, signal Com1can be used as a timing signal.

[0145] For the display of image pixels on the row of rank i, display data DATA are serially provided by timing controller 18 to display pixel Pix41,1, clocked by signal CLK_COL, starting from the display data regarding the display pixel DataNat the last column to the display data Data1regarding the display pixel at the first column. Display data DATA are serially transmitted from display pixel Pix41,1to display pixel Pix41,2, and from display pixel Pix42,2to display pixel Pix41,3, clocked by signal CLK_COL that is also transmitted from display pixel Pix41,1to display pixel Pix41,2, and fromB22364PCT – IR00209    display pixel Pix42,2to display pixel Pix41,3. Display data DATA are serially transmitted from display pixel Pix41,jto display pixel Pix41,j+1, clocked by signal CLK_COL that is also transmitted from display pixel Pix41,jto display pixel Pix41,j+1, until the display data DataNregarding the display pixel at the last column reach display pixel Pix41,N. At that point, each display pixel Pix41,1, Pix41,2, and Pix41,j, j varying from 3 to N, has received and stored display data Datajconcerning the column of rank j and provides display data Datajto pad P_Col.

[0146] Figure 29 partially and schematically shows another embodiment of a display screen 110. Display screen 110 shown in Figure 29 comprises all the elements of display screen 30 shown in Figure 5 with the difference that display pixels of the second type Pix2 (Pixel & Driver) are not located on the first row and the first column but are located on row of rank i and column of rank j. Therefore, column of rank j of array 32 comprises display pixels of the second type Pix2k,j, k varying from 1 to M, and row of rank i of array 32 comprises display pixels of the second type Pix2i,k, k varying from 1 to N. The others display pixels of array 32 are of the first type Pix1 (Pixel). Timing controller 18 is coupled to display pixel Pix2i,jat row of rank i and column of rank j. Timing controller 18 is configured to send the four signals CLK_COL, DATA, CLK_ROW, STD to display pixel Pix2i,j. This embodiment is of particular interest to manufactures bezel-less screens or bezel-less screen tiles to be assembled.

[0147] In the embodiments previously disclosed, the dimensions of the conductive pads and the layout of conductive pads on lower surface 38 of control circuit 34 of display pixel Pix1, Pix2, Pix3, Pix4, and Pix5 are particularly imposed by the rules of design of the display pixel and byB22364PCT – IR00209    the method of assembly of the display pixels in the display screen.

[0148] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these embodiments can be combined and other variants will readily occur to those skilled in the art. In the embodiment previously described, each display pixel Pix2, Pix3, Pix4, and Pix5 comprises pad P_Vdd that receives inferior supply voltage Vdd. As a variation, inferior supply voltage Vdd can be generated inside control circuit 34 of display pixel Pix2, Pix3, Pix4, and Pix5, for example from supply voltage Vcc. In that case, pad P_Vdd is not present.

[0149] Finally, the practical implementation of the embodiments and variants described herein is within the capabilities of those skilled in the art based on the functional description provided hereinabove.

Claims

B22364PCT – IR00209    CLAIMS 1. A display screen (30; 60; 70; 80; 90; 100) comprising an array of display pixels arranged in rows and in columns, each display pixel comprising at least one light-emitting source (LED_R, LED_G, LED_B), and a light-emitting source driver circuit (45) for driving said light-emitting source, the display pixels including first display pixels (Pix1) and second display pixels (Pix2; Pix3; Pix4; Pix5), at least some of the second display pixels being serially connected in a first succession, each second display pixel of the first succession further comprising a first transmission circuit (50, 52; 64, 66) configured to: -send first display data (Dataj) to the display pixels of the column of said second display pixel and to transmit second display data (DATA) to the following second display pixel of the first succession; or -send a first selection signal (Comi) to the display pixels of the row of said second display pixel and to transmit a second selection signal (STD) to the following second display pixel of the first succession.

2. The display screen of claim 1, wherein each display pixel (Pix1, Pix2; Pix3; Pix4; Pix5) comprises first and second bonding electrically conductive pads (P_Row, P_Col) connected to said light-emitting source driver circuit (45), each second display pixels (Pix2; Pix3; Pix4; Pix5) further comprising third and fourth bonding electrically conductive pads (P_STD_IN, P_DATA_IN, P_DATA_STD_IN, P_STD_OUT, P_DATA_OUT, P_DATA_STD_OUT) connected to said first transmission circuit (50, 52; 64, 66), said first transmission circuit (50, 52; 64, 66) being configured, when the third bonding electrically conductive pad (P_STD_IN, P_DATA_IN, P_DATA_STD_IN) is electricallyB22364PCT – IR00209    connected to the outside of the display pixel, to send a first signal (STD, DATA), received on the third bonding electrically conductive pad (P_STD_IN, P_DATA_IN, P_DATA_STD_IN), to the fourth bonding electrically conductive pad (P_STD_OUT, P_DATA_OUT, P_DATA_STD_OUT), and to send a second signal (Comi, Dataj) to the light- emitting source driver circuit (45) and to one of the first and second bonding electrically conductive pads (P_Row, P_Col), wherein the first signal corresponds to a first selection signal (STD) and wherein the second signal corresponds to a second selection signal (Comi); or wherein the first signal corresponds to first display data (DATA) and wherein the second signal corresponds to second display data (Dataj).

3. The display screen of claim 2, wherein, for each first display pixel (Pix1), the first bonding electrically conductive pad (P_Row) is intended to receive the second selection signal (Comi) and the second bonding electrically conductive pad (P_Col) is intended to receive the second data signal (Dataj).

4. The display screen of claim 3, comprising, for each row, a first electrically conductive track (E_Rowi) connecting the first bonding electrically conductive pads (P_Row) of the first and second display pixels (Pix1, Pix2, Pix3, Pix4, Pix5) of said row, and, for each column, a second electrically conductive track (E_Colj) connecting the second bonding electrically conductive pads (P_Col) of the first and second display pixels (Pix1, Pix2, Pix3, Pix4, Pix5) of said column.

5. The display screen of claim 4, wherein, in the first succession, the fourth bonding electrically conductive padB22364PCT – IR00209    (P_STD_OUT, P_DATA_OUT) of one second display pixel (Pix2; Pix3; Pix4; Pix5) of the first succession is connected to the third bonding electrically conductive pad (P_STD_IN, P_DATA_IN) of the following second display pixel (Pix2; Pix3; Pix4; Pix5) of the first succession.

6. The display screen of claim 5, wherein, for each second display pixel (Pix2; Pix3; Pix4; Pix5) of the first succession, the light-emitting source driver circuit (45) of the second display pixel is configured to receive the second signal (Comi, Dataj) sent by the first transmission circuit (50, 52) of the second display pixel to drive the light-emitting source (LED_R, LED_G, LED_B) and, for each second display pixel (Pix2; Pix3; Pix4; Pix5) not in the first succession, the third bonding electrically conductive pad (P_STD_IN, P_DATA_IN) of the second display pixel is not electrically connected to the outside of the second display pixel and the light-emitting source driver circuit (45) of the second display pixel is configured to receive the second signal (Comi, Dataj), received on the first bonding electrically conductive pad (P_Row), to drive the light-emitting source (LED_R, LED_G, LED_B).

7. The display screen of any one of claims 2 to 6, wherein each second display pixel (Pix2) further comprises a second transmission circuit (52), and fifth and sixth electrically bonding electrically conductive pads (P_DATA_IN, P_DATA_OUT) connected to said second transmission driver circuit (52), said second transmission circuit (52) being configured, when the fifth bonding electrically conductive pad (P_DATA_IN) is electrically connected to the outside of the display pixel, to send a third signal (DATA), received on the fifth bonding electrically conductive pad (P_DATA_IN), to the sixth bonding electrically conductiveB22364PCT – IR00209    pad (P_DATA_OUT), and to send a fourth signal (Dataj) to the light-emitting source driver circuit (45) and to the other of the first and second bonding electrically conductive pads (P_Row, P_Col), wherein the first signal corresponds to the first selection signal (STD), wherein the second signal corresponds to the second selection signal (Comi), wherein the third signal corresponds to the first display data (DATA), wherein the fourth signal corresponds to the second display data (Dataj), wherein the first transmission circuit (50) of each second display pixel of the first succession is configured to send the second selection signal (Comi) to the display pixels of the row of said second display pixel and to transmit the first selection signal (STD) to the following second display pixel of the first succession, wherein at least some of the second display pixels (Pix2; Pix3) are serially connected in a second succession, and wherein the second transmission circuit (52) of each second display pixel (Pix2) of the second succession is configured to send the second display data (Dataj) to the display pixels of the column of said second display pixel and to transmit the first display data (DATA) to the following second display pixel of the second succession.

8. The display screen of claim 7, wherein, in the second succession, the sixth bonding electrically conductive pad (P_DATA_OUT) of one second display pixel (Pix2) of the second succession is connected to the fifth bonding electrically conductive pad (P_DATA_IN) of the following second display pixel (Pix2) of the second succession.

9. The display screen of claim 8, wherein, for each second display pixel (Pix2) of the second succession, the light- emitting source driver circuit (45) of the second displayB22364PCT – IR00209    pixel is configured to receive the fourth signal (Dataj) sent by the second transmission circuit (52) of the second display pixel to drive the light-emitting source (LED_R, LED_G, LED_B) and, for each second display pixel (Pix2) not in the second succession, the fifth bonding electrically conductive pad (P_DATA_IN) of the second display pixel is not electrically connected to the outside of the second display pixel and the light-emitting source driver circuit (45) of the second display pixel is configured to receive the fourth signal (Dataj), received on the first bonding electrically conductive pad (P_Col), to drive the light- emitting source (LED_R, LED_G, LED_B).

10. The display screen of any one of claims 7 to 9, comprising a row and a column of the second display pixels (Pix2), the other display pixels of the display screen being the first display pixels (Pix1).

11. The display screen of any one of claims 2 to 6, wherein the first transmission circuit of each second display pixels (Pix3) comprises a driver electronic circuit (64) and a demultiplexer (ll), said driver electronic circuit (64) being configured to receive the first data signal (DATA) and the first selection signal (STD) and configured to send the second data signal (Dataj) or the second selection signal (Comi) to the demultiplexer (66), said demultiplexer (66) being configured to transmit the second data signal (Dataj) to the second electrically conductive pad (P_Col) or the second selection signal (Comi) to the first electrically conductive pad (P_Row) according to a control signal.

12. The display screen of claim 11, comprising a row and a column of the second display pixels (Pix3) except for one display pixel that is one of the first display pixels (Pix1),B22364PCT – IR00209    the other display pixels of the display screen being the other first display pixels (Pix1).

13. The display screen of any one of claims 2 to 6, wherein the first transmission circuit (52) of each second display pixel (Pix4) of the first succession is configured to send the second data signal (Dataj) to the display pixels of the column of said second display pixel and to transmit the first data signal (DATA) to the following second display pixel of the first succession, wherein the display pixels include third display pixels (Pix5) different from the second display pixels (Pix4), wherein the third display pixels are serially connected in a second succession, and wherein each third display pixel comprises a third transmission circuit (50) configured to send the second selection signal (Comi) to the display pixels of the row of said third display pixel and to transmit the first selection signal (STD) to the following third display pixel of the second succession.

14. The display screen of claim 13, comprising a row of the second display pixels (Pix4) and a column of the third display pixels (Pix5) except for the display pixel at the intersection of said row and said column that is one of the first display pixels (Pix1), the other display pixels of the display screen being the other first display pixels (Pix1).

15. The display screen of claim 13, comprising a row of the second display pixels (Pix4) and a column of the third display pixels (Pix5) except for the display pixel of said row, or comprising a column of the third display pixels (Pix5) and a row of the second display pixels (Pix4) except for the display pixel of said column, the other displayB22364PCT – IR00209    pixels of the display screen being the first display pixels (Pix1).

16. The display screen of claim 13, comprising a row of the second display pixels (Pix4) except for one display pixel of said row that is a third display pixel (Pix5) and a column of the third display pixels (Pix5) except for one display pixel of said column that is a second display pixel (Pix4), the other display pixels of the display screen being the first display pixels (Pix1) except for one display pixel that is a second display pixel (Pix4) or a third display pixel (Pix5).

17. The display screen of any one of claims 1 to 16, wherein each light-emitting source driver circuit (45) comprises a storage circuit for storing at least one digital signal, the light-emitting source driver circuit being configured to drive said light-emitting source (LED_R, LED_G, LED_B) based on the stored digital signal, and to update said stored digital signal from the first data signal (Dataj) upon the detection of a pattern of the first selection signal (Comi).

18. The display screen of claim 17, wherein said light- emitting source driver circuit (45) is configured not to update said stored digital signal from the first data signal (Dataj) when the pattern of the first selection signal (Comi) is not detected.

19. The display screen of any one of claims 1 to 18, wherein each display pixel comprises a stack of a first electronic circuit (34) comprising the light-emitting source driver circuit (45) and a second electronic circuit (36) comprising the light-emitting source (LED_R, LED_G, LED_B).B22364PCT – IR00209    20. A display pixel (Pix2; Pix3; Pix4; Pix5) comprising: -at least one light-emitting source (LED_R, LED_G, LED_B); -a light-emitting source driver circuit (45) for driving said light-emitting source; -first and second bonding electrically conductive pads (P_Row, P_Col) connected to said light-emitting source driver circuit (45); -a first transmission circuit (50, 52; 64, 66); and -third and fourth bonding electrically conductive pads (P_STD_IN, P_DATA_IN, P_DATA_STD_IN, P_STD_OUT, P_DATA_OUT, P_DATA_STD_OUT) connected to said first transmission circuit (50, 52; 64, 66), said first transmission circuit (50, 52; 64, 66) being configured, when the third bonding electrically conductive pad (P_STD_IN, P_DATA_IN, P_DATA_STD_IN) is electrically connected to the outside of the display pixel, to send a first signal (STD, DATA), received on the third bonding electrically conductive pad (P_STD_IN, P_DATA_IN, P_DATA_STD_IN), to the fourth bonding electrically conductive pad (P_STD_OUT, P_DATA_OUT, P_DATA_STD_OUT), and to send a second signal (Comi, Dataj) to the light-emitting source driver circuit (45) and to one of the first and second bonding electrically conductive pads (P_Row, P_Col).

21. The display pixel of claim 20, wherein the light- emitting source driver circuit (45) is configured to receive the second signal (Comi, Dataj) received on said one of the first and second bonding electrically conductive pads (P_Row, P_Col) when the third bonding electrically conductive pad (P_STD_IN, P_DATA_IN) is not electrically connected to the outside of the display pixel.

22. The display pixel of claim 20 or 21, further comprising:B22364PCT – IR00209    -a second transmission circuit (52); and -fifth and sixth electrically bonding electrically conductive pads (P_DATA_IN, P_DATA_OUT) connected to said second transmission circuit (52), said second transmission circuit (52) being configured, when the fifth bonding electrically conductive pad (P_DATA_IN) is electrically connected to the outside of the display pixel, to send a third signal (DATA), received on the fifth bonding electrically conductive pad (P_DATA_IN), to the sixth bonding electrically conductive pad (P_DATA_OUT), and to send a fourth signal (Dataj) to the light-emitting source driver circuit (45) and to the other of the first and second bonding electrically conductive pads (P_Row, P_Col).

23. The display pixel of claim 22, wherein the light- emitting source driver circuit (45) is configured to receive the fourth signal (Dataj) received on said other of the first and second bonding electrically conductive pads (P_Row, P_Col) when the fifth bonding electrically conductive pad (P_DATA_IN) is not electrically connected to the outside of the display pixel.

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