Multiple buck-boost-based ultra-high step-ups DC-DC converters

Abstract

The present disclosure proposes a family of ultra-high step-up DC-DC converters for photovoltaic (PV) systems, fuel cells, switched-mode power supplies, etc. The suggested layouts are made by combining a buck-boost-based input stage with voltage multiplier (VM) cells and coupled-inductors (CI) cells. The VM network of each topology contains an arbitrary number of cells to increase the voltage gain. The proposed topologies are categorized based on the number of their magnetizing components in single-inductor (SI) and dual-inductor (DI) converters. The second inductor of DI converters increases the voltage gain without the need for extreme duty cycles, high coupling ratios, or adding more VM cells.

Description

[0001] Multiple buck-boost-based ultra-high step-ups DC-DC converters

[0002] TECHNICAL FIELD

[0003] The present disclosure particularly relates to ultra-high step-up DC-DC converters. In general, power electronics converters are developed to manipulate the electrical waveforms to produce the required power for a special device or condition the power derived from a special source, such as a PV panel, for grid injection. This invention can be categorized as a DC-to-DC (or simply DC-DC) converter, which is a group of power electronics converters along with DC- AC, AC-DC, and AC-AC converters.

[0004] BACKGROUND

[0005] Renewable energy sources such as photovoltaic (PV) panels, wind turbines, fuel cells, and some other minorities are considered the most remarkable solutions for traditional energy source issues, including their shortage, environmental contamination, global warming, carbon dioxide emissions, etc. However, the low output voltages that PV panels produce, typically lower than 50 V, need to be compensated somehow. A high-step-up DC-DC converter next to the panel is more desirable than having PV cells connected in series due to the shadow effect, soiling effect, and panels mismatch it may cause. The conventional boost converter can be the abovementioned compensator. Nonetheless, its voltage gain characteristics are not very promising, while high values of voltage step-up are required. One of the main goals of power electronics research is to come up with high step-up DC-DC converters that provide high voltage gain at the proper duty cycles, which are usually between 0.3 and 0.7.

[0006] To achieve high voltage gain without increasing the duty cycle, conventional step-up DC- DC converters need to be developed to be more efficient. Accordingly, some techniques, such as switched-capacitor (SC), coupled-inductor (CI), quadratic boost (QB), dual-inductor (DI), and their combinations, have been proposed to enhance the performance of the traditional options.

[0007] The QB converters provide high voltage gain because of the duty cycle (D) squared appears in their voltage gain equations. However, their complex topologies result in complicated analyses and high costs. DI converters refer to converters comprising two inductors, each of which is directly involved in increasing the voltage gain. Each inductor in these converters usually has its own power switch or a couple of diodes to control its operation. It should be pointed out that interleaved structures should not be misunderstood with the DI technique. Interleaving leads to an input current ripple reduction and does not affect the voltage gain of the converter. Finally, VM and CI techniques are considered the most famous methods to increase the voltage gain of the converters.

[0008] SUMMARY

[0009] The present disclosure provides some ultra-high step-up DC-DC converters that can make very high voltage gains with low voltage and current stresses. The undesired issues in DC-DC converters, such as diode reverse recovery, voltage spikes on power switches, and high input currents, are well managed using the inherent characteristics of the proposed topologies or additional circuits. For instance, to suppress the voltage spikes on power switches, passive or active clamp circuits can be added to the converter. Active clamps can provide soft switching capability in addition to spike elimination, which is highly recommended in Ci-based topologies. However, all proposed topologies are presented in their simple form, and soft switching realization using active clamps is not mentioned in this report. A buck-boost-based stage, which is common in all proposed topologies and placed right after the input source, provides more flexibility for adding and designing other stages compared to many other input configurations in DC-DC converters.

[0010] The proposed DI converters of the present disclosure may operate in many different conduction modes, considering that each of their inductors may operate in DCM or CCM. However, there are situations where some inductors in some of the DI converters never operate in DCM. Nevertheless, in some of these topologies, an uncommon type of CCM operation has been observed, which is called imperfect continuous conduction mode (ICCM). In this disclosure, a mathematical approach is presented to analyze the different operational modes of the proposed DI converters and derive the closed-form expressions for voltage gain. Noting that the mentioned conditions may not occur in the case of adding active or passive clamps to, for instance, suppress the voltage spikes or realize the soft switching capability. However, this disclosure concentrates on the analysis of the proposed topologies in their original form, providing the necessary tools for analyzing the converters integrated with other auxiliary circuits.

[0011] BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG. 1 is the general circuit diagram of topology A.

[0013] FIG. 2 is a special case of topology A comprising two VM cells,

[0014] FIG. 3 (a) indicates the key waveforms of the converter of FIG. 2 in CCM,

[0015] FIG. 3 (b) indicates the key waveforms of the converter of FIG. 2 in DCM,

[0016] FIG. 4 shows the equivalent circuits of different operational states of the converter in FIG. 2,

[0017] FIG. 5 is an interleaved version of topology A with two VM cells,

[0018] FIG. 6 is the general circuit diagram of topology B.

[0019] FIG. 7 is the general circuit diagram of topology C.

[0020] FIG. 8 is the general circuit diagram of topology D.

[0021] FIG. 9 demonstrates the key waveforms of topology D having one VM cell on its left side in CCM,

[0022] FIG. 10 is the coupled-inductor of the buck-boost-based stage being modeled by an equivalent inductor. When power switch S i is off,

[0023] FIG. 11 depicts the modeling of a special part of topology D to formulate the current of diode Di,

[0024] FIG. 12 shows the current waveforms of magnetizing inductances of topology D (LmJand Lm2), when both of them operate in DCM,

[0025] FIG. 13 is the general circuit diagram of topology E. FIG. 14 indicates the key waveforms of topology E having one VM cell on its right side in CCM,

[0026] FIG. 15 is a special case of topology E having one VM cell on its right side,

[0027] FIG. 16 (a) shows the key waveforms of topology E in FIG. 15 at the PCCM-ICCM boundary,

[0028] FIG. 16 (b) shows the key waveforms of topology E in FIG. 15 in ICCM,

[0029] FIG. 17 (a) depicts some key waveforms of topology E in FIG. 15 in PCCM,

[0030] FIG. 17 (b) depicts some key waveforms of topology E in FIG. 15 in ICCM,

[0031] FIG. 18 is a linear characteristic of the PCCM-ICCM boundary,

[0032] FIG. 19 shows the equivalent circuits of different operational states of the converter in FIG. 15 in ICCM,

[0033] FIG. 20 shows the current waveform of the equivalent inductor of topology E.

[0034] FIG. 21 shows the current waveforms of the magnetizing inductances of topology E in ICCM in the PSPICE simulator for Vin= 30 V, RL= 500 fl,

[0035] FIG. 22 is an active clamp unit to be connected to a power switch in the proposed topologies,

[0036] FIG. 23 is an interleaved structure of topology C as an example of DI topologies,

[0037] FIG. 24 (a) shows the MOSFET gate-source and drain-source voltages and drain-source current waveforms when Vin= 30 V and Vout=380 V under full load conditions: Pout=300 W,

[0038] FIG. 24 (b) shows the MOSFET gate-source and drain-source voltages and drain-source current waveforms when Vi„= 30 V and Vout=380 V under light load conditions: Pout=70 W,

[0039] FIG. 25 (a) shows the different capacitor voltage waveforms when Vtn= 30 V and VOut=380 V under full load conditions: Pout=300 W, FIG. 25 (a) shows the different capacitor voltage waveforms when V(n= 30 V and Vout=380 V under full load conditions: Pout=300 W,

[0040] FIG. 25 (b) shows the different capacitor voltage waveforms when Vm= 30 V and Vout=380 V under light load conditions: Pout=70 W,

[0041] FIG. 26 (a) shows the different capacitors voltage waveforms when Vin= 30 V and Vmil=380 V under full load conditions: Pout=300 W,

[0042] FIG. 26 (b) shows the different capacitor voltage waveforms, when Vi„= 30 V and Vmil=380 V under light load conditions: Pout=70 W,

[0043] FIG. 27 indicates different waveforms of diode Di under full load condition,

[0044] FIG. 28 indicates different waveforms of diode Di under light load condition,

[0045] FIG. 29 (a) indicates the input and output voltages and input current waveforms of the converter, when Vin=30 V and Vout=380 V under full-load conditions: Pout=300 W,

[0046] FIG. 29 (b) indicates the input and output voltages and input current waveforms of the converter when Vin=30 V and Vout=380 V under light-load condition: Pout=70 W,

[0047] FIG. 30 is the efficiency curve of the prototype converter versus its output power, when Vin=30 V, Vout=380 V, and fs= 50 kHz,

[0048] FIG. 31 demonstrates the voltage gain curves of the proposed topologies in CCM operation.

[0049] DETAILED DESCRIPTION

[0050] The converter 1 in FIG. 1 is called topology A. This converter comprises a buck -boost based input stage 2, a VM network 3, and a resistive load RL. The VM network can contain an arbitrary number of VM cells to obtain high voltage conversion ratios. In the buck -boost-based input stage 2, the input source Vinis connected to the drain of power switch Sy, at its positive polarity, and to the capacitor Cr, at its negative polarity through the conducting path 4. Therefore, it is possible for the input source energy to be transferred to the magnetizing inductance of the coupled inductor. The capacitor Ci, which is connected to the drain of the power switch S i at one end, and to the cathode of diode Di at the other one, and the capacitor Cr, which is connected to the non-dotted end of the primary winding of the coupled inductor at one end, and to the anode of diode Drat the other one, receive the stored energy in the coupled-inductor and participate directly in the voltage gain production of the converter. Diodes Di and Drwhich are connected together at node 5 (cathode of Drto anode of Di) and to the dot of the secondary winding of the coupledinductor, are responsible for processing the stored energy in the mentioned capacitors. Moreover, the dot of the primary winding of the coupled-inductor is connected to its secondary winding at its end, without a dot at the source of the power switch Si. Eventually, the converter 1 is grounded at conducting path 4.

[0051] The VM network 3 comprises n VM cells, which can be divided in n / 2 stages. For instance, the first stage, which is connected to the buck-boost-based network 2, consists of two VM cells. The first cell consists of capacitors Ci and Cvi, and diodes Du and D12, and the second cell consists of capacitors C2 and CV2, and diodes D21 and 22. Capacitors Cviand CV2 in these two cells are connected together in node 5 of the buck-boost-based stage 2. In addition, the first cell is connected to the buck-boost-based stage 2, at the anode of diode D,, through the cathode of diode Du. Moreover, the second cell is connected to it, at the cathode of diode Di, through the anode of diode D21. The next stages will be attached to the first one in a same manner. Finally, a resistive load is connected to them at the cathode of diode Dn2 at one end, and the anode of diode D(n-i)2 at the other one.

[0052] A simple model of the converter, including the diodes1forward resistances, has only two operational states. Therefore, this model is considered in this section to analyze the converter. Although the diodes' forward resistances are added to simplify the converter modeling, their voltage drops have been ignored to obtain the ideal voltage gain expression. To simplify the analysis, the following assumptions are considered:

[0053] Although the power switch is supposed to be ideal and the switching transients are ignored, diodes1forward resistances are added to the converter modeling.

[0054] The voltage ripples of the capacitors are ignored, and all capacitor voltages are assumed to be constant. The coupled-inductor is modeled by a magnetizing inductance Lmi, an ideal transformer comprising a primary winding Np, secondary winding Ns, and a leakage inductance Liki. The transformer turns ratio m and its coupling coefficient ki are defined as follows:

[0055] FIG. 2 depicts a special case of the converter having two VM cells. To simplify the analysis and descriptions, the converter of FIG. 2 is going to be considered in this document. Some key waveforms and different operational states of the converter under its CCM operation are respectively given in FIGs. 3 and 4. Here, these operational states are discussed in summary.

[0056] State I (to-tti) During this operational state, power switch Si and diodes D2, D3, and D, are conducting current. Then, the energy of the input source is transferred to both magnetizing and leakage inductances. The magnetic core's stored energy is then sent to capacitors C2, Ci, and C4 by the coupled-inductor's secondary side. This is done through diodes that are in their conduction mode. The reverse recovery problem of the diodes is significantly reduced due to the leakage inductance of the coupled inductor. The following set of equations explains the behavior of the converter in this state mathematically:

[0057] State II (ti - 12) By turning off the power switch Sy and diodes D2, D3, and D„ the previous operational state is terminated. Afterwards, diodes Di, D4, and D5 turn on, which provide the necessary paths for the capacitors Ci, CV2, and C3 to be charged during this interval. The following set of equations explains the behavior of the converter in this state mathematically: According to the state analysis, key waveforms, and equivalent circuits of each interval, the voltage gain expression of the converter can be derived by considering the volt-second balance principle of the magnetizing inductance. Additionally, setting ki to one will yield the ideal voltage gain expression. To derive the output voltage according to the equivalent circuit of each operational state in FIG. 4, it can simply be written:

[0058] VClis obtainable from the volt-second balance of the magnetizing inductance Lm.

[0059] Moreover, Vc, VCs, and Vccan be found by some straightforward algebraic calculations on (2) and (3). In consequence, the voltage gain of the converter can be expressed as:

[0060] Similarly, the voltage gain of topology A, containing n VM cells, can be expressed as follows:

[0061] > (1 + n)(l + mk

[0062] MCCM,A — 1 n

[0063] Thus, = 1, the ideal voltage gain expression of topology A can be rewritten as:

[0064] _ (l + n)(l + m)

[0065] MCCM,A — — D

[0066] This topology may operate under the DCM, whether leakage inductance is ignored or not. The same approach, which is used for CCM operation, can be used here for calculating the voltage gain of this topology with n number of VM cells in DCM:

[0067] Moreover, for the ideal condition, one can let k be equal to unity. Therefore, it can be written that:

[0068] The CCM-DCM boundary can be identified by equating the average value of the magnetizing inductance current to half of its ripple value, which leads to equations (10) for k = 1. Noting that for a constant load resistance (RL= cte), a boundary inductance (L1B) can be found, while a constant input inductance (Lml= cte) leads to a boundary resistance (RB).

[0069] Therefore, the CCM-DCM boundary can be specified as follows, based on the boundary resistance: operation

[0070] (ID operation

[0071] To complete the mathematical analysis of topology A, the voltage stresses of the power switches, diodes, and capacitors are calculated, here.

[0072] Prior to discussing the second exemplary embodiment of this disclosure, an interleaved version of topology A is presented in FIG. 5. As it was mentioned earlier, interleaving leads to input current ripple reduction and processing more power. According to FIG. 5, interleaving has only been applied on the buck-boost-based stage, and the second stage of the converter remains unchanged. This is recommended due to the very low stresses of the second stage compared to the first one, especially in DI topologies, which makes it unnecessary for the second stage to become interleaved using extra components. Therefore, the interleaved structure will stay the same for all proposed topologies at their buck-boost-based input stage.

[0073] The converter 1 in FIG. 6 is another exemplary embodiment of the present invention, which is called topology B. The buck-boost-based input stage of this converter is the same as topology A. Moreover, the capacitors of the VM cells on each side of this topology experience a different voltage stress compared to the other one. Therefore, this topology comprises m VM cells on the right side and 12 on the left side. The VM stage on the left side is connected to the buck -boost- based stage in the same way suggested for topology A. However, on the right side, an inductor, followed by a power switch to control its operation, is added to the converter. The power switch S2 is connected to the cathode of diode Di in the buck-boost-based stage at its drain. In addition, it is connected to the inductor L2 at its source, which is connected to the anode of diode Di at its other end. The VM stage on the right side is connected to the converter through its first cell. Thus, the cathode of diode Dmis connected to the anode of diode Di, and the available end of the capacitor Cvir is connected to the source of power switch S2. The resistive load is connected to the converter in the same manner discussed for topology A. It has to be pointed out that both power switches in this topology should be fed by synchronized pulses.

[0074] Noting that the mathematical analyses of topologies B and D are very similar. Therefore, to avoid redundancies, a detailed analysis of topology B will be skipped here. Thus, providing its voltage gain characteristic seems sufficient for this section.

[0075] Letting k be unity, results in the ideal voltage gain expression for this topology:

[0076] The converter 1 in Fig. 7 is another exemplary embodiment of the present invention, which is called topology C. The buck-boost-based input stage of this converter is the same as topology A. Moreover, the capacitors of the VM cells on each side of this topology experience a different voltage stress compared to the other one. Therefore, this topology comprises m VM cells on the right side and n.2 on the left side. The VM stage on the right side is connected to the buck -boost- based stage in the same way suggested for topology A. However, on the left side, an inductor, followed by a power switch to control its operation, is added to the converter. The power switch S2 is connected to the anode of diode D2 in the buck-boost stage at its source. In addition, it is connected to the inductor L2 at its drain, which is connected to the cathode of diode D2 through its other end. The VM stage on the left side is connected to the converter through its first cell. Thus, the anode of diode Dm is connected to the cathode of diode D2, and the available end of the capacitor Cm is connected to the drain of power switch S2. The resistive load is connected to the converter in the same way as in topology A. It should be pointed out that the power switches in this topology must operate in opposite modes. Accordingly, the power switch Si has to be turned off while the power switch S2 conducts, and vice versa. Noting that the mathematical analysis of topology E, which is very similar to topology C, will be presented later, completely. Thus, providing the voltage gain characteristic of topology C seems sufficient for this section.

[0077] / n7\ 1 + mfci

[0078] MCCM,C = (1 + ”1 + -^)1_D(I5)

[0079] To obtain the ideal voltage gain,

[0080] The converter 1 in Fig. 8 is another exemplary embodiment of the present invention, which is called topology D. This topology is obtained from topology B by turning the inductor L2 to the primary winding of a coupled inductor, which is called L2,,. This winding is connected to the source of power switch S2 at its non-dotted end. Moreover, the secondary side of this coupled inductor Lm is connected to the anode of diode D3 at its dot and to the cathode of diode D2 at its other end. The cathode of diode D3 is connected to capacitor C3, which is connected to the cathode of diode D2 on the other side. Eventually, the left-side VM stage is connected to the cathode of diode D3 through the anode of diode Dm. The power switches in this topology should be fed the way suggested for topology B. FIG. 9 shows the key waveforms of this topology in CCM. Therefore, the voltage gain expressions of this topology, considering the impact of the leakage inductances, can be formulated as:

[0081] Furthermore, the voltage gain expression of this exemplary embodiment, neglecting the impact of the leakage inductances, can be written as:

[0082] To simplify the analysis, the coupled-inductor of the buck-boost-based stage, which is common for all proposed topologies, can be modeled by an inductor when the power switch is turned off, as depicted in FIG. 10. This equivalent inductor can be found by some straightforward algebraic calculations, as follows:

[0083] Leq= Ltkl+ Lml(l + mJ2« Lml(l + mt)2(19)

[0084] Two magnetizing inductances have been used in topologies B and D. Since each inductor can operate in DCM conditions, there are four possible voltage gain characteristics for each topology. All these possible voltage gain expressions are given for topology D in the DCM condition, for n1= 0 but n2greater than or equal to unity (n2> 1). Initially, the voltage gain of this topology when magnetizing inductances Lmjand Lm2are respectively operating under the DCM and CCM conditions is given as follows:

[0085] In addition, the normalized discharging time duration ofm, under DCM condition can be expressed as follows:

[0086] By considering cut-sets (1) and (2), as identified in FIG. 2, it can be proven that the average current values of the inductor Lm]and the input power source are equal for all topologies, including topology D. Nonetheless, deriving the average current value of an inductor Lm2requires some more calculations. Consequently, FIG. 8 suggests that:

[0087] Using the equivalent inductor modeling in FIG. 11, the current of the diode D1, which is expressed in (23), can be calculated. Now, ILmcan be derived by substituting (23) into (22).

[0088] Therefore, the voltage gain expressions of the two remaining DCM cases can be calculated, accordingly. In these two remaining cases, the ratio m2is considered unity to simplify the expressions. Considering the average current value of the inductor Lm2, the voltage gain of the converter under the DCM condition for this inductor is achieved in the same manner as for inductor Lmj-

[0089] The current waveforms of both magnetizing inductances in DCM are plotted in FIG. 12 simultaneously. Considering the fact that, at the CCM-DCM boundary, the average current values of these magnetizing inductances should be equal to half of their ripple values, normalized time durations d1and d2can be eliminated from the equations. Eventually, the mathematical calculations to find the converter voltage gain expression in the DCM operation mode for both Lmjand Lm2lead to the following quartic equation:

[0090] The voltage gain will be found by solving this quartic equation. In addition, the CCM-DCM boundaries can be characterized in the same manner as those used for topology A. Consequently, the boundary characteristics for Lmjcan be derived as follows:

[0091] Similarly, the CCM-DCM boundary for Lm2can be expressed as:

[0092] Noting that nd RB2CI are the boundary resistances of the magnetizing inductances and Lm2, respectively.

[0093] The buck-boost-based stage is common for all topologies. Thus, the voltages stresses of the rest of the elements of topology D, can be written as follows:

[0094] The converter 1 in Fig. 13 is another exemplary embodiment of the present invention, which is called topology E. This topology is obtained from topology C by turning the inductor L2 to the primary winding of a coupled inductor, which is called L2,,. The dot of this winding is connected to the drain of power switch S2. Moreover, the secondary side of this coupled inductor L2S is connected to the anode of diode Di at its dot, and to the cathode of diode D3 at its other end. The anode of diode D3 is connected to capacitor C3, which is connected to the anode of diode Di on the other side. Eventually, the right side VM stage is connected to the anode of diode D3 through the cathode of diode Dnr. The power switches in this topology should be fed in the way suggested for topology C. FIG. 14 shows the key waveforms of this topology in CCM. The voltage gain expressions of this topology considering the impact of the leakage inductances, can be formulated as:

[0095] Furthermore, the voltage gain expression of this topology, neglecting the impact of the leakage inductances, can be written as:

[0096] It has been observed that the magnetizing inductor k.„2of both topologies C and E can operate under CCM or DCM conditions, while the magnetizing inductor Lmjcan only operate under the CCM condition. In this section, topology E, as given in FIG. 15, for n1= 1 and n2= 0, is going to be analyzed. The inductor Lmjdoes not operate in DCM simply because its current flows through the power switch Sj during the first half cycle, and through the power switch S2during the second one, as depicted in FIG. 13. However, there is a subinterval during the conduction interval of the power switch S2, where all diodes have been turned off. FIG. 17 indicates the current waveforms of both inductors and two diodes of the converter under two different types of CCM. Although only two different operational states occur during a switching period in FIG. 17 (a), FIG. 17 (b) clearly contains three different time subintervals. In fact, FIG. 17 (a) indicates the common familiar CCM operation called perfect CCM (or PCCM) in this section, which leads the uncommon CCM operation in FIG. 17 (b) to be called imperfect CCM (or ICCM). During the latest subinterval of ICCM, all diodes are off and switch S2is still in conduction mode. txand tyin FIG. 17 represent the conduction time durations of diodes D and D4, respectively. The mathematical analysis of topology E in ICCM for both inductors is presented here based on these two-time durations, particularly tx. It has to be mentioned that besides the operational modes shown in FIG. 17, there is another one, which is very similar to FIG. 17 (b) except the inductor Lmjenters its DCM region, too. Although this mode is not discussed in this disclosure, the following analyses will provide a proper approach to performing it, too. Using FIG. 15 and averaging the current waveforms over a switching period, it can be written: According to FIG. 17, txand tyrepresent the conduction time durations of diodes Dj and D4, respectively. Therefore, the equation tx= txb= (1 — £))TSspecifies the PCCM operation, while the inequality tx< txb= (1 — D)TSrelates to ICCM. Consequently, (32) can be used to characterize the PCCM-ICCM boundary. To present a linear boundary, different admittances of topology E are defined as follows:

[0097] Thus, the boundary characteristics can be obtained as follows:

[0098] FIG. 18 depicts the PCCM-ICCM boundary for a specified load resistance value. It should be mentioned that, in spite of the PCCM condition, voltage gain is not constant in ICCM. Finally, y2and yeqparameters in FIG. 18 can be expressed as follows:

[0099] At this point, a proper approach to finding the voltage gain expression of this topology, while both magnetizing inductances Lm]and Lm2operate at ICCM is going to be developed. As mentioned before, the inductance Lm2can operate in DCM, too, which requires more complicated calculations to derive the mathematical expressions. Thus, the DCM operation of the magnetizing inductance Lm2will not be presented. FIG. 19 demonstrates the equivalent circuits of different operational states of the converter in FIG. 15 operating at ICCM.

[0100] Prior to providing the analysis of the converter in this mode of operation, it is worth mentioning that the key parameter of the following calculations is tx. Although txis not one of the independent parameters of the system, it leads to a simple expression for voltage gain. Eventually, txwill be removed from the expressions. Now, to derive the voltage gain expression for ICCM operation of both and Lm2(M]CCM E), using (32), volt-second balance law, constant slopes of the inductors' current waveforms during every interval, and FIGs 16 and 19 we can write: ty — tX(36)

[0101] / 3tx2MICCM,E -5t2 (37) rU Lx

[0102] To eliminate txfrom (39), another relationship is required. Although the equivalent inductor Leqmodeling is valid only when power switch Sj is off according to its definition, it can be extended to the conduction mode of the respected power switch, for our mathematical purposes, as demonstrated in FIG. 20, too. Consequently, its current can be expressed as follows:

[0103] As a result, taking FIG. 20 into consideration will help you find the missing relationship: (40) can be rearranged as a cubic function versus the variable txconsidering (37) and the fact that Vcis proportional to MICCM,E. Therefore, by obtaining the value of tx, the converter voltage gain can be calculated by substituting it into (37).

[0104] At this point, txcan be found by solving equation (42) resulting in a voltage gain expression as a function of only the independent parameters of the system. In addition to voltage gain, the average current value of the inductor Lm2can be calculated by substituting the derived value of txinto the following expression, which is obtained considering FIG. 20:

[0105] In addition, the average current value of Lm2in PCCM can also be derived as follows:

[0106] FIG. 21 shows the current waveforms of the magnetizing inductances in the ICCM powered by the PSPICE simulator. The simulation has been conducted for Vin= 30 7, RL= 500 fl, and D = 0.5 (for both power switches).

[0107] The voltage stresses of the rest of the components of topology E, as shown in FIG. 13, can be derived as follows:

[0108] At this point, a brief description of utilizing an active clamp to realize soft switching will be given. Noting that this is considered a well-known optional technique to add some desirable characteristics such as soft switching, higher efficiency, voltage spike elimination, etc., this is not an inventive feature of the present disclosure. FIG. 22 demonstrates how to connect an active clamp unit to a power switch in the proposed topologies. It is required for the additional power switch to operate in the opposite mode of the main power switch with a dead time. It is necessary to mention that Sc, Cc, and Cr, in FIG. 22, are clamp power switch, clamp capacitor, and resonance capacitor, respectively.

[0109] Prior to presenting some experimental results, interleaving for DI topologies is going to be discussed. The interleaved structure of topology A has been mentioned initially in this section in FIG. 4. Therefore, the interleaved structure of DI topologies can be derived using FIG. 4, in the same manner suggested for deriving their non-interleaved versions from topology A. For instance, the interleaved structure of topology C can be obtained by placing the extra switch-inductor network in the corresponding branch the way FIG. 23 suggests. It is worth mentioning, that the power switch S3should be synchronized to or operate in the opposite mode of the power switch the same branch.

[0110] To make sure that the suggested converters and the analyses work correctly, a prototype of topology A is built. This prototype has only two VM cells, as shown in FIG. 2. The component specifications of the prototype are given in TABLE I. This prototype has been tested under fullload and light-load conditions.

[0111] Some experimental key waveforms of the converter have been plotted in FIGs. 24-29 under the full-load conditions, when input and output voltages are respectively 30 V and 380 V, and 300 W is delivered to the output load. The converter operates at 50 kHz under the CCM condition. FIG. 24 shows the power MOSFET gate-source and drain-source voltages and their drain-source current waveforms under full-load and light-load conditions, respectively. These waveforms clearly show that the power switch operates under a low voltage stress condition. A passive RCD clamp has been used here to eliminate the drain-source voltage ringing. It has to be mentioned that the soft switching characteristic can also be realized using additional active clamp circuits. Nonetheless, it has not been the subject of this report.

[0112] TABLE I

[0113] PROTOTYPE SPECIFICATIONS

[0114] Different capacitor voltage waveforms are also given in FIGs. 25 and 26 under different conditions. In addition, FIGs. 27 and 28 show the voltage, current, and power loss waveforms of diode Dj under the full load condition. The input and output voltage waveforms of the prototype converter, as given in FIG. 29, clearly show the proper voltage conversion process of the converter to achieve the desired output voltage value.

[0115] FIG. 30 indicates the efficiency curve of the implemented converter versus its output power under the nominal input voltage value, which shows that the prototype converter maximum efficiency is approximately equal to 95.7% in practice.

[0116] Voltage gain curves can be plotted using the closed-form expressions of the voltage gain for different proposed topologies. To provide a comparison, all voltage gain characteristics of the proposed topologies are indicated in FIG. 31, for specified values of turns ratios (m = m1= 1.1 and m2= 1).

[0117] At the end, it would be very useful to compare the proposed topologies with state-of-the-art converters. High step-up DC-DC converters have been developed with different characteristics in many journals and patents. Some of the proposed topologies in different patents and research papers with the most desirable characteristics are considered for this section. These converters are going to be compared to each other in different aspects, such as voltage gain and stresses on their components, to provide a proper insight of what they can offer. TABLEs II and III contain the closed form expressions of the voltage gain and the voltage stress of the power switches, as well as the values of some key parameters for these topologies.

[0118] TABLE II

[0119] A MATHEMATICAL COMPARISON BETWEEN SOME HIGH STEP-UP DC-DC CONVERTERS

Claims

ClaimsWhat is claimed is:1- An ultra-high step-up DC-DC converter comprising: a buck-boost based network containing a power switch and a couple of diodes to manipulate the derived energy from the input voltage source, a couple of capacitors to store that energy holding some DC voltage levels, and a coupled-inductor to transfer and distribute the received energy to the mentioned capacitors; a switch-inductor network, which is an inductor connected to a power switch in series, to significantly improve the voltage gain characteristic of the converter; a couple of independent Cockcroft- Walton voltage multiplier networks. One network utilizesvoltage multiplier cells, while the other network incorporates n2cells to achieve even greater voltage gain when necessary.2- The ultra-high step-up DC-DC converter according to claim 1, wherein its buck-boost based network is electrically connected to the positive end of the input voltage source at the drain of its power switch, and to the negative end of said input voltage source at the non-dotted end of the primary side of its coupled-inductor, which is connected to the source of that power switch at its dotted end.3- The ultra-high step-up DC-DC converter according to claim 1, wherein the non-dotted end of the secondary side of the coupled-inductor of its buck-boost based network is connected to the dotted end of the primary side of that coupled-inductor, while its dotted end is connected to a node, where the cathode of one of the diodes of the buck-boost based network meets the anode of the other one.4- The ultra-high step-up DC-DC converter according to claim 1, wherein one of the capacitors of its buck-boost based network is placed in between the positive end of the input voltage source and the available cathode of one of the diodes of the mentioned buck-boost based network, and the other capacitor is placed in between the available anode of the other diode and the negative end of the input voltage source.5- The ultra-high step-up DC-DC converter according to claim 1, wherein its switchinductor network, which consists of an inductor connected to the source of a power switch, is paralleled with one of the diode of the buck-boost based network, which has been connected to the dotted end of the secondary side of the coupled-inductor of the mentioned buck-boost based network, at its cathode.6- The ultra-high step-up DC-DC converter according to claim 1, wherein its Cockcroft- Walton voltage multiplier network containing voltage multiplier cells is connectedto the inductor of its switch-inductor network, through the cathode of the first diode of the voltage multiplier network.7- The ultra-high step-up DC-DC converter according to claim 1, wherein its Cockcroft- Walton voltage multiplier network containing n2voltage multiplier cells is connected to one of the diode of the buck-boost based network, which has been connected to the dotted end of the secondary side of the coupled-inductor of the mentioned buck-boost based network, at its anode, through the anode of its first diode.8- The ultra-high step-up DC-DC converter according to claim 1, which its output terminals are specified by the available ends of the last diodes of each voltage multiplier networks.9- The ultra-high step-up DC-DC converter according to claim 1, wherein its both power switches must be fed by synchronized pulses.10- The ultra-high step-up DC-DC converter according to claim 1, wherein each of its magnetizing components including the magnetizing inductance of the coupled-inductor of the buck-boost based network and the inductor of the switch inductor network, might operate in CCM or DCM, leading to four different modes of operation and four different voltage gain characteristics.11- The ultra-high step-up DC-DC converter according to claim 1, wherein its switchinductor network is shifted to a parallel connection to the other diode of the buck-boost based network from its current place.12- The ultra-high step-up DC-DC converter according to claim 11, wherein its switchinductor network consists of and inductor connected to the drain of a power switch instead of its source.13- The ultra-high step-up DC-DC converter according to claim 11, wherein its power switches must operate in opposite modes.14- The ultra-high step-up DC-DC converter according to claim 11, wherein the inductor of its switch-inductor network might operate in CCM or DCM, while the magnetizing inductance of the coupled-inductor of its buck-boost based network is not able to operate in DCM. However, another mode of operation has been observed for both mentioned magnetizing components called imperfect continuous conduction mode (ICCM). Therefore, three different modes of operation are possible including, CCM operation of both magnetizing components, ICCM operation of both magnetizing components, and DCM operation of only one magnetizing component, which is the inductor of its switch-inductor network.15- The ultra-high step-up DC-DC converter according to claim 1, wherein the inductor of its switch-inductor network turns to the primary side of a coupled-inductor, connected to the source of the power switch of the said switch-inductor network at its non-dotted end.16- The ultra-high step-up DC-DC converter according to claim 15, wherein the dotted end of the secondary side of the coupled-inductor of the switch-inductor network is connected to the anode of an additional diode, which its cathode is connected to one end of an additional capacitor, which its other end is connected to the non-dotted end of the secondary side of the said coupled-inductor, at the cathode of one of the diodes of the buck-boost based network, which its anode is connected to the dotted end of the secondary side of the coupled-inductor of the mentioned buck-boost based network.17- The ultra-high step-up DC-DC converter according to claim 15, wherein its Cockcroft- Walton voltage multiplier network containing n2voltage multiplier cells is paralleled with its diode, which is connected to the secondary side of the coupled-inductor of its switch-inductor network.18- The ultra-high step-up DC-DC converter according to claim 15, wherein its both power switches must be fed by synchronized pulses.19- The mentioned modes of operation of the claim 10 for the ultra-high step-up DC-DC converter of claim 1, is applicable for the ultra-high step-up DC-DC converter of claim 15, too.20- The ultra-high step-up DC-DC converter according to claim 11, wherein the inductor of its switch-inductor network turns to the primary side of a coupled-inductor, connected to the drain of the power switch of the said switch-inductor network at its dotted end.21- The ultra-high step-up DC-DC converter according to claim 20, wherein the non-dotted end of the secondary side of the coupled-inductor of the switch-inductor network is connected to the cathode of an additional diode, which its anode is connected to one end of an additional capacitor, which its other end is connected to the dotted end of the secondary side of the said coupled-inductor, at the anode of one of the diodes of the buck-boost based network, which its cathode is connected to the dotted end of the secondary side of the coupled-inductor of the mentioned buck-boost based network.22- The ultra-high step-up DC-DC converter according to claim 20, wherein its Cockcroft- Walton voltage multiplier network containing voltage multiplier cells is paralleledwith its diode, which is connected to the secondary side of the coupled-inductor of its switch-inductor network.23- The ultra-high step-up DC-DC converter according to claim 20, wherein its power switches must operate in opposite modes.24- The mentioned modes of operation of the claim 14 for the ultra-high step-up DC-DC converter of claim 11, is applicable for the ultra-high step-up DC-DC converter of claim 20, too.

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