Electronic component and method for manufacturing same

Abstract

[Problem to be solved] To improve the reliability of an electronic component including a capacitor provided on a substrate. [Solution] An electronic component 100 comprise: a conductor layer M1 including a conductor pattern 31 which is a lower electrode of a capacitor formed on a region 111 of a substrate 110; a lamination film of an adhesion film 22 and a dielectric film 23 covering the upper surface and the side surface of the conductor pattern 31; a conductor pattern 41 which is an upper electrode of the capacitor covering the upper surface of the conductor pattern 31 via the lamination film; and a dielectric film 24 covering the upper surface and the side surface of the conductor pattern 41 and a portion of the surface of the dielectric film 23 that is not covered with the conductor pattern 41. A region 112 of the substrate 110 is covered with the dielectric film 24 without being covered with the conductor layer M1, the adhesion layer 22, and the dielectric film 23. End surfaces of the adhesion layer 22 and the dielectric film 23 are located on the ends of the region 112 and are covered with the dielectric film 24.

Description

Electronic components and their manufacturing method

[0001] The present disclosure relates to electronic components and methods for manufacturing the same.

[0002] Patent Document 1 discloses an electronic component that includes a capacitor provided on a substrate.

[0003] Japanese Patent Application Laid-Open No. 2021-101480

[0004] However, in the electronic component described in Patent Document 1, the upper and side surfaces of the lower electrode of the capacitor are directly covered with a dielectric film, which causes a problem that peeling easily occurs at the interface between the two.

[0005] This disclosure describes a technique for improving product reliability in an electronic component including a capacitor provided on a substrate and a manufacturing method thereof.

[0006] An electronic component according to one aspect of the present disclosure includes a substrate including a first region in which a lower electrode of a capacitor is formed, a second region in which a first conductor pattern spaced from the capacitor electrode is formed, and a third region located between the first and second regions in which no conductor pattern is formed; a first conductor layer including at least the lower electrode of the capacitor and the first conductor pattern; an adhesive film covering an upper surface and side surfaces of the lower electrode and the first conductor pattern; a first dielectric film covering, via the adhesive film, the upper surface and side surfaces of the lower electrode and the first conductor pattern; and an upper electrode of the capacitor covering a portion of the upper surface of the lower electrode via a first dielectric film; a second dielectric film covering the upper surface and side surfaces of the upper electrode and a portion of the surface of the first dielectric film not covered by the upper electrode; and a first insulating layer covering the first conductor layer and the upper electrode via the second dielectric film, wherein the portion of the upper surface of the lower electrode not covered by the upper electrode and the side surfaces of the lower electrode are covered by an adhesion layer, the first dielectric film, and the second dielectric film, and a third region of the substrate is not covered by the adhesion layer and the first dielectric film but is covered by the second dielectric film.

[0007] An electronic component according to another aspect of the present disclosure comprises a substrate including a first region in which a lower electrode of a capacitor is formed and a second region in which a conductor pattern is not formed, a first conductor layer including the lower electrode of the capacitor formed on the first region of the substrate, an adhesive film covering the upper and side surfaces of the lower electrode, a first dielectric film covering the upper and side surfaces of the lower electrode via the adhesive film, an upper electrode of the capacitor covering the upper surface of the lower electrode via the adhesive film and the first dielectric film, and a second dielectric film covering the upper and side surfaces of the upper electrode and a portion of the surface of the first dielectric film not covered by the upper electrode, wherein the second region of the substrate is covered by the second dielectric film without being covered by the adhesive layer and the first dielectric film, and the end faces of the adhesive layer and the first dielectric film are both located at the ends of the second region, and the end faces are covered by the second dielectric film.

[0008] A method for manufacturing an electronic component according to one aspect of the present disclosure includes the steps of: forming a first conductor layer including a lower electrode of a capacitor on a substrate; depositing an adhesive film over the entire surface to cover the upper and side surfaces of the lower electrode with the adhesive film; depositing a first dielectric film over the entire surface to cover the upper and side surfaces of the lower electrode with the first dielectric film via the adhesive film; forming an upper electrode of the capacitor on the upper surface of the lower electrode via the adhesive film and the first dielectric film; patterning the first dielectric film and the adhesive film to remove the first dielectric film and the adhesive film in at least a portion of an area where the first conductor layer is not formed; and depositing a second dielectric film over the entire surface to cover the upper and side surfaces of the upper electrode, portions of the surface of the first dielectric film not covered by the upper electrode, and portions from which the first dielectric film and the adhesive film have been removed, with the second dielectric film.

[0009] According to the present disclosure, a technique for improving product reliability is provided in an electronic component having a structure in which a capacitor is provided on a substrate and in a manufacturing method thereof.

[0010] FIG. 1 is a schematic perspective view showing the appearance of an electronic component 100 according to an embodiment of the technology disclosed herein. FIG. 2 is a schematic cross-sectional view of the electronic component 100. FIG. 3 is a process diagram for describing a method for manufacturing the electronic component 100. FIG. 4 is a process diagram for describing a method for manufacturing the electronic component 100. FIG. 5 is a process diagram for describing a method for manufacturing the electronic component 100. FIG. 6 is a process diagram for describing a method for manufacturing the electronic component 100. FIG. 7 is a process diagram for describing a method for manufacturing the electronic component 100. FIG. 8 is a process diagram for describing a method for manufacturing the electronic component 100. FIG. 9 is a process diagram for describing a method for manufacturing the electronic component 100. FIG. 10 is a process diagram for describing a method for manufacturing the electronic component 100. FIG. 11 is a process diagram for describing a method for manufacturing the electronic component 100. FIG. 12 is a process diagram for describing a method for manufacturing the electronic component 100.

[0011] Hereinafter, embodiments of the technology according to the present disclosure will be described in detail with reference to the accompanying drawings.

[0012] Fig. 1 is a schematic perspective view showing the appearance of an electronic component 100 according to an embodiment of the technology disclosed herein. Fig. 2 is a schematic cross-sectional view of the electronic component 100.

[0013] 1, the electronic component 100 includes a substrate 110, a functional layer 120 formed on the surface of the substrate 110, and a plurality of terminal electrodes 131 to 134 formed on the surface of the functional layer 120. The number of terminal electrodes is not particularly limited. The material of the substrate 110 is not particularly limited as long as it is chemically and thermally stable, generates little stress, and can maintain a smooth surface. Examples of materials that can be used for the substrate 110 include silicon single crystal, alumina, sapphire, aluminum nitride, MgO single crystal, SrTiO single crystal, surface-oxidized silicon, glass, quartz, ferrite, and organic films.

[0014] In the embodiment shown in Fig. 2, the surface of the substrate 110 is covered with a planarization layer 21. The planarization layer 21 is made of alumina (Al ２ O ３ ), silicon nitride (Si ３ N ４), silicon oxide (SiO ２ The functional layer 120 provided on the substrate 110 includes a planarizing layer 21, and conductor layers M1, MM, and M2 and insulating layers 11 and 12 formed on the planarizing layer 21. The conductor layers M1 and MM are embedded in the insulating layer 11, and the conductor layer M2 is embedded in the insulating layer 12. The insulating layers 11 and 12 can be made of organic insulating materials such as polyimide resin, epoxy resin, or benzocyclobutene resin.

[0015] The conductor layer M1 is the bottommost conductor layer and includes conductor patterns 31 and 32. The conductor pattern 31 is formed on the substrate 110 via a planarization layer 21. In the embodiment illustrated in FIG. 2 , region 111 is the region on the substrate 110 where the conductor pattern 31 is formed. The conductor pattern 32 is formed on the substrate 110 via the planarization layer 21. In the embodiment illustrated in FIG. 2 , region 112 is the region on the substrate 110 where the conductor pattern 32 is formed. In the embodiment illustrated in FIG. 2 , regions 113 to 115 located between region 111 and region 112 do not have any other conductor patterns. Here, the conductor pattern 31 constitutes the lower electrode of the capacitor C. The conductor pattern 32 may be, for example, a connection pattern that connects one circuit element to another, or may be part of a pattern that constitutes an inductor. These conductor patterns 31, 32 are both in contact with the planarizing layer 21 and are composed of a thin seed layer S containing, for example, titanium (Ti), chromium (Cr), or tantalum (Ta), and a plating layer P provided on the seed layer S, which is made of copper (Cu) or the like and has a thickness greater than that of the seed layer S and a resistance value lower than that of the seed layer S. Similarly, the conductor patterns located on the other conductor layers MM, M2 may be composed of, for example, a laminate of a seed layer S and a plating layer P.

[0016] The top surface 31a and side surface 31b of the conductor pattern 31 and the top surface 32a and side surface 32b of the conductor pattern 32 are covered with a dielectric film 23 (sometimes referred to as a first dielectric film) via an adhesive film 22. That is, the top surface 31a and side surface 31b of the conductor pattern 31, which is the lower electrode, and the top surface 32a and side surface 32b of the conductor pattern 32 are covered with the adhesive film 22, and further, the top surface 31a and side surface 31b of the conductor pattern 31, which is the lower electrode, and the top surface 32a and side surface 32b of the conductor pattern 32 are covered with the dielectric film 23 via the adhesive film 22. Here, the top surface 31a of the conductor pattern 31 and the top surface 32a of the conductor pattern 32 are planes approximately parallel to the surface of the substrate 110. The side surface 31b of the conductor pattern 31 and the side surface 32b of the conductor pattern 32 are planes approximately perpendicular to the surface of the substrate 110. Due to manufacturing errors or the like, the top surfaces of the conductor patterns (e.g., top surface 31a of conductor pattern 31 and top surface 32a of pattern 32) may be slightly inclined with respect to the surface of the substrate 110 (e.g., about ±5° with respect to the surface of the substrate 110), which is also included in the range of being approximately parallel. Similarly, the side surfaces of the conductor patterns (e.g., side surface 31b of conductor pattern 31 and side surface 32b of conductor pattern 32) may be slightly inclined with respect to the direction perpendicular to the surface of the substrate 110 (e.g., about ±5° with respect to the direction perpendicular to the surface of the substrate 110), which is also included in the range of being approximately perpendicular. The same applies to other conductor patterns hereinafter in this specification.

[0017] The adhesive film 22 may be made of, for example, titanium (Ti), chromium (Cr), tantalum (Ta), or at least one of their oxides and nitrides. The dielectric film 23 may be made of silicon nitride (Si ３ N ４ ) or other inorganic insulating material. The adhesive film 22 may have higher adhesiveness to the conductor layer M1 and the planarizing layer 21 than the dielectric film 23. The adhesive film 22 is interposed between the conductor patterns 31 and 32 included in the conductor layer M1 and the dielectric film 23, and thus, for example, silicon nitride (Si ３ N ４Peeling at the interface between the dielectric film 23 made of, for example, copper (Cu) and the conductor patterns 31, 32 is suppressed. In particular, the adhesive film 22 covers not only the upper surfaces 31 a, 32 a of the conductor patterns 31, 32 but also the side surfaces 31 b, 32 b, thereby suppressing peeling of the dielectric film 23 over a wide range.

[0018] The laminated film of the adhesive film 22 and the dielectric film 23 is formed not only on the upper surfaces 31a, 32a and side surfaces 31b, 32b of the conductor patterns 31, 32, but also on regions 114, 115 of the substrate 110. In the embodiment illustrated in FIG. 2 , region 114 is a region where the laminated film of the adhesive film 22 and the dielectric film 23 is formed continuously from the side surface 31b of the conductor pattern 31 in a direction parallel to the surface of the substrate 110. Region 114 is located between regions 111 and 112 and adjacent to region 111. For example, the width of region 114 (the length in a direction approximately parallel to the surface of the substrate 110) may be in a range of approximately 0.1 to 2.0 times the thickness of the conductor pattern 31 (the height in a direction approximately perpendicular to the surface of the substrate 110). In the embodiment illustrated in FIG. 2 , region 114 is a region where the laminated film of the adhesive film 22 and the dielectric film 23 is formed continuously from the side surface 32b of the conductor pattern 32 in a direction parallel to the surface of the substrate 110. Region 115 is located between region 112 and region 111 and is adjacent to region 112. Region 113 is a region located between region 114 and region 115. For example, the width of region 115 (the length in a direction substantially parallel to the surface of substrate 110) may be in the range of approximately 0.1 to 2.0 times the thickness of conductor pattern 32 (the height in a direction substantially perpendicular to the surface of substrate 110).

[0019] One of the side surfaces of the conductor pattern 31 is located on the boundary between the region 111 and the region 114. One of the side surfaces of the conductor pattern 32 is located on the boundary between the region 112 and the region 115. Here, the laminated film of the adhesive film 22 and the dielectric film 23 covering the upper surface 31a of the conductor pattern 31, the laminated film of the adhesive film 22 and the dielectric film 23 covering the side surface 31b of the conductor pattern 31, and the laminated film of the adhesive film 22 and the dielectric film 23 covering the region 114 of the substrate 110 are continuously formed. Similarly, the laminated film of the adhesive film 22 and the dielectric film 23 covering the upper surface 32a of the conductor pattern 32, the laminated film of the adhesive film 22 and the dielectric film 23 covering the side surface 32b of the conductor pattern 32, and the laminated film of the adhesive film 22 and the dielectric film 23 covering the region 115 of the substrate 110 are continuously formed.

[0020] In contrast, neither the adhesive film 22 nor the dielectric film 23 is formed on the region 113 located between the regions 114 and 115. As a result, even if the adhesive film 22 is made of a conductive material, the conductor patterns 31 and 32 will not be short-circuited via the adhesive film 22. Furthermore, even if at least one of the adhesive film 22 and the dielectric film 23 is made of a material with high stress, the adhesive film 22 and the dielectric film 23 are removed in the region 113, so stress is released in this portion. The end face 22a of the adhesive film 22 covering the conductor pattern 31 and the end face 23a of the dielectric film 23 are aligned in plan view, and these end faces 22a, 23a are located on the boundary between the region 113 and the region 114. Similarly, the end face 22b of the adhesive film 22 covering the conductor pattern 32 and the end face 23b of the dielectric film 23 are aligned in plan view, and these end faces 22b, 23b are located on the boundary between the region 113 and the region 115.

[0021] A conductor pattern 41 is formed on the upper surface 31a of the conductor pattern 31, with an adhesive film 22 and a dielectric film 23 interposed therebetween. The conductor pattern 41 belongs to a conductor layer MM located between the conductor layers M1 and M2, and constitutes the upper electrode of a capacitor C. This constitutes a capacitor C in which the conductor pattern 31 serves as the lower electrode, the conductor pattern 41 serves as the upper electrode, and the dielectric film 23 serves as a capacitive insulating film. In the embodiment illustrated in Fig. 2, the thickness of the conductor layer MM is thinner than that of the conductor layers M1 and M2, thereby improving the pattern accuracy of the conductor layer MM.

[0022] The top surface 41a and side surface 41b of the conductor pattern 41 constituting the upper electrode, and the portion of the surface of the dielectric film 23 not covered by the conductor pattern 41, are covered with another dielectric film 24 (sometimes referred to as a second dielectric film). Here, the top surface 41a of the conductor pattern 41 is a surface approximately parallel to the surface of the substrate 110. The side surface 41b of the conductor pattern 41 is a surface approximately perpendicular to the surface of the substrate 110.

[0023] The dielectric film 24 is made of silicon nitride (Si ３ N ４ ), or may be made of the same material as the dielectric film 23. The dielectric film 24 serves to prevent direct contact between the conductor pattern 41 and the insulating layer 11 by covering the top surface 41a and side surface 41b of the conductor pattern 41 that constitutes the upper electrode. This is because, if the insulating layer 11 is made of an organic insulating material such as polyimide resin, moisture absorbed into the insulating layer 11 may reduce the reliability of the conductor pattern 41. In this embodiment, the top surface 41a and side surface 41b of the conductor pattern 41 are made of silicon nitride (Si ３ N ４ Since the conductive pattern 41 is covered with the dielectric film 24 made of an inorganic insulating material such as silicon nitride (Si), the moisture resistance is improved, and the reliability of the conductive pattern 41 is enhanced. ３ N ４In the case where the dielectric film 24 is made of silicon nitride (Si ), almost the entire surface of the conductor pattern 41, including the upper surface 41a, the side surface 41b, and the lower surface 41c, is in contact with the same inorganic insulating material, so that local stress is less likely to be applied to the conductor pattern 41. ３ N ４ ) makes it difficult for the metal material such as copper (Cu) that forms the conductor pattern 41 to diffuse into the insulating layer 11 .

[0024] 2, the dielectric film 24 may be formed, for example, on the entire surface. As a result, the dielectric film 24 is formed not only on the upper surface 41a and side surface 41b of the conductor pattern 41, but also on the portion of the surface of the dielectric film 23 that is not covered by the conductor pattern 41, and on the region 113 of the substrate 110 that is not covered by the dielectric film 23. Since the planarizing layer 21 is exposed on the region 113 of the substrate 110, the planarizing layer 21 and the insulating layer 11 are not in direct contact with each other on the region 113 of the substrate 110, with the dielectric film 24 interposed between them. Here, if the planarizing layer 21 is made of, for example, alumina (Al ２ O ３ In the present embodiment, however, the planarization layer 21 exposed on the region 113 of the substrate 110 is made of a material such as silicon nitride (Si) that has a higher adhesiveness to the insulating layer 11 than the planarization layer 21, because the adhesiveness between the two is low. ３ N ４ ) is covered with the dielectric film 24 made of SiO 2 , so that peeling is less likely to occur on the region 113 of the substrate 110 .

[0025] Furthermore, an end face 22a of the adhesive film 22 and an end face 23a of the dielectric film 23 are located on the boundary between the region 113 and the region 114 of the substrate 110. These end faces 22a, 23a are also covered with the dielectric film 24. Similarly, an end face 22b of the adhesive film 22 and an end face 23b of the dielectric film 23 are located on the boundary between the region 113 and the region 115 of the substrate 110. These end faces 22b, 23b are also covered with the dielectric film 24. As a result, the end faces 22a, 22b of the adhesive film 22 are not in direct contact with the insulating layer 11, and therefore corrosion of the adhesive film 22 can be prevented.

[0026] The thickness of the dielectric film 24 may be thinner than the thickness of the dielectric film 23. This is because the dielectric film 23 functions as a capacitive insulating film of the capacitor C, and therefore its thickness is determined by the capacitance required for the capacitor C, and a certain thickness is required to ensure sufficient withstand voltage, whereas the dielectric film 24 is used to protect the conductor pattern 41 and the adhesive film 22 and to prevent peeling on the region 113 of the substrate 110, and therefore these functions can be achieved even if the thickness is thinner than that of the dielectric film 23.

[0027] The conductor layers M1 and MM are embedded in the insulating layer 11 via the dielectric film 24 having such a configuration. The conductor layer M2 is a second conductor layer provided on the surface of the insulating layer 11 and includes a conductor pattern 51. The conductor pattern 51 is connected to the conductor pattern 41, which is the upper electrode of the capacitor C, via a via provided in the insulating layer 11. The conductor layer M2 is embedded in the insulating layer 12. The terminal electrodes 131 to 134 shown in FIG. 1 are provided on the surface of the insulating layer 12, for example.

[0028] As described above, electronic component 100 according to this embodiment includes adhesive film 22, which can prevent peeling at the interface between conductor layer M1 and dielectric film 23. Moreover, since conductor layers M1 and MM are entirely covered with another dielectric film 24, direct contact between conductor layer MM and adhesive film 22 and insulating layer 11 can be prevented, and peeling can be prevented on region 113 of substrate 110 where dielectric film 23 is not present.

[0029] Next, a method for manufacturing the electronic component 100 according to this embodiment will be described.

[0030] 3 to 12 are process diagrams illustrating the manufacturing method of electronic component 100 according to this embodiment. In the manufacturing process of electronic component 100, a large number of electronic components 100 are obtained using an aggregate substrate, but the manufacturing process shown in FIGS. 3 to 12 focuses on a single electronic component 100.

[0031] First, as shown in FIG. 3 , a planarization layer 21 is formed on the surface of the substrate 110 using a sputtering method or the like, and the surface is smoothed by grinding or a mirror-finishing process such as CMP. Thereafter, a seed layer S is formed on the surface of the planarization layer 21 using a sputtering method or the like. Next, as shown in FIG. 4 , a resist layer R1 is spin-coated on the seed layer S, and the resist layer R1 is patterned to expose the seed layer S in the region where the conductor layer M1 is to be formed. The region where the conductor layer M1 is to be formed includes regions 111 and 112 of the substrate 110. In this state, electrolytic plating is performed using the seed layer S as a power source to form a plating layer P on the seed layer S, as shown in FIG. 5 . The stack of the seed layer S and the plating layer P constitutes the conductor layer M1. In the cross section shown in FIG. 5 , the conductor layer M1 includes conductor patterns 31 and 32. Then, as shown in FIG. 6 , the resist layer R1 is removed, and the seed layer S exposed on the surface is removed to complete the conductor layer M1. The seed layer S can be removed by etching such as ion milling.

[0032] Next, as shown in Fig. 7, an adhesive film 22 is formed on the entire surface of the conductor layer M1, including its upper and side surfaces, using a sputtering method or the like. As a result, the upper surface 31a and side surface 31b of the conductor pattern 31, the upper surface 32a and side surface 32b of the conductor pattern 32, and the planarization layer 21 located on regions 113 to 115 of the substrate 110 are covered with the adhesive film 22. Furthermore, as shown in Fig. 8, a dielectric film 23 is formed on the surface of the adhesive film 22. As a result, the upper surface 31a and side surface 31b of the conductor pattern 31 and the upper surface 32a and side surface 32b of the conductor pattern 32 are covered with a laminated film of the adhesive film 22 and the dielectric film 23, and regions 113 to 115 of the substrate 110 where no conductor patterns are formed on the conductor layer M1 are covered with a laminated film of the adhesive film 22 and the dielectric film 23. The dielectric film 23 can be formed by sputtering, plasma CVD, MOCVD, sol-gel method, electron beam evaporation, or the like.

[0033] 9, a conductor pattern 41 is formed on the upper surface 31a of the conductor pattern 31 via an adhesive film 22 and a dielectric film 23 using a method similar to that used to form the conductor layer M1. The conductor pattern 41 is also made of a laminate of a seed layer S and a plating layer P. This completes the conductor layer MM, forming a capacitor C with the conductor pattern 31 as the lower electrode and the conductor pattern 41 as the upper electrode.

[0034] 10 , a resist layer R2 is formed to cover the conductor layer M1 and its periphery, and then the laminated film of the adhesive film 22 and the dielectric film 23 is patterned using the resist layer R2 as a mask. As a result, as shown in FIG. 11 , the dielectric film 23 and the adhesive film 22 on the region 113 of the substrate 110 are successively removed in this order, exposing the planarization layer 21 on the region 113. Because the regions 113 and 114 of the substrate 110 are covered with the resist layer R2, the laminated film of the adhesive film 22 and the dielectric film 23 formed on the regions 113 and 114 of the substrate 110 remains. As a result, an end face 22a of the adhesive film 22 and an end face 23a of the dielectric film 23 are formed on the boundary between the regions 113 and 114 of the substrate 110, and an end face 22b of the adhesive film 22 and an end face 23b of the dielectric film 23 are formed on the boundary between the regions 113 and 115 of the substrate 110.

[0035] Next, after removing the resist layer R2, as shown in FIG. 12 , a dielectric film 24 is formed over the entire surface of the substrate 110 on which the conductor layers M1 and MM have been formed. As a result, the upper surface 41 a and side surface 41 b of the conductor pattern 41 are covered with the dielectric film 24, and the portion of the surface of the dielectric film 23 that is not covered with the conductor layer MM and the surface of the planarization layer 21 exposed in the region 113 of the substrate 110 are also covered with the dielectric film 24. The dielectric film 24 can be formed using the same method as the dielectric film 23. Here, if the thickness of the dielectric film 24 is made thinner than that of the dielectric film 23, the process time required to form the dielectric film 24 can be shortened.

[0036] Thereafter, an insulating layer 11 is formed in which the conductor layers M1 and MM are embedded via a dielectric film 24, and a conductor layer M2 is formed on the surface of the insulating layer 11. Further, an insulating layer 12 is formed in which the conductor layer M2 is embedded, and terminal electrodes 131 to 134 are formed on the surface thereof, thereby completing the electronic component 100 according to this embodiment.

[0037] As described above, in the method for manufacturing electronic component 100 according to this embodiment, adhesive film 22 and dielectric film 23 are successively formed, and then conductor pattern 41, which serves as the upper electrode, is formed without patterning these films. This makes it difficult for foreign matter to get between conductor pattern 31, which serves as the lower electrode, and conductor pattern 41, which serves as the upper electrode. For example, compared to a method in which adhesive film 22 is formed and then patterned before dielectric film 23 is formed, in the method for manufacturing electronic component 100 according to this embodiment, residues of the resist layer used for patterning are less likely to remain on the surface of adhesive film 22. In this embodiment, patterning of adhesive film 22 and dielectric film 23 is not performed until conductor pattern 41 is formed, and the laminated film of adhesive film 22 and dielectric film 23 is patterned after conductor pattern 41 is formed. As a result, compared to a method in which, for example, adhesive film 22 and dielectric film 23 are successively formed and then patterned before forming conductor pattern 41, which is the upper electrode, the method for manufacturing electronic component 100 according to this embodiment makes it less likely that foreign matter, such as residues of a resist layer, will remain between conductor pattern 31, which is the lower electrode, and conductor pattern 41, which is the upper electrode, thereby making it possible to form a capacitor C with higher reliability.

[0038] Furthermore, since the adhesive film 22 and the dielectric film 23 are patterned consecutively using the same resist layer R2, the number of steps can be reduced. Moreover, since the adhesive film 22 and the dielectric film 23 are patterned consecutively, the dielectric film 23 and the planarizing layer 21 do not come into direct contact with each other, and the adhesive film 22 is always interposed between them. This makes it difficult for the dielectric film 23 to peel off, further improving the reliability of the product.

[0039] The above describes embodiments of the technology according to the present disclosure, but the technology according to the present disclosure is not limited to the above embodiments, and various modifications are possible within the scope of the gist of the technology, and it goes without saying that these modifications are also included within the scope of the technology according to the present disclosure.

[0040] The technology according to the present disclosure includes, but is not limited to, the following configuration examples.

[0041] An electronic component according to one aspect of the present disclosure includes a substrate including a first region in which a lower electrode of a capacitor is formed, a second region in which a first conductor pattern spaced from the capacitor electrode is formed, and a third region located between the first and second regions in which no conductor pattern is formed; a first conductor layer including at least the lower electrode of the capacitor and the first conductor pattern; an adhesive film covering an upper surface and side surfaces of the lower electrode and the first conductor pattern; a first dielectric film covering, via the adhesive film, the upper surface and side surfaces of the lower electrode and the first conductor pattern; and a first dielectric film that covers the upper surface and side surfaces of the upper electrode and a portion of the surface of the first dielectric film that is not covered by the upper electrode, and a first insulating layer that covers the first conductor layer and the upper electrode via the second dielectric film, wherein the portion of the upper surface of the lower electrode that is not covered by the upper electrode and the side surfaces of the lower electrode are covered by an adhesion layer, the first dielectric film, and the second dielectric film, and a third region of the substrate is not covered by the adhesion layer and the first dielectric film but is covered by the second dielectric film. This improves the moisture resistance of the upper electrode and makes it less likely that the first insulating layer will peel off on the third region.

[0042] The electronic component may further include a planarization layer covering the surface of the substrate, and the planarization layer provided on the third region of the substrate may be in contact with the second dielectric film. In this case, by selecting a material for the second dielectric film that has higher adhesion to the first insulating layer than the planarization layer, peeling of the first insulating layer on the third region is less likely to occur.

[0043] In the electronic component, the substrate may further include a fourth region located between the first region and the third region and adjacent to the first region, the fourth region of the substrate being covered with an adhesive layer and a first dielectric film, and a first end face of the adhesive layer and a first end face of the first dielectric film located on the fourth region of the substrate are both located on the boundary between the third region and the fourth region, and the first end face may be covered with a second dielectric film. This makes it difficult for the first dielectric film covering the lower electrode to peel off, and prevents corrosion of the adhesive film covering the lower electrode.

[0044] In the electronic component, the substrate may further include a fifth region located between the second region and the third region and adjacent to the second region, the fifth region of the substrate being covered with an adhesive layer and a first dielectric film, and a second end face of the adhesive layer and a second end face of the first dielectric film located on the fifth region of the substrate are both located on the boundary between the third region and the fifth region, and the second end face may be covered with the second dielectric film. This makes it difficult for the first dielectric film covering the first conductor pattern to peel off, and can prevent corrosion of the adhesive film covering the first conductor pattern.

[0045] In the electronic component, the second dielectric film may be thinner than the first dielectric film, thereby ensuring the reliability of the capacitor and shortening the process time required to form the second dielectric film.

[0046] According to another aspect of the present disclosure, an electronic component includes a substrate including a first region where a lower electrode of a capacitor is formed and a second region where a conductor pattern is not formed, a first conductor layer including the lower electrode of the capacitor formed on the first region of the substrate, an adhesive film covering an upper surface and side surfaces of the lower electrode, a first dielectric film covering the upper surface and side surfaces of the lower electrode via the adhesive film, an upper electrode of the capacitor covering the upper surface of the lower electrode via the adhesive film and the first dielectric film, and a second dielectric film covering the upper surface and side surfaces of the upper electrode and a portion of the surface of the first dielectric film not covered by the upper electrode, wherein the second region of the substrate is not covered by the adhesive layer and the first dielectric film but is covered by the second dielectric film, and end faces of the adhesive layer and the first dielectric film are both located at edges of the second region and are covered by the second dielectric film. This improves moisture resistance of the upper electrode, makes it less likely that the first dielectric film will peel off, and prevents corrosion of the adhesive film.

[0047] The electronic component further includes a planarization layer covering the surface of the substrate and a first insulating layer covering the first conductor layer and the upper electrode via a second dielectric film, and the planarization layer provided on the second region of the substrate may be in contact with the second dielectric film without being in contact with the first insulating layer. In this case, by selecting a material for the second dielectric film that has higher adhesion to the first insulating layer than the planarization layer, peeling of the first insulating layer on the second region is less likely to occur.

[0048] In the electronic component, the substrate may further include a third region located between the first region and the second region and adjacent to the first region, the third region of the substrate being covered with an adhesive layer, a first dielectric film, and a second dielectric film, and end faces of the adhesive layer and the first dielectric film are both located on the boundary between the second region and the third region and covered with the second dielectric film. This makes it difficult for the first dielectric film covering the lower electrode to peel off, and prevents corrosion of the adhesive film covering the lower electrode.

[0049] In the electronic component, the second dielectric film may be thinner than the first dielectric film, thereby ensuring the reliability of the capacitor and shortening the process time required to form the second dielectric film.

[0050] A method for manufacturing an electronic component according to one aspect of the present disclosure includes the steps of: forming a first conductor layer including a lower electrode of a capacitor on a substrate; depositing an adhesive film on the entire surface to cover the upper and side surfaces of the lower electrode with the adhesive film; depositing a first dielectric film on the entire surface to cover the upper and side surfaces of the lower electrode with the first dielectric film via the adhesive film; forming an upper electrode of the capacitor on the upper surface of the lower electrode via the adhesive film and the first dielectric film; patterning the first dielectric film and the adhesive film to remove the first dielectric film and the adhesive film from at least a portion of an area where the first conductor layer is not formed; and depositing a second dielectric film on the entire surface to cover the upper and side surfaces of the upper electrode, portions of the surface of the first dielectric film not covered by the upper electrode, and portions from which the first dielectric film and the adhesive film have been removed, with the second dielectric film. This method makes it difficult for foreign matter, such as resist layer residue, to remain between the lower electrode and the upper electrode, thereby enabling the formation of a highly reliable capacitor.

[0051] The method for manufacturing an electronic component described above may further include a step of covering the surface of the substrate with a planarizing layer before forming the first conductor layer, and in the patterning step, the first dielectric film and the adhesive film may be continuously removed until the planarizing layer is exposed, thereby making it possible to pattern the first dielectric film and the adhesive film in a single step.

[0052] The method for manufacturing the electronic component may further include, after forming the second dielectric film, forming a first insulating layer through the second dielectric film to embed the first conductor layer and the upper electrode therein. In this case, by selecting a material for the second dielectric film that has higher adhesion to the first insulating layer than the planarizing layer, peeling of the first insulating layer on the second region is less likely to occur.

[0053] This application claims the benefit of Japanese Patent Application No. 2023-108383, filed on June 30, 2023, the entire disclosure of which is incorporated herein by reference.

[0054] 11, 12 Insulating layer 21 Planarizing layer 22 Adhesion film 22a, 22b End surface of adhesion film 23, 24 Dielectric film 23a, 23b End surface of dielectric film 31, 32, 41, 51 Conductive pattern 31a, 32a, 41a Upper surface of conductive pattern 31b, 32b, 41b Side surface of conductive pattern 41c Lower surface of conductive pattern 100 Electronic component 110 Substrate 111-115 Region 120 Functional layer 131-134 Terminal electrode C Capacitor M1, MM, M2 Conductive layer P Plating layer R1, R2 Resist layer S Seed layer

Claims

1. A substrate including a first region in which a lower electrode of a capacitor is formed, a second region in which a first conductor pattern spaced from the capacitor electrode is formed, and a third region located between the first region and the second region in which no conductor pattern is formed; a first conductor layer including at least the lower electrode of the capacitor and the first conductor pattern; an adhesive film covering an upper surface and side surfaces of the lower electrode and an upper surface and side surfaces of the first conductor pattern; a first dielectric film covering, via the adhesive film, the upper surface and side surfaces of the lower electrode and the upper surface and side surfaces of the first conductor pattern; an upper electrode of the capacitor covering, via the adhesive film and the first dielectric film, a part of the upper surface of the lower electrode; a second dielectric film covering the upper surface and side surfaces of the upper electrode and a part of the surface of the first dielectric film not covered by the upper electrode; and a first insulating layer covering the first conductor layer and the upper electrode via the second dielectric film, an electronic component, wherein a portion of the top surface of the lower electrode not covered by the upper electrode and the side surface of the lower electrode are covered by the adhesion layer, the first dielectric film, and the second dielectric film, and the third region of the substrate is not covered by the adhesion layer and the first dielectric film, but is covered by the second dielectric film.

2. The electronic component according to claim 1, further comprising a planarization layer covering a surface of said substrate, said planarization layer provided on said third region of said substrate being in contact with said second dielectric film.

3. The electronic component of claim 1, wherein the substrate further includes a fourth region located between the first region and the third region and adjacent to the first region, the fourth region of the substrate being covered with the adhesion layer and the first dielectric film, a first end face of the adhesion layer and a first end face of the first dielectric film located on the fourth region of the substrate are both located on the boundary between the third region and the fourth region, and the first end face is covered with the second dielectric film.

4. The electronic component described in claim 3, wherein the substrate further includes a fifth region located between the second region and the third region and adjacent to the second region, the fifth region of the substrate being covered with the adhesion layer and the first dielectric film, a second end face of the adhesion layer and a second end face of the first dielectric film located on the fifth region of the substrate are both located on the boundary between the third region and the fifth region, and the second end face is covered with the second dielectric film.

5. The electronic component according to any one of claims 1 to 4, wherein the second dielectric film is thinner than the first dielectric film.

6. An electronic component comprising: a substrate including a first region in which a lower electrode of a capacitor is formed and a second region in which a conductor pattern is not formed; a first conductor layer including a lower electrode of a capacitor formed on the first region of the substrate; an adhesive film covering an upper surface and side surfaces of the lower electrode; a first dielectric film covering the upper surface and side surfaces of the lower electrode via the adhesive film; an upper electrode of the capacitor covering the upper surface of the lower electrode via the adhesive film and the first dielectric film; and a second dielectric film covering the upper surface and side surfaces of the upper electrode and a portion of the surface of the first dielectric film not covered by the upper electrode, wherein the second region of the substrate is covered by the second dielectric film without being covered by the adhesive layer and the first dielectric film, an end face of the adhesive layer and an end face of the first dielectric film are both located at an end of the second region, and the end face is covered by the second dielectric film.

7. The electronic component according to claim 6, further comprising: a planarization layer covering the surface of the substrate; and a first insulating layer covering the first conductor layer and the upper electrode via the second dielectric film, wherein the planarization layer provided on the second region of the substrate contacts the second dielectric film without contacting the first insulating layer.

8. The electronic component described in claim 7, wherein the substrate further includes a third region located between the first region and the second region and adjacent to the first region and the second region, the third region of the substrate being covered by the adhesion layer, the first dielectric film, and the second dielectric film, and an end face of the adhesion layer and an end face of the first dielectric film are both located on the boundary between the second region and the third region and are covered by the second dielectric film.

9. The electronic component according to claim 6, wherein the second dielectric film is thinner than the first dielectric film.

10. A method for manufacturing an electronic component, comprising: a step of forming a first conductor layer including a lower electrode of a capacitor on a substrate; a step of covering an upper surface and side surfaces of the lower electrode with an adhesive film by forming an adhesive film over the entire surface; a step of covering the upper surface and side surfaces of the lower electrode with the first dielectric film via the adhesive film by forming a first dielectric film over the entire surface; a step of forming an upper electrode of the capacitor on the upper surface of the lower electrode via the adhesive film and the first dielectric film; a step of removing the first dielectric film and the adhesive film in at least a part of an area where the first conductor layer is not formed by patterning the first dielectric film and the adhesive film; and a step of forming a second dielectric film over the entire surface to cover the upper surface and side surfaces of the upper electrode, portions of the surface of the first dielectric film not covered by the upper electrode, and portions from which the first dielectric film and the adhesive film have been removed, with the second dielectric film.

11. The method for manufacturing an electronic component described in claim 10, further comprising a step of covering the surface of the substrate with a planarizing layer before forming the first conductor layer, and in the patterning step, the first dielectric film and the adhesion film are successively removed until the planarizing layer is exposed.

12. The method for manufacturing an electronic component according to claim 10 or 11, further comprising the step of forming a first insulating layer in which the first conductor layer and the upper electrode are embedded via the second dielectric film after forming the second dielectric film.

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