Direct memory access descriptor processing method, system, and apparatus, device, and medium

Abstract

The present application relates to the technical field of field-programmable gate arrays, and discloses a direct memory access descriptor processing method, system, and apparatus, a device, and a medium. The method comprises: acquiring a first direct memory access descriptor to be processed that is transmitted by a target accelerator functional unit; acquiring an existing second direct memory access descriptor; if the first direct memory access descriptor and the second direct memory access descriptor can be merged, merging the first direct memory access descriptor with the second direct memory access descriptor; if not ending the merging operation, returning to the step of acquiring the first direct memory access descriptor to be processed that is transmitted by the target accelerator functional unit and the subsequent steps; and if ending the merging operation, transmitting the second direct memory access descriptor to a peripheral component interconnect express IP core for processing. In the present invention, a field-programmable gate array can process a plurality of direct memory access descriptors at one time, improving computing capability.

Description

Direct memory access descriptor processing method, system, device, equipment and medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on July 19, 2023, with application number 202310884534.4, and application name “Direct Memory Access Descriptor Processing Method, System, Device, Equipment and Medium”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of field programmable gate array technology, and more specifically, to a direct memory access descriptor processing method, system, device, equipment and medium. Background Art

[0004] With the growing demand for computing power from technologies like cloud computing and artificial intelligence, heterogeneous accelerated computing units (CPUs) combined with field-programmable gate array (FPGA) accelerator cards are becoming the mainstream computing unit in data centers. Within the FPGA, the accelerator functional unit (AFU) stores computational results in random access memory (RAM). After each computation, the AFU sends a direct memory access (DMA) descriptor to port 1 of the peripheral component interconnect express (PCI-E) intellectual property core (IP core). Port 3 of the PCI-E IP core then reads the result data from the RAM into host memory. After the memory access operation is complete, port 2 of the PCI-E IP core outputs a completion message to the AFU.

[0005] However, as the computation speed of FPGA accelerator cards continues to increase, the amount of computational result data continues to grow. Each calculation requires transferring the computational result data generated within the FPGA to the host memory. The acceleration function unit quickly sends direct memory access descriptors to port 1 of the Peripheral Device Interconnect (PDI) IP core. However, the PDI IP core's processing efficiency for direct memory access descriptors is limited. Excessive PDI descriptors reduce PDI transmission efficiency, increasing the delay in outputting completion information from port 2 of the PDI IP core. This leads to an accumulation of computational result data, exhaustion of idle pointers, and the suspension of computation by the acceleration function unit, thus reducing the overall computational power of the FPGA accelerator card.

[0006] Summary of the Invention

[0007] The purpose of this application is to provide a method for processing direct memory access descriptors, which can, to a certain extent, solve the technical problem of how to improve the computing power of field programmable AND gate arrays. This application also provides a direct memory access descriptor processing system, device, electronic device, and non-volatile readable storage medium.

[0008] According to a first aspect of an embodiment of the present application, a method for processing a direct memory access descriptor is provided, comprising:

[0009] Acquire a first direct memory access descriptor to be processed transmitted by a target acceleration function unit in a field programmable AND gate array;

[0010] Get the existing second direct memory access descriptor;

[0011] Determining whether the first direct memory access descriptor and the second direct memory access descriptor can be merged;

[0012] If the first direct memory access descriptor and the second direct memory access descriptor can be merged, merging the first direct memory access descriptor into the second direct memory access descriptor;

[0013] Determine whether to end the merge operation;

[0014] If the merging operation is not terminated, returning to the step of obtaining the first direct memory access descriptor to be processed transmitted by the target acceleration function unit in the field programmable AND gate array and subsequent steps;

[0015] If the merging operation is completed, the second direct memory access descriptor is transmitted to the peripheral device fast interconnect IP core in the field programmable and gate array for processing.

[0016] In some embodiments, determining whether the first direct memory access descriptor and the second direct memory access descriptor can be merged includes:

[0017] Get the last direct memory access descriptor merged with the second direct memory access descriptor;

[0018] Determining whether the last direct memory access descriptor and the first direct memory access descriptor can be merged;

[0019] If the last direct memory access descriptor and the first direct memory access descriptor can be merged, then determining that the first direct memory access descriptor and the second direct memory access descriptor can be merged;

[0020] If the last direct memory access descriptor and the first direct memory access descriptor cannot be merged, it is determined that the first direct memory access descriptor and the second direct memory access descriptor cannot be merged.

[0021] In some embodiments, determining whether the last direct memory access descriptor and the first direct memory access descriptor can be merged includes:

[0022] Parsing the first source address, the first destination address, and the first data length value in the final direct memory access descriptor;

[0023] Taking the sum of the first source address and the first data length as the first expected source address;

[0024] Taking the sum of the first destination address and the first data length as the first expected destination address;

[0025] Parsing the second source address and the second destination address in the first direct memory access descriptor;

[0026] If the first expected source address is consistent with the second source address, and the first expected destination address is consistent with the second destination address, then determining that the last direct memory access descriptor and the first direct memory access descriptor can be merged;

[0027] If the first expected source address is inconsistent with the second source address and / or the first expected destination address is inconsistent with the second destination address, it is determined that the tail DMA descriptor cannot be merged with the first DMA descriptor.

[0028] In some embodiments, after merging the first direct memory access descriptor into the second direct memory access descriptor, the method further includes:

[0029] The first direct memory access descriptor is stored as the latest last direct memory access descriptor.

[0030] In some embodiments, determining whether the first direct memory access descriptor and the second direct memory access descriptor can be merged includes:

[0031] Parsing a third source address, a third destination address, and a third data length value in the second direct memory access descriptor;

[0032] Taking the sum of the third source address and the third data length as the second expected source address;

[0033] The sum of the third destination address and the third data length is used as the second expected destination address;

[0034] Parsing the second source address and the second destination address in the first direct memory access descriptor;

[0035] If the second expected source address is consistent with the second source address, and the second expected destination address is consistent with the second destination address, determining that the first direct memory access descriptor and the second direct memory access descriptor can be merged;

[0036] If the second expected source address is inconsistent with the second source address and / or the second expected destination address is inconsistent with the second destination address, it is determined that the first direct memory access descriptor and the second direct memory access descriptor cannot be merged.

[0037] In some embodiments, merging the first direct memory access descriptor into the second direct memory access descriptor includes:

[0038] Parsing a third data length value in the second direct memory access descriptor;

[0039] Parsing a second data length value in the first direct memory access descriptor;

[0040] Calculating a sum of the third data length value and the second data length value;

[0041] The source address and the destination address of the second direct memory access descriptor are kept unchanged, and the sum is used as the latest data length value of the second direct memory access descriptor.

[0042] In some embodiments, the initial second direct memory access descriptor is empty, and a result of merging the initial second direct memory access descriptor and the first first direct memory access descriptor of the merging operation is set to be the first first direct memory access descriptor itself.

[0043] In some embodiments, after obtaining a first direct memory access descriptor to be processed transmitted by a target acceleration function unit in a field programmable AND gate array and before obtaining an existing second direct memory access descriptor, the method further includes:

[0044] Determining whether the first direct memory access descriptor is the first direct memory access descriptor of the merge operation;

[0045] If the first direct memory access descriptor is the first direct memory access descriptor of the merge operation, the first direct memory access descriptor is used as the second direct memory access descriptor, and the steps of obtaining the first direct memory access descriptor to be processed transmitted by the target acceleration function unit in the field programmable AND gate array and subsequent steps are returned;

[0046] If the first direct memory access descriptor is not the first direct memory access descriptor of the merge operation, the steps of obtaining the existing second direct memory access descriptor and subsequent steps are executed.

[0047] In some embodiments, further comprising:

[0048] The target identification information of each first direct memory access descriptor of the merge operation is recorded.

[0049] In some embodiments, after transmitting the second direct memory access descriptor to the peripheral device fast interconnect IP core in the field programmable AND gate array for processing, the method further includes:

[0050] receiving first information of a second direct memory access descriptor transmitted by a peripheral device fast interconnect IP core and completing the characterization processing;

[0051] Based on the target identification information, second information indicating that the corresponding first direct memory access descriptor has been processed is transmitted to the target acceleration function unit.

[0052] In some embodiments, based on the target identification information, transmitting second information indicating that the corresponding first direct memory access descriptor has been processed to the target acceleration function unit includes:

[0053] parsing identification information of a second direct memory access descriptor in the second information;

[0054] If the identification information of the second direct memory access descriptor is consistent with the target identification information, a step of transmitting second information indicating that the corresponding first direct memory access descriptor has been processed to the target acceleration function unit based on the target identification information is performed.

[0055] In some embodiments, recording target identification information of each first direct memory access descriptor of a merge operation includes:

[0056] If the identification information between the first direct memory access descriptors is continuous, then recording the first identification of the first first direct memory access descriptor of the merge operation, and recording the number of first direct memory access descriptors merged by the merge operation;

[0057] The first identifier and the number are used as target identifier information.

[0058] In some embodiments, transmitting the second direct memory access descriptor to a peripheral device fast interconnect IP core in a field programmable AND gate array for processing includes:

[0059] The second direct memory access descriptor is transmitted to the peripheral device fast interconnect IP core for processing through the first port of the peripheral device fast interconnect IP core.

[0060] In some embodiments, receiving first information of a second direct memory access descriptor transmitted by a peripheral device express interconnect IP core and completing processing includes:

[0061] The first information indicating that the second direct memory access descriptor transmitted by the peripheral device fast interconnect IP core is received through the second port of the peripheral device fast interconnect IP core.

[0062] In some embodiments, further comprising:

[0063] The processing state of the first direct memory access descriptor is recorded by the state machine.

[0064] In some embodiments, after determining whether the first direct memory access descriptor and the second direct memory access descriptor can be merged, the method further includes:

[0065] If the first direct memory access descriptor and the second direct memory access descriptor cannot be merged, the second direct memory access descriptor is transmitted to the peripheral device fast interconnect IP core for processing, the first direct memory access descriptor is used as the second direct memory access descriptor, and the execution is returned to obtain the first direct memory access descriptor transmitted by the target acceleration function unit in the field programmable and gate array and subsequent steps.

[0066] According to a second aspect of an embodiment of the present application, a direct memory access descriptor processing system is provided, comprising:

[0067] A first acquisition module is used to acquire a first direct memory access descriptor to be processed transmitted by a target acceleration functional unit in a field programmable AND gate array;

[0068] A second acquisition module, configured to acquire an existing second direct memory access descriptor;

[0069] a first determining module, configured to determine whether the first direct memory access descriptor and the second direct memory access descriptor can be merged; if the first direct memory access descriptor and the second direct memory access descriptor can be merged, merging the first direct memory access descriptor into the second direct memory access descriptor;

[0070] The second judgment module is used to determine whether to terminate the merging operation; if the merging operation is not terminated, the first acquisition module is controlled to return to execute the steps of acquiring the first direct memory access descriptor to be processed transmitted by the target acceleration functional unit in the field programmable AND gate array and subsequent steps; if the merging operation is terminated, the second direct memory access descriptor is transmitted to the peripheral device fast interconnect IP core in the field programmable AND gate array for processing.

[0071] According to a third aspect of an embodiment of the present application, a direct memory access descriptor processing device is provided, comprising:

[0072] A first first-in-first-out memory connected to the target acceleration function unit in the field programmable AND gate array, used for storing a first direct memory access descriptor to be processed transmitted by the target acceleration function unit;

[0073] a merge controller connected to the first FIFO memory and the second FIFO memory, configured to determine whether a first direct memory access descriptor and a second direct memory access descriptor stored in the second FIFO memory can be merged; if the first direct memory access descriptor and the second direct memory access descriptor can be merged, merging the first direct memory access descriptor into the second direct memory access descriptor in the second FIFO memory; determining whether to terminate the merge operation; if the merge operation is not terminated, returning to the step of determining whether the first direct memory access descriptor and the second direct memory access descriptor can be merged and subsequent steps after the first direct memory access descriptor stored in the first FIFO memory is updated; and if the merge operation is terminated, transmitting the second direct memory access descriptor stored in the second FIFO memory to a peripheral device fast interconnect IP core in a field programmable AND gate array for processing;

[0074] The second first-in first-out memory is used to store the existing second direct memory access descriptor.

[0075] In some embodiments, it further includes:

[0076] The direct memory access descriptor register connected to the first FIFO memory and the merge controller is used to store the first direct memory access descriptor as the latest tail direct memory access descriptor.

[0077] In some embodiments, it further includes:

[0078] a third FIFO memory connected to the second FIFO memory, and configured to record target identification information of each first direct memory access descriptor of the merge operation;

[0079] a fourth FIFO memory connected to the third FIFO memory, for recording a number of values ​​of the first direct memory access descriptors merged by the merge operation;

[0080] The counter connected to the fourth FIFO memory and the target acceleration functional unit is used to record the quantity value of the second information transmitted to the target acceleration functional unit, indicating that the corresponding first direct memory access descriptor has been processed.

[0081] According to a fourth aspect of the embodiments of the present application, there is provided an electronic device, including:

[0082] Memory for storing computer programs;

[0083] A processor is used to implement the steps of any of the above direct memory access descriptor processing methods when executing a computer program.

[0084] According to a fifth aspect of an embodiment of the present application, a non-volatile readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above direct memory access descriptor processing methods are implemented.

[0085] The present application provides a direct memory access descriptor processing method, which includes obtaining a first direct memory access descriptor to be processed transmitted by a target acceleration function unit in a field programmable AND gate array; obtaining an existing second direct memory access descriptor; determining whether the first direct memory access descriptor and the second direct memory access descriptor can be merged; if the first direct memory access descriptor and the second direct memory access descriptor can be merged, merging the first direct memory access descriptor into the second direct memory access descriptor; determining whether to terminate the merging operation; if the merging operation is not terminated, returning to the step of obtaining the first direct memory access descriptor to be processed transmitted by the target acceleration function unit in the field programmable AND gate array and subsequent steps; if the merging operation is terminated, transmitting the second direct memory access descriptor to a peripheral device fast interconnect IP core in the field programmable AND gate array for processing. The present application can merge the direct memory access descriptors transmitted by the target acceleration function unit and transmit the second direct memory access descriptor to a peripheral device fast interconnect IP core for processing, so that the field programmable AND gate array can process multiple direct memory access descriptors at one time, thereby improving the processing efficiency of the field programmable AND gate array for direct memory access descriptors and thereby improving the computing power of the field programmable AND gate array. The direct memory access descriptor processing system, device, electronic device and non-volatile readable storage medium provided in this application also solve the corresponding technical problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0086] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0087] FIG1 is a first schematic diagram of a direct memory access descriptor processing method provided by an embodiment of the present application;

[0088] FIG2 is a second schematic diagram of a direct memory access descriptor processing method provided by an embodiment of the present application;

[0089] FIG3 is a schematic structural diagram of a direct memory access descriptor processing system provided in an embodiment of the present application;

[0090] FIG4 is a schematic structural diagram of a direct memory access descriptor processing device provided in an embodiment of the present application;

[0091] FIG5 is a schematic diagram of a state machine of a direct memory access descriptor processing device;

[0092] FIG6 is a schematic diagram showing the connection of a field programmable gate array;

[0093] FIG7 is a schematic diagram of the internal structure of a field programmable AND gate array;

[0094] FIG8 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0095] FIG9 is another schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0096] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0097] Please refer to FIG1 , which is a first schematic diagram of a direct memory access descriptor processing method provided in an embodiment of the present application.

[0098] Some embodiments of the present application provide a method for processing a direct memory access descriptor, which may include the following steps:

[0099] Step S101: obtaining a first direct memory access descriptor to be processed transmitted by a target acceleration function unit in a field programmable AND gate array.

[0100] In actual applications, the first direct memory access descriptor to be processed transmitted by the target acceleration functional unit in the field programmable AND gate array can be obtained first. The number of target acceleration functional units, the type of the first direct memory access descriptor, etc. can be determined according to actual needs.

[0101] Step S102: Obtain an existing second direct memory access descriptor.

[0102] In actual applications, after obtaining the first direct memory access descriptor, the existing second direct memory access descriptor may also be obtained, so as to subsequently merge the first direct memory access descriptor with the second direct memory access descriptor.

[0103] It should be noted that the existing second direct memory access descriptor is a direct memory access descriptor that existed before the first direct memory access descriptor was received, and the content of the second direct memory access descriptor can be determined at different times during the merge operation. For example, when the merge operation starts, the second direct memory access descriptor can be the first direct memory access descriptor received; and after the merge operation starts, the second direct memory access descriptor refers to the result obtained by merging multiple direct memory access descriptors in the process of processing the direct memory access descriptors according to the method of the present application, that is, the merged result obtained before processing the first direct memory access descriptor. In addition, it should be noted that the first direct memory access descriptor and the second direct memory access descriptor in the present application are determined according to the type of merge operation, that is, the first direct memory access descriptor refers to the direct memory access descriptor transmitted by the target acceleration functional unit to participate in the merge operation, and the second direct memory access descriptor refers to the merged result of a single direct memory access descriptor or multiple direct memory access descriptors obtained before the first direct memory access descriptor during the merge operation.

[0104] Step S103: determining whether the first direct memory access descriptor and the second direct memory access descriptor can be merged; if the first direct memory access descriptor and the second direct memory access descriptor can be merged, executing step S104; if the first direct memory access descriptor and the second direct memory access descriptor cannot be merged, executing step S107.

[0105] Step S104: Merge the first direct memory access descriptor into the second direct memory access descriptor.

[0106] In actual applications, after obtaining the first direct memory access descriptor and the existing second direct memory access descriptor, it can be determined whether the first direct memory access descriptor and the second direct memory access descriptor can be merged; if the first direct memory access descriptor and the second direct memory access descriptor can be merged, the first direct memory access descriptor can be merged into the second direct memory access descriptor to obtain the latest second direct memory access descriptor.

[0107] In actual applications, in the process of determining whether the first direct memory access descriptor and the second direct memory access descriptor can be merged, in order to quickly perform the merge determination, the last direct memory access descriptor that the second direct memory access descriptor is merged with can be obtained; and it is determined whether the last direct memory access descriptor and the first direct memory access descriptor can be merged; if the last direct memory access descriptor and the first direct memory access descriptor can be merged, it is determined that the first direct memory access descriptor and the second direct memory access descriptor can be merged; if the last direct memory access descriptor and the first direct memory access descriptor cannot be merged, it is determined that the first direct memory access descriptor and the second direct memory access descriptor cannot be merged.

[0108] In a specific application scenario, in the process of determining whether the last direct memory access descriptor and the first direct memory access descriptor can be merged, the first source address, the first destination address and the first data length value in the last direct memory access descriptor can be parsed; the sum of the first source address and the first data length value is used as the first expected source address; the sum of the first destination address and the first data length value is used as the first expected destination address; the second source address and the second destination address in the first direct memory access descriptor are parsed; if the first expected source address is consistent with the second source address and the first expected destination address is consistent with the second destination address, then it is determined that the last direct memory access descriptor and the first direct memory access descriptor can be merged; if the first expected source address is inconsistent with the second source address and / or the first expected destination address is inconsistent with the second destination address, then it is determined that the last direct memory access descriptor and the first direct memory access descriptor cannot be merged. In addition, in an actual application scenario, after merging the first direct memory access descriptor into the second direct memory access descriptor, the first direct memory access descriptor can also be stored as the latest last direct memory access descriptor so that the last direct memory access descriptor can be quickly obtained during the next round of merging operations.

[0109] In a specific application scenario, in the process of determining whether the first direct memory access descriptor and the second direct memory access descriptor can be merged, in order to simplify the merging judgment operation, the third source address, the third destination address and the third data length value in the second direct memory access descriptor can be parsed; the sum of the third source address and the third data length value is used as the second expected source address; the sum of the third destination address and the third data length value is used as the second expected destination address; the second source address and the second destination address in the first direct memory access descriptor are parsed; if the second expected source address is consistent with the second source address, and the second expected destination address is consistent with the second destination address, then it is determined that the first direct memory access descriptor and the second direct memory access descriptor can be merged; if the second expected source address is inconsistent with the second source address and / or the second expected destination address is inconsistent with the second destination address, then it is determined that the first direct memory access descriptor and the second direct memory access descriptor cannot be merged.

[0110] Step S105: Determine whether to end the merge operation; if not, return to step S101. If the merge operation is ended, execute step S106.

[0111] Step S106: Transmit the second direct memory access descriptor to the peripheral device fast interconnect intellectual property core in the field programmable AND gate array for processing.

[0112] In practical applications, considering that multiple direct memory access descriptors may need to be merged, after merging the first direct memory access descriptor into the second direct memory access descriptor, it can be determined whether the merging operation is terminated. If the merging operation is not terminated, the process returns to step S101 to obtain the latest first direct memory access descriptor for merging. If the merging operation is terminated, the final second direct memory access descriptor can be transmitted to the peripheral device interconnect IP core in the field programmable and gate array for processing.

[0113] It should be noted that the conditions for terminating the merge operation can be determined according to the specific application scenario. For example, the condition for terminating the merge operation can be that the number of direct memory access descriptors merged in the second direct memory access descriptor reaches a preset number. During this process, the number of first direct memory access descriptors participating in the merge operation can be recorded and updated in real time. After the recorded number reaches the preset number, it is determined that the merge operation is terminated. Taking the preset number of 5 as an example, the 5 direct memory access descriptors transmitted by the target acceleration functional unit are merged, and then the merge operation is terminated. For example, the condition for terminating the merge operation can be that the target acceleration functional unit no longer transmits the first direct memory access descriptor, etc. During this process, the target acceleration functional unit can be received. After the first direct memory access descriptor is transmitted by the target acceleration function unit, timing can be started. If no new first direct memory access descriptor is received from the target acceleration function unit within the preset time, it can be determined that the target acceleration function unit no longer transmits the first direct memory access descriptor. Alternatively, after receiving the end instruction transmitted by the target acceleration function unit, it can be determined that the target acceleration function unit no longer transmits the first direct memory access descriptor. Alternatively, after merging the first direct memory access descriptor with the second direct memory access descriptor, if the latest first direct memory access descriptor transmitted by the target acceleration function unit is not received, it is considered that the target accelerator function unit no longer transmits the first direct memory access descriptor, etc. This application does not make specific limitations here.

[0114] Step S107: Transmit the second direct memory access descriptor to the peripheral device rapid interconnect intellectual property core for processing, use the first direct memory access descriptor as the second direct memory access descriptor, and return to step S101.

[0115] In actual applications, when it is determined that the first direct memory access descriptor and the second direct memory access descriptor cannot be merged, the second direct memory access descriptor can be transmitted to the peripheral device fast interconnect IP core for processing, and the first direct memory access descriptor is used as the second direct memory access descriptor, and the process returns to step S101 to perform the next round of direct memory access descriptor merging operations starting from the first direct memory access descriptor.

[0116] The present application provides a direct memory access descriptor processing method, which includes obtaining a first direct memory access descriptor to be processed transmitted by a target acceleration function unit in a field programmable AND gate array; obtaining an existing second direct memory access descriptor; determining whether the first direct memory access descriptor and the second direct memory access descriptor can be merged; if the first direct memory access descriptor and the second direct memory access descriptor can be merged, merging the first direct memory access descriptor into the second direct memory access descriptor; determining whether to terminate the merging operation; if the merging operation is not terminated, returning to the step of obtaining the first direct memory access descriptor to be processed transmitted by the target acceleration function unit in the field programmable AND gate array and subsequent steps; if the merging operation is terminated, transmitting the second direct memory access descriptor to a peripheral device fast interconnect IP core in the field programmable AND gate array for processing. The present application can merge the direct memory access descriptors transmitted by the target acceleration function unit and transmit the second direct memory access descriptor to a peripheral device fast interconnect IP core for processing, so that the field programmable AND gate array can process multiple direct memory access descriptors at one time, thereby improving the processing efficiency of the field programmable AND gate array for direct memory access descriptors and thereby improving the computing power of the field programmable AND gate array.

[0117] Please refer to FIG. 2 , which is a second schematic diagram of a direct memory access descriptor processing method provided in an embodiment of the present application.

[0118] Based on the foregoing, some embodiments of the present application provide a method for processing a direct memory access descriptor, which may include the following steps:

[0119] Step S201: obtaining a first direct memory access descriptor to be processed transmitted by a target acceleration functional unit in a field programmable AND gate array.

[0120] Step S202: Obtain an existing second direct memory access descriptor.

[0121] Step S203: determine whether the first direct memory access descriptor and the second direct memory access descriptor can be merged; if the first direct memory access descriptor and the second direct memory access descriptor can be merged, execute step S204; if the first direct memory access descriptor and the second direct memory access descriptor cannot be merged, execute step S211.

[0122] Step S204: Parse the third data length value in the second direct memory access descriptor.

[0123] Step S205: Parse the second data length value in the first direct memory access descriptor.

[0124] Step S206: Calculate the sum of the third data length value and the second data length value.

[0125] Step S207: Keep the source address and destination address of the second direct memory access descriptor unchanged, and use the sum as the latest data length value of the second direct memory access descriptor.

[0126] In practical applications, during the process of merging a first direct memory access descriptor into a second direct memory access descriptor, the third data length value in the second direct memory access descriptor can be parsed; the second data length value in the first direct memory access descriptor can be parsed; the sum of the third data length value and the second data length value can be calculated; the source address and destination address of the second direct memory access descriptor remain unchanged, and the sum is used as the latest data length value of the second direct memory access descriptor. In this way, the source address and destination address of the second direct memory access descriptor are the source address and destination address of the first direct memory access descriptor received during the merging process, and the data length value of the second direct memory access descriptor is the sum of the data length values ​​of all direct memory access descriptors involved in the merging process.

[0127] Step S208: Determine whether to end the merge operation; if not, return to step S201. If the merge operation is ended, execute step S209.

[0128] Step S209: transmitting the second direct memory access descriptor to the peripheral device fast interconnect intellectual property core in the field programmable AND gate array for processing.

[0129] Step S210: transmitting the second direct memory access descriptor to the peripheral device rapid interconnect intellectual property core for processing, using the first direct memory access descriptor as the second direct memory access descriptor, and returning to step S201.

[0130] In actual applications, in order to facilitate the execution of the merge operation, the initial second direct memory access descriptor can be set to empty, and the result of merging the initial second direct memory access descriptor and the first first direct memory access descriptor of the merge operation is set to the first first direct memory access descriptor itself. For ease of understanding, assume that there are three direct memory access descriptors that can be merged, namely direct memory access descriptor 1, direct memory access descriptor 2, and direct memory access descriptor 3. When direct memory access descriptor 1 is received, the second direct memory access descriptor is initially empty, and the result of merging direct memory access descriptor 1 and the second direct memory access descriptor is direct memory access descriptor 1 itself. At this time, the content of the latest second direct memory access descriptor is the same as the content of direct memory access descriptor 1; when direct memory access descriptor 2 is received, the latest second direct memory access descriptor is equivalent to direct memory access descriptor 1 itself, so direct memory access descriptor 2 is the same as the latest direct memory access descriptor. The merging result of the new second direct memory access descriptor is the merging result of direct memory access descriptor 1 and direct memory access descriptor 2. At this time, the content of the latest second direct memory access descriptor is the merging result of direct memory access descriptor 1 and direct memory access descriptor 2; correspondingly, when direct memory access descriptor 3 is received, the latest second direct memory access descriptor is equivalent to the merging result of direct memory access descriptor 1 and direct memory access descriptor 2, so the merging result of direct memory access descriptor 3 and the latest second direct memory access descriptor is the merging result of direct memory access descriptor 1, direct memory access descriptor 2 and direct memory access descriptor 3.

[0131] In a specific application scenario, in order to facilitate the execution of the merge operation, after obtaining the first direct memory access descriptor to be processed transmitted by the target acceleration functional unit in the field programmable AND gate array and before obtaining the existing second direct memory access descriptor, it is also possible to determine whether the first direct memory access descriptor is the first direct memory access descriptor of the merge operation; if the first direct memory access descriptor is the first direct memory access descriptor of the merge operation, the first direct memory access descriptor is used as the second direct memory access descriptor, and the process returns to execute the steps of obtaining the first direct memory access descriptor to be processed transmitted by the target acceleration functional unit in the field programmable AND gate array and subsequent steps; if the first direct memory access descriptor is not the first direct memory access descriptor of the merge operation, the process of obtaining the existing second direct memory access descriptor and subsequent steps is executed.

[0132] In practical applications, in order to facilitate operations on direct memory access descriptors, such as processing responses to direct memory access descriptors, target identification information of each first direct memory access descriptor of the merge operation may also be recorded.

[0133] In a specific application scenario, after the peripheral device fast interconnect IP core processes the second direct memory access descriptor, it will return the corresponding processing result. Therefore, after transmitting the second direct memory access descriptor to the peripheral device fast interconnect IP core in the field programmable and gate array for processing, it can also receive the first information transmitted by the peripheral device fast interconnect IP core indicating that the processing of the second direct memory access descriptor is completed; and based on the target identification information, it can transmit to the target acceleration function unit the second information indicating that the corresponding first direct memory access descriptor has been processed, so as to feedback the execution result of the direct memory access descriptor to the target acceleration function unit.

[0134] In a specific application scenario, in order to accurately process the execution result of the direct memory access descriptor, in the process of transmitting the second information indicating that the corresponding first direct memory access descriptor has been processed to the target acceleration function unit based on the target identification information, the identification information of the second direct memory access descriptor in the second information can be parsed; if the identification information of the second direct memory access descriptor is consistent with the target identification information, the step of transmitting the second information indicating that the corresponding first direct memory access descriptor has been processed to the target acceleration function unit based on the target identification information is executed.

[0135] In a specific application scenario, in the process of recording the target identification information of each first direct memory access descriptor of a merge operation, in order to facilitate the recording of the target identification information, the first identification of the first first direct memory access descriptor of the merge operation can be recorded, and the number of values ​​of the first direct memory access descriptors merged by the merge operation can be recorded, provided that the identification information between the first direct memory access descriptors is continuous; the first identification and the number of values ​​are used as the target identification information. Accordingly, in the process of transmitting the second information indicating that the corresponding first direct memory access descriptor has been processed to the target acceleration functional unit, the second information indicating that the number of values ​​of the first direct memory access descriptor starting from the first identification has been processed can be transmitted to the target acceleration functional unit.

[0136] In a specific application scenario, in the process of transmitting the second direct memory access descriptor to the peripheral device fast interconnect IP core in the field programmable AND gate array for processing, the second direct memory access descriptor can be transmitted to the peripheral device fast interconnect IP core for processing through the first port of the peripheral device fast interconnect IP core. The data structure of the direct memory access descriptor can be determined according to actual needs. For example, bits 0 to 63 of the direct memory access descriptor can be the source physical address of the direct memory access data, that is, the internal random access memory address in the field programmable AND gate array; bits 64 to 127 can be the destination physical address of the direct memory access data, that is, the host memory physical address in the field programmable AND gate array; bits 128 to 145 can be the length of the direct memory access data, in bytes, etc.; bits 146 to 153 can be identification information of the direct memory access descriptor, etc.

[0137] In a specific application scenario, during the process of receiving the first information of the second direct memory access descriptor transmitted by the peripheral device fast interconnect IP core after completing the characterization processing, the first information of the second direct memory access descriptor transmitted by the peripheral device fast interconnect IP core can be received through the second port of the peripheral device fast interconnect IP core. The data structure of the first information can be determined based on actual needs. For example, bits 0 to 7 of the first information can be identification information of the direct memory access descriptor; bits 8 to 30 can be reserved bits and are meaningless; bit 31 can be a success flag signal of the direct memory access descriptor, where 0 indicates a successful direct memory access operation and 1 indicates a failure of the direct memory access operation.

[0138] In a specific application scenario, in order to facilitate understanding of the processing progress of the direct memory access descriptor, the processing status of the first direct memory access descriptor may also be recorded through a state machine.

[0139] Please refer to FIG3 , which is a schematic structural diagram of a direct memory access descriptor processing system provided in an embodiment of the present application.

[0140] Some embodiments of the present application provide a direct memory access descriptor processing system, which may include:

[0141] A first acquisition module 11 is configured to acquire a first direct memory access descriptor to be processed that is transmitted by a target acceleration functional unit in a field programmable AND gate array;

[0142] A second acquiring module 12 is configured to acquire an existing second direct memory access descriptor;

[0143] a first determining module 13, configured to determine whether the first direct memory access descriptor and the second direct memory access descriptor can be merged; if the first direct memory access descriptor and the second direct memory access descriptor can be merged, merging the first direct memory access descriptor into the second direct memory access descriptor;

[0144] The second judgment module 14 is used to judge whether to end the merging operation; if the merging operation is not ended, the first acquisition module is controlled to return to execute the steps of acquiring the first direct memory access descriptor to be processed transmitted by the target acceleration function unit in the field programmable AND gate array and subsequent steps; if the merging operation is ended, the second direct memory access descriptor is transmitted to the peripheral device fast interconnect IP core in the field programmable AND gate array for processing.

[0145] Some embodiments of the present application provide a direct memory access descriptor processing system, in which a first judgment module can be specifically used to: obtain the last direct memory access descriptor that is last merged with the second direct memory access descriptor; determine whether the last direct memory access descriptor and the first direct memory access descriptor can be merged; if the last direct memory access descriptor and the first direct memory access descriptor can be merged, then determine that the first direct memory access descriptor and the second direct memory access descriptor can be merged; if the last direct memory access descriptor and the first direct memory access descriptor cannot be merged, then determine that the first direct memory access descriptor and the second direct memory access descriptor cannot be merged.

[0146] Some embodiments of the present application provide a direct memory access descriptor processing system, in which a first judgment module can be specifically used to: parse the first source address, the first destination address and the first data length value in the last direct memory access descriptor; use the sum of the first source address and the first data length value as the first expected source address; use the sum of the first destination address and the first data length value as the first expected destination address; parse the second source address and the second destination address in the first direct memory access descriptor; if the first expected source address is consistent with the second source address and the first expected destination address is consistent with the second destination address, determine that the last direct memory access descriptor can be merged with the first direct memory access descriptor; if the first expected source address is inconsistent with the second source address and / or the first expected destination address is inconsistent with the second destination address, determine that the last direct memory access descriptor cannot be merged with the first direct memory access descriptor.

[0147] In a direct memory access descriptor processing system provided by some embodiments of the present application, the first judgment module can be specifically used to: after merging the first direct memory access descriptor into the second direct memory access descriptor, store the first direct memory access descriptor as the latest last direct memory access descriptor.

[0148] Some embodiments of the present application provide a direct memory access descriptor processing system, in which a first judgment module can be specifically used to: parse a third source address, a third destination address, and a third data length value in a second direct memory access descriptor; use the sum of the third source address and the third data length value as the second expected source address; use the sum of the third destination address and the third data length value as the second expected destination address; parse the second source address and the second destination address in the first direct memory access descriptor; if the second expected source address is consistent with the second source address and the second expected destination address is consistent with the second destination address, determine that the first direct memory access descriptor and the second direct memory access descriptor can be merged; if the second expected source address is inconsistent with the second source address and / or the second expected destination address is inconsistent with the second destination address, determine that the first direct memory access descriptor and the second direct memory access descriptor cannot be merged.

[0149] Some embodiments of the present application provide a direct memory access descriptor processing system, in which the second judgment module can be specifically used to: parse the third data length value in the second direct memory access descriptor; parse the second data length value in the first direct memory access descriptor; calculate the sum of the third data length value and the second data length value; keep the source address and destination address of the second direct memory access descriptor unchanged, and use the sum as the latest data length value of the second direct memory access descriptor.

[0150] Some embodiments of the present application provide a direct memory access descriptor processing system, in which an initial second direct memory access descriptor is empty, and a merge result of the initial second direct memory access descriptor and the first first direct memory access descriptor of a merge operation is set to the first first direct memory access descriptor itself.

[0151] Some embodiments of the present application provide a direct memory access descriptor processing system, which may further include:

[0152] The third judgment module is used to determine whether the first direct memory access descriptor to be processed transmitted by the target acceleration functional unit in the field programmable AND gate array is the first direct memory access descriptor of the merge operation after the first acquisition module acquires the first direct memory access descriptor to be processed and transmitted by the target acceleration functional unit in the field programmable AND gate array, and before the second acquisition module acquires the existing second direct memory access descriptor; if the first direct memory access descriptor is the first direct memory access descriptor of the merge operation, the first direct memory access descriptor is used as the second direct memory access descriptor, and the steps of acquiring the first direct memory access descriptor to be processed transmitted by the target acceleration functional unit in the field programmable AND gate array and subsequent steps are returned; if the first direct memory access descriptor is not the first direct memory access descriptor of the merge operation, the steps of acquiring the existing second direct memory access descriptor and subsequent steps are executed.

[0153] Some embodiments of the present application provide a direct memory access descriptor processing system, which may further include:

[0154] The recording module is used to record the target identification information of each first direct memory access descriptor of the merge operation.

[0155] Some embodiments of the present application provide a direct memory access descriptor processing system, which may further include:

[0156] A receiving module, configured to receive first information indicating that the processing of the second direct memory access descriptor is completed, transmitted by the peripheral device fast interconnect IP core, after the second judgment module transmits the second direct memory access descriptor to the peripheral device fast interconnect IP core in the field programmable and gate array for processing;

[0157] The transmission module is used to transmit second information indicating that the corresponding first direct memory access descriptor has been processed to the target acceleration function unit based on the target identification information.

[0158] Some embodiments of the present application provide a direct memory access descriptor processing system, in which a transmission module can be specifically used to: parse the identification information of the second direct memory access descriptor in the second information; if the identification information of the second direct memory access descriptor is consistent with the target identification information, then execute the step of transmitting the second information indicating that the corresponding first direct memory access descriptor has been processed to the target acceleration function unit based on the target identification information.

[0159] Some embodiments of the present application provide a direct memory access descriptor processing system, in which a recording module can be specifically used to: if the identification information between each first direct memory access descriptor is continuous, record the first identifier of the first first direct memory access descriptor of the merge operation, and record the number value of the first direct memory access descriptors merged by the merge operation; and use the first identifier and the number value as target identification information.

[0160] Some embodiments of the present application provide a direct memory access descriptor processing system, in which the second judgment module can be specifically used to: transmit the second direct memory access descriptor to the peripheral device fast interconnect IP core for processing through the first port of the peripheral device fast interconnect IP core.

[0161] Some embodiments of the present application provide a direct memory access descriptor processing system, in which the receiving module can be specifically used to: receive the first information of the second direct memory access descriptor transmitted by the peripheral device fast interconnect IP core through the second port of the peripheral device fast interconnect IP core and complete the processing.

[0162] Some embodiments of the present application provide a direct memory access descriptor processing system, which may further include:

[0163] The state machine module is used to record the processing state of the first direct memory access descriptor through the state machine.

[0164] Some embodiments of the present application provide a direct memory access descriptor processing system, in which the first judgment module can also be used to: after determining whether the first direct memory access descriptor and the second direct memory access descriptor can be merged, if the first direct memory access descriptor and the second direct memory access descriptor cannot be merged, transmit the second direct memory access descriptor to the peripheral device fast interconnect IP core for processing, use the first direct memory access descriptor as the second direct memory access descriptor, and return to execute the first direct memory access descriptor transmitted by the target acceleration function unit in the field programmable AND gate array and subsequent steps.

[0165] Please refer to FIG4 , which is a schematic structural diagram of a direct memory access descriptor processing device provided in an embodiment of the present application.

[0166] Some embodiments of the present application provide a direct memory access descriptor processing device, which may include:

[0167] A first first-in-first-out memory 21 connected to the target acceleration functional unit in the field programmable AND gate array, for storing a first direct memory access descriptor to be processed transmitted by the target acceleration functional unit;

[0168] A merge controller 22 connected to the first FIFO memory and the second FIFO memory is configured to determine whether the first direct memory access descriptor and the second direct memory access descriptor stored in the second FIFO memory can be merged; if the first direct memory access descriptor and the second direct memory access descriptor can be merged, the first direct memory access descriptor is merged into the second direct memory access descriptor in the second FIFO memory; determine whether to terminate the merge operation; if the merge operation is not terminated, after the first direct memory access descriptor stored in the first FIFO memory is updated, return to the step of determining whether the first direct memory access descriptor and the second direct memory access descriptor can be merged and subsequent steps; if the merge operation is terminated, the second direct memory access descriptor stored in the second FIFO memory is transmitted to a peripheral device fast interconnect IP core in a field programmable and gate array for processing;

[0169] The second FIFO memory 23 is used to store the existing second DMA descriptor.

[0170] Some embodiments of the present application provide a direct memory access descriptor processing device, which may further include:

[0171] The direct memory access descriptor register 24 connected to the first FIFO memory and the merge controller is used to store the first direct memory access descriptor as the latest tail direct memory access descriptor.

[0172] Some embodiments of the present application provide a direct memory access descriptor processing device, which may further include:

[0173] A third FIFO memory 25 connected to the second FIFO memory is used to record target identification information of each first DMA descriptor of the merge operation; in a specific application scenario, the data structure of the third FIFO memory may be 0-7 bits for recording identification information, 8-23 bits for recording the number of DMA descriptors to be merged, etc.

[0174] A fourth first-in-first-out memory 26 connected to the third first-in-first-out memory is used to record the number of first direct memory access descriptors merged by the merge operation; in a specific application scenario, the data structure of the fourth first-in-first-out memory can be 0-7 bits to record identification information, 8-23 bits to record the number of merged direct memory access descriptors, and 24 bits to record a flag indicating whether the direct memory access descriptor is successfully processed, etc.

[0175] The counter 27 connected to the fourth FIFO memory and the target acceleration functional unit is used to record the number of second information transmitted to the target acceleration functional unit indicating that the corresponding first direct memory access descriptor has been processed.

[0176] For the corresponding description of the direct memory access descriptor processing device provided in some embodiments of the present application, please refer to the above embodiments and will not be repeated here.

[0177] It should be noted that the state machine of the direct memory access descriptor processing device can be as shown in Figure 5. The initial state of the state machine is State 1. When the first FIFO memory is not empty and the second FIFO memory is not full, the data of the first FIFO memory is read into the direct memory access descriptor register and the state is jumped to State 2. Otherwise, the state is maintained. In State 2, when it is determined that the first FIFO memory is not empty and the source address and destination address of the output port are consistent with the expected source address and expected destination address of the direct memory access descriptor register, the state is jumped to State 3 and the data of the first FIFO memory is read into the direct memory access descriptor register. If the above condition is not met and the first FIFO memory is empty or the second FIFO memory is full, the state is jumped to State 1, the data of the first FIFO memory is not read, and the data of the direct memory access descriptor register is written into the second FIFO memory. If neither of the above two conditions is met, the state is maintained, the data of the first FIFO memory is read into the direct memory access descriptor register, and the data of the direct memory access descriptor register is written into the second FIFO memory. In state 3, if the first FIFO is empty, or the source address of the output port of the first FIFO is inconsistent with the expected source address of the DMA descriptor register, or the destination address of the output port of the first FIFO is inconsistent with the expected destination address of the DMA descriptor register, or the merge count counter reaches the set upper limit, the process jumps to state 4. If the above conditions are not met, the process maintains state 3 and reads the data of the first FIFO into the DMA descriptor register. In state 4, the merged DMA descriptor is written into the second FIFO. If the first FIFO is not empty and the second FIFO is not full, the process jumps to state 2 and reads the data of the first FIFO into the DMA descriptor register. Otherwise, the process jumps to state 1.

[0178] To facilitate understanding of the workflow of the direct memory access descriptor processing device in the present application, it is now described in conjunction with the scenarios of Figures 6 and 7. In Figure 6, there are two 10G Ethernet optical ports and two 4GB SDRAMs (synchronous dynamic random-access memory) connected to the field programmable gate array as memory, which can be connected to the server's central processing unit through peripheral device fast interconnection; in Figure 7, the field programmable gate array includes three accelerated computing units, a pointer management module, a peripheral device fast interconnection IP core, a descriptor channel merging module, a random access memory and the device of the present application, wherein the pointer management module internally stores the source address and destination address of the direct memory access operation and identification information, and each source address and destination address are separated by 1024 bytes, and the identification information is a continuous increasing sequence with an interval of 1. The function of the descriptor channel merging module is to merge the three direct memory access descriptors into one and send it, and receive the direct memory access operation completion information and return it to the corresponding direct memory access descriptor sending module; the workflow of the direct memory access descriptor processing device in the present application is as follows:

[0179] The three acceleration functional units simultaneously perform different types of calculations on the original data, with the calculation result data length being 1024 bytes. They then sequentially obtain the direct memory access operation identifier, source address, and destination address from the pointer management module. Based on the source address, the result data is stored in the internal RAM of the field programmable AND gate array. Based on the identifier information, source address, and destination address, a direct memory access descriptor is issued to transfer the result data to the host memory. It should be noted that since the three acceleration computing units use the same pointer management module and the three result data lengths are all 1024 bytes, the three result data are stored contiguously in the internal RAM of the field programmable AND gate array and the host memory.

[0180] The direct memory access descriptors issued by the three acceleration functional units are successively input into the device of the present application through the channel merging module and are first stored in the first first-in-first-out memory. The state machine of the merging controller jumps from state 1 to state 2, and the first direct memory access descriptor is read out from the first first-in-first-out memory and stored in the direct memory access descriptor register. In state 2, the data stored in the direct memory access descriptor register is calculated to obtain the expected source address and expected destination address of the first direct memory access descriptor, which are consistent with the source address and destination address of the second direct memory access descriptor of the output port of the first first-in-first-out memory, and jumps to state 3 to obtain a merged direct memory access descriptor, and its source address, destination address and identifier are the source address, destination address and identifier of the first direct memory access descriptor, and the length is the sum of the lengths of the first direct memory access descriptor and the second direct memory access descriptor. The second direct memory access descriptor is read out from the first first-in-first-out memory and stored in the direct memory access descriptor register. In State 3, the data stored in the DMA descriptor register is calculated to obtain the expected source address and expected destination address of the second DMA descriptor, which are consistent with the source address and destination address of the third DMA descriptor at the output port of the first FIFO memory. State 3 is maintained, and the source address, destination address, and identifier of the new merged DMA descriptor are obtained and maintained as the source address, destination address, and identifier of the current merged DMA descriptor. The length of the new merged DMA descriptor is the length of the current merged DMA descriptor plus the length of the third DMA descriptor. The third DMA descriptor is read from the first FIFO memory and stored in the DMA descriptor register. In State 3, the first FIFO memory is determined to be empty, and the process jumps to State 4. In State 4, the merged DMA descriptor is written to the second FIFO memory. The first FIFO memory is determined to be empty, and the process jumps to State 1. The second FIFO memory sends the merged DMA descriptor to port 1 of the peripheral device fast interconnect IP core, and writes the identifier and the number of merges (3) of the merged DMA descriptor into the third FIFO memory.

[0181] The peripheral device fast interconnect IP core directly accesses and transfers the three calculation result data stored in the random access memory inside the field programmable and gate array to the host memory based on the merged direct memory access descriptor. After the direct memory access operation is successful, port 2 of the peripheral device fast interconnect IP core returns the completion information to the device module of the present application. The device module of the present application compares the identifier of the returned direct memory access completion information with the identifier of the output port of the third first-in-first-out memory, determines that the values ​​are consistent, reads data from the third first-in-first-out memory, and writes the success flag of the returned direct memory access completion information, the number of merges, and the direct memory access descriptor identifier into the fourth first-in-first-out memory.

[0182] After the fourth first-in-first-out memory is not empty, a data is read from the fourth first-in-first-out memory. It is determined that the value of the combined direct memory access descriptors output by the fourth first-in-first-out memory is 3, and three direct memory access completion messages are continuously output to the downstream module. The identifier of the first direct memory access completion message is the identifier output by the fourth first-in-first-out memory, and the identifiers of the second and third output completion messages are the first identifier plus 1 and 2 respectively. The flag signals of the three direct memory access completion messages recording whether the direct memory access descriptors are successfully processed are all the flag signals output by the fourth first-in-first-out memory recording whether the direct memory access descriptors are successfully processed.

[0183] After receiving the three DMA completion messages, the descriptor channel merging module returns the DMA completion messages to the three acceleration functional units. This completes the DMA operation of transferring the computation result data to the host memory.

[0184] The present application also provides an electronic device and a non-volatile readable storage medium, both of which have the corresponding effects of the direct memory access descriptor processing method provided in the embodiment of the present application. Please refer to Figure 8, which is a structural diagram of an electronic device provided in the embodiment of the present application.

[0185] An electronic device provided in an embodiment of the present application includes a memory 201 and a processor 202. The memory 201 stores a computer program, and when the processor 202 executes the computer program, the steps of the direct memory access descriptor processing method described in any of the above embodiments are implemented.

[0186] Referring to FIG9 , another electronic device provided in some embodiments of the present application may further include: an input port 203 connected to the processor 202 for transmitting commands inputted from the outside to the processor 202; a display unit 204 connected to the processor 202 for displaying the processing results of the processor 202 to the outside world; and a communication module 205 connected to the processor 202 for enabling communication between the electronic device and the outside world. The display unit 204 may be a display panel, a laser scanning display, or the like; the communication methods used by the communication module 205 include, but are not limited to, Mobile High Definition Link (MHL), Universal Serial Bus (USB), High Definition Multimedia Interface (HDMI), wireless connections such as Wireless Fidelity (WiFi), Bluetooth communication technology, Bluetooth Low Energy communication technology, and communication technology based on IEEE802.11s.

[0187] An embodiment of the present application provides a non-volatile readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of the direct memory access descriptor processing method described in any of the above embodiments are implemented.

[0188] The non-volatile readable storage medium involved in this application includes random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the technical field.

[0189] For the description of the relevant parts of the direct memory access descriptor processing system, device, electronic device, and non-volatile readable storage medium provided in the embodiments of the present application, please refer to the detailed description of the corresponding parts in the direct memory access descriptor processing method provided in the embodiments of the present application, and no further description is given here. In addition, the parts of the above-mentioned technical solutions provided in the embodiments of the present application that are consistent with the implementation principles of the corresponding technical solutions in the prior art are not described in detail to avoid excessive elaboration.

[0190] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0191] The above description of the disclosed embodiments will enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A direct memory access descriptor processing method, characterized in that: include: Obtaining a first direct memory access descriptor to be processed transmitted by a target acceleration function unit in a field programmable AND gate array; Get the existing second direct memory access descriptor; Determining whether the first direct memory access descriptor and the second direct memory access descriptor can be merged; If the first direct memory access descriptor and the second direct memory access descriptor can be merged, merging the first direct memory access descriptor into the second direct memory access descriptor; Determine whether to end the merge operation; If the merging operation is not terminated, returning to execute the steps of obtaining the first direct memory access descriptor to be processed transmitted by the target acceleration function unit in the field programmable AND gate array and the subsequent steps; If the merging operation is completed, the second direct memory access descriptor is transmitted to the peripheral device fast interconnect IP core in the field programmable and gate array for processing.

2. The method according to claim 1, characterized in that The determining whether the first direct memory access descriptor and the second direct memory access descriptor can be merged includes: Obtaining the last merged tail direct memory access descriptor in the second direct memory access descriptor; Determining whether the last direct memory access descriptor and the first direct memory access descriptor can be merged; If the last direct memory access descriptor and the first direct memory access descriptor can be merged, determining that the first direct memory access descriptor and the second direct memory access descriptor can be merged; If the last direct memory access descriptor and the first direct memory access descriptor cannot be merged, it is determined that the first direct memory access descriptor and the second direct memory access descriptor cannot be merged.

3. The method according to claim 2, characterized in that The determining whether the last direct memory access descriptor and the first direct memory access descriptor can be merged includes: Parsing the first source address, the first destination address and the first data length value in the end direct memory access descriptor; Taking the sum of the first source address and the first data length value as the first expected source address; Taking the sum of the first destination address and the first data length value as a first expected destination address; Parsing a second source address and a second destination address in the first direct memory access descriptor; If the first expected source address is consistent with the second source address, and the first expected destination address is consistent with the second destination address, determining that the last direct memory access descriptor and the first direct memory access descriptor can be merged; If the first expected source address is inconsistent with the second source address and / or the first expected destination address is inconsistent with the second destination address, it is determined that the last direct memory access descriptor cannot be merged with the first direct memory access descriptor.

4. The method according to claim 3, characterized in that After merging the first direct memory access descriptor into the second direct memory access descriptor, the method further includes: The first direct memory access descriptor is stored as the latest tail direct memory access descriptor.

5. The method according to claim 1, characterized in that The determining whether the first direct memory access descriptor and the second direct memory access descriptor can be merged includes: Parsing a third source address, a third destination address, and a third data length value in the second direct memory access descriptor; Taking the sum of the third source address and the third data length value as the second expected source address; Using the sum of the third destination address and the third data length value as the second expected destination address; Parsing a second source address and a second destination address in the first direct memory access descriptor; If the second expected source address is consistent with the second source address, and the second expected destination address is consistent with the second destination address, determining that the first direct memory access descriptor and the second direct memory access descriptor can be merged; If the second expected source address is inconsistent with the second source address and / or the second expected destination address is inconsistent with the second destination address, it is determined that the first direct memory access descriptor and the second direct memory access descriptor cannot be merged.

6. The method according to claim 1, characterized in that The step of merging the first direct memory access descriptor into the second direct memory access descriptor comprises: Parsing a third data length value in the second direct memory access descriptor; Parsing a second data length value in the first direct memory access descriptor; Calculate the sum of the third data length value and the second data length value; The source address and the destination address of the second direct memory access descriptor are kept unchanged, and the sum is used as the latest data length value of the second direct memory access descriptor.

7. The method according to claim 6, characterized in that The initial second direct memory access descriptor is empty, and a result of merging the initial second direct memory access descriptor and the first first direct memory access descriptor of the merging operation is set to be the first first direct memory access descriptor itself.

8. The method according to claim 6, characterized in that After acquiring the first direct memory access descriptor to be processed transmitted by the target acceleration function unit in the field programmable AND gate array and before acquiring the existing second direct memory access descriptor, the method further includes: Determining whether the first direct memory access descriptor is a first direct memory access descriptor of a merge operation; If the first direct memory access descriptor is the first direct memory access descriptor of the merge operation, the first direct memory access descriptor is used as the second direct memory access descriptor, and the steps of obtaining the first direct memory access descriptor to be processed transmitted by the target acceleration function unit in the field programmable AND gate array and subsequent steps are returned; If the first direct memory access descriptor is not the first direct memory access descriptor of the merge operation, the steps of obtaining the existing second direct memory access descriptor and subsequent steps are performed.

9. The method according to claim 8, characterized in that Also includes: The target identification information of each of the first direct memory access descriptors of the merge operation is recorded.

10. The method according to claim 9, characterized in that After transmitting the second direct memory access descriptor to the peripheral device fast interconnect IP core in the field programmable and gate array for processing, the method further includes: Receive the first information of the second direct memory access descriptor transmitted by the peripheral device fast interconnect IP core and complete the characterization processing; Based on the target identification information, second information indicating that the corresponding first direct memory access descriptor has been processed is transmitted to the target acceleration function unit.

11. The method according to claim 10, characterized in that The transmitting, based on the target identification information, to the target acceleration function unit, second information indicating that the corresponding first direct memory access descriptor has been processed, comprises: parsing identification information of the second direct memory access descriptor in the second information; If the identification information of the second direct memory access descriptor is consistent with the target identification information, the step of transmitting, based on the target identification information, second information indicating that the corresponding first direct memory access descriptor has been processed to the target acceleration function unit is executed.

12. The method according to claim 11, characterized in that The target identification information of each of the first direct memory access descriptors of the record merging operation includes: If the identification information between the first direct memory access descriptors is continuous, then recording the first identification of the first first direct memory access descriptor of the merging operation, and recording the number of the first direct memory access descriptors merged by the merging operation; The first identifier and the number of values ​​are used as the target identifier information.

13. The method according to claim 12, characterized in that The transmitting the second direct memory access descriptor to the peripheral device fast interconnect IP core in the field programmable and gate array for processing includes: The second direct memory access descriptor is transmitted to the peripheral device fast interconnect IP core for processing through the first port of the peripheral device fast interconnect IP core.

14. The method according to claim 13, characterized in that The receiving of the characterization processing of the peripheral device fast interconnect IP core transmission to complete the first information of the second direct memory access descriptor includes: The first information indicating that the second direct memory access descriptor transmitted by the peripheral device fast interconnect IP core is received through the second port of the peripheral device fast interconnect IP core.

15. The method according to claim 1, characterized in that Also includes: The processing status of the first direct memory access descriptor is recorded by a state machine.

16. The method according to claim 1, characterized in that After determining whether the first direct memory access descriptor and the second direct memory access descriptor can be merged, the method further includes: If the first direct memory access descriptor and the second direct memory access descriptor cannot be merged, the second direct memory access descriptor is transmitted to the peripheral device fast interconnect IP core for processing, the first direct memory access descriptor is used as the second direct memory access descriptor, and the step of obtaining the first direct memory access descriptor transmitted by the target acceleration function unit in the field programmable AND gate array and subsequent steps is returned.

17. A direct memory access descriptor processing system, characterized in that: include: A first acquisition module is used to acquire a first direct memory access descriptor to be processed transmitted by a target acceleration function unit in a field programmable AND gate array; A second acquisition module, used for acquiring an existing second direct memory access descriptor; A first judging module, configured to judge whether the first direct memory access descriptor and the second direct memory access descriptor can be merged; If the first direct memory access descriptor and the second direct memory access descriptor can be merged, merging the first direct memory access descriptor into the second direct memory access descriptor; The second judgment module is used to judge whether to end the merging operation; If the merging operation is not terminated, the first acquisition module is controlled to return to execute the acquisition of the first direct memory access descriptor to be processed transmitted by the target acceleration function unit in the field programmable AND gate array and subsequent steps; if the merging operation is terminated, the second direct memory access descriptor is transmitted to the peripheral device fast interconnect IP core in the field programmable AND gate array for processing.

18. A direct memory access descriptor processing device, characterized in that: include: A first first-in first-out memory connected to the target acceleration function unit in the field programmable AND gate array, used for storing a first direct memory access descriptor to be processed transmitted by the target acceleration function unit; a merging controller connected to the first FIFO memory and the second FIFO memory, used to determine whether the first DIMA descriptor can be merged with the second DIMA descriptor stored in the second FIFO memory; If the first direct memory access descriptor and the second direct memory access descriptor can be merged, merging the first direct memory access descriptor into the second direct memory access descriptor in the second first-in-first-out memory; determining whether to terminate the merging operation; If the merging operation is not terminated, after the first direct memory access descriptor stored in the first FIFO memory is updated, returning to execute the step of determining whether the first direct memory access descriptor and the second direct memory access descriptor can be merged and the subsequent steps; If the merging operation is terminated, the second direct memory access descriptor stored in the second first-in first-out memory is transmitted to the peripheral device fast interconnect IP core in the field programmable and gate array for processing; The second first-in first-out memory is used to store the existing second direct memory access descriptor.

19. The device according to claim 18, characterized in that Also includes: The direct memory access descriptor register connected to the first FIFO memory and the merge controller is used to store the first direct memory access descriptor as the latest tail direct memory access descriptor.

20. The device according to claim 19, characterized in that Also includes: a third FIFO memory connected to the second FIFO memory, and used for recording target identification information of each of the first direct memory access descriptors of the merge operation; a fourth FIFO memory connected to the third FIFO memory, used for recording the number of values ​​of the first direct memory access descriptors merged by the merge operation; A counter connected to the fourth FIFO memory and the target acceleration function unit is used to record the quantity value of the second information transmitted to the target acceleration function unit, indicating that the corresponding first direct memory access descriptor has been processed.

21. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the direct memory access descriptor processing method as claimed in any one of claims 1 to 16 when executing the computer program.

22. A non-volatile readable storage medium, characterized in that: The non-volatile readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the direct memory access descriptor processing method according to any one of claims 1 to 16 are implemented.

Images