PCIE device management architecture, method and system, and device and medium

Abstract

The present application relates to the technical field of servers, and in particular relates to a PCIE device management architecture, method and system, and a device and a medium. The method comprises: acquiring a driver program of a PCIE first switch chip, installing the driver program of the PCIE first switch chip to a baseboard management controller, and establishing a PCIE specification and protocol of a baseboard management controller chip and the PCIE first switch chip; configuring a PCIE first controller in the baseboard management controller to be in an RC mode, and configuring a PCIE second controller of a central processing unit to be in an EP mode; and managing a PCIE device by means of the baseboard management controller, which is configured to be in the RC mode, so as to improve the efficiency of the baseboard management controller managing the PCIE device.

Description

PCIE device management architecture, method, system, device and medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on July 19, 2023, with application number 202310884018.1, and application name “PCIE device management architecture, method, system, device and medium”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of server technology, and in particular to a PCIE device management architecture, method, system, device and medium. Background Art

[0004] The RC (Root Complex) is a key component in the PCIE (Peripheral Component Interconnect Express) architecture. Its introduction is closely related to the X86 system architecture. In fact, only the X86 architecture has a standard RC specification definition; other systems do not have all the standard RC functions.

[0005] The X86-based BMC (Baseboard Management Controller) chip can obtain PCIE device information through RC. However, in order to obtain PCIE device information, the ARM-based BMC chip needs to capture PCIE device information through the PCH (Platform Controller Hub) and pass the PCIE device information to the ARM-based BMC chip in an in-band manner. Therefore, the ARM-based BMC chip cannot directly obtain PCIE device information or directly manage PCIE devices, resulting in poor management efficiency of the ARM-based BMC chip for PCIE devices.

[0006] Summary of the Invention

[0007] On the one hand, a PCIE device management architecture is provided, and the PCIE device management architecture includes:

[0008] A baseboard management controller, wherein the baseboard management controller is provided with a baseboard management controller chip, a PCIE first switching chip, and a PCIE first controller, the baseboard management controller chip is connected to the PCIE first switching chip, and the PCIE first controller is configured in RC (Root Complex) mode; and

[0009] The central processing unit is in communication with the baseboard management controller. The central processing unit is provided with a PCIE second controller, and the PCIE second controller is configured in EP mode.

[0010] The central processing unit is connected to a PCIE second switching chip, and the PCIE second switching chip is connected to multiple PCIE devices;

[0011] The PCIE device is directly controlled by a baseboard management controller configured in RC mode.

[0012] In one embodiment, a south bridge chip is connected between the central processing unit and the baseboard management controller, and an embedded controller is provided in the south bridge chip.

[0013] On the other hand, a PCIE device management method is provided, the PCIE device management method comprising:

[0014] Obtain a driver for the PCIE first switch chip, install the driver for the PCIE first switch chip into the baseboard management controller, and establish PCIE specifications and protocols between the baseboard management controller chip and the PCIE first switch chip;

[0015] Configuring the PCIE first controller in the baseboard management controller to RC mode, and configuring the PCIE second controller of the central processing unit to EP (Endpoint Device) mode; and

[0016] The PCIE device is directly controlled by the baseboard management controller configured in RC mode.

[0017] In one embodiment, configuring the PCIE first controller in the baseboard management controller to RC mode includes:

[0018] The register of the PCIE first controller in the baseboard management controller is configured to configure the PCIE first controller in the baseboard management controller to an RC mode.

[0019] In one embodiment, configuring the register of the PCIE first controller in the baseboard management controller includes:

[0020] Configure the controller register of the PCIE first controller in the baseboard management controller.

[0021] In one embodiment, configuring the register of the PCIE first controller in the baseboard management controller further includes:

[0022] The MCTP (Management Component Transport Protocol) register of the PCIE first controller in the baseboard management controller is configured.

[0023] In one embodiment, configuring the register of the PCIE first controller in the baseboard management controller further includes:

[0024] The XDMA (Xing Distributed Media Architecture) register of the PCIE first controller in the baseboard management controller is configured.

[0025] In one embodiment, configuring the PCIE second controller of the central processing unit to EP mode includes:

[0026] The PCIE second controller of the central processing unit is configured to EP mode, so that the terminal where the central processing unit is located is configured as an agent terminal.

[0027] In one embodiment, after configuring the PCIE second controller of the central processing unit to EP mode, the method further includes:

[0028] The baseboard management controller configured in RC mode is used as the bus owner to obtain the management authority of the PCIE device, so as to communicate with the PCIE device through the terminal where the central processing unit configured as the agent is located.

[0029] In one embodiment, directly controlling a PCIE device through a baseboard management controller configured in RC mode includes:

[0030] The PCIE device is directly controlled through the baseboard management controller configured in RC mode and address operation instructions.

[0031] In one embodiment, directly controlling a PCIE device through a baseboard management controller configured in RC mode includes:

[0032] PCIE devices are directly controlled through the baseboard management controller configured in RC mode and MCTP control instructions.

[0033] In one embodiment, directly controlling a PCIE device through a baseboard management controller configured in RC mode includes:

[0034] Accessing the configuration space of the PCIE device through the baseboard management controller configured in RC mode; and

[0035] Control the device's configuration space to enable or disable the device, and set the PCIE device's interrupt mode.

[0036] In one embodiment, directly controlling the PCIE device through a baseboard management controller configured in RC mode further includes:

[0037] Obtain device information of PCIE devices through the baseboard management controller configured in RC mode;

[0038] The device information of the PCIE device is stored in the memory of the baseboard management controller so that the device information can be displayed on the display interface.

[0039] In one embodiment, before directly controlling the PCIE device using a baseboard management controller configured in RC mode and MCTP control instructions, the method further includes:

[0040] PCIE devices are discovered through the MCTP protocol, and device identification codes are assigned to discovered PCIE devices and baseboard management controllers configured in RC mode.

[0041] In one embodiment, discovering a PCIE device through the MCTP protocol and assigning a device identification code to the discovered PCIE device and a baseboard management controller configured in RC mode includes:

[0042] Send a 0x0B control request broadcast packet to the PCIE device and inform the baseboard management controller of the device identification code;

[0043] Receive the response 0x0B command of the PCIE device and obtain the PCIE device with the undiscovered mark;

[0044] Send a 0x0C control request broadcast packet to the PCIE device and inform the baseboard management controller of the device identification code;

[0045] Receive the response 0x0C command of the PCIE device carrying the not found mark;

[0046] Sending a 0x01 control request to the PCIE device and carrying a device identification code for configuring the PCIE device, so as to mark the PCIE device carrying an undiscovered flag as a discovered flag and assign a device identification code to the PCIE device; and

[0047] Receive a PCIE device marked as discovered and its corresponding device identification code.

[0048] In one embodiment, before sending a 0x0B control request broadcast packet to the PCIE device and informing the baseboard management controller of the device identification code, the method further includes:

[0049] Receive a 0x0D control request from a PCIE device and obtain a PCIE device with a not found flag; and

[0050] Send a response 0x0D command to the PCIE device carrying the not found mark.

[0051] In one embodiment, a PCIE device management method further includes:

[0052] Obtain PCIE device fault information through the baseboard management controller configured in RC mode.

[0053] In one embodiment, a PCIE device management method further includes:

[0054] Configuring the PCIE first controller in the baseboard management controller to EP mode, and configuring the PCIE second controller of the central processing unit to RC mode; and

[0055] Directly control PCIE devices through the central processing unit configured in RC mode.

[0056] In another aspect, a PCIE device management system is provided, the PCIE device management system comprising:

[0057] A driver module is used to obtain a driver for the PCIE first switching chip, install the driver for the PCIE first switching chip into the baseboard management controller, and establish a PCIE specification and protocol between the baseboard management controller chip and the PCIE first switching chip;

[0058] A mode configuration module, configured to configure the PCIE first controller in the baseboard management controller to RC mode, and configure the PCIE second controller of the central processing unit to EP mode; and

[0059] The management module is used to directly control the PCIE device through a baseboard management controller configured in RC mode.

[0060] In another aspect, a computer device is provided, comprising a memory, a processor, and computer-readable instructions stored in the memory and executable by the processor, wherein when the processor executes the computer-readable instructions, the following steps are implemented:

[0061] Obtain a driver for the PCIE first switch chip, install the driver for the PCIE first switch chip into the baseboard management controller, and establish PCIE specifications and protocols between the baseboard management controller chip and the PCIE first switch chip;

[0062] The first PCIE controller in the baseboard management controller is configured to be in RC mode, and the second PCIE controller of the central processing unit is configured to be in EP mode;

[0063] The PCIE device is directly controlled by the baseboard management controller configured in RC mode.

[0064] In another aspect, one or more non-volatile computer-readable storage media storing computer-readable instructions are provided. When the computer-readable instructions are executed by one or more processors, the one or more processors are caused to perform the following steps:

[0065] Obtain a driver for the PCIE first switch chip, install the driver for the PCIE first switch chip into the baseboard management controller, and establish PCIE specifications and protocols between the baseboard management controller chip and the PCIE first switch chip;

[0066] The first PCIE controller in the baseboard management controller is configured to be in RC mode, and the second PCIE controller of the central processing unit is configured to be in EP mode;

[0067] The PCIE device is directly controlled by the baseboard management controller configured in RC mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0069] FIG1 is a first architectural diagram of a PCIE device management architecture provided by one or more embodiments of the present application;

[0070] FIG2 is a second architecture diagram of a PCIE device management architecture provided by one or more embodiments of the present application;

[0071] FIG3 is a flowchart of a first method of a PCIE device management method provided by one or more embodiments of the present application;

[0072] FIG4 is a flowchart of a second method of the PCIE device management method provided by one or more embodiments of the present application;

[0073] FIG5 is a system structure diagram of a PCIE device management system provided by one or more embodiments of the present application;

[0074] FIG6 is a device structure diagram of a computer device provided in one or more embodiments of the present application. DETAILED DESCRIPTION

[0075] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0076] In some embodiments, referring to FIG. 2 , FIG. 2 is a second architecture diagram of the PCIE device management architecture provided in an embodiment of the present application.

[0077] The PCIE device management architecture includes:

[0078] A baseboard management controller is provided with a baseboard management controller chip, a PCIE first switching chip and a PCIE first controller. The baseboard management controller chip is connected to the PCIE first switching chip, and the PCIE first controller is configured in RC mode.

[0079] The central processing unit is in communication with the baseboard management controller. The central processing unit is provided with a PCIE second controller, and the PCIE second controller is configured in EP mode.

[0080] The central processing unit is connected to a PCIE second switching chip, and the PCIE second switching chip is connected to multiple PCIE devices;

[0081] The PCIE device is directly controlled by a baseboard management controller configured in RC mode.

[0082] As shown in the PCIE device management architecture diagram in Figure 2, the baseboard management controller is connected to the central processing unit, and the central processing unit is connected to the PCIE second switch chip (PCIE Switch). Multiple PCIE devices are connected to the PCIE second switch chip. In the PCIE device management architecture of the existing X86 architecture, the central processing unit is the master end (bus owner). The central processing unit has a standard RC specification protocol, has all the functions of RC, and has the authority to access PCIE devices. However, the baseboard management controller as the slave end does not have the authority to actively obtain PCIE device information, and can only capture PCIE device information through the embedded controller, and then send the PCIE device information to the baseboard management controller in an in-band manner. As a result, the baseboard management controller cannot directly obtain PCIE device information or directly manage PCIE devices, which further leads to poor management efficiency of PCIE devices by the ARM architecture baseboard management controller. To improve the management capabilities of an ARM-based baseboard management controller for PCIE devices, this application adds a first PCIE switch chip (PCIE Switch) to the baseboard management controller, connects the first PCIE switch chip to the baseboard management controller chip, and establishes a PCIE communication mechanism between the first PCIE switch chip and the baseboard management controller chip. The operating mode of the first PCIE controller is then set to RC mode, i.e., the master end (bus owner). The baseboard management controller is connected to a central processing unit (CPU), which is equipped with a second PCIE controller. The second PCIE controller in the CPU is set to EP mode, i.e., the slave end. A second PCIE switch chip is connected to the CPU for expanding multiple PCIE devices. Since the master end has the active authority to operate the slave end; therefore, the baseboard management controller configured in RC mode has the authority to obtain PCIE device information as the master end and establishes a PCIE communication mechanism. Therefore, the baseboard management controller has the management authority over the PCIE device as the RC, and the baseboard management controller can directly obtain the device information of the PCIE device, such as PCIE device ID, Vender ID, Subsystem ID, Subsystem Vendor ID, etc.; and the baseboard management controller, as the real bus owner (Bus Owner), directly accesses the configuration space of the PCIE device and obtains the BAR (Base Address Register) information of the PCIE device. This information is used to determine the address space of the PCIE device for memory mapping and access in the system, thereby realizing direct control of the PCIE device by the baseboard management controller.

[0083] The PCIE device management architecture of the present application adds a PCIE first switching chip to the baseboard management controller. The baseboard management controller chip is communicated with the PCIE first switching chip, and the PCIE first controller is configured to RC mode. The baseboard management controller obtains management authority over the PCIE device, can directly obtain device information of the PCIE device and directly control the PCIE device, thereby improving the management efficiency of the baseboard management controller over the PCIE device; in addition, since the embedded controller can only work after the server is fully started, the baseboard management controller can obtain device information of the PCIE device through the embedded controller. Therefore, the method of obtaining PCIE device information through the embedded controller takes a long time. The baseboard management controller of the present application is used as an RC, obtains management authority over the PCIE device, and does not need to obtain device information of the PCIE device through the embedded controller, thereby improving the speed at which the baseboard management controller obtains PCIE device information.

[0084] In one embodiment, a south bridge chip is connected between the central processing unit and the baseboard management controller, and an embedded controller is provided in the south bridge chip.

[0085] The PCIE device management architecture, shown in Figure 1, also includes a PCH southbridge chip, which connects between the CPU and the baseboard management controller (BMC). The southbridge chip houses an ME (Management Engine), an embedded controller. Both the primary and secondary PCIE controllers are capable of EP and RC modes. These modes can be configured based on actual needs. For example, the primary PCIE controller in the BMC can be configured in EP mode (slave mode), while the secondary PCIE controller in the CPU can be configured in RC mode (master mode (bus owner)). In this case, the CPU obtains management authority over the PCIE devices, while the BMC can only retrieve device information from the embedded controller and then send it to the BMC. Furthermore, the embedded controller connects to the PMT (Hardware Telemetry Reporting Tool), Intel's platform monitoring technology that can be used within organizations and data centers to monitor performance and collect data on their hardware. This makes the lives of system administrators much easier, as they can access all data in XML format.

[0086] In the PCIE device management architecture of the present application, both the central processing unit and the baseboard management controller are equipped with PCIE controllers, and both have RC mode and EP mode. Therefore, the central processing unit and the baseboard management controller of the present application can be configured with different working modes according to actual needs, thereby improving the versatility of the PCIE device management architecture.

[0087] In some embodiments, referring to FIG. 3 , FIG. 3 is a flow chart of a first method of a PCIE device management method provided in an embodiment of the present application.

[0088] A PCIE device management method includes the following steps:

[0089] S101, obtaining a driver for a PCIE first switch chip, installing the driver for the PCIE first switch chip into a baseboard management controller, and establishing a PCIE specification and protocol between the baseboard management controller chip and the PCIE first switch chip;

[0090] Specifically, a PCIE first switching chip is added to the baseboard management controller, so the driver of the PCIE first switching chip must be obtained first, and then the driver of the PCIE first switching chip must be installed to the baseboard management controller so that the first switching chip can operate normally on the baseboard management controller; in addition, the driver of the PCIE first switching chip will establish communication between the baseboard management controller chip and the PCIE first switching chip, that is, establish the PCIE specifications and protocols between the baseboard management controller chip and the PCIE first switching chip, so that PCIE communication can be achieved between the baseboard management controller chip and the PCIE first switching chip.

[0091] S102, configuring the PCIE first controller in the baseboard management controller to RC mode, and configuring the PCIE second controller of the central processing unit to EP mode;

[0092] Specifically, after PCIE communication is achieved between the baseboard management controller chip and the PCIE first switching chip, the PCIE first controller in the baseboard management controller is configured to RC mode, that is, the master end (bus owner); then the PCIE second controller of the central processing unit is configured to EP mode, that is, the slave end; so that the PCIE device can be directly controlled by the baseboard management controller configured in RC mode.

[0093] S103: directly controlling the PCIE device through a baseboard management controller configured in RC mode.

[0094] Specifically, since the master end has the active authority to operate the slave end; therefore, the baseboard management controller configured in RC mode as the master end has the authority to obtain PCIE device information and establishes a PCIE communication mechanism. Therefore, the baseboard management controller as the RC has the management authority over the PCIE device, and the baseboard management controller can directly obtain the device information of the PCIE device and directly control the PCIE device.

[0095] The PCIE device management method of the present application establishes a PCIE communication protocol between a baseboard management controller chip and a first PCIE switching chip, and configures the first PCIE controller to RC mode, thereby obtaining management authority over the PCIE device, and is capable of directly obtaining device information of the PCIE device and directly controlling the PCIE device, thereby improving the management efficiency of the baseboard management controller over the PCIE device. In addition, the baseboard management controller of the present application is used as an RC to obtain management authority over the PCIE device, without the need to obtain device information of the PCIE device through an embedded controller, thereby improving the speed at which the baseboard management controller obtains PCIE device information.

[0096] In one embodiment, configuring the PCIE first controller in the baseboard management controller to RC mode includes:

[0097] The register of the PCIE first controller in the baseboard management controller is configured to configure the PCIE first controller in the baseboard management controller to an RC mode.

[0098] Specifically, to configure the PCIE first controller in the baseboard management controller to RC mode, it is necessary to configure the register of the PCIE first controller and modify the register parameters of the PCIE first controller to configure the PCIE first controller in the baseboard management controller to RC mode.

[0099] The register of the PCIE first controller is configured to configure the PCIE first controller in the baseboard management controller to RC mode. The baseboard management controller configured to RC mode obtains management authority over the PCIE device, can directly obtain device information of the PCIE device and directly control the PCIE device, thereby improving the management efficiency of the baseboard management controller over the PCIE device.

[0100] In one embodiment, configuring the register of the PCIE first controller in the baseboard management controller includes:

[0101] Configure the controller register of the PCIE first controller in the baseboard management controller.

[0102] Specifically, the controller register of the PCIE first controller in the baseboard management controller is configured, that is, the controller register (controller register) of the PCIE first controller in the baseboard management controller is configured to configure the root port (root port), and the PCIE device and the baseboard management controller communicate through the root port, that is, the controller register of the PCIE first controller of the baseboard management controller is initialized, and PEHR30: Miscellaneous Control 30h Register is configured to configure the root port (root port).

[0103] In one embodiment, configuring the register of the PCIE first controller in the baseboard management controller further includes:

[0104] Configure the MCTP register of the first PCIE controller in the baseboard management controller.

[0105] Specifically, the MCTP registers of the first PCIE controller in the baseboard management controller are configured, that is, the MCTP-related communication protocols are configured to implement MCTP communication, such as configuring the transmit command address (MCTP04: TX Command Address), the receive buffer address (MCTPO8: RX Buffer Address), and the MCTP14: MCTP device identification code (EID).

[0106] In one embodiment, configuring the register of the PCIE first controller in the baseboard management controller includes:

[0107] Configure the XDMA register of the PCIE first controller in the baseboard management controller.

[0108] Specifically, the XDMA register of the first PCIE controller in the baseboard management controller is configured to enable DMA memory access (direct memory access). The DMA controller copies data directly from the device IO register to the main memory without passing through the CPU, and notifies the CPU when the transfer is complete. This allows the CPU to focus on other tasks, improving data transfer efficiency.

[0109] In one embodiment, configuring the PCIE second controller of the central processing unit to EP mode includes:

[0110] The PCIE second controller of the central processing unit is configured to EP mode, so that the terminal where the central processing unit is located is configured as an agent terminal.

[0111] Specifically, the CPU's PCIE secondary controller is configured in EP mode. This means the CPU acts as a slave to the BMC, accepting control from the BMC. The BMC then gains management rights over the PCIE devices. The CPU's terminal is configured as a proxy, meaning the host terminal (terminal) can be set to RC Proxy, enabling the BMC to directly access the PCIE device's configuration space as the true bus owner.

[0112] The terminal where the central processor is located is configured as an agent, so that the baseboard management controller can directly access the configuration space of the PCIE device as the real bus owner, thereby improving the management efficiency of the baseboard management controller for PCIE devices and increasing the speed at which the baseboard management controller obtains PCIE device information.

[0113] In one embodiment, after configuring the PCIE second controller of the central processing unit to EP mode, the method further includes:

[0114] The baseboard management controller configured in RC mode is used as the bus owner to obtain the management authority of the PCIE device, so as to communicate with the PCIE device through the terminal where the central processing unit configured as the agent is located.

[0115] Specifically, the PCIE first controller in the baseboard management controller is configured as RC mode, that is, the master end, that is, the baseboard management controller configured in RC mode is used as the bus owner, that is, the baseboard management controller configured in RC mode obtains management authority over the PCIE device, so as to communicate with the PCIE device through the terminal where the central processing unit configured as the agent end is located, thereby realizing management of the PCIE device.

[0116] As the real bus owner, the baseboard management controller communicates directly with the PCIE device through the terminal where the central processing unit is located, which is configured as the agent. The bus owner can access the configuration space of the PCIE device, which improves the management efficiency of the baseboard management controller for the PCIE device and increases the speed at which the baseboard management controller obtains PCIE device information.

[0117] In one embodiment, directly controlling a PCIE device through a baseboard management controller configured in RC mode includes:

[0118] The PCIE device is directly controlled through the baseboard management controller configured in RC mode and address operation instructions.

[0119] Specifically, a baseboard management controller configured in RC mode can manage PCIE devices as the bus owner. Specifically, the baseboard management controller configured in RC mode manages PCIE devices through address manipulation instructions, which is the PCIE between the CPU and BMC in Figures 1 and 2. Because PCIE is a physical layer protocol, it directly sends and receives transaction layer packets (TLPs) provided by the driver through address manipulation. Therefore, a baseboard management controller configured in RC mode directly controls PCIE devices through address manipulation instructions.

[0120] In one embodiment, directly controlling a PCIE device through a baseboard management controller configured in RC mode includes:

[0121] Access the configuration space of the PCIE device through the baseboard management controller configured in RC mode;

[0122] Specifically, the PCIE device is managed by the baseboard management controller configured in RC mode, that is, the configuration space of the PCIE device is accessed by the baseboard management controller configured in RC mode to implement relevant configuration of the configuration space of the PCIE device or obtain device information of the PCIE device.

[0123] Control the device's configuration space to enable or disable the device, and set the PCIE device's interrupt mode.

[0124] Specifically, the configuration space of the PCIE device is accessed through the baseboard management controller configured in RC mode, and the operations performed may include enabling the PCIE device (enable control), disabling the PCIE device (disable control), setting the terminal mode of the PCIE device, and the like.

[0125] As the real bus owner, the baseboard management controller can access the configuration space of the PCIE device, thereby improving the management efficiency of the baseboard management controller for the PCIE device.

[0126] In one embodiment, directly controlling the PCIE device by using a baseboard management controller configured in RC mode further includes:

[0127] Obtain device information of PCIE devices through the baseboard management controller configured in RC mode;

[0128] Specifically, the device information of the PCIE device is stored in the memory of the baseboard management controller so that the display interface can display the device information. The received PCIE device information can be displayed through the web or command mode or other feasible modes.

[0129] By configuring the baseboard management controller in RC mode, the device information of the PCIE device can be obtained, and then the device information of the PCIE device can be stored in the memory of the baseboard management controller for the display interface to display the device information, so that the staff can timely understand the relevant PCIE device information, diagnose and solve PCIE device failures, and improve the reliability and stability of the PCIE device.

[0130] In one embodiment, directly controlling a PCIE device through a baseboard management controller configured in RC mode includes:

[0131] PCIE devices are directly controlled through the baseboard management controller configured in RC mode and MCTP control instructions.

[0132] Specifically, a baseboard management controller configured in RC mode can not only manage PCIE devices through address operation instructions but also directly control PCIE devices through MCTP control instructions, which is the MTCP over PCIE method shown in Figures 1 and 2. While the aforementioned method of managing PCIE devices through address instructions requires parsing of received and sent information, managing PCIE devices through MCTP control instructions requires only the use of MCTP control instructions, as the MCTP protocol is a specialized protocol that does not require parsing. Since all currently used PCIE devices support the MCTP protocol, adopting the MCTP control instruction management method improves the efficiency of the baseboard management controller's management of PCIE devices. The technical solutions for address operation instructions and MCTP control instructions can be interchanged based on actual needs.

[0133] The MCTP control instruction management method is adopted to improve the management efficiency of the baseboard management controller for PCIE devices.

[0134] In one embodiment, before directly controlling the PCIE device using a baseboard management controller configured in RC mode and MCTP control instructions, the method further includes:

[0135] PCIE devices are discovered through the MCTP protocol, and device identification codes are assigned to discovered PCIE devices and baseboard management controllers configured in RC mode.

[0136] Specifically, before managing PCIE devices through a baseboard management controller configured in RC mode and MCTP control instructions, it is necessary to assign device identification codes (EIDs) to the baseboard management controller and PCIE devices to facilitate determining the source EID and destination EID, thereby enabling the baseboard management controller to communicate with and manage the PCIE devices.

[0137] In one embodiment, discovering a PCIE device through the MCTP protocol and assigning a device identification code to the discovered PCIE device and a baseboard management controller configured in RC mode includes:

[0138] Send a 0x0B control request broadcast packet to the PCIE device and inform the baseboard management controller of the device identification code;

[0139] Receive the response 0x0B command of the PCIE device and obtain the PCIE device with the undiscovered mark;

[0140] Send a 0x0C control request broadcast packet to the PCIE device and inform the baseboard management controller of the device identification code;

[0141] Receive the response 0x0C command of the PCIE device carrying the not found mark;

[0142] Send a 0x01 control request to the PCIE device and carry a device identification code for configuring the PCIE device, so as to mark the PCIE device carrying the undiscovered mark as a discovered mark and assign a device identification code to the PCIE device;

[0143] Receive a PCIE device marked as discovered and its corresponding device identification code.

[0144] Specifically, according to the MCTP protocol, the process of assigning identification codes to PCIE devices and baseboard management controllers is as follows: the bus owner (the baseboard management controller configured in RC mode) sends a 0x0B control request broadcast packet to the PCIE device and informs the bus owner of the device identification code; the bus owner receives the PCIE device's response 0x0B instruction and obtains the PCIE device with the undiscovered mark; the bus owner sends a 0x0C control request broadcast packet to the PCIE device and informs the bus owner of the device identification code; the bus owner receives the response 0x0C instruction of the PCIE device with the undiscovered mark; the bus owner sends a 0x01 control request to the PCIE device and carries the device identification code for configuring the PCIE device; the PCIE device with the undiscovered mark is marked as discovered and assigned a corresponding device identification code, and the bus owner receives the PCIE device marked as discovered and its corresponding device identification code.

[0145] Assign device identification codes (EIDs) to the baseboard management controller and PCIE devices to facilitate the determination of source EIDs and destination EIDs, thereby enabling the baseboard management controller to manage PCIE devices and improving management efficiency.

[0146] In one embodiment, before sending a 0x0B control request broadcast packet to the PCIE device and informing the baseboard management controller of the device identification code, the method further includes:

[0147] Receive the 0x0D control request sent from the PCIE device and obtain the PCIE device with the undiscovered mark;

[0148] Send a response 0x0D command to the PCIE device carrying the not found mark.

[0149] Specifically, in the process of assigning device identification codes to PCIE devices, some PCIE devices need to actively send control requests to the bus owner. Therefore, for such PCIE devices, before the bus owner sends a 0x0B instruction, it is necessary to receive a 0x0D control request sent from the PCIE device and obtain a PCIE device with an undiscovered mark; then send a response 0x0D instruction to the PCIE device with the undiscovered mark to continue executing the bus owner sending a 0x0B instruction operation step to assign device identification codes to the baseboard management controller and PCIE devices.

[0150] In one embodiment, a PCIE device management method further includes:

[0151] Obtain PCIE device fault information through the baseboard management controller configured in RC mode.

[0152] Specifically, since the baseboard management controller configured in RC mode in this application obtains the permission to manage PCIE devices directly through the central processing unit configured as the agent as the bus owner, the baseboard management controller configured in RC mode can directly obtain the fault information of PCIE devices through the central processing unit configured as the agent, without having to wait for the server to be fully powered on and the embedded controller to operate normally to obtain the fault information.

[0153] By obtaining the fault information of the PCIE device through the baseboard management controller configured in RC mode, the time for obtaining the fault information is reduced, the efficiency of obtaining the fault information is improved, and the maintenance personnel are notified more promptly to perform maintenance on the PCIE device in the fault state.

[0154] In one embodiment, a PCIE device management method further includes:

[0155] The first PCIE controller in the baseboard management controller is configured to be in EP mode, and the second PCIE controller of the central processing unit is configured to be in RC mode;

[0156] Specifically, both the first PCIE controller and the second PCIE controller have EP mode and RC mode. The working modes of the first PCIE controller and the second PCIE controller are configured according to actual needs. For example, the first PCIE controller in the baseboard management controller is configured to EP mode, that is, the slave end; the second PCIE controller in the central processing unit is configured to RC mode, that is, the master end (bus owner); at this time, the central processing unit obtains the authority to manage the PCIE device, and the baseboard management controller cannot actively obtain the device information of the PCIE device, nor can it access the configuration space of the PCIE device.

[0157] Directly control PCIE devices through the central processing unit configured in RC mode.

[0158] Specifically, at this time, the central processing unit obtains the management authority of the PCIE device, and the baseboard management controller can only capture the device information of the PCIE device through the embedded controller, and then send the device information of the PCIE device to the baseboard management controller.

[0159] In some embodiments, referring to FIG4 , FIG4 is a flowchart of a second method of the PCIE device management method provided in an embodiment of the present application. In the method shown in FIG4 , for the same or similar contents as those in the method shown in FIG3 , reference can be made to the description of the method in FIG3 , and no further description is given here.

[0160] S201, obtaining a driver for a PCIE first switch chip, installing the driver for the PCIE first switch chip into a baseboard management controller, and establishing a PCIE specification and protocol between the baseboard management controller chip and the PCIE first switch chip;

[0161] A PCIE first switching chip is added to the baseboard management controller, so the driver of the PCIE first switching chip must be obtained first, and then the driver of the PCIE first switching chip must be installed to the baseboard management controller so that the first switching chip can operate normally on the baseboard management controller; in addition, the driver of the PCIE first switching chip will establish communication between the baseboard management controller chip and the PCIE first switching chip, that is, establish the PCIE specifications and protocols between the baseboard management controller chip and the PCIE first switching chip, so that PCIE communication can be achieved between the baseboard management controller chip and the PCIE first switching chip.

[0162] S202: Configure a controller register, an MCTP register, and an XDMA register of a first PCIE controller in a baseboard management controller to configure the first PCIE controller in the baseboard management controller to an RC mode;

[0163] Configure the controller registers of the PCIE primary controller in the baseboard management controller to configure the root port. The PCIE device and the baseboard management controller communicate through the root port. Configure MCTP-related communication protocols to implement MCTP communication. Configure DMA memory access (direct memory access).

[0164] S203, configuring the PCIE second controller of the central processing unit to EP mode, so as to configure the terminal where the central processing unit is located as an agent terminal;

[0165] The CPU's PCIE secondary controller is configured in EP mode, meaning the CPU acts as a slave to the BMC, accepting control from the BMC. The BMC then gains management authority over the PCIE devices. The CPU's terminal is configured as a proxy, meaning the host terminal can be set to RC Proxy, enabling the BMC to directly access the PCIE device's configuration space as the true bus owner.

[0166] S204, using the baseboard management controller configured in RC mode as the bus owner to obtain management authority for the PCIE device, so as to communicate with the PCIE device through the terminal where the central processing unit configured as the agent is located;

[0167] The PCIE first controller in the baseboard management controller is configured as RC mode, that is, the master end, that is, the baseboard management controller configured in RC mode is used as the bus owner, that is, the baseboard management controller configured in RC mode obtains management authority over the PCIE device, so as to communicate with the PCIE device through the terminal where the central processing unit configured as the agent end is located, thereby realizing management of the PCIE device.

[0168] S205: Discover PCIE devices through the MCTP protocol, and assign device identification codes to the discovered PCIE devices and the baseboard management controller configured in RC mode;

[0169] Before managing PCIE devices using a baseboard management controller configured in RC mode and MCTP control instructions, it is necessary to assign device identification codes (EIDs) to the baseboard management controller and PCIE devices to facilitate the determination of the source EID and destination EID, enabling the baseboard management controller to manage the PCIE devices.

[0170] S206: Directly control the PCIE device through a baseboard management controller configured in RC mode and MCTP control instructions.

[0171] The PCIE device is managed through the baseboard management controller configured in RC mode and the MCTP control instructions. That is, the configuration space of the PCIE device is accessed through the baseboard management controller configured in RC mode and the MCTP control instructions to implement relevant configuration of the configuration space of the PCIE device or obtain device information of the PCIE device.

[0172] It should be understood that although the steps in the flowcharts of Figures 3 to 4 are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in Figures 3 to 4 may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0173] In some embodiments, referring to FIG. 5 , FIG. 5 is a system structure diagram of a PCIE device management system provided in an embodiment of the present application.

[0174] The PCIE device management system of this embodiment includes:

[0175] A driver module is used to obtain a driver for the PCIE first switching chip, install the driver for the PCIE first switching chip into the baseboard management controller, and establish a PCIE specification and protocol between the baseboard management controller chip and the PCIE first switching chip;

[0176] A PCIE first switching chip is added to the baseboard management controller, so the driver of the PCIE first switching chip is first obtained through the driver module, and then the driver of the PCIE first switching chip is installed to the baseboard management controller through the driver module, so that the first switching chip can operate normally on the baseboard management controller; in addition, the driver of the PCIE first switching chip will establish communication between the baseboard management controller chip and the PCIE first switching chip, that is, establish the PCIE specifications and protocols between the baseboard management controller chip and the PCIE first switching chip, so that PCIE communication can be achieved between the baseboard management controller chip and the PCIE first switching chip.

[0177] A mode configuration module is used to configure the PCIE first controller in the baseboard management controller to RC mode and the PCIE second controller of the central processing unit to EP mode;

[0178] After PCIE communication is established between the baseboard management controller chip and the first PCIE switch chip, the mode configuration module configures the first PCIE controller in the baseboard management controller to RC mode, i.e., the master end (bus owner); and then configures the second PCIE controller of the central processing unit to EP mode, i.e., the slave end; so that the baseboard management controller configured in RC mode can manage the PCIE device;

[0179] The management module is used to directly control the PCIE device through a baseboard management controller configured in RC mode.

[0180] Since the master end has the active authority to operate the slave end; therefore, the baseboard management controller configured in RC mode as the master end has the authority to obtain PCIE device information and establishes a PCIE communication mechanism. Therefore, the baseboard management controller as the RC has the management authority over the PCIE device. The baseboard management controller can directly obtain the device information of the PCIE device and directly control the PCIE device through the management module.

[0181] For the specific definition of the PCIE device management system, please refer to the definition of the method above and will not be repeated here. Each module in the above-mentioned PCIE device management system can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory of the computer device in software form, so that the processor can call and execute the corresponding operations of each of the above modules.

[0182] In some embodiments, a computer device is provided, including a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor. When the processor executes the computer-readable instructions, the steps of the PCIE device management method are implemented.

[0183] The computer device may be a terminal, and its internal structure diagram may be shown in FIG6 . The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer-readable instructions. The internal memory provides an environment for the operation of the operating system and computer-readable instructions in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer-readable instructions are executed by the processor, a PCIE device management method is implemented. The display screen of the computer device may be a liquid crystal display or an electronic ink display screen, and the input device of the computer device may be a touch layer covering the display screen, or a key, trackball, or touchpad provided on the computer device housing, or an external keyboard, touchpad, or mouse.

[0184] Those skilled in the art should understand that the structure shown in Figure 6 is merely a block diagram of a portion of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0185] In one embodiment, a computer device is provided, including a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor. When the processor executes the computer-readable instructions, the following steps are performed:

[0186] Obtain a driver for the PCIE first switch chip, install the driver for the PCIE first switch chip into the baseboard management controller, and establish PCIE specifications and protocols between the baseboard management controller chip and the PCIE first switch chip;

[0187] The first PCIE controller in the baseboard management controller is configured to be in RC mode, and the second PCIE controller of the central processing unit is configured to be in EP mode;

[0188] The PCIE device is directly controlled by the baseboard management controller configured in RC mode.

[0189] In some embodiments, a computer-readable storage medium is provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor, the following steps are implemented:

[0190] Obtain a driver for the PCIE first switch chip, install the driver for the PCIE first switch chip into the baseboard management controller, and establish PCIE specifications and protocols between the baseboard management controller chip and the PCIE first switch chip;

[0191] The first PCIE controller in the baseboard management controller is configured to be in RC mode, and the second PCIE controller of the central processing unit is configured to be in EP mode;

[0192] The PCIE device is directly controlled by the baseboard management controller configured in RC mode.

[0193] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing related hardware through computer-readable instructions, and the computer-readable instructions can be stored in a non-volatile computer-readable storage medium. When the computer-readable instructions are executed, they may include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0194] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0195] The above embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A PCIE device management architecture, characterized in that: The PCIE device management architecture includes: A baseboard management controller, wherein a baseboard management controller chip, a PCIE first switching chip and a PCIE first controller are arranged in the baseboard management controller, the baseboard management controller chip is connected to the PCIE first switching chip, and the PCIE first controller is configured in RC mode; and A central processing unit is connected to the baseboard management controller for communication, wherein a PCIE second controller is provided in the central processing unit, and the PCIE second controller is configured as an EP mode; The central processing unit is connected to a PCIE second switching chip, and the PCIE second switching chip is connected to a plurality of PCIE devices; Wherein, the PCIE device is directly controlled by the baseboard management controller configured in RC mode.

2. The PCIE device management architecture according to claim 1, characterized in that: A south bridge chip is connected between the central processing unit and the baseboard management controller, and an embedded controller is arranged in the south bridge chip.

3. A PCIE device management method using the PCIE device management architecture as described in any one of claims 1 to 2, characterized in that: The PCIE device management method comprises: Obtain a driver for a PCIE first switching chip, install the driver for the PCIE first switching chip into a baseboard management controller, and establish a PCIE specification and protocol between the baseboard management controller chip and the PCIE first switching chip; The PCIE first controller in the baseboard management controller is configured to be in RC mode, and the PCIE second controller of the central processing unit is configured to be in EP mode; and The PCIE device is directly controlled by the baseboard management controller configured in RC mode.

4. The PCIE device management method according to claim 3, characterized in that: The configuring the PCIE first controller in the baseboard management controller to the RC mode includes: The register of the PCIE first controller in the baseboard management controller is configured to configure the PCIE first controller in the baseboard management controller to an RC mode.

5. The PCIE device management method according to claim 4, characterized in that: The configuring the register of the PCIE first controller in the baseboard management controller includes: The controller register of the PCIE first controller in the baseboard management controller is configured to configure the root port.

6. The PCIE device management method according to claim 5, characterized in that: The configuring the register of the PCIE first controller in the baseboard management controller also includes: The MCTP register of the PCIE first controller in the baseboard management controller is configured.

7. The PCIE device management method according to claim 6, characterized in that: The configuring the register of the PCIE first controller in the baseboard management controller also includes: The XDMA register of the PCIE first controller in the baseboard management controller is configured.

8. The PCIE device management method according to claim 7, characterized in that: The configuring the PCIE second controller of the central processing unit to the EP mode includes: The PCIE second controller of the central processor is configured as an EP mode, so as to configure the terminal where the central processor is located as an agent terminal.

9. The PCIE device management method according to claim 8, characterized in that: After configuring the PCIE second controller of the central processing unit to the EP mode, the method further includes: The baseboard management controller configured in RC mode is used as a bus owner to obtain management authority over the PCIE device, so as to communicate with the PCIE device through the terminal where the central processor configured as an agent is located.

10. The PCIE device management method according to claim 3, characterized in that: Directly controlling the PCIE device by the baseboard management controller configured in RC mode includes: The PCIE device is directly controlled by the baseboard management controller configured in RC mode and address operation instructions.

11. The PCIE device management method according to claim 3, characterized in that: Directly controlling the PCIE device by the baseboard management controller configured in RC mode includes: The PCIE device is directly controlled by the baseboard management controller configured in RC mode and the MCTP control instruction.

12. The PCIE device management method according to claim 3, characterized in that: Directly controlling the PCIE device by the baseboard management controller configured in RC mode includes: Accessing the configuration space of the PCIE device through the baseboard management controller configured in RC mode; and The configuration space of the PCIE device is controlled to enable or disable the device, and the interrupt mode of the PCIE device is set.

13. The PCIE device management method according to claim 3, characterized in that: The directly controlling the PCIE device by the baseboard management controller configured in RC mode further includes: Acquiring device information of the PCIE device by configuring the baseboard management controller in RC mode; and The device information of the PCIE device is stored in the memory of the baseboard management controller so that the display interface can display the device information.

14. The PCIE device management method according to claim 3, characterized in that: The method further comprises: The fault information of the PCIE device is obtained by the baseboard management controller configured in RC mode.

15. The PCIE device management method according to claim 11, characterized in that: Before directly controlling the PCIE device through the baseboard management controller configured in RC mode and the MCTP control instruction, the method further includes: The PCIE device is discovered through the MCTP protocol, and the discovered PCIE device and the PCIE device configured in RC mode are The baseboard management controller assigns a device identification code.

16. The PCIE device management method according to claim 15, characterized in that: The method of discovering the PCIE device through the MCTP protocol and allocating a device identification code to the discovered PCIE device and the baseboard management controller configured in the RC mode includes: Send a 0x0B control request broadcast packet to the PCIE device and inform the baseboard management controller of the device identification code; Receive a response 0x0B instruction of the PCIE device and obtain a PCIE device carrying a not found mark; Send a 0x0C control request broadcast packet to the PCIE device and inform the baseboard management controller of the device identification code; Receive the response 0x0C instruction of the PCIE device carrying the unfound mark; Sending a 0x01 control request to the PCIE device and carrying a device identification code for configuring the PCIE device, so as to mark the PCIE device carrying an undiscovered mark as a discovered mark and assign a device identification code to the PCIE device; and A PCIE device marked as discovered and its corresponding device identification code are received.

17. The PCIE device management method according to claim 16, characterized in that: Before sending a 0x0B control request broadcast packet to the PCIE device and informing the baseboard management controller of the device identification code, the method further includes: Receiving a 0x0D control request sent from the PCIE device and acquiring a PCIE device carrying an unfound mark; and Send a response 0x0D instruction to the PCIE device carrying the not found mark.

18. The PCIE device management method according to claim 3, characterized in that: The method further comprises: The PCIE first controller in the baseboard management controller is configured to be in EP mode, and the PCIE second controller of the central processing unit is configured to be in RC mode; and The PCIE device is directly controlled by the central processing unit configured in RC mode.

19. A PCIE device management system, characterized in that: The PCIE device management system includes: A driver module, used to obtain a driver program of a PCIE first switching chip, install the driver program of the PCIE first switching chip into a baseboard management controller, and establish a PCIE specification and protocol between the baseboard management controller chip and the PCIE first switching chip; A mode configuration module, configured to configure the PCIE first controller in the baseboard management controller to the RC mode, and configure the PCIE second controller of the central processing unit to the EP mode; and The management module is used to directly control the PCIE device through the baseboard management controller configured in RC mode.

20. A computer device comprising a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor, characterized in that: When the processor executes the computer-readable instructions, the steps of the method described in any one of claims 3 to 18 are implemented.

21. One or more non-volatile computer-readable storage media storing computer-readable instructions, wherein when the computer-readable instructions are executed by one or more processors, the one or more processors execute the steps of the method as claimed in any one of claims 3 to 18.

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