Processing device and display system

Abstract

The present invention provides a processing device with reduced power consumption. This processing device includes first and second line memories, a frame memory, and a processing circuit. The first line memory acquires a first line of data out of first image data and holds the first line of data. The frame memory holds second image data. The second line memory acquires a second line of data out of second image data read from the frame memory, and holds the second line of data. The processing circuit compares the first line of data read from the first line memory with the second line of data read from the second line memory, and transmits the comparison result to the first line memory. The first line memory acquires the comparison result from the processing circuit, and transmits the first line of data to the second line memory when the comparison result is that the first and second lines do not match. The second line memory writes the first line of data over the held second line of data.

Description

Processing device and display system

[0001] One aspect of the present invention relates to a processing device and a display system.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, sensors, processing devices (including processors), electronic devices, systems, operating methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] In recent years, improvements have been made in various aspects to display devices included in wearable devices, monitors, mobile phones (e.g., smartphones), wristwatch-type information terminals, tablet-type information terminals, notebook PCs (personal computers), etc. for XR (Extended Reality or Cross Reality) such as VR (Virtual Reality) and AR (Augmented Reality). For example, display devices are being developed to improve screen resolution, color reproducibility (NTSC ratio), size of driving circuits, and power consumption.

[0004] For example, in order to reduce power consumption, there is an operating method in which image data of two consecutive frames is compared, and if the image data is identical to each other, rewriting of one image data with the other image data is omitted.

[0005] Specifically, one such operation method is described in Patent Document 1. Patent Document 1 describes an operation method in which image data of the nth frame (where n is an integer of 1 or more) is stored in a first storage device, the mth row of the n+1th frame (where m is an integer of 1 or more) is stored in a second storage device, the image data of the mth row of each of the nth frame and the n+1th frame is read, a comparison circuit is used to determine whether or not the image data matches, and a write control circuit determines whether or not to write the image data of the mth row of the n+1th frame to the mth row of a display unit based on the determination result.

[0006] JP 2014-29503 A

[0007] In the above operating method, for example, if the image data in the mth row of the nth frame and the n+1th frame are the same, the image data in the mth row of the display unit is not rewritten, but on the other hand, the first storage device sequentially rewrites the image data for each frame. That is, even if the image data in the mth row of the nth frame and the n+1th frame are the same, the first storage device rewrites the image data from the mth row of the nth frame to the mth row of the n+1th frame. In this way, power consumption is generated even when the same image data is rewritten in the same mth row in the first storage device, so it is necessary not to rewrite the image data when the image data in the mth row of the nth frame and the n+1th frame are the same.

[0008] Furthermore, in the above operating method, the image data of the mth row of the n+1th frame read from the second storage device is input to the judgment circuit, and the judgment data generated by the judgment circuit is input to the write control circuit, so the writing speed (frame frequency) of image data to the display unit is affected not only by the read speed of the first storage device, but also by the processing time by the judgment circuit and the write control circuit. For example, when rewriting image data of the nth frame with image data of the n+1th frame on the display unit, if the processing time by the judgment circuit or the write control circuit is long, it takes time for the image data of the mth row of the n+1th frame read from the second storage device to reach the pixel circuit of the display unit, making it difficult to increase the frame frequency.

[0009] An object of one embodiment of the present invention is to provide a processing device capable of comparing image data between previous and next frames.An object of one embodiment of the present invention is to provide a processing device with reduced power consumption.An object of one embodiment of the present invention is to provide a display system including the processing device.An object of one embodiment of the present invention is to provide a display system in which a decrease in frame frequency is suppressed.An object of one embodiment of the present invention is to provide a novel processing device or a novel display system.

[0010] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems. Therefore, one embodiment of the present invention does not necessarily solve all of the above problem and other problems.

[0011] One aspect of the present invention, which solves the above problem, is a processing device including a first line memory, a second line memory, a frame memory, and a processing circuit.

[0012] For example, the frame memory is assumed to hold image data for the t-th frame (where t is an integer equal to or greater than 1) in advance. This image data can be displayed by pixel circuits with M rows and N columns (where M and N are both integers equal to or greater than 1). In other words, the frame memory holds image data for the 1st to Mth rows of the t-th frame.

[0013] The first line memory also holds image data of the i-th row (where i is an integer between 1 and M) of the t+1-th frame transmitted from outside the processing device.

[0014] The second line memory holds image data of the i-th row of the t-th frame read out from the frame memory.

[0015] The processing circuit compares the image data of the i-th row of the t+1th frame read from the first line memory with the image data of the i-th row of the t-th frame read from the second line memory. If the comparison shows that the image data of the i-th row of the t+1th frame does not match the image data of the i-th row of the t-th frame, the first line memory transmits the read image data of the i-th row of the t+1th frame to the frame memory, and the frame memory rewrites the image data of the i-th row of the t-th frame that it holds with the image data of the i-th row of the t+1th frame. If the comparison shows that the image data of the i-th row of the t+1th frame matches the image data of the i-th row of the t-th frame, the first line memory does not transmit the image data of the i-th row of the t+1th frame to the frame memory, and does not rewrite the image data of the i-th row of the t-th frame with the image data of the i-th row of the t+1th frame in the frame memory.

[0016] In order to solve the above problem, an example of the configuration of a processing device including a first line memory, a second line memory, a frame memory, and a processing circuit that performs the above-mentioned comparison will be described below.

[0017] (1) One aspect of the present invention is a processing device including a first line memory, a second line memory, a frame memory, a processing circuit, and a storage circuit. The first line memory has a function of acquiring data of a first row of first image data and storing the first row data. The frame memory has a function of storing second image data. The second line memory has a function of acquiring data of a second row of second image data read from the frame memory and storing the second row data. The processing circuit has a function of comparing the data of the first row read from the first line memory with the data of the second row read from the second line memory and outputting comparison data including a comparison result.

[0018] The first line memory has a function of acquiring comparison data from the processing circuit and outputting the first row data to the frame memory when the comparison data includes a comparison result indicating that the first row data and the second row data do not match. The frame memory has a function of rewriting the stored second row data with the first row data transmitted from the first line memory. The storage circuit has a function of acquiring the comparison data from the processing circuit and storing the comparison data.

[0019] (2) Alternatively, in one aspect of the present invention, in the above (1), the processing circuit may have a configuration including N exclusive NOR circuits (here, N is an integer of 1 or more) and a NAND circuit including N input terminals.

[0020] In particular, it is preferable that one of the N exclusive NOR circuits has a function of performing a first logical operation using the value of the j-th column (where j is an integer between 1 and N) of the first row data read from the first line memory and the value of the j-th column of the second row data read from the second line memory, and outputting the result of the first logical operation. Also, it is preferable that the NAND circuit has a function of acquiring the N results of the first logical operations from the N input terminals, respectively, and performing a second logical operation using the N results of the first logical operations to generate comparison data.

[0021] (3) Another aspect of the present invention is a display system including a display device and the processing device according to (1), wherein the display device includes a first driver circuit, a second driver circuit, and a pixel circuit, and the processing device includes a signal processing circuit.

[0022] The signal processing circuit has a function of acquiring comparison data read from the storage circuit and generating a control signal using the comparison data. The first drive circuit has a function of performing a third logical operation using a control signal transmitted from the signal processing circuit and a selection signal for selecting a pixel circuit and transmitting the result of the third logical operation to the pixel circuit. The second drive circuit has a function of determining whether to transmit the first row data or the second row data to the pixel circuit in accordance with the control signal transmitted from the signal processing circuit.

[0023] (4) Alternatively, according to one embodiment of the present invention, in the above-described (3), the first driver circuit may include a decoder and an AND circuit.

[0024] In particular, the decoder preferably has a function of generating a selection signal and transmitting the selection signal to a first input terminal of the AND circuit. The signal processing circuit preferably has a function of transmitting a control signal to a second input terminal of the AND circuit. The AND circuit preferably has a function of performing a third logical operation using the control signal and the selection signal and outputting the result of the third logical operation.

[0025] (5) Alternatively, according to one embodiment of the present invention, in the above (3), the second driver circuit may include a holding circuit, a digital-to-analog conversion circuit, and a switch. In particular, it is preferable that an output terminal of the holding circuit is electrically connected to an input terminal of the digital-to-analog conversion circuit. It is also preferable that a first terminal of the switch is electrically connected to the output terminal of the digital-to-analog conversion circuit, a second terminal of the switch is electrically connected to the pixel circuit, and a control terminal of the switch is electrically connected to a wiring to which a control signal is transmitted. It is also preferable that the frame memory has a function of transmitting data of the first row or the second row to the input terminal of the holding circuit.

[0026] Next, an embodiment of the present invention that is different from the above (1) to (5) will be described.

[0027] One aspect of the present invention is a display system including a processing device and a display device, wherein the processing device includes a first line memory, a second line memory, a first frame memory, a second frame memory, a storage circuit, and a processing circuit.

[0028] The second frame memory is assumed to have image data for the t-th frame (where t is an integer greater than or equal to 1) stored in advance. This image data can be displayed by pixel circuits with M rows and N columns (where M and N are each an integer greater than or equal to 1). In other words, the second frame memory stores image data for the 1st to Mth rows of the t-th frame.

[0029] The first line memory also stores image data of the i-th row (where i is an integer between 1 and M) of the t+1-th frame transmitted from outside the processing device. The first frame memory also stores image data of the i-th row of the t+1-th frame.

[0030] The second frame memory also reads out image data for the i-th row of the t-th frame and transmits it to the second line memory. At this time, the second frame memory can transmit the image data for the i-th row of the t-th frame to the display device. The second line memory holds the image data for the i-th row of the t-th frame read out from the second frame memory.

[0031] The processing circuit compares the image data of the i-th row of the t+1-th frame read from the first line memory with the image data of the i-th row of the t-th frame read from the second line memory, and stores the comparison result in the memory circuit.

[0032] In other words, with the above configuration, while the processing circuit is comparing the image data of the i-th row of the t+1th frame read out from the first line memory with the image data of the i-th row of the t-th frame read out from the second line memory, the image data of the i-th row of the t-th frame can be transmitted from the second frame memory to the display device.

[0033] Below, we describe an example configuration of a display system that solves the above problem and includes a first line memory, a second line memory, a first frame memory, a second frame memory, a memory circuit, and a processing circuit that performs the above-mentioned comparison.

[0034] (6) One aspect of the present invention is a display system including a first line memory, a second line memory, a first frame memory, a second frame memory, a processing circuit, and a storage circuit. The first line memory has a function of acquiring first row data of first image data and storing the first row data. The first frame memory has a function of acquiring first row data read from the first line memory and storing the first row data. The second frame memory has a function of storing second image data and a function of reading second row data of the second image data and transmitting the second row data to a second storage circuit and a display device. The second line memory has a function of acquiring second row data read from the second frame memory and storing the second row data. The processing circuit has a function of comparing the first row data read from the first line memory with the second row data read from the second line memory and outputting comparison data including a comparison result. The storage circuit has a function of acquiring the comparison data from the processing circuit and storing the comparison data.

[0035] (7) Alternatively, in one aspect of the present invention, in the above (6), the processing circuit may include N (here, N is an integer of 1 or more) exclusive NOR circuits and a NAND circuit.

[0036] In particular, it is preferable that one of the N exclusive NOR circuits has a function of performing a first logical operation using the value of the j-th column (j is an integer between 1 and N) of the first row data read from the first line memory and the value of the j-th column of the second row data read from the second line memory, and outputting the result of the first logical operation. Also, it is preferable that the NAND circuit has a function of performing a second logical operation using the N results of the first logical operations from each of its N input terminals, and generating comparison data.

[0037] (8) Alternatively, in one embodiment of the present invention, in the above-described (6), the display device may include a first driver circuit, a second driver circuit, and a pixel circuit, and the processing device may include a signal processing circuit.

[0038] In particular, it is preferable that the signal processing circuit has a function of acquiring comparison data read from the memory circuit and generating a control signal using the comparison data. Also, it is preferable that the first drive circuit has a function of performing a third logical operation using a control signal transmitted from the signal processing circuit and a selection signal for selecting a pixel circuit, and transmitting the result of the third logical operation to the pixel circuit. Also, it is preferable that the second drive circuit has a function of determining whether to transmit data of the first row or data of the second row to the pixel circuit in accordance with the control signal transmitted from the signal processing circuit.

[0039] (9) Alternatively, according to one embodiment of the present invention, in the above-described (8), the first driver circuit may include a decoder and an AND circuit.

[0040] In particular, the decoder preferably has a function of generating a selection signal and transmitting the selection signal to a first input terminal of the AND circuit. The signal processing circuit preferably has a function of transmitting a control signal to a second input terminal of the AND circuit. The AND circuit preferably has a function of performing a third logical operation using the control signal and the selection signal and outputting the result of the third logical operation.

[0041] (10) Alternatively, according to one embodiment of the present invention, in the above (8), the second driver circuit may include a holding circuit, a digital-to-analog conversion circuit, and a switch. In particular, it is preferable that the output terminal of the holding circuit is electrically connected to the input terminal of the digital-to-analog conversion circuit. It is also preferable that the first terminal of the switch is electrically connected to the output terminal of the digital-to-analog conversion circuit. It is also preferable that the second terminal of the switch is electrically connected to the pixel circuit. It is also preferable that the control terminal of the switch is electrically connected to a wiring to which a control signal is transmitted. It is also preferable that the first frame memory has a function of transmitting data of the first row or data of the second row to the input terminal of the holding circuit.

[0042] Next, one embodiment of the present invention that is different from the above (1) to (10) will be described.

[0043] One aspect of the present invention is a display system including a processing device and a display device, the processing device including a frame memory, a storage circuit, and a processing circuit, and the frame memory includes a first memory cell and a second memory cell.

[0044] The memory cell also has a function of simultaneously executing a write operation from the first memory cell and a read operation from the second memory cell, and a function of simultaneously executing a read operation from the first memory cell and a read operation from the second memory cell.

[0045] The second memory cell is assumed to have image data for the t-th frame (where t is an integer greater than or equal to 1) stored in advance. The image data can be displayed by pixel circuits with M rows and N columns (where M and N are each an integer greater than or equal to 1). In other words, the second memory cell stores image data for the 1st to Mth rows of the t-th frame.

[0046] Furthermore, the first memory cell holds image data for the (t+1)th frame transmitted from outside the processing device. As described above, while the image data for the (t+1)th frame is being held in the first memory cell, the image data for the (t)th frame in the second memory cell can be output.

[0047] Below, a description will be given of an example of the configuration of a processing device including a frame memory, a storage circuit, and a processing circuit that performs the above-mentioned comparison, and a display system including the processing device.

[0048] (11) One aspect of the present invention is a processing device including a frame memory, a storage circuit, and a processing circuit. The frame memory includes a first memory cell and a second memory cell. The frame memory has a function of overlapping a write operation on one of the first memory cell and the second memory cell and a read operation on the other of the first memory cell and the second memory cell. The frame memory also has a function of overlapping a read operation on the first memory cell and a read operation on the second memory cell. The processing circuit has a function of comparing first image data read from the first memory cell with second image data read from the second memory cell and outputting comparison data including a comparison result. The storage circuit has a function of acquiring the comparison data from the processing circuit and holding the comparison data.

[0049] (12) Alternatively, according to one embodiment of the present invention, in the above (11), the frame memory may have a first selection circuit, a second selection circuit, and a third selection circuit, and each of the first memory cell and the second memory cell may have a first transistor, a second transistor, and a capacitor.

[0050] In particular, in each of the first memory cell and the second memory cell, one of the source and drain of the first transistor is preferably electrically connected to one of a pair of terminals of the capacitance element and the gate of the second transistor. The first selection circuit is preferably electrically connected to the gate of the first transistor of the first memory cell. The second selection circuit is preferably electrically connected to the gate of the first transistor of the second memory cell. The third selection circuit is preferably electrically connected to the other of the pair of terminals of the first capacitance element of the first memory cell and the other of the pair of terminals of the first capacitance element of the second memory cell.

[0051] (13) Alternatively, in one aspect of the present invention, in the above (12), the processing circuit may have a configuration including N exclusive NOR circuits (here, N is an integer of 1 or more) and a NAND circuit including N input terminals.

[0052] In particular, it is preferable that one of the N exclusive NOR circuits has a function of performing a first logical operation using the value of the jth column (where j is an integer between 1 and N) of the first image data read from the first memory cell and the value of the jth column of the second image data read from the second memory cell, and outputting the result of the first logical operation. Also, it is preferable that the NAND circuit has a function of acquiring the N results of the first logical operations from the N input terminals, respectively, and performing a second logical operation using the N results of the first logical operations to generate comparison data.

[0053] (14) Another aspect of the present invention is a display system including a display device and the processing device described in (11). The display device includes a first driver circuit, a second driver circuit, and a pixel circuit, and the processing device includes a signal processing circuit. The signal processing circuit has a function of acquiring comparison data read from the memory circuit and generating a control signal using the comparison data. The first driver circuit has a function of performing a third logical operation using a control signal transmitted from the signal processing circuit and a selection signal for selecting the pixel circuit and transmitting the result of the third logical operation to the pixel circuit. The frame memory has a function of reading first image data from the first memory cell and transmitting the first image data to the second driver circuit while rewriting the second image data stored in the second memory cell with third image data. The second driver circuit has a function of determining whether to transmit the first image data to the pixel circuit in response to the control signal transmitted from the signal processing circuit.

[0054] (15) Alternatively, according to one embodiment of the present invention, in the above-described (14), the first driver circuit may include a decoder and an AND circuit.

[0055] In particular, the decoder preferably has a function of generating a selection signal and transmitting the selection signal to a first input terminal of the AND circuit. The signal processing circuit preferably has a function of transmitting a control signal to a second input terminal of the AND circuit. The AND circuit preferably has a function of performing a third logical operation using the control signal and the selection signal and outputting the result of the third logical operation.

[0056] (16) Alternatively, in one aspect of the present invention, in the above (14), the second driver circuit may include a holding circuit, a digital-to-analog conversion circuit, and a switch. In particular, it is preferable that the output terminal of the holding circuit is electrically connected to the input terminal of the digital-to-analog conversion circuit. It is also preferable that the first terminal of the switch is electrically connected to the output terminal of the digital-to-analog conversion circuit, the second terminal of the switch is electrically connected to the pixel circuit, and the control terminal of the switch is electrically connected to a wiring to which a control signal is transmitted. It is also preferable that the frame memory has a function of transmitting the first image data to the input terminal of the holding circuit.

[0057] The memory circuits included in the processing devices described in (11) to (16) above may be replaced with two memory circuits, i.e., a first memory circuit and a second memory circuit, so that while comparison data is being written to one of the first memory circuit and the second memory circuit, different comparison data can be read from the other of the first memory circuit and the second memory circuit.

[0058] Below, we will describe an example of the configuration of a processing device that includes a frame memory, a first storage circuit, a second storage circuit, and a processing circuit, and a display system that includes the processing device, in order to solve the above problem.

[0059] (17) Another embodiment of the present invention is a processing device including a frame memory, a first memory circuit, a second memory circuit, and a processing circuit. The frame memory includes a first memory cell and a second memory cell. The frame memory has a function of overlapping a write operation on one of the first memory cell and the second memory cell and a read operation on the other of the first memory cell and the second memory cell. The frame memory also has a function of overlapping a read operation on the first memory cell and a read operation on the second memory cell. The processing circuit has a function of comparing first image data read from the first memory cell with second image data read from the second memory cell and outputting first comparison data including a comparison result. One of the first memory circuit and the second memory circuit has a function of acquiring the first comparison data from the processing circuit and holding the first comparison data.

[0060] (18) Alternatively, according to one embodiment of the present invention, in the above (17), the frame memory may have a first selection circuit, a second selection circuit, and a third selection circuit, and each of the first memory cell and the second memory cell may have a first transistor, a second transistor, and a capacitor.

[0061] In particular, in each of the first memory cell and the second memory cell, one of the source and drain of the first transistor is preferably electrically connected to one of a pair of terminals of the capacitance element and the gate of the second transistor. The first selection circuit is preferably electrically connected to the gate of the first transistor of the first memory cell. The second selection circuit is preferably electrically connected to the gate of the first transistor of the second memory cell. The third selection circuit is preferably electrically connected to the other of the pair of terminals of the first capacitance element of the first memory cell and the other of the pair of terminals of the first capacitance element of the second memory cell.

[0062] (19) Alternatively, in one aspect of the present invention, in the above (18), the processing circuit may have a configuration including N exclusive NOR circuits (here, N is an integer of 1 or more) and a NAND circuit including N input terminals.

[0063] In particular, it is preferable that one of the N exclusive NOR circuits has a function of performing a first logical operation using the value of the jth column (here, j is an integer between 1 and N) of the first image data read from the first memory cell and the value of the jth column of the second image data read from the second memory cell, and outputting the result of the first logical operation. Also, it is preferable that the NAND circuit has a function of acquiring the N results of the first logical operations from the N input terminals, respectively, and performing a second logical operation using the N results of the first logical operations to generate first comparison data.

[0064] (20) Another aspect of the present invention is a display system including a display device and the processing device described in (17). The display device includes a first driving circuit, a second driving circuit, and a pixel circuit, and the processing device includes a signal processing circuit. The signal processing circuit has a function of acquiring first comparison data read from one of the first memory circuit and the second memory circuit and generating a control signal using the first comparison data. The first driving circuit has a function of performing a third logical operation using a control signal transmitted from the signal processing circuit and a selection signal for selecting the pixel circuit and transmitting the result of the third logical operation to the pixel circuit. The frame memory has a function of reading first image data from the first memory cell and transmitting the first image data to the second driving circuit while writing third image data to the second memory cell. The second driving circuit has a function of determining whether to transmit the first image data to the pixel circuit in accordance with the control signal transmitted from the signal processing circuit.

[0065] (21) Alternatively, according to one aspect of the present invention, in the above (20), the processing circuit may have a function of comparing the first image data read from the first memory cell with the third image data read from the second memory cell, and outputting second comparison data including a comparison result. In this case, it is preferable that the other of the first memory circuit and the second memory circuit has a function of acquiring the second comparison data from the processing circuit and holding the second comparison data.

[0066] (22) Alternatively, in one embodiment of the present invention, in the above-described (21), the first driver circuit may include a decoder and an AND circuit.

[0067] In particular, the decoder preferably has a function of generating a selection signal and transmitting the selection signal to a first input terminal of the AND circuit. The signal processing circuit preferably has a function of transmitting a control signal to a second input terminal of the AND circuit. Furthermore, the AND circuit preferably performs a third logical operation using the control signal and the selection signal and outputs the result of the third logical operation.

[0068] (23) Alternatively, in one aspect of the present invention, in the above (21), the second driver circuit preferably includes a holding circuit, a digital-to-analog conversion circuit, and a switch. In particular, it is preferable that the output terminal of the holding circuit is electrically connected to the input terminal of the digital-to-analog conversion circuit. It is also preferable that the first terminal of the switch is electrically connected to the output terminal of the digital-to-analog conversion circuit, the second terminal of the switch is electrically connected to the pixel circuit, and the control terminal of the switch is electrically connected to a wiring to which a control signal is transmitted. It is also preferable that the frame memory has a function of transmitting the first image data to the input terminal of the holding circuit.

[0069] By using the processing device described in (1) or (2) above or the display system described in any one of (3) to (5) above, when the image data for the mth row of the nth frame and the n+1th frame are the same, it is possible to prevent the image data for the mth row of the nth frame from being rewritten to the mth row of the n+1th frame in the frame memory. Therefore, when there is no change in at least one row of image data between previous and next frames in the frame memory, it is possible to reduce the number of times that image data for each row is rewritten. This reduces the power consumption of the frame memory.

[0070] Furthermore, by using the display system described in any one of (6) to (10) above, it is possible to transmit image data of the mth row of the nth frame to the display device while comparing image data of the mth row of each of the nth frame and the n+1th frame. Therefore, even if the processing time of each circuit included in the processing device is long, it is possible to transmit image data to the display device during that processing time, thereby preventing a decrease in the frame frequency of the display system.

[0071] Furthermore, by using a processing device described in any one of (11) to (13), (17) to (19) above, or a display system described in any one of (14) to (16), (20) to (23) above, it is possible to prevent a decrease in the frame frequency of the display system while reducing the circuit area more than the processing device described in (1) or (2) above, or the processing device described in each of (3) to (10) above.

[0072] According to one embodiment of the present invention, a processing device capable of comparing image data between previous and next frames can be provided. Alternatively, according to one embodiment of the present invention, a processing device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a display system including the processing device can be provided. Alternatively, according to one embodiment of the present invention, a display system in which a decrease in frame frequency is suppressed can be provided. Alternatively, according to one embodiment of the present invention, a novel processing device or a novel display system can be provided.

[0073] Note that the effects of one embodiment of the present invention are not limited to the above-described effects. The above-described effects do not preclude the existence of other effects. The other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the above-described effects and other effects. Therefore, one embodiment of the present invention may not have the above-described effects in some cases.

[0074] FIG. 1 is a block diagram showing an example of the configuration of a display system. FIG. 2 is a flowchart showing an example of the operation of the display system. FIG. 3 is a block diagram showing an example of the configuration of a circuit included in the display system. FIG. 4 is a block diagram showing an example of the configuration of a circuit included in the display system. FIG. 5 is a block diagram showing an example of the configuration of a circuit included in the display system. FIG. 6 is a block diagram showing an example of the configuration of a circuit included in the display system. FIG. 7 is a block diagram showing an example of the configuration of a circuit included in the display system. FIGS. 8A and 8B are circuit diagrams showing an example of the configuration of a circuit included in the display system. FIG. 9A is a block diagram showing an example of the configuration of a circuit included in the display system, and FIG. 9B is a timing chart showing an example of the operation of the circuit included in the display system. FIGS. 10A to 10D are circuit diagrams showing an example of the configuration of a circuit included in the display system. FIG. 11 is a timing chart showing an example of the operation of the circuit included in the display system. FIG. 12 is a block diagram showing an example of the configuration of a circuit included in the display system. FIG. 13 is a timing chart showing an example of the operation of the circuit included in the display system. FIG. 14 is a block diagram showing an example of the configuration of a display system. FIG. 15 is a flowchart showing an example of the operation of the display system. FIG. 16 is a block diagram showing an example of the configuration of a circuit included in the display system. FIG. 17 is a block diagram showing an example of the configuration of a circuit included in the display system. Fig. 18 is a block diagram showing an example of the configuration of a circuit included in the display system. Fig. 19 is a block diagram showing an example of the configuration of a circuit included in the display system. Fig. 20 is a block diagram showing an example of the configuration of a display system. Fig. 21 is a flowchart showing an example of the operation of the display system. Fig. 22 is a block diagram showing an example of the configuration of a circuit included in the display system. Fig. 23 is a block diagram showing an example of the configuration of a circuit included in the display system. Fig. 24 is a timing chart showing an example of the operation of a circuit included in the display system. Fig. 25 is a timing chart showing an example of the operation of a circuit included in the display system. Fig. 26 is a block diagram showing an example of the configuration of a circuit included in the display system. Fig. 27 is a block diagram showing an example of the configuration of a display system. Fig. 28 is a flowchart showing an example of the operation of the display system.FIG. 29 is a block diagram showing an example of the configuration of a circuit included in a display system. FIG. 30 is a block diagram showing an example of the configuration of a circuit included in a display system. FIG. 31 is a block diagram showing an example of the configuration of a circuit included in a display system. FIGS. 32A to 32F are circuit diagrams showing an example of the configuration of a memory cell. FIGS. 33A to 33F are circuit diagrams showing an example of the configuration of a memory cell. FIGS. 34A to 34D are circuit diagrams showing an example of the configuration of a pixel circuit. FIGS. 35A and 35B are circuit diagrams showing an example of the configuration of a pixel circuit. FIGS. 36A and 36B are circuit diagrams showing an example of the configuration of a pixel circuit. FIG. 37 is a circuit diagram showing an example of the configuration of a pixel circuit. FIGS. 38A to 38C are schematic perspective views showing an example of the configuration of a display device. FIG. 39 is a block diagram showing an example of the configuration of a display device. FIG. 40 is a schematic cross-sectional view showing an example of the configuration of a display device. FIG. 41A is a schematic plan view showing an example of the configuration of a transistor, and FIGS. 41B and 41C are schematic cross-sectional views showing an example of the configuration of a transistor. Fig. 42A is a schematic plan view showing an example of the configuration of a transistor, and Figs. 42B and 42C are schematic cross-sectional views showing an example of the configuration of a transistor. Figs. 43A to 43C are schematic cross-sectional views showing an example of the configuration of a part of a display device. Fig. 44 is a schematic cross-sectional view showing an example of the configuration of a display device. Fig. 45 is a schematic cross-sectional view showing an example of the configuration of a display device. Fig. 46 is a schematic cross-sectional view showing an example of the configuration of a display device. Figs. 47A and 47B are diagrams showing an example of the configuration of a display module. Figs. 48A to 48I are diagrams showing examples of electronic devices.

[0075] (Additional Notes Related to the Present Specification) In the present specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. Also, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit, and another example of a semiconductor device is an electronic component in which a chip is housed in a package. Also, for example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device, or may include a semiconductor device.

[0076] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film or a layer).

[0077] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, an inductor, a resistive element, a diode, a display device, a light-emitting device, and a load) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0078] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (for example, inverters, NAND circuits, and NOR circuits), signal conversion circuits (for example, digital-analog conversion circuits, analog-digital conversion circuits, and gamma correction circuits), potential level conversion circuits (for example, power supply circuits such as step-up circuits or step-down circuits, and level shifter circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplifier circuits (for example, circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, and buffer circuits), signal generation circuits, memory circuits, and control circuits) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0079] It should be noted that when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit sandwiched between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit sandwiched between them).

[0080] Furthermore, for example, it can be expressed as follows: "X, Y, the source (e.g., sometimes referred to as one of the first terminal or the second terminal) and the drain (e.g., sometimes referred to as the other of the first terminal or the second terminal) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source of the transistor, the drain of the transistor, and Y." Or, it can be expressed as follows: "The source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to specify the order of connections in the circuit configuration, it is possible to distinguish between the source and drain of the transistor and determine the technical scope. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film or a layer).

[0081] Note that even when independent components are shown electrically connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has both the function of a wiring and the function of an electrode. Therefore, in this specification, the term "electrically connected" also includes such a case where one conductive film has the functions of multiple components.

[0082] In this specification, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, a "resistance element" includes a wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, or a coil. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, a resistance value can be, for example, 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0083] In this specification, a "capacitive element" can refer to a circuit element having a capacitance value higher than 0 F, for example. A "capacitive element" (including a "capacitive element" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in a "capacitive element" can be rephrased as a "pair of electrodes," a "pair of conductive regions," a "pair of regions," or a "pair of terminals." The terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It may also be, for example, 1 pF or more and 10 μF or less.

[0084] However, there are cases where a circuit has an area with unintended capacitance, that is, "parasitic capacitance." Examples of "parasitic capacitance" include an area including different wirings connected via an insulator, and gate capacitance occurring in a transistor. In this specification, unless otherwise specified, the term "capacitive element" is explained as not including "parasitic capacitance."

[0085] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. For this reason, in this specification, the terms source and drain are sometimes interchangeable. Furthermore, in this specification, when describing the connection relationship of a transistor, the terms "one of the source and drain" and "the other of the source and drain" are sometimes used. Furthermore, "one of the source and drain" may be referred to as "a first terminal of the transistor" or "a first electrode of the transistor," and "the other of the source and drain" may be referred to as "a second terminal of the transistor" or "a second electrode of the transistor."

[0086] Depending on the structure of the transistor, a back gate may be provided in addition to the three terminals described above. In this case, in this specification, one of the gate or the back gate of the transistor may be referred to as a first gate, and the other of the gate or the back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, in this specification, when a transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, etc.

[0087] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. With a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Alternatively, the multi-gate structure can provide a source-drain voltage-drain current characteristic with a flat slope, where the drain current does not change significantly even when the source-drain voltage changes when operating in the saturation region. For example, by utilizing a source-drain voltage-drain current characteristic with a flat slope, an ideal current source circuit, an active load with a very high resistance, and the like can be realized. As a result, a differential circuit, a current mirror circuit, and the like with excellent characteristics can be realized.

[0088] Furthermore, even when a single circuit element is depicted on a circuit diagram, the circuit element may actually include multiple circuit elements. For example, when a single resistor is depicted on a circuit diagram, this includes the case where two or more resistors are directly connected in series. Furthermore, two or more resistors directly connected in series may be represented as a single resistor. For example, when a single capacitance element is depicted on a circuit diagram, this includes the case where two or more capacitance elements are directly connected in parallel. Furthermore, two or more capacitance elements directly connected in parallel may be represented as a single capacitance element. Furthermore, when a single transistor is depicted on a circuit diagram, this includes the case where two or more transistors are directly connected in series with their sources and drains connected together and their gates connected together. Furthermore, when two or more transistors are directly connected in series with their sources and drains connected together and their gates connected together, this may be represented as a single transistor. For example, when one transistor is shown on a circuit diagram, this includes a case where the first terminals of two or more transistors are directly connected to each other, the second terminals of the respective transistors are directly connected to each other, and the gates of the respective transistors are directly connected to each other. Also, a configuration in which the first terminals of two or more transistors are directly connected to each other, the second terminals of the respective transistors are directly connected to each other, and the gates of the respective transistors are directly connected to each other can sometimes be represented as a single transistor.

[0089] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows, or a device that can select and switch a path for a current to flow.

[0090] Furthermore, the switch may have two or more terminals for passing current in addition to the control terminal. For example, an electrical switch, a mechanical switch, or the like may be used. In other words, the switch is not limited to a specific type as long as it has the function of controlling current.

[0091] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source and drain of the transistor are considered to be electrically short-circuited, or a state in which current can flow between the source and drain. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor are considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0092] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls the conductive and non-conductive states.

[0093] In this specification, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, or an impurity region depending on the circuit configuration and device structure. A terminal, a wiring, or the like can also be referred to as a node.

[0094] Furthermore, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0095] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0096] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0097] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of components, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the counter may be omitted in the claims. For example, a component referred to with the ordinal number "first" in one embodiment of this specification may be referred to with a different ordinal number, such as "second" or "third," in other embodiments or claims. Furthermore, for example, a component referred to with the ordinal number "first" in one embodiment of this specification may be omitted in other embodiments or claims.

[0098] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, etc., and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0099] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0100] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the orientation in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees. Similarly, the expression "column direction" may be rephrased as "row direction" by rotating the orientation of the drawing by 90 degrees.

[0101] Furthermore, in this specification, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film". For example, the term "insulating film" can be changed to the term "insulating layer". Furthermore, depending on the situation, the terms "film" and "layer" can be replaced with other terms without using them. For example, the terms "conductive layer" or "conductive film" can be changed to the term "conductor". Furthermore, for example, the terms "insulating layer" or "insulating film" can be changed to the term "insulator".

[0102] Furthermore, the terms "electrode," "wiring," and "terminal" used herein do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0103] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, a term such as "signal line" may be changed to the term "power line." Furthermore, a term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, the term "signal" may be changed to the term "potential."

[0104] In addition, in this specification, timing charts in the drawings may be used to explain an operation method of a semiconductor device. The timing charts used in the description show ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potentials or currents) shown in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including nodes) in the timing charts may be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as long and the other as short, the lengths of the two periods may be equal, or one period may be short and the other may be long. For example, to clearly illustrate the timing chart, two or more overlapping signals may be intentionally shifted.

[0105] In this specification, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0106] In this specification, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0107] In this specification, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0108] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0109] In this specification, the configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. When multiple configuration examples are shown in one embodiment, the configuration examples can be combined with each other as appropriate.

[0110] In addition, the content (part or all of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (part or all of the content) described in that embodiment and another content (part or all of the content) described in one or more other embodiments.

[0111] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0112] Furthermore, a figure (part or all) described in one embodiment can be combined with another part of that figure, another figure (part or all) described in that embodiment, and at least one figure (part or all) described in one or more other embodiments to form even more figures.

[0113] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0114] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Furthermore, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings or the like, the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0115] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0116] Embodiment 1 In this embodiment, a processing device according to one embodiment of the present invention and a display system including the processing device will be described.

[0117] 1 is a block diagram showing an example of the configuration of a display system according to one embodiment of the present invention. The display system DSYS shown in FIG. 1 includes, as an example, a display device DSP and a processing device PRC. The display device DSP also includes a pixel array unit PXA and a driving circuit unit DRA.

[0118] The pixel array unit PXA includes, as an example, a plurality of pixel circuits PX. The plurality of pixel circuits PX are arranged in an array within the pixel array unit PXA. In particular, FIG. 1 shows, as an example, an example in which the plurality of pixel circuits PX are arranged in a matrix of M rows and N columns (here, M and N are each an integer of 1 or greater) within the pixel array unit PXA.

[0119] In order to distinguish each of the pixel circuits PX within the pixel array section PXA, an address is added to the reference numeral of each of the pixel circuits PX shown in Fig. 1. For example, the pixel circuit PX located in row 1, column 1 is illustrated as PX[1,1], the pixel circuit PX located in row M, column 1 is illustrated as PX[M,1], the pixel circuit PX located in row 1, column N is illustrated as PX[1,N], and the pixel circuit PX located in row M, column N is illustrated as PX[M,N]. Furthermore, although not shown in Fig. 1, the pixel circuit PX located in row i, column j (where i is an integer between 1 and M, and j is an integer between 1 and N) is referred to as pixel circuit PX[i,j] in this specification.

[0120] The pixel circuit PX can be a pixel circuit to which one or more light emitting devices selected from the group consisting of a liquid crystal display device, a light emitting device including an organic electroluminescence (EL) material, a light emitting device including an inorganic EL material, and a light emitting device including a light emitting diode such as a mini LED (Light Emitting Diode) or a micro LED are applied.

[0121] In the pixel array section PXA, wirings SL[1] to SL[N] extend in the column direction, and wirings GL[1] to GL[M] extend in the row direction.

[0122] For example, the wiring GL[i] is connected to each of the pixel circuits PX[i,1] to PX[i,N]. For example, the wiring SL[j] is connected to each of the pixel circuits PX[1,j] to PX[M,j].

[0123] For example, each of the wirings SL[1] to SL[N] functions as a wiring for transmitting an image signal.

[0124] For example, each of the wirings GL[1] to GL[M] functions as a wiring for transmitting a selection signal for selecting a pixel circuit PX to which an image signal is written.

[0125] 1, each of the wirings SL[1] to SL[N] is illustrated as a single wiring, but each of the wirings SL[1] to SL[N] can be regarded as a wiring group in which two or more wirings are grouped together. Similarly, in FIG. 1, each of the wirings GL[1] to GL[M] is illustrated as a single wiring, but each of the wirings GL[1] to GL[M] can be regarded as a wiring group in which two or more wirings are grouped together.

[0126] The drive circuit unit DRA includes, for example, a drive circuit SD and a drive circuit GD.

[0127] For example, the driver circuit SD is connected to each of the wirings SL[1] to SL[N], and the driver circuit GD is connected to each of the wirings GL[1] to GL[M].

[0128] The driver circuit GD functions as, for example, a gate driver circuit for selecting pixel circuits PX to which an image signal is to be written. That is, the driver circuit GD has a function of transmitting a selection signal to the wiring GL of a row to which an image signal is to be written and transmitting a non-selection signal to the wiring GL of a row not to which an image signal is to be written. For this reason, the driver circuit GD is sometimes called a selection circuit or a gate line selection circuit.

[0129] The drive circuit GD also has a function of switching the selection signal sent to a specific row to a non-selection signal when the display image of that row does not change between frames before and after the image displayed in the pixel array unit PXA. Whether the display image of the specific row changes is determined by a control signal sent to the drive circuit GD and generated by a signal processing circuit PG, which will be described later.

[0130] The drive circuit SD has a function as a source driver circuit for transmitting an image signal to the pixel circuit PX, for example.

[0131] The drive circuit SD also has a function of not transmitting an image signal for the second image to a given row when the display image of the first image displayed in the pixel array unit PXA does not change between the first image and the second image, which is the frame following the first image. In other words, the drive circuit SD can operate so as not to overwrite the first image data written in the pixel circuits of that row with the second image data. In this case, for example, the drive circuit SD may have a function of setting its output to high impedance at the timing when the image signal for the second image to be transmitted to that row should not be transmitted. Furthermore, this timing is determined by a control signal generated by a signal processing circuit PG, which will be described later, and transmitted to the drive circuit SD.

[0132] The processing device PRC has a memory circuit FM, a memory circuit LM1, a memory circuit LM2, a memory circuit FGM, a processing circuit SGPR, a signal processing circuit PG, and a control circuit TC.

[0133] The memory circuit LM1 functions as a first line memory, for example. Specifically, for example, the memory circuit LM1 temporarily stores image data for at least one row of an image to be displayed in the pixel array unit PXA. The memory circuit LM1 also functions to acquire image data D[i] (image data may also be referred to as an image signal) to be transmitted to the i-th row of the pixel array unit PXA from outside the processing device PRC. The memory circuit LM1 also functions to read out the stored image data D[i] and transmit it to the processing circuit SGPR. The memory circuit LM1 may also have a function to read out the stored image data D[i] and transmit it to the memory circuit FM in accordance with comparison data (described later) transmitted from the processing circuit SGPR.

[0134] The memory circuit FM functions as a frame memory, for example. Specifically, the memory circuit FM temporarily stores image data for all rows of an image to be displayed in the pixel array unit PXA. The memory circuit FM also acquires, from the memory circuit LM1, image data D[1] to D[M] to be transmitted to the first to Mth rows of the pixel array unit PXA, respectively. The memory circuit FM also sequentially reads out the stored image data D[1] to D[M] and transmits them to the drive circuit SD. The memory circuit FM also reads out the stored image data D[i] and transmits it to the memory circuit LM2.

[0135] The memory circuit LM2, for example, functions as a second line memory. Specifically, for example, the memory circuit LM2, like the memory circuit LM1, functions to temporarily store at least one row of image data for an image to be displayed in the pixel array unit PXA. Furthermore, the number of rows of image data that can be stored in the memory circuit LM2 is preferably equal to that of the memory circuit LM1. Furthermore, for example, the memory circuit LM2 functions to acquire image data D[i] from the memory circuit FM. Furthermore, the memory circuit LM2 functions to read out the stored image data D[i] and transmit it to the processing circuit SGPR.

[0136] For example, the processing circuit SGPR has a function of comparing a predetermined number of rows of image data read out from each of the memory circuits LM1 and LM2. Specifically, the processing circuit SGPR has a function of comparing the image data D[i] of the i-th row held in each of the memory circuits LM1 and LM2, outputting comparison data C[i] as a result of the comparison, and transmitting the comparison data C[i] to the memory circuit FGM. The processing circuit SGPR may also have a function of transmitting the comparison data C[i] to the memory circuit LM1.

[0137] For example, the memory circuit FGM has a function of holding comparison data C[i] transmitted from the processing circuit SGPR. The memory circuit FGM can hold comparison data C[1] to C[M] for the number of rows in the pixel array unit PXA. The memory circuit FGM also has a function of reading out the comparison data C[i] and transmitting it to the signal processing circuit PG. The memory circuit FGM is sometimes referred to as a flag memory because it holds comparison data used to determine whether or not to rewrite an image displayed in the pixel array unit PXA.

[0138] The control circuit TC, for example, has the function of controlling each circuit included in the processing device PRC and each circuit included in the display device DSP. For example, the control circuit TC has the function of transmitting command signals to the drive circuits included in the memory circuit LM1, memory circuit LM2, memory circuit FM, and memory circuit FGM to perform write operations, read operations, etc. The control circuit TC also has the function of transmitting command signals to the drive circuits SD and drive circuit GD to perform write operations, read operations, etc. The control circuit TC also has the function of transmitting command signals to control the on / off switching of switching elements included in the memory circuit LM1, memory circuit LM2, memory circuit FM, memory circuit FGM, and processing circuit SGPR. The control circuit TC also has the function of generating clock signals to be supplied to each circuit included in the processing device PRC and each circuit included in the display device DSP.

[0139] In addition, the control circuit TC may have the function of transmitting a control signal generated by the signal processing circuit PG, a clock signal generated by the control circuit TC, etc. as a synchronization signal to two or more selected circuits, in order to synchronize two or more selected circuits, each circuit included in the processing device PRC and each circuit included in the display device DSP.

[0140] For example, the signal processing circuit PG has a function of generating a control signal (sometimes referred to as a pulse control signal) using the comparison data C[1] to C[M] sequentially read from the memory circuit FGM, and a function of transmitting the control signal to the driver circuit GD and the driver circuit SD.

[0141] <Example of Operation of Display System> Next, an example of operation of the display system DSYS shown in FIG. 1 will be described.

[0142] Fig. 2 is a flowchart showing an example of the operation of the display system DSYS in Fig. 1. This example of the operation includes steps ST1 to ST14.

[0143] The flowchart in FIG. 2 shows the operation of rewriting the t-th frame (t is an integer equal to or greater than 1) image, which is pre-displayed on the pixel array unit PXA, with the t+1-th frame image.

[0144] The memory circuit FM stores image data D （ｔ） [1] to Image Data D （ｔ） It is assumed that [M] is held.

[0145] In step ST1, as an example, i, which is a variable of the row number of the pixel array unit PXA, is set to 1.

[0146] In step ST2, for example, image data D of the i-th row of the t+1-th frame is input from the outside of the processing device PRC to the memory circuit LM1. （ｔ＋１） Step ST2 also includes an operation of transmitting image data D[i] to the memory circuit LM1. （ｔ＋１） The operation in which [i] is written is also included.

[0147] In step ST3, for example, image data D （ｔ＋１） It involves the operation of reading [i] and sending it to the processing circuit SGPR.

[0148] In step ST4, for example, the image data D （ｔ） [i] is read out and transmitted to the memory circuit LM2. （ｔ） It also includes the operation of reading [i] and sending it to the processing circuit SGPR.

[0149] In step ST5, for example, the processing circuit SGPR （ｔ） [i] and image data D （ｔ＋１） In addition, step ST5 includes an operation of comparing the image data D （ｔ） [i] and image data D （ｔ＋１） If [i] matches, the processing circuit SGPR outputs the comparison data C （ｔ＋１） [i] to the memory circuit FGM. （ｔ） [i] and image data D （ｔ＋１） If [i] does not match, the processing circuit SGPR outputs the comparison data C （ｔ＋１） The comparison data C （ｔ＋１） The logic included in [i] is an example, and depending on the circuit configuration, for example, image data D （ｔ） [i] and image data D （ｔ＋１） If [i] matches, the comparison data C （ｔ＋１） [i] contains logic "1", and image data D （ｔ） [i] and image data D （ｔ＋１） If [i] does not match, the comparison data C （ｔ＋１） [i] may include logic "0".

[0150] In step ST5, for example, the comparison data C （ｔ＋１） The operation in which [i] is written is also included.

[0151] In step ST5, for example, comparison data C （ｔ＋１） When [i] is "1", image data D （ｔ＋１） [i] is read out and transmitted to the memory circuit FM. At this time, the memory circuit FM reads out the image data D （ｔ） [i] is the image data D read out from the memory circuit LM1 （ｔ＋１） The comparison data C （ｔ＋１） Even if [i] is "0", the image data D （ｔ＋１） [i] is read out and the image data D held in the memory circuit FM is （ｔ） In this case, the image data D （ｔ） [i] and image data D （ｔ＋１） Since [i] is the same data, this operation is performed by （ｔ） This can be considered as a refresh operation of [i].

[0152] In step ST5 and subsequent steps, for convenience, the image data D held in the memory circuit FM is used regardless of whether the image data in the memory circuit FM is rewritten or not. （ｔ） [i] is image data D （ｔ＋１） This will be referred to as [i].

[0153] In step ST6, it is determined whether i has reached M. If i has not reached M, the process proceeds from step ST6 to step ST7. If i has reached M, the process proceeds from step ST6 to step ST8.

[0154] Step ST7 includes an operation of adding 1 to i. After adding 1 to i, the process returns to step ST2.

[0155] In step ST8, as an example, k is defined as a variable representing the row number of the pixel array unit PXA. In step ST8, k is set to 1. In steps ST8 to ST14, k is a variable that satisfies the range of 1 to M.

[0156] When proceeding to step ST9, since step ST5 has been repeatedly performed from i=1 to i=M, the comparison data C （ｔ＋１） [1] to Comparison Data C （ｔ＋１） In step ST9, for example, the comparison data C is stored in the memory circuit FGM. （ｔ＋１） [k] is read out and transmitted to the signal processing circuit PG.

[0157] In step ST10, as an example, the signal processing circuit PG generates a continuous pulse signal and comparison data C （ｔ＋１） [k] and the comparison data C （ｔ＋１） The step ST10 includes an operation of generating a control signal including information [k]. Also, as an example, step ST10 includes an operation of transmitting the control signal to the drive circuit GD and the drive circuit SD. For specific logical operations, please refer to the description of the configuration example of the signal processing circuit PG described later.

[0158] In step ST11, the image data D held in the memory circuit FM is （ｔ＋１） [k] is read out and input to the drive circuit SD.

[0159] Step ST12 includes an operation in which the drive circuit GD performs a logical operation on the selection signal, the logic of which is set to "1" and which is sent to the k-th row of the pixel array unit PXA, and the control signal. （ｔ＋１） When the logic of [k] is "0", the selection signal is converted into a non-selection signal (logic "0") with the logic set to "0" as a result of the logical operation, and is sent to the wiring GL[k]. （ｔ＋１） When the logic of [k] is "1", the selection signal is not converted into a non-selection signal as a result of the logical operation, but is sent to the wiring GL[k] as a logic "1" as is. Note that at this time, it is preferable to regard a non-selection signal with a logic "0" as a low-level potential signal, and a selection signal with a logic "1" as a high-level potential signal.

[0160] In step ST12, the drive circuit SD determines whether or not to set the output of the drive circuit SD to high impedance in response to the control signal generated by the signal processing circuit PG. （ｔ＋１） When the logic of [k] is "0", the driving circuit SD sets its output to high impedance, and the image data D （ｔ＋１） [k] is not output. （ｔ＋１） When the logic of [k] is "1", the driving circuit SD （ｔ＋１） [k] is output.

[0161] In step ST13, it is determined whether k has reached M. If k has not reached M, the process proceeds from step ST13 to step ST14. If k has reached M, the present operation example ends.

[0162] Step ST14 includes an operation of adding 1 to k. After adding 1 to k, the process returns to step ST9.

[0163] After this operation example is completed, the image of the t+1th frame may be rewritten to the image of the t+2th frame by referring to the operation example of steps ST1 to ST14.

[0164] By performing the operation example of steps ST1 to ST14, it is possible to compare image data between previous and next frames and rewrite image data for rows in the pixel array unit PXA that have been changed, thereby reducing the power consumption of the display system.

[0165] In this specification, each process or operation shown in a flowchart is classified by function and shown as a mutually independent step. However, in actual processes or operations, it is difficult to separate the processes or operations shown in a flowchart by function, and there may be cases where one step involves multiple steps, or where one step involves multiple steps. Therefore, the processes shown in the flowchart are not limited to the steps described in the specification, and can be appropriately rearranged depending on the situation. Specifically, the order of steps can be rearranged, and steps can be added or deleted depending on the situation.

[0166] Therefore, the operation method of the processing device of one embodiment of the present invention or the operation method of the display system including the processing device is not limited to the above-described operation example of the flowchart in Fig. 2. For example, in the flowchart in Fig. 2, steps ST1 to ST7 compare image data of previous and next frames and write the comparison data to the memory circuit FGM, and steps ST8 to ST14 read the comparison data from the memory circuit FGM, generate a control signal from the comparison data, and write image data to the display device. However, steps ST8 to ST14 can be performed simultaneously with all or part of the period in which steps ST1 to ST7 are performed.

[0167] Specifically, in steps ST1 to ST7, image data D （ｔ＋１） [i] and image data D （ｔ＋２） [i] is compared with the comparison data C （ｔ＋２） [i] is acquired and stored in the memory circuit FGM as comparison data C （ｔ＋２） [i] is written, and in steps ST8 to ST14, the comparison data C is written from the memory circuit FGM. （ｔ＋１） [k] and image data D from the memory circuit FM. （ｔ＋１） [i] is read and the comparison data C （ｔ＋１） Based on [k], the image data D is output to the pixel array unit PXA of the display device DSP. （ｔ＋１）That is, the memory circuit FGM may write the comparison data C （ｔ＋２） Write operation of [i] and comparison data C （ｔ＋１） By switching between the readout operation of [k] and the readout operation of [k], the operating method of a processing device according to one embodiment of the present invention or the operating method of a display system including a processing device can overlap part or all of the periods of steps ST1 to ST7 and steps ST8 to ST14. This allows the comparison process of image data of previous and next frames in steps ST1 to ST7 and the writing of image data to the display device in steps ST8 to ST14 to be performed simultaneously, thereby reducing the impact of the time required for the comparison process. Furthermore, since the impact of the time required for the comparison process can be reduced, the frame frequency of the display device can be increased.

[0168] <Configuration Example of Each Circuit in Display System> Next, a configuration example of each circuit included in the display system DSYS shown in FIG. 1 will be described.

[0169] In this configuration example, the operation of rewriting the image of the tth frame (where t is an integer greater than or equal to 1) that is pre-displayed in the pixel array unit PXA with the image of the t+1th frame is shown.

[0170] The memory circuit FM stores image data D （ｔ） [1] to Image Data D （ｔ） It is assumed that [M] is held.

[0171] [Memory Circuit LM1] Fig. 3 is a block diagram showing a configuration example of the memory circuit LM1. In Fig. 3, a processing circuit SGPR and a memory circuit FM are also shown in order to show the connection configuration of the memory circuit LM1 and its periphery.

[0172] The memory circuit LM1 shown in FIG. 3 includes, as an example, a drive circuit WBD1, a drive circuit WWD1, a drive circuit RWD1, a drive circuit RBD1, a memory cell unit MCA1, and an output unit OPT1.

[0173] The memory cell unit MCA1 has, as an example, a plurality of memory cells MC1. Also, in Fig. 3, as an example, N memory cells MC1 are arranged in one row in the memory cell unit MCA1. Note that in Fig. 3, the N memory cells MC1 may be arranged in the column direction instead of the row direction.

[0174] In order to distinguish between the multiple memory cells MC1 in the memory cell unit MCA1, the reference numerals of the multiple memory cells MC1 shown in Figure 3 are accompanied by an address. For example, the memory cell MC1 located in the first column is illustrated as MC1[1], and the memory cell MC1 located in the Nth column is illustrated as MC1[N]. Furthermore, although not shown in Figure 3, the memory cell MC1 located in the jth column is referred to as memory cell MC1[j] in this specification.

[0175] The specific configuration of the memory cells MC1[1] to MC1[N] will be described later.

[0176] The memory cells MC1[1] to MC1[N] store image data D of the i-th row transmitted from the outside of the processing device PRC. （ｔ＋１） The image data D[i] of the i-th row stored in the memory cells MC1[1] to MC1[N] is also stored. （ｔ＋１） As an example, [i] is ultimately transmitted to the pixel circuits PX[i,1] to PX[i,N] in the i-th row of the pixel array unit PXA.

[0177] In FIG. 3, the image data of the i-th row transmitted from outside the memory device LM1 is indicated as D[i].

[0178] The image data D handled by the display system DSYS （ｔ＋１） When one column of [i] (image data written to one pixel circuit PX) can be expressed as a 1-bit digital potential (high-level potential or low-level potential), each of the memory cells MC1[1] to MC1[N] is preferably configured to hold 1-bit data. In this case, the image data written to one pixel circuit PX can be expressed as a 1-bit digital potential.

[0179] In addition, image data D handled by the display system DSYS （ｔ＋１） When [i] can be expressed as a digital potential of 2 bits or more, each of the memory cells MC1[1] to MC1[N] is preferably configured to hold data of 2 bits or more. （ｔ＋１） When one column of [i] is expressed as an 8-bit digital potential, each of memory cells MC1[1] to MC1[N] preferably includes eight memory elements capable of storing 1 bit. In this case, for example, the memory cell unit MCA1 may be configured such that 8×N memory elements are arranged in a single column. In addition, in this case, the image data written to one pixel circuit PX may be an analog potential obtained by digital-to-analog conversion of the 8-bit digital potential.

[0180] As an example, the memory cell MC1[j] is connected to a wiring WBL1[j], a wiring RBL1[j], a wiring WWL1, and a wiring RWL1.

[0181] The wirings WBL1[1] to WBL1[N] transmit image data D （ｔ＋１） The wiring WWL1 functions as a wiring (sometimes referred to as a write data line, a write bit line, etc.) that transmits image data D[i] read from the memory cells MC1[1] to MC1[N]. The wiring WWL1 also functions as a wiring (sometimes referred to as a write word line) that transmits a write selection signal to the memory cells MC1[1] to MC1[N]. The wiring RWL1 also functions as a wiring (sometimes referred to as a read word line) that transmits a read selection signal to the memory cells MC1[1] to MC1[N]. The wiring RWL1 may also function as a wiring that transmits not only a read selection signal but also a write selection signal. The wirings RBL1[1] to RBL1[N] are respectively connected to the wirings RBL1[1] to RBL1[N]. （ｔ＋１）It functions as a wiring for transmitting [i] (sometimes called a read data line, a read bit line, etc.).

[0182] As an example, the drive circuit WBD1 receives image data D （ｔ＋１） [i] is acquired and the image data D （ｔ＋１） The driver circuit WBD1 has a function of distributing data for each column included in [i] to each of the wirings WBL1[1] to WBL1[N]. That is, the driver circuit WBD1 has a function as a write bit line driver circuit in the memory cell unit MCA1, for example.

[0183] As an example, the driver circuit WWD1 writes image data D （ｔ＋１） When writing [i] to the wiring WWL1, the wiring WWL1 has a function of transmitting a selection signal for writing to the wiring WWL1. For example, when a selection signal for writing is transmitted to the wiring WWL1, the write transistors included in each of the memory cells MC1[1] to MC1[N] are turned on, so that the memory cells MC1[1] to MC1[N] can write the image data D （ｔ＋１） After that, the driver circuit WWD1 transmits a non-selection signal to the wiring WWL1, so that the write transistors included in the memory cells MC1[1] to MC1[N] are turned off. （ｔ＋１） [i]. That is, the drive circuit WWD1 functions as a write word line driver circuit in the memory cell unit MCA1, for example. Also, from the above, the drive circuit WWD1 may be called a selection circuit.

[0184] As an example, the driver circuit RWD1 receives image data D （ｔ＋１）When reading out the image data D[i], the memory cells MC1[1] to MC1[N] have a function of transmitting a selection signal for reading to the wiring RWL1. For example, when a selection signal for reading is transmitted to the wiring RWL1, the memory cells MC1[1] to MC1[N] transmit the image data D[i] to the wirings RBL[1] to RBL[N], respectively. （ｔ＋１） [i]. That is, the drive circuit RWD1 functions as a read word line driver circuit in the memory cell unit MCA1, for example. Also, from the above, the drive circuit RWD1 may be called a selection circuit.

[0185] For example, the driver circuit RBD1 has a function of receiving a read selection signal from the wiring RWL1 and amplifying the read potentials output from the memory cells MC1[1] to MC1[N] to the wirings RBL[1] to RBL[N] to a level at which the read potentials can be handled as digital data. （ｔ＋１） [i] can be transmitted as digital data to the memory circuit FM or the processing circuit SGPR. That is, the drive circuit RBD1 has a function as a read circuit in the memory cell unit MCA1, for example.

[0186] For example, the driver circuit RBD1 can be configured to have N sense amplifiers SA1 as shown in FIG. 3. In this configuration, each of the wirings RBL1[1] to RBL1[N] is connected to a sense amplifier SA1. The image data D read out from the memory cells MC1[1] to MC1[N] by the N sense amplifiers SA1 is （ｔ＋１） The read potential corresponding to [i] can be amplified to a level that can be treated as digital data.

[0187] As an example, the output unit OPT1 selects one of the processing circuit SGPR and the memory circuit FM, and outputs the image data D read from the memory cells MC1[1] to MC1[N] to the selected one. （ｔ＋１） It has the function of transmitting [i].

[0188] For example, the output unit OPT1 can be configured to have N switching circuits SWC1 as shown in Fig. 3. In this configuration, each of the N switching circuits SWC1 has a switch SW1A and a switch SW1B.

[0189] For example, an electrical switch or a mechanical switch can be used as the switch SW1A and the switch SW1B. Furthermore, a transistor or an analog switch can be used as one of the electrical switches. In particular, the transistor is preferably an OS transistor, for example. The OS transistor will be described in detail in Embodiment 7 or the like.

[0190] In this specification, each of the switches SW1A and SW1B is a switch that turns on when a high-level potential is input to its control terminal and turns off when a low-level potential is input to its control terminal. Furthermore, all switches described in this specification, including the switches SW1A and SW1B, turn on when a high-level potential is input to their control terminal and turn off when a low-level potential is input to their control terminal, unless otherwise specified.

[0191] In the j-th column, a first terminal of the switch SW1A is connected to the sense amplifier SA1, a second terminal of the switch SW1A is connected to the line OL1[j], and a control terminal of the switch SW1A is connected to the line SWL1A. Also, a first terminal of the switch SW1B is connected to the sense amplifier SA1, a second terminal of the switch SW1B is connected to the line WBLF[j], and a control terminal of the switch SW1B is connected to the line SWL1B.

[0192] The wirings OL1[1] to OL1[N] are connected to the processing circuit SGPR. The wirings WBLF[1] to WBLF[N] are connected to the memory circuit FM.

[0193] The wiring SWL1A functions as a wiring for switching the switch SW1A included in the switching circuit SWC1 between an on state and an off state, and therefore, for example, a high-level potential or a low-level potential is supplied to the wiring SWL1A as a signal for switching the state.

[0194] The wiring SWL1B functions as a wiring for switching the on state and off state of the switch SW1B included in the switching circuit SWC1. For this reason, for example, a high-level potential or a low-level potential is supplied to the wiring SWL1B as a signal for switching, similar to the wiring SWL1A.

[0195] Note that the potentials of the wirings SWL1A and SWL1B can be supplied from, for example, the control circuit TC.

[0196] The wiring SWL1B is connected to the comparison data C output from the processing circuit SGPR, not the control circuit TC. （ｔ＋１） [i] may be transmitted. This configuration will be explained in detail in the processing circuit SGPR.

[0197] In FIG. 3, the wirings OL1[1] to OL1[N] transmit the image data D from the memory circuit LM1 to the processing circuit SGPR. （ｔ＋１） The wirings WBLF[1] to WBLF[N] are shown as wirings for transmitting image data D[i] from the memory circuit LM1 to the memory circuit FM. （ｔ＋１） [i] is shown as a wiring for transmitting.

[0198] 3 shows that the memory circuit LM1 and the processing circuit SGPR are connected using multiple wirings, OL1[1] to OL1[N]. However, a configuration may be adopted in which a multiplexer is provided in the memory circuit LM1 and a demultiplexer is provided in the processing circuit SGPR, and the multiplexer and the demultiplexer are connected to each other. This configuration can reduce the number of wirings provided between the memory circuit LM1 and the processing circuit SGPR. Similarly, while FIG. 3 shows that the memory circuit LM1 and the memory circuit FM are connected using multiple wirings, WBLF1[1] to WBLF1[N], this configuration can reduce the number of wirings provided between the memory circuit LM1 and the processing circuit FM. Alternatively, a multiplexer may be provided in the memory circuit LM1 and a demultiplexer may be provided in the memory circuit FM, and the multiplexer and the demultiplexer may be connected to each other. This configuration can reduce the number of wirings provided between the memory circuit LM1 and the memory circuit FM.

[0199] [Memory Circuit FM] Fig. 4 is a block diagram showing an example of the configuration of the memory circuit FM. In Fig. 4, in order to show the connection configuration between the memory circuit FM and its peripheral circuits, the memory circuit LM1, the memory circuit LM2, and the drive circuit SD included in the display device DSP are also shown.

[0200] In addition, in the description of the configuration example of the memory circuit FM, the image data D （ｔ） [i] and image data D （ｔ＋１） [i] will be collectively referred to as image data D[i].

[0201] The memory circuit FM shown in FIG. 4 includes, as an example, a drive circuit WWDF, a drive circuit RWDF, a drive circuit RBDF, a memory cell unit MCAF, and an output unit OPTF.

[0202] The memory cell unit MCAF has, as an example, a plurality of memory cells MCF. In addition, in Fig. 4, as an example, MxN memory cells MCF are arranged in a matrix in the memory cell unit MCAF.

[0203] In order to distinguish between the plurality of memory cells MCF in the memory cell unit MCAF, addresses are added to the reference numerals of the plurality of memory cells MCF shown in Fig. 4. For example, the memory cell MCF located in row 1, column 1 is illustrated as MCF[1,1], the memory cell MCF located in row M, column 1 is illustrated as MCF[M,1], the memory cell MCF located in row 1, column N is illustrated as MCF[1,N], and the memory cell MCF located in row M, column N is illustrated as MCF[M,N]. Furthermore, although not shown in Fig. 4, the memory cell MCF located in row i, column j is referred to as memory cell MCF[i,j] in this specification.

[0204] Furthermore, for the memory cell MCF, unless otherwise specified, the description of the memory cell MC1 in the memory circuit LM1 can be referred to.

[0205] As an example, the memory cell MCF[i,j] is connected to a wiring WBLF[j], a wiring RBLF[j], a wiring WWLF[i], and a wiring RWLF[i].

[0206] For example, the wirings WBLF[1] to WBLF[N] each function as a write data line, a write bit line, or the like in the memory cells MCF[i,1] to MCF[i,N] located in the i-th row of the memory circuit FM. Furthermore, in the memory circuit LM1 shown in FIG. 3, when the switch SW1B of the switching circuit SWC1 is turned on, image data D[i] read from the memory cell unit MCA1 of the memory circuit LM1 is transmitted to the wirings WBLF[1] to WBLF[N]. For example, the j-th column component of the image data D[i] is transmitted to the memory cell MCF[i] via the wiring WBLF[j].

[0207] For each of the wirings RBLF[1] to RBLF[N], the description of the wirings RBL1[1] to RBL1[N] of the memory circuit LM1 can be referred to unless otherwise specified. For each of the wirings WWLF[1] to WWLF[M], the description of the wiring WWL1 of the memory circuit LM1 can be referred to unless otherwise specified. For each of the wirings RWLF[1] to RWLF[M], the description of the wiring RWL1 of the memory circuit LM1 can be referred to unless otherwise specified.

[0208] For example, the driver circuit WWDF has a function of transmitting a write select signal or a non-select signal to the wiring WWLF[i] when writing image data D[i] to the memory cells MCF[i,1] to MCF[i,N] in the i-th row of the memory cell unit MCAF. The driver circuit WWDF also has a function of transmitting a non-select signal to the wirings WWLF[1] to WWLF[M] excluding the wiring WWLF[i] to prevent writing to the memory cells MCF[1,1] to MCF[M,N] in rows other than the i-th row of the memory cell unit MCAF. By sequentially transmitting a select signal to each of the wirings WWLF[1] to WWLF[M], the memory cells MCF included in the memory cell unit MCAF can be sequentially selected row by row as the write destination of image data. That is, for example, the driver circuit WWDF functions as a write word line driver circuit in the memory cell unit MCAF. Further, the drive circuit WWDF may be called a selection circuit due to the above.

[0209] For example, while the driver circuit WWDF transmits a write selection signal to the wiring WWLF[i] and transmits a non-selection signal to the wirings WWLF[1] to WWLF[M] other than the wiring WWLF[i], image data D[i] is transmitted from the memory circuit LM1 to the wirings WBLF[1] to WBLF[N], thereby allowing the image data D[i] to be written to the memory cells MCF[i,1] to MCF[i,N] in the i-th row of the memory cell unit MCAF.

[0210] For example, the driver circuit RWDF has a function of transmitting a read selection signal to the wiring RWLF[i] when reading image data D[i] from the memory cells MCF[i,1] to MCF[i,N] in the i-th row of the memory cell unit MCAF. The driver circuit RWDF also has a function of transmitting a non-selection signal to the wirings RWLF[1] to RWLF[M] excluding the wiring RWLF[i] to prevent reading from the memory cells MCF[1,1] to MCF[M,N] in rows other than the i-th row of the memory cell unit MCAF. By sequentially transmitting a selection signal to each of the wirings RWLF[1] to RWLF[M], the memory cells MCF[1,1] to MCF[M,N] included in the memory cell unit MCAF can be sequentially selected row by row as the source of image data reading. That is, for example, the driver circuit RWDF functions as a read word line driver circuit in the memory cell unit MCAF. Further, the drive circuit WWDF may be called a selection circuit due to the above.

[0211] For example, the driver circuit RWDF sends a read selection signal to the wiring RWLF[i] and a non-selection signal to the wirings RWLF[1] to RWLF[M] other than the wiring RWLF[i], thereby outputting a read potential corresponding to the image data D[i] from each of the memory cells MCF[i,1] to MCF[i,N] in the i-th row of the memory cell unit MCAF to each of the wirings RBLF[1] to RBLF[N].

[0212] Unless otherwise specified, the description of the drive circuit RBDF can be referred to for the drive circuit RBD1 of the memory circuit LM1. As an example, the drive circuit RBDF has N sense amplifiers SAF as shown in FIG. 4. The sense amplifiers SAF can have the same configuration as the sense amplifier SA1 shown in FIG. 3.

[0213] As an example, the output unit OPTF has a function of selecting one of the memory circuit LM2 and the driver circuit SD and transmitting image data D[i] read out from the memory cells MCF[i,1] to MCF[i,N] to the selected one.

[0214] For example, the output unit OPTF can be configured to have N switching circuits SWCF as shown in Fig. 4. In this configuration, each of the N switching circuits SWCF has a switch SWFA and a switch SWFB.

[0215] For example, switches applicable to the switch SW1A or the switch SW1B of the memory circuit LM1 can be used for the switch SWFA and the switch SWFB. Therefore, unless otherwise specified, the description of the switch SW1A or the switch SW1B of the memory circuit LM1 can be referred to for the switch SWFA and the switch SWFB.

[0216] Furthermore, for example, the output unit OPTF can be configured to include a switching circuit MX, as shown in FIG. 4 . The switching circuit MX, for example, has N input terminals and one output terminal. For example, the switching circuit MX has a function of establishing a conductive state between one selected from the N input terminals and one output terminal, and establishing a non-conductive state between the remaining input terminal and the one output terminal. In other words, for example, the switching circuit MX functions as a multiplexer. This allows the switching circuit MX to select one column of data from N columns of image data D[i] read from the memory cell unit MCAF and output the data to the output terminal of the switching circuit MX. In particular, by sequentially switching the input terminal that is in a conductive state with the output terminal in the switching circuit MX, the image data D[i] read from the memory cell unit MCAF can be sequentially output to the wiring PDL, column by column.

[0217] In the j-th column, a first terminal of the switch SWFA is connected to the sense amplifier SAF, a second terminal of the switch SWFA is connected to the wiring WBL2[j], and a control terminal of the switch SWFA is connected to the wiring SWLFA. Also, a first terminal of the switch SWFB is connected to the sense amplifier SAF, a second terminal of the switch SWFB is connected to one of the N input terminals of the switching circuit MX, and a control terminal of the switch SWFB is connected to the wiring SWLFB.

[0218] The wirings WBL2[1] to WBL2[N] are connected to the memory circuit LM2. An output terminal of the switching circuit MX is connected to the wiring PDL.

[0219] The wiring SWLFA functions as a wiring for switching the on state and off state of the switch SWFA included in the switching circuit SWCF, and therefore, for example, a high-level potential or a low-level potential is supplied to the wiring SWLFA as a signal for the switching.

[0220] The wiring SWLFB functions as a wiring for switching the on state and off state of the switch SWFB included in the switching circuit SWCF. For this reason, for example, a high-level potential or a low-level potential is supplied to the wiring SWLFB as a signal for switching, similar to the wiring SWLFA.

[0221] In Figure 4, wirings WBL2[1] to WBL2[N] are shown as wirings for transmitting image data D[i] from the memory circuit FM to the memory circuit LM2, and wiring PDL is shown as wiring for transmitting image data D[i] from the memory circuit FM to the driver circuit SD.

[0222] 4, the memory circuit FM and the memory circuit LM2 are connected using a plurality of wirings WBL2[1] to WBL2[N], but a multiplexer may be provided in the memory circuit FM, a demultiplexer may be provided in the memory circuit LM2, and the multiplexer and the demultiplexer may be connected to each other. With such a configuration, the number of wirings provided between the memory circuit FM and the memory circuit LM2 can be reduced.

[0223] 4, the memory circuit FM and the driver circuit SD are connected using the wiring PDL, but the output unit OPTF may not be provided with a switching circuit MX, and the second terminals of the multiple switches SWFB may be directly connected to the driver circuit SD. This allows the image data D[i] to be transmitted all at once, thereby reducing the time required to transmit the image data.

[0224] [Memory Circuit LM2] Fig. 5 is a block diagram showing an example of the configuration of the memory circuit LM2. In Fig. 5, the memory circuit FM and the processing circuit SGPR are also shown to show the connection configuration between the memory circuit LM2 and its peripheral circuits.

[0225] The memory circuit LM2 shown in FIG. 5 includes, as an example, a drive circuit WWD2, a drive circuit RWD2, a drive circuit RBD2, a memory cell unit MCA2, and an output unit OPT2.

[0226] The memory cell unit MCA2 has, as an example, a plurality of memory cells MC2. Also, in Fig. 5, as an example, in the memory cell unit MCA2, N memory cells MC2 are arranged in a row, similar to the memory cell unit MCA1. Note that in Fig. 3, the N memory cells MC2 may be arranged in a column direction instead of in a row direction.

[0227] Unless otherwise specified, the description of the memory cell MC1 in the memory circuit LM1 can be referred to for the memory cell MC2.

[0228] As an example, the memory cell MC2[j] is connected to a wiring WBL2[j], a wiring RBL2[j], a wiring WWL2, and a wiring RWL2.

[0229] The wirings WBL2[1] to WBL2[N] each function as a write data line, a write bit line, or the like in the memory cells MC2[1] to MC2[N] of the memory circuit LM2, for example. In addition, the wirings WBL2[1] to WBL2[N] are used to transmit the image data D[i,1] to D[i,N] read from the memory cells MC[i,1] to MC[i,N] in the i-th row of the memory cell unit MCAF of the memory circuit FM when the switch SWFA of the switching circuit SWCF is turned on in the memory circuit FM shown in FIG. （ｔ） [i] is transmitted. As an example, image data D （ｔ） The j-th column component of [i] is transmitted to the memory cell MC2[i] via the wiring WBL2[j].

[0230] For the wirings RBL2[1] to RBL2[N], the description of the wirings RBL1[1] to RBL1[N] in the memory circuit LM1 can be referred to unless otherwise specified. For the wiring WWL2, the description of the wiring WWL1 in the memory circuit LM1 can be referred to unless otherwise specified. For the wiring RWL2, the description of the wiring RWL1 in the memory circuit LM1 can be referred to unless otherwise specified.

[0231] Unless otherwise specified, the description of the drive circuit WWD1 of the memory circuit LM1 can be referred to for the drive circuit WWD2, and the description of the drive circuit RWD1 of the memory circuit LM1 can be referred to for the drive circuit RWD2, unless otherwise specified.

[0232] Unless otherwise specified, the description of the drive circuit RBD2 for the drive circuit RBD1 of the memory circuit LM1 can be referred to. As an example, the drive circuit RBD2 includes N sense amplifiers SA2 as shown in FIG. 5. The sense amplifiers SA2 can have the same configuration as the sense amplifiers SA1 shown in FIG. 3.

[0233] As an example, the output unit OPT2 has a function of selecting whether or not to output image data D[i] read from memory cells MC2[1] to MC2[N] of the memory circuit LM2 to each of wirings OL2[1] to OL2[N].

[0234] 5, the output unit OPT2 may have N switches SW2. Note that the switches SW2 may be, for example, switches that can be used as the switches SW1A or SW1B of the memory circuit LM1. Therefore, unless otherwise specified, the description of the switches SW1A or SW1B of the memory circuit LM1 may be referred to for the switches SW2.

[0235] Each of the wirings OL2[1] to OL2[N] is connected to the processing circuit SGPR.

[0236] In FIG. 5, the wirings OL2[1] to OL2[N] are used to transmit image data D from the memory circuit LM2 to the processing circuit SGPR. （ｔ） [i] is shown as a wiring for transmitting.

[0237] 5, the memory circuit LM2 and the processing circuit SGPR are connected using a plurality of wirings OL2[1] to OL2[N], but a multiplexer may be provided in the memory circuit LM2, a demultiplexer may be provided in the processing circuit SGPR, and the multiplexer and the demultiplexer may be connected to each other. With such a configuration, the number of wirings provided between the memory circuit LM2 and the processing circuit SGPR can be reduced.

[0238] [Processing Circuit SGPR] Fig. 6 is a block diagram showing an example of the configuration of the processing circuit SGPR. In Fig. 6, in order to show the connection configuration between the processing circuit SGPR and its peripheral circuits, the memory circuit LM1, the memory circuit LM2, the memory circuit FGM, and the signal processing circuit PG are also shown.

[0239] 6 includes, for example, a comparison circuit CPA and a logic circuit LGMP. The comparison circuit CPA includes, for example, comparators CPAa[1] to CPAa[N].

[0240] Each of the comparators CPAa[1] to CPAa[N] has a first input terminal, a second input terminal, and an output terminal.

[0241] The logic circuit LGMP has N input terminals and one output terminal. In the logic circuit LGMP, the input terminal in the j-th column is referred to as the j-th input terminal.

[0242] In the j-th column, the first input terminal of the comparator CPAa[j] is connected to the wiring OL1[j], the second input terminal of the comparator CPAa[j] is connected to the wiring OL2[j], and the output terminal of the comparator CPAa[j] is connected to the j-th input terminal of the logic circuit LGMP.

[0243] The output terminal of the logic circuit LGMP is connected to a wiring WBLG, which will be described later. In FIG. 6, the wiring WBLG transmits the comparison data C from the processing circuit SGPR to the memory circuit FGM. （ｔ＋１） [i] is shown as a wiring for transmitting.

[0244] Each of the comparators CPAa[1] to CPAa[N] has a function of outputting, when the same data is input to the first input terminal and the second input terminal, a signal indicating that the data match (hereinafter referred to as "false" in terms of logic), to its output terminal. Furthermore, each of the comparators CPAa[1] to CPAa[N] has a function of outputting, when different data is input to the first input terminal and the second input terminal, a signal indicating that the data do not match (hereinafter referred to as "true" in terms of logic), to its output terminal. For this reason, each of the comparators CPAa[1] to CPAa[N] can be, for example, an XOR circuit (exclusive OR circuit) or an XNOR circuit (exclusive NOR circuit).

[0245] The logic circuit LGMP has a function of outputting, to its output terminal, a signal indicating that the image data held in the memory circuits LM1 and LM2 match ("false") when all of the information of the signals input from the first input terminal to the Nth input terminal is "false." Furthermore, when one or more of the information of the signals input from the first input terminal to the Nth input terminal is "true," the logic circuit LGMP has a function of outputting, to its output terminal, a signal indicating that the image data held in the memory circuits LM1 and LM2 do not match ("true"). For this reason, the logic circuit LGMP can be, for example, an AND circuit (logical product circuit), a NAND circuit (negative logical product circuit), an OR circuit (logical sum circuit), or a NOR circuit (negative logical sum circuit) having N input terminals.

[0246] Hereinafter, the information output from the logic circuit LGMP will be referred to as comparison data. （ｔ＋１） [i] is transmitted, and image data D read out from memory circuit LM2 is transmitted from wiring OL2. （ｔ） Assume that [i] is transmitted.

[0247] In particular, image data D （ｔ） [i] and image data D （ｔ＋１） [i] are input to the processing circuit SGPR to obtain the comparison data C （ｔ＋１） [i] is generated. （ｔ＋１） [i] is transmitted from the processing circuit SGPR to the memory circuit FGM via the wiring WBLG.

[0248] 8A shows, as an example, a processing circuit SGPR in which each of the comparators CPAa[1] to CPAa[N] is an XOR circuit (exclusive OR circuit), and the logic circuit LGMP is an OR circuit (logical OR circuit). Although not shown in FIG. 6, the processing circuit SGPR may be provided with a switch SWP at the end of the output terminal of the logic circuit LGMP, as shown in FIG. 8A. In this case, the switch SWP can be used as an output unit in the processing circuit SGPR of FIG. 8A. The output unit outputs the comparison data C generated by the processing circuit SGPR. （ｔ＋１） It functions as a circuit or circuit element that selects whether or not to transmit [i] to the wiring WBLG.

[0249] 8A, a first terminal of the switch SWP is connected to an output terminal of the logic circuit LGMP, a second terminal of the switch SWP is connected to a wiring WBLG (described later), and a control terminal of the switch SWP is connected to a wiring SWLP.

[0250] For example, a switch applicable to the switch SW1A or the switch SW1B of the memory circuit LM1 can be used as the switch SWP. Therefore, unless otherwise specified, the description of the switch SW1A or the switch SW1B of the memory circuit LM1 can be referred to for the switch SWP.

[0251] The wiring SWLP functions as a wiring for switching the on state and off state of the switch SWP included in the processing circuit SGPR. For this reason, for example, a high-level potential or a low-level potential is supplied to the wiring SWLP as a signal for switching the on state and off state.

[0252] In the case of the circuit configuration of FIG. 8A, when the same data is input to the first input terminal and the second input terminal of each of the comparators CPAa[1] to CPAa[N] (for example, image data D （ｔ） [i] and image data D （ｔ＋１） In each of the comparators CPAa[1] to CPAa[N], when different data are input to the first input terminal and the second input terminal (for example, when the image data D （ｔ） [i] and image data D （ｔ＋１） The logic of "true" output when the j-th column of each of [i] does not match is set to "1".

[0253] In addition, in the logic circuit LGMP, when all of the logics of the signals input from the first input terminal to the Nth input terminal are "false" (here, "0"), the comparison data C （ｔ＋１） The logic of "false" output as [i] is set to "0". In addition, in the logic circuit LGMP, when one or more of the logics of the signals input from the first input terminal to the Nth input terminal are "true" (here, "1"), the comparison data C （ｔ＋１） The logic of "true" output as [i] is set to "1".

[0254] That is, the image data D transmitted from the memory circuit LM1 to the processing circuit SGPR （ｔ＋１） [i] and image data D transmitted from the memory circuit LM2 to the processing circuit SGPR （ｔ） If [i] and [i] match, the processing circuit SGPR sends the comparison data C to the wiring WBLG. （ｔ＋１） The logic of "false" is "0" which is [i]. Also, the image data D transmitted from the memory circuit LM1 to the processing circuit SGPR is （ｔ＋１） [i] and image data D transmitted from the memory circuit LM2 to the processing circuit SGPR （ｔ） If [i] and do not match, the processing circuit SGPR sends the comparison data C to the wiring WBLG. （ｔ＋１） "1" is output as the "true" logic of [i].

[0255] Also, the circuit configuration of Fig. 8A is one example, and the processing circuit SGPR of Fig. 6 may have the circuit configuration of Fig. 8B. The processing circuit SGPR shown in Fig. 8B is a modified example of the processing circuit SGPR of Fig. 8A, and differs from the processing circuit SGPR of Fig. 8A in that each of the comparators CPAa[1] to CPAa[N] is an NXOR circuit (exclusive negative OR circuit) and the logic circuit LGMP is a NAND circuit (negative logical product circuit).

[0256] In the case of the processing circuit SGPR of FIG. 8B, similarly to the processing circuit SGPR of FIG. 8A, when the same data is input to the first input terminal and the second input terminal of each of the comparators CPAa[1] to CPAa[N] (for example, image data D （ｔ） [i] and image data D （ｔ＋１） When the j-th column of each of [i] matches, the output terminal of the logic circuit LGMP receives the comparison data C （ｔ＋１） In addition, when different data is input to the first input terminal and the second input terminal of one or more of the comparators CPAa[1] to CPAa[N] (for example, when the image data D （ｔ） [i] and image data D （ｔ＋１） When the j-th column of each of [i] does not match, the output terminal of the logic circuit LGMP receives the comparison data C （ｔ＋１） The logic of [i] is output as "1".

[0257] 6 may be connected to the wiring SWL1B as shown in FIG. 7. In particular, at this time, the comparison data C （ｔ＋１） The logic of [i] is “0” (image data D （ｔ） and image data D （ｔ＋１） The comparison data C output from the output terminal of the logic circuit LGMP corresponds to a low level potential. （ｔ＋１） The logic of [i] is "1" (image data D （ｔ） and image data D （ｔ＋１） (if they do not match) preferably corresponds to a high level potential.

[0258] In the memory circuit LM1 of FIG. 3, the comparison data C output from the output terminal of the logic circuit LGMP （ｔ＋１） When the logic of [i] is "0", a low level potential corresponding to the logic "0" is input to the wiring SWL1B. At this time, each of the multiple switching circuits SWC1 included in the output section OPT1 is turned off. Therefore, there is no conduction between the memory circuit LM1 and the memory circuit FM, and the image data D read out from the memory circuit LM1 is （ｔ＋１） is not transmitted to the memory circuit FM. On the other hand, the comparison data C output from the output terminal of the logic circuit LGMP （ｔ＋１） When the logic of [i] is "1", a high level potential corresponding to the logic "1" is input to the wiring SWL1B. At this time, each of the multiple switching circuits SWC1 included in the output section OPT1 is turned on. Therefore, a conductive state is established between the memory circuit LM1 and the memory circuit FM, and the image data D read out from the memory circuit LM1 is （ｔ＋１） can be transmitted to the storage circuit FM.

[0259] [Memory Circuit FGM] Next, a memory circuit FGM that can be applied to Fig. 1 will be described. Note that here, as a configuration example of the memory circuit FGM, a block diagram of the memory circuit FGM shown in Fig. 6 will be described.

[0260] The memory circuit FGM shown in FIG. 6 includes, as an example, a driver circuit WWDG, a driver circuit RWDG, a sense amplifier SAG, a memory cell unit MCAG, and a switch SWG.

[0261] The memory cell unit MCAG has, as an example, a plurality of memory cells MCG. Also, in Fig. 6, as an example, M memory cells MCG are arranged in a column in the memory cell unit MCAG. Note that in Fig. 3, the M memory cells MCG may be arranged in a row direction instead of in a column direction.

[0262] In order to distinguish between the multiple memory cells MCG in the memory cell unit MCAG, addresses are added to the reference numerals of the multiple memory cells MCG shown in Figure 6. For example, a memory cell MCG located in the first row is shown as MCG[1], and a memory cell MCG located in the Mth row is shown as MCG[M]. Furthermore, although not shown in Figure 6, a memory cell MCG located in the i-th row is referred to as a memory cell MCG[i] in this specification.

[0263] Furthermore, for the memory cell MCG, unless otherwise specified, the description of the memory cell MC1 in the memory circuit LM1 can be referred to.

[0264] For example, the memory cell MCG[i] is connected to a wiring WBLG, a wiring RBLG, a wiring WWLG[i], and a wiring RWLG[i]. The wiring RBLG is connected to a sense amplifier SAG.

[0265] The wiring WBLG functions as, for example, a write data line or a write bit line in the memory cell MCG[i]. （ｔ＋１） [i] is sent.

[0266] For the wiring RBLG, unless otherwise specified, the description of the wirings RBL1[1] to RBL1[N] of the memory circuit LM1 can be referred to. For each of the wirings WWLG[1] to WWLG[M], unless otherwise specified, the description of the wiring WWL1 of the memory circuit LM1 can be referred to. For each of the wirings RWLG[1] to RWLG[M], unless otherwise specified, the description of the wiring RWL1 of the memory circuit LM1 can be referred to.

[0267] As an example, the drive circuit WWDG stores comparison data C in the memory cell MCG[i] of the memory cell unit MCAG. （ｔ＋１）The driver circuit WWDG has a function of transmitting a write selection signal to the wiring WWLG[i] when writing data to the wiring WWLG[i]. The driver circuit WWDG also has a function of transmitting a non-selection signal to the wirings WWLG[1] to WWLG[M] excluding the wiring WWLG[i] to prevent writing to each of the memory cells MCG[1] to MCG[M] in rows other than the i-th row of the memory cell unit MCAG. By sequentially transmitting a selection signal to each of the wirings WWLG[1] to WWLG[M], the memory cells MCG included in the memory cell unit MCAG can be sequentially selected row by row as the write destination of the comparison data. In other words, the driver circuit WWDG functions as a write word line driver circuit, for example. The driver circuit WWDG may also be referred to as a selection circuit from the above.

[0268] For example, while the driver circuit WWDG transmits a write selection signal to the wiring WWLG[i] and transmits non-selection signals to the wirings WWLG[1] to WWLG[M] other than the wiring WWLG[i], the processing circuit SGPR transmits the comparison data C （ｔ＋１） By transmitting [i], the comparison data C is stored in the memory cell MCG[i] in the i-th row of the memory cell unit MCAG. （ｔ＋１） [i] can be written.

[0269] For example, the driver circuit RWDG has a function of transmitting a read selection signal to the wiring RWLG[i] when reading comparison data C[i] from the memory cell MCG[i] of the memory cell unit MCAG. The driver circuit RWDG also has a function of transmitting a non-selection signal to the wirings RWLG[1] to RWLG[M] excluding the wiring RWLG[i] to prevent reading from each of the memory cells MCG[1] to MCG[M] in rows other than the i-th row of the memory cell unit MCAG. By sequentially transmitting a selection signal to each of the wirings RWLG[1] to RWLG[M], the memory cells MCG included in the memory cell unit MCAG can be sequentially selected row by row as the source of the comparison data. That is, the driver circuit RWDG functions as a read word line driver circuit, for example. The driver circuit RWDG may also be referred to as a selection circuit.

[0270] For example, the driver circuit RWDG transmits a read selection signal to the wiring RWLG[i] and transmits a non-selection signal to the wirings RWLG[1] to RWLG[M] other than the wiring RWLG[i], thereby transmitting the comparison data C from the memory cell MCG[i] in the i-th row of the memory cell unit MCAG to the wiring RBLG[i]. （ｔ＋１） A read potential according to [i] can be output.

[0271] The sense amplifier SAG has a function of amplifying a read potential corresponding to comparison data read from any one of the memory cells MCG[1] to MCG[M] to a level at which the read potential can be treated as digital data. In other words, the sense amplifier SAG has the same function as the sense amplifier SA1 included in the drive circuit RBD1 of the memory circuit LM1 described above. Therefore, the sense amplifier SAG can have a configuration similar to that of the sense amplifier SA1 shown in FIG. 3, for example.

[0272] 6, a first terminal of the switch SWG is connected to a sense amplifier SAG, a second terminal of the switch SWG is connected to a signal processing circuit PG via a wiring FOL (described later), and a control terminal of the switch SWG is connected to a wiring SWLG.

[0273] For example, a switch applicable to the switch SW1A or the switch SW1B of the memory circuit LM1 can be used as the switch SWG. Therefore, unless otherwise specified, the description of the switch SW1A or the switch SW1B of the memory circuit LM1 can be referred to for the switch SWG.

[0274] The wiring SWLG functions as a wiring for switching the on state and off state of the switch SWG included in the memory circuit FGM. For this reason, for example, a high-level potential or a low-level potential is supplied to the wiring SWLG as a signal for switching the on state and off state.

[0275] 6, the wiring FOL transmits the comparison data C from the memory circuit FGM to the signal processing circuit PG. （ｔ＋１） [i] is shown as a wiring for transmitting.

[0276] [Signal Processing Circuit PG] Fig. 9A is a block diagram showing an example of the configuration of the signal processing circuit PG. In Fig. 9A, a memory circuit FGM is also shown in order to show the connection configuration between the signal processing circuit PG and its peripheral circuits.

[0277] The signal processing circuit PG includes, for example, a pulse signal generating circuit PWG and a logic circuit CPB. The logic circuit CPB includes a first input terminal, a second input terminal, and an output terminal.

[0278] A first input terminal of the logic circuit CPB is connected to the memory circuit FGM via a wiring FOL, a second input terminal of the logic circuit CPB is connected to the pulse signal generating circuit PWG via a wiring POL, and an output terminal of the logic circuit CPB is connected to a wiring PWCL.

[0279] The pulse signal generating circuit PWG is connected to the wiring PWIL.

[0280] The pulse signal generation circuit PWG has a function of outputting a clock signal having a predetermined pulse width or a predetermined duty ratio to the wiring POL in response to a signal transmitted to the wiring PWIL. Note that the signal transmitted to the wiring PWIL may be generated by, for example, a control circuit TC. In other words, the pulse signal generation circuit PWG may be configured such that the pulse width or duty ratio of the clock signal is adjusted by the control circuit TC.

[0281] For example, the wiring PWIL functions as a wiring that applies a predetermined potential. For example, the pulse width of a clock signal output from the pulse signal generation circuit PWG to the wiring POL can be determined according to a fixed potential applied to the wiring PWIL. In other words, the duty ratio of the clock signal can be determined according to the fixed potential applied to the wiring PWIL.

[0282] Also, the comparison data C transmitted from the memory circuit FGM to the logic circuit CPB （ｔ＋１） [1] to Comparison Data C （ｔ＋１） It is preferable that the duty ratio of the clock signal is adjusted so that the period of the high level potential of the clock signal falls within each period [M].

[0283] Also, the comparison data C transmitted from the memory circuit FGM to the logic circuit CPB （ｔ＋１） [1] to Comparison Data C （ｔ＋１） It is preferable that the output of [M] and the transmission of the clock signal transmitted from the pulse signal generating circuit PWG to the logic circuit CPB are synchronized so as to be performed simultaneously. For this reason, each of the memory circuit FGM and the pulse signal generating circuit PWG receives, for example, a synchronization signal, and outputs the comparison data C （ｔ＋１） [1] to Comparison Data C （ｔ＋１） It is preferable that the clock signal [M] is outputted sequentially and the clock signal is outputted from the pulse signal generating circuit PWG.

[0284] With the above configuration, the comparison data C[1] to C[M] output from the memory circuit FGM to the wiring FOL can be input sequentially to the first input terminal of the logic circuit CPB in synchronization with a clock signal of a predetermined duty ratio output from the pulse signal generating circuit PWG to the wiring POL.

[0285] The logic circuit CPB can be, for example, a logical product circuit (AND circuit). Specifically, the logic circuit CPB receives the comparison data C from the wiring FOL. （ｔ＋１） [1] to Comparison Data C （ｔ＋１） The comparison data C has a function of outputting the result of logical ANDing [M] and the clock signal from the wiring POL to the wiring PWCL. （ｔ＋１） When the logic of [i] is "0" (in other words, when the image data D[i] read out from the memory circuit LM1 and the memory circuit LM2 match), the logic circuit CPB outputs "0" (low-level potential) as a logical product to the wiring PWCL regardless of the potential of the clock signal. （ｔ＋１） When the logic of [i] is "1" (in other words, when the image data D[i] read out from each of the memory circuits LM1 and LM2 do not match), the logic circuit CPB outputs "1" (high-level potential) as the logical product to the wiring PWCL during the period when the clock signal is at a high-level potential, and outputs "0" (low-level potential) as the logical product to the wiring PWCL during the period when the clock signal is at a low-level potential.

[0286] For example, as shown in the timing chart of FIG. 9B, comparison data C is input from the wiring FOL to the first input terminal of the logic circuit CPB. （ｔ＋１） [1] to Comparison Data C （ｔ＋１） Consider a case where the comparison data C [6] is transmitted sequentially and a clock signal is transmitted from the wiring POL to the second input terminal of the logic circuit CPB. （ｔ＋１） [1] and comparison data C （ｔ＋１） [2] and comparison data C （ｔ＋１）When the logic of each of [4] and [5] is "1", a clock signal is sent to the second input terminal of the logic circuit PCB, and a waveform similar to that of the clock signal is output from the output terminal of the logic circuit CPB. （ｔ＋１） [3] and comparison data C （ｔ＋１） [5] and comparison data C （ｔ＋１） When the logic of each of [6] and [7] is "0", a low level potential is output to the output terminal of the logic circuit CPB regardless of the waveform similar to that of the clock signal.

[0287] That is, in the logic circuit CPB, the comparison data C from the wiring FOL （ｔ＋１） [1] to Comparison Data C （ｔ＋１） By calculating the logical product of [M] and the clock signal from the wiring POL, comparison data C （ｔ＋１） [1] to Comparison Data C （ｔ＋１） A pulse signal reflecting the logic of [M] can be generated and output to the output terminal of the logic circuit CPB. Note that the pulse signal can be used as a control signal to be sent to the drive circuit SD and the drive circuit GD.

[0288] [Driver Circuit GD] Next, a configuration example of the driver circuit GD included in the driver circuit unit DRA of the display device DSP will be described. Each of the driver circuits GD in Figures 10A to 10D is a block diagram showing a configuration example that can be applied to the driver circuit GD shown in Figure 1.

[0289] 10A , the driver circuit GD includes a circuit RDC, a logic circuit PWCS, and a circuit BFS. The logic circuit PWCS includes logic circuits LGA[1] to LGA[M]. The circuit BFS includes buffer circuits BF[1] to BF[M].

[0290] The circuit RDC is connected to the wiring GSPL, the wiring CLK1L, and the wirings RL[1] to RL[M].

[0291] For example, the circuit RDC functions as a row decoder for transmitting a selection signal to the pixel circuits PX in the pixel array unit PXA. When the circuit RDC is configured to sequentially transmit selection signals to the first to Mth rows of the pixel array unit PXA, the circuit RDC preferably includes a shift register. In this case, the circuit RDC is preferably configured such that selection signals (with a logic value of "1") output from the shift register are sequentially output from each of the wirings RL[1] to RL[M]. The circuit RDC is preferably configured such that a non-selection signal (with a logic value of "0") is output to the wirings RL[1] to RL[M] other than the wiring RL to which the selection signal is output.

[0292] 10A, for example, it is preferable that the wiring GSPL functions as a wiring that transmits a start pulse signal to be input to the shift register, and the wiring CLK1L functions as a wiring that transmits a clock signal for driving the shift register. Note that the start pulse signal transmitted to the wiring GSPL and the clock signal transmitted to the wiring CLK1L can each be generated by, for example, a control circuit TC.

[0293] Furthermore, the period of the selection signal transmitted from the circuit RDC to each of the wirings RL[1] to RL[M] (the period when the logic is "1" or the period when the potential is high) is preferably shorter than the period of the high potential of the clock signal transmitted to the wiring POL, and the period of the selection signal is preferably synchronized so as to fall within the period of the high potential of the clock signal. For example, as shown in the timing chart of FIG. 11, the period of the selection signal (the period when the potential is high) of the wirings RL[1] to RL[6] may be generated so as to fall within the period of the high potential of the clock signal transmitted to the wiring POL.

[0294] In the logic circuit PWCS, each of the logic circuits LGA[1] to LGA[M] can be a logical product circuit (AND circuit). In addition, in the i-th row, the first input terminal of the logic circuit LGA[i] is connected to the wiring RL[i], and the second input terminal of the logic circuit LGA[i] is connected to the wiring PWCL. Note that a control signal is transmitted from the logic circuit CPB described in FIG. 9A to the wiring PWCL.

[0295] Therefore, a selection signal or non-selection signal for the i-th row of the pixel array section PXA is input from the wiring RL[i] to the first input terminal of the logic circuit LGA[i], and a control signal is input from the wiring PWCL to the second input terminal of the logic circuit LGA[i].

[0296] In particular, from the wiring PWCL, the comparison data C （ｔ＋１） While the control signal generated in response to [i] is being transmitted, it is preferable that a selection signal (logic "1", here a high level potential) is transmitted from the wiring RL[i]. （ｔ＋１） When the logic of [i] is "0" (low level potential) (in other words, the image data D read out from the memory circuit LM1 （ｔ＋１） [i] and image data D read out from memory circuit LM2 （ｔ） When the logic of the comparison data C[i] is "1" (high level potential) (in other words, when the image data D[i] read out from the memory circuit LM1 is "0"), a signal with a logic of "0" (low level potential) is output from the output terminal of the logic circuit LGA[i]. In other words, the selection signal (logic "1", here a high level potential) from the wiring RL[i] is changed by the logic circuit LGA[i] to a non-selection signal (logic "0", here a low level potential). Also, when the logic of the comparison data C[i] is "1" (high level potential) (in other words, when the image data D[i] read out from the memory circuit LM1 is "0"), （ｔ＋１） [i] and image data D read out from memory circuit LM2 （ｔ） When the logic circuit LGA[i] and the wiring RL[i] do not match, a signal with a logic value of "1" (high-level potential) is output from the output terminal of the logic circuit LGA[i]. In other words, the selection signal (with a logic value of "1", here a high-level potential) from the wiring RL[i] is output as is to the output terminal of the logic circuit LGA[i].

[0297] For example, as shown in the timing chart of FIG. 11, the comparison data C （ｔ＋１） [1] to Comparison Data C （ｔ＋１） Let us consider a case where a control signal generated in accordance with [6] is transmitted and selection signals (logic "1", here a high-level potential) are transmitted sequentially from each of the wirings RL[1] to RL[6]. Note that the control signal is assumed to be the control signal generated in the operation example of the timing chart of FIG. 9B.

[0298] Comparison data C （ｔ＋１） [1] and comparison data C （ｔ＋１） [2] and comparison data C （ｔ＋１） When the logic of each of the wirings RL[1] and RL[4] is "1" (high-level potential), during a period in which a selection signal (logic "1", here high-level potential) is transmitted to the wiring RL[1], a logic "1" signal (high-level potential) is output from the output terminal of the logic circuit LGA[1]. Similarly, during a period in which a selection signal (logic "1", here high-level potential) is transmitted to the wiring RL[2], a logic "1" signal (high-level potential) is output from the output terminal of the logic circuit LGA[2]. During a period in which a selection signal (logic "1", here high-level potential) is transmitted to the wiring RL[4], a logic "1" signal (high-level potential) is output from the output terminal of the logic circuit LGA[4]. On the other hand, during a period in which a non-selection signal (logic "0", here low-level potential) is transmitted to the wiring RL[1], a logic "0" signal (low-level potential) is output from the output terminal of the logic circuit LGA[1]. Similarly, during a period in which a non-selection signal (logic "0", here a low-level potential) is transmitted to the wiring RL[2], a signal with a logic "0" (low-level potential) is output from the output terminal of the logic circuit LGA[2], and during a period in which a selection signal (logic "1", here a high-level potential) is transmitted to the wiring RL[4], a logic "1" (high-level potential) is output from the output terminal of the logic circuit LGA[4]. That is, the comparison data C （ｔ＋１） When the logic of [i] is "1", the selection signal (logic "1", here a high-level potential) from the wiring RL[i] can be said to be output directly to the output terminal of the logic circuit LGA[i].

[0299] Comparison data C （ｔ＋１） [3] and comparison data C （ｔ＋１） [5] and comparison data C （ｔ＋１） When the logic of each of the wirings RL[6] and RL[6] is "0", a signal with a logic of "0" (low level potential) is output from the output terminal of the logic circuit LGA[3] regardless of the signal (selection signal (logic "1", here a high level potential) or non-selection signal (logic "0", here a low level potential)) sent to the wiring RL[3]. Similarly, a signal with a logic of "0" (low level potential) is output from the output terminal of the logic circuit LGA[5] regardless of the signal (selection signal (logic "1", here a high level potential) or non-selection signal (logic "0", here a low level potential)) sent to the wiring RL[5], and a signal with a logic of "0" (low level potential) is output from the output terminal of the logic circuit LGA[6] regardless of the signal (selection signal (logic "1", here a high level potential) or non-selection signal (logic "0", here a low level potential)) sent to the wiring RL[6]. In other words, （ｔ＋１） When the logic of [i] is "0" (low level potential), it can be said that the selection signal (logic "1", here high level potential) from wiring RL[i] is converted into a non-selection signal (logic "0", here low level potential) by the logic circuit LGA[i].

[0300] As described above, if the image data of the i-th row of the pixel array unit PXA does not change (if the logic of the comparison data C[i] is "0" (low level potential)), there is no need to write image data to the pixel circuits PX of the i-th row of the pixel array unit PXA, and the logic circuit PWCS can convert the selection signal for the i-th row of the pixel array unit PXA to a non-selection signal by a control signal generated in accordance with the comparison data C[i]. Also, if the image data of the i-th row of the pixel array unit PXA changes (if the logic of the comparison data C[i] is "1" (high level potential)), the logic circuit PWCS can transmit a selection signal to the i-th row of the pixel array unit PXA by a control signal generated by the signal processing circuit PG in accordance with the comparison data C[i], in order to write new image data to the pixel circuits PX of the i-th row of the pixel array unit PXA.

[0301] 10A, the output terminal of the logic circuit LGA[i] is connected to the input terminal of the buffer circuit BF[i], and the output terminal of the buffer circuit BF[i] is connected to the wiring GL[i].

[0302] The buffer circuit BF[i] included in the circuit BFS has functions such as suppressing attenuation of the selection signal transmitted to the wiring GL[i], reducing the influence of noise signals flowing through the wiring GL[i], etc. Note that in the display device DSP, if there is no attenuation of the selection signal or if the influence of noise signals is small, the circuit BFS does not need to be provided in the driver circuit GD.

[0303] 10B , the circuit BFS may include level shifters LS[1] to LS[M], the output terminal of the buffer circuit BF[i] may be connected to the input terminal of the level shifter LS[i], and the wiring GL[i] may be connected to the output terminal of the level shifter LS[i].

[0304] For example, the level shifter LS[i] has a function of converting the potential of one or both of a selection signal and a non-selection signal transmitted from the output terminal of the buffer circuit BF[i] into a level that can be handled by the pixel circuits PX[i,1] to PX[i,M]. Note that if the potential of one or both of a selection signal and a non-selection signal transmitted from the output terminal of the buffer circuit BF[i] can be handled as is by the pixel circuits PX[i,1] to PX[i,M], the level shifters LS[1] to LS[M] do not need to be provided in the circuit BFS.

[0305] 10A may be changed to the circuit configuration shown in Fig. 10C. The driver circuit GD shown in Fig. 10C has a configuration in which the logic circuits LGA[1] to LGA[M] shown in Fig. 10A are changed to logic circuits LGN[1] to LGN[M], which are negative AND (NAND) circuits, and the buffer circuits BF[1] to BF[M] shown in Fig. 10A are changed to inverters NT[1] to NT[M], which are negation (NOT) circuits (sometimes called inverters).

[0306] The configuration of the driver circuit GD in Figure 10C can also produce output results similar to those of the driver circuit GD in Figure 10A. Furthermore, the logic circuits LGN[1] to LGN[M], which are NAND circuits, used in the driver circuit GD in Figure 10C can have fewer transistors than the logic circuits LGA[1] to LGA[M], which are AND circuits. Similarly, the inverters NT[1] to NT[M] used in the driver circuit GD in Figure 10C can have fewer transistors than the buffer circuits BF[1] to BF[M] used in the driver circuit GD in Figure 10A. Therefore, the circuit area of ​​the driver circuit GD in Figure 10C is smaller than that of the driver circuit GD in Figure 10A.

[0307] In addition, in the driver circuit GD in FIG. 10C, similarly to FIG. 10B, level shifters LS[1] to LS[M] may be provided in the circuit BFS (see FIG. 10D).

[0308] [Driver Circuit SD] Next, a configuration example of the driver circuit SD included in the driver circuit unit DRA of the display device DSP will be described. The driver circuit SD in Fig. 12 is a block diagram showing a configuration example that can be applied to the driver circuit SD in Fig. 1.

[0309] 12, the driver circuit SD includes a shift register SR, holding circuits LA[1] to LA[N], digital-to-analog conversion circuits DAC[1] to DAC[N], and switches SWS[1] to SWS[N]. Focusing on the j-th column, the holding circuit LA[j] (not shown) includes a latch circuit LATS[j] and a latch circuit LATH[j].

[0310] The shift register SR has an input terminal and output terminals equal in number to the columns of the pixel array unit PXA (here, N terminals).

[0311] An input terminal of the shift register SR is connected to the line SSPL. In the j-th column, the j-th output terminal of the shift register SR is connected to the control terminal of the latch circuit LATS[j].

[0312] The input terminals of the latch circuits LATS[1] to LATS[N] are connected to the wiring PDL. In the j-th column, the output terminal of the latch circuit LATS[j] is connected to the input terminal of the latch circuit LATH[j], and the output terminal of the latch circuit LATH[j] is connected to the input terminal of the digital-to-analog conversion circuit DAC[j].

[0313] Further, the control terminals of the latch circuits LATH[1] to LATH[N] are connected to a wiring LTHL.

[0314] The input terminal of the latch circuit LATS[j] can be the input terminal of the holding circuit LA[j], and the output terminal of the latch circuit LATH[j] can be the output terminal of the holding circuit LA[j].

[0315] In the j-th column, the output terminal of the digital-to-analog conversion circuit DAC[j] is connected to the first terminal of the switch SWS[j], the second terminal of the switch SWS[j] is connected to the wiring SL[j], and the control terminal of the switch SWS[j] is connected to the wiring PWCL.

[0316] 12, the connection point between the output terminal of the digital-analog conversion circuit DAC[1] and the first terminal of the switch SWS[1] is illustrated as a node ND[1]. Similarly, the connection point between the output terminal of the digital-analog conversion circuit DAC[N] and the first terminal of the switch SWS[N] is illustrated as a node ND[N].

[0317] For example, the shift register SR has serially connected holding circuits, and has a function of holding information corresponding to a signal input to the holding circuit and a function of sequentially transmitting the signal corresponding to the information to an adjacent holding circuit. Furthermore, for example, the shift register SR has a function of outputting a signal corresponding to the information held in the holding circuit to one of N output terminals of the shift register SR. Note that the signal may be a strobe signal in the latch circuits LATS[1] to LATS[N].

[0318] 12, each of the plurality of latch circuits LATS has a function of acquiring and holding image data transmitted from the memory circuit FM, for example. Furthermore, the latch circuit LATH has a function of acquiring the image data from the latch circuit LATS and outputting the image data to the digital-analog conversion circuit DAC, for example. As shown in FIG. 12, by connecting the latch circuit LATS and the latch circuit LATH in series, the holding circuit LA can simultaneously acquire and hold the first image data transmitted from the memory circuit FM by the latch circuit LATS and transmit the second image data to the digital-analog conversion circuit DAC by the latch circuit LATH.

[0319] For example, each of the latch circuits LATS[1] to LATS[N] can capture image data sequentially transmitted to the wiring PDL by sequentially transmitting a strobe signal from each of the multiple output terminals of the shift register SR. At this time, the image data is transmitted from the output terminals of each of the latch circuits LATS[1] to LATS[N] to the input terminals of the latch circuits LATH[1] to LATH[N]. When a strobe signal is not transmitted to the wiring LTHL, each of the latch circuits LATH[1] to LATH[N] only captures the image data. When a strobe signal is transmitted to the wiring LTHL, each of the latch circuits LATH[1] to LATH[N] transmits the image data from the output terminal to the input terminal of the digital-to-analog conversion circuit DAC.

[0320] The digital-analog conversion circuits DAC[1] to DAC[N] have a function of converting digital data, which is image data input to their respective input terminals, into analog data, and also have a function of outputting the analog data from their respective output terminals.

[0321] For example, the switches applicable to the switch SW1A or the switch SW1B of the memory circuit LM1 can be used as the switches SWS[1] to SWS[N]. Therefore, unless otherwise specified, the description of the switch SW1A or the switch SW1B of the memory circuit LM1 can be referred to for the switches SWS[1] to SWS[N].

[0322] The wiring PWCL functions as a wiring for switching the on and off states of the switches SWS[1] to SWS[N]. The wiring PWCL shown in FIG. 12 can be the wiring PWCL connected to the signal processing circuit PG described in FIG. 9A. That is, the switches SWS[1] to SWS[N] switch between the on and off states in response to a control signal transmitted to the wiring PWCL.

[0323] An example of the operation of the drive circuit SD is shown in the timing chart of FIG. （ｔ＋１） [1] to Comparison Data C （ｔ＋１） 13 shows the relationship between the control signal generated by transmitting the signal processing circuit PG to the node ND[j] and the wiring SL[j], and the image data flowing through the node ND[j] and the wiring SL[j], and the potential changes in the wirings GL[1] to GL[6]. Note that the timing chart in FIG. 11 can be referred to for the wirings FOL, POL, PWCL, and GL[1] to GL[6] shown in FIG.

[0324] As shown in FIG. 13, the comparison data C （ｔ＋１） At the timing when [1] (logic "1") is transmitted, image data D, which is analog data, is output from the output terminal of the digital-to-analog conversion circuit DAC[j]. （ｔ＋１） Therefore, the potential of the node ND[j] is （ｔ＋１） At this time, since a signal with a logic value of “1” (high-level potential) is input to the wiring PWCL, the switch SWS is turned on, and the potential of the wiring SL[j] is also set to the same level as the image data D （ｔ＋１） The potential is determined according to [1].

[0325] In addition, since the logic of the signal transmitted to the wiring GL[1] is "1" (high level potential) and the logic of the signals transmitted to the other wirings GL is "0" (low level potential), （ｔ＋１） [1] is written to pixel circuit PX[1,j].

[0326] Also, comparison data C is （ｔ＋１） At the timing when [2] (logic "1") is being transmitted, image data D, which is analog data, is output from the output terminal of the digital-to-analog conversion circuit DAC[j]. （ｔ＋１） Therefore, the potential of the node ND[j] is （ｔ＋１）At this time, since a signal with a logic value of “1” (high-level potential) is input to the wiring PWCL, the switch SWS is turned on, and the potential of the wiring SL[j] is also set to the same level as the image data D （ｔ＋１） The potential is determined according to [2].

[0327] In addition, the logic of the signal transmitted to the wiring GL[2] is "1" (high level potential), and the logic of the signals transmitted to the other wirings GL is "0" (low level potential). （ｔ＋１） [2] is written to pixel circuit PX[2,j].

[0328] Also, comparison data C is （ｔ＋１） At the timing when [3] (logic "0", here a low level potential) is transmitted, image data D, which is analog data, is output from the output terminal of the digital-to-analog conversion circuit DAC[j]. （ｔ＋１） Therefore, the potential of the node ND[j] is （ｔ＋１） At this time, since a signal with a logic value of “0” (low-level potential) is input to the wiring PWCL, the switch SWS is turned off, and the potential of the wiring SL[j] is set to the image data D （ｔ＋１） [3], but image data D （ｔ＋１） The potential remains at the level according to [2].

[0329] In addition, comparative data C （ｔ＋１） Since the logic of [3] is "0" (low level potential), the image data D of the t-th frame （ｔ） [3] and the t+1th frame image data D （ｔ＋１） 13, since the logic of the signal transmitted to the wiring GL[3] is "0" (low level potential) at this timing, no image is written to the pixel circuit PX[3,j].

[0330] Also, comparison data C is （ｔ＋１）At the timing when [4] (logic "1", here a high level potential) is transmitted, image data D, which is analog data, is output from the output terminal of the digital-to-analog conversion circuit DAC[j]. （ｔ＋１） Therefore, the potential of the node ND[j] is （ｔ＋１） At this time, since a signal with a logic value of “1” (high-level potential) is input to the wiring PWCL, the switch SWS is turned on, and the potential of the wiring SL[j] is also set to the same value as the image data D （ｔ＋１） The potential is determined according to [4].

[0331] In addition, the logic of the signal transmitted to the wiring GL[4] is "1" and the logic of the signals transmitted to the other wirings GL is "0". （ｔ＋１） [4] is written to pixel circuit PX[4,j].

[0332] Also, comparison data C is （ｔ＋１） [5] or comparison data C （ｔ＋１） At the timing when [6] (both logic values ​​are "0") is being transmitted, image data D, which is analog data, is output from the output terminal of the digital-to-analog conversion circuit DAC[j]. （ｔ＋１） [5] or image data D （ｔ＋１） Therefore, the potential of the node ND[j] is （ｔ＋１） [5] or image data D （ｔ＋１） At this time, since a signal with a logic value of “0” (low-level potential) is input to the wiring PWCL, the switch SWS is turned off, and the potential of the wiring SL[j] is set to the image data D （ｔ＋１） [5] or image data D （ｔ＋１） [6], but image data D （ｔ＋１） The potential remains at the potential according to [4].

[0333] In addition, comparative data C （ｔ＋１） [5] or comparison data C （ｔ＋１） Since the logic of [6] is "0", the image data D of the t-th frame （ｔ） [5] and the t+1th frame image data D （ｔ＋１）[5] is the same data, and is the image data D of the t-th frame. （ｔ） [6] and the t+1th frame image data D （ｔ＋１） 13, at these timings, the logic of the signals transmitted to the wirings GL[5] and GL[6] is "0" (low-level potential), so no image is written to the pixel circuits PX[5,j] and PX[6,j].

[0334] As explained in the timing chart above, when the logic of the control signal transmitted to the wiring PWCL is "1", that is, when the image data D （ｔ） [i] and image data D （ｔ＋１） When the pixel circuit PX[i, j] does not match the image data D （ｔ） [i] to image data D （ｔ＋１） Therefore, in the j-th column, the switch SWS[j] is turned on. At this time, the image data D converted into analog data is output from the output terminal of the digital-to-analog conversion circuit DAC[j]. （ｔ＋１） [i] is transmitted to the pixel circuit PX[i,j] via the wiring SL[j]. As a result, the image data D （ｔ） [i] to image data D （ｔ＋１） It is rewritten to [i].

[0335] In addition, the logic of the control signal transmitted to the wiring PWCL is "0" (low level potential), that is, the image data D （ｔ） [i] and image data D （ｔ＋１） When the pixel circuit PX[i, j] matches the image data D （ｔ） [i] to image data D （ｔ＋１） Therefore, in the j-th column, the switch SWS[j] is turned off. At this time, the image data D converted into analog data is （ｔ＋１） [i] is not transmitted to the pixel circuit PX[i,j] via the line SL[j].

[0336] At this time, since the switch SWS[j] is in an off state, the output of the drive circuit SD becomes high impedance, and the line SL[j] carries the image data D from the output terminal of the digital-to-analog conversion circuit DAC[j]. （ｔ＋１） In this respect, the potential of the wiring SL[j] is not input in accordance with the image data D[i] of another row other than the i-th row. （ｔ＋１） Since the potential is in accordance with the image data D, when the switch SWS[j] is turned off, the potential is changed to the image data D （ｔ＋１） There is no need to supply electric charges to change the potential according to [i], and power consumption in the display system DSYS can be reduced.

[0337] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes.

[0338] Embodiment 2 In this embodiment, a configuration example of a display system according to one embodiment of the present invention, which can suppress a decrease in frame frequency, will be described.

[0339] <Example of display system configuration> The display system DSYSA of Figure 14 is a modified example of the display system DSYS of Figure 1, and differs from the display system DSYS of Figure 1 in that the processing device PRC has memory circuits FM1 and FM2 instead of the memory circuit FM, and memory circuits FGM1 and FGM2 instead of the memory circuit FGM.

[0340] Therefore, in this specification, for the configuration of part of the display system DSYSA in Fig. 14, the description of the display system DSYSA in Fig. 1 can be referred to. Also, in this specification, in the description of the display system DSYSA in Fig. 14, the description of parts that overlap with the content of the display system DSYS in Fig. 1 may be omitted.

[0341] 1 can be referred to for the pixel array portion PXA included in the display device DSP in Fig. 14. In addition, the descriptions of the wirings SL[1] to SL[N] and the wirings GL[1] to GL[M] in Fig. 1 can be referred to for the wirings SL[1] to SL[N] and the wirings GL[1] to GL[M].

[0342] For the driver circuit SD and driver circuit GD included in the display device DSP of FIG. 14, the description of the driver circuit SD and driver circuit GD of FIG. 1 can be referred to.

[0343] For the signal processing circuit PG included in the processing device PRC in FIG. 14, the description of the signal processing circuit PG in FIG. 1 can be referred to.

[0344] The memory circuit LM1 has a function as a first line memory, for example. Specifically, the memory circuit LM1 has a function of temporarily storing image data for at least one row of an image to be displayed in the pixel array unit PXA. The memory circuit LM1 also has a function of temporarily storing image data D （ｔ） The memory circuit LM1 has a function of acquiring the image data D[i] (the image data may be referred to as an image signal) from outside the processing device PRC. （ｔ） [i] and transmits it to the memory circuit FM1 or the processing circuit SGPR.

[0345] The memory circuit LM2 has a function as a second line memory, for example. Specifically, the memory circuit LM2 has a function of temporarily storing image data for at least one row of an image to be displayed in the pixel array unit PXA. The memory circuit LM2 also has a function of temporarily storing image data D （ｔ＋１） The memory circuit LM2 has a function of acquiring the image data D[i] (the image data may be called an image signal) from outside the processing device PRC. （ｔ＋１） [i] and transmits it to the memory circuit FM2 or the processing circuit SGPR.

[0346] The memory circuit FM1 has a function as a first frame memory, for example. Specifically, the memory circuit FM1 has a function of temporarily storing image data for all rows of an image to be displayed in the pixel array unit PXA. The memory circuit FM1 also has a function of temporarily storing image data D1 transmitted to each of the first to Mth rows of the pixel array unit PXA, for example. （ｔ） [1] to Image Data D （ｔ） The memory circuit FM1 has a function of acquiring the image data D （ｔ） [1] to Image Data D （ｔ） The signal processing circuit 100 has a function of sequentially reading out each of [M] and transmitting them to the driver circuit SD.

[0347] The memory circuit FM2 has a function as a second frame memory, for example. Specifically, the memory circuit FM2 has a function of temporarily storing image data for all rows of an image to be displayed in the pixel array unit PXA. The memory circuit FM2 also has a function of temporarily storing image data D1 transmitted to each of the first to Mth rows of the pixel array unit PXA, for example. （ｔ＋１） [1] to Image Data D （ｔ＋１） The memory circuit FM2 has a function of acquiring the image data D （ｔ＋１） [1] to Image Data D （ｔ＋１） The signal processing circuit 100 has a function of sequentially reading out each of [M] and transmitting them to the driver circuit SD.

[0348] The memory circuit FGM1 functions as a first flag memory, for example. （ｔ） The memory circuit FGM1 has a function of storing comparison data C[i] for the number of rows of the pixel array unit PXA. （ｔ） [1] to Comparison Data C （ｔ） The memory circuit FGM1 can store the comparison data C （ｔ） [i] and transmits it to the signal processing circuit PG.

[0349] The memory circuit FGM2 functions as a second flag memory, for example. （ｔ＋１） The memory circuit FGM2 stores the comparison data C[i] for the number of rows of the pixel array unit PXA. （ｔ＋１） [1] to Comparison Data C （ｔ＋１） The memory circuit FGM2 can store the comparison data C （ｔ＋１） [i] and transmits it to the signal processing circuit PG.

[0350] The control circuit TC, for example, has a function of controlling each circuit included in the processing device PRC and each circuit included in the display device DSP. For example, the control circuit TC has a function of transmitting command signals to the drive circuits included in each of the memory circuits LM1, LM2, FM1, FM2, FGM1, and FGM2 to perform write operations, read operations, etc. The control circuit TC also has a function of transmitting command signals to the drive circuits SD and GD to perform write operations, read operations, etc. The control circuit TC also has a function of transmitting command signals to control the on / off switching of switching elements included in each of the memory circuits LM1, LM2, FM1, FM2, FGM1, FGM2, and processing circuit SGPR. The control circuit TC also has a function of generating clock signals to be supplied to each circuit included in the processing device PRC and each circuit included in the display device DSP.

[0351] In addition, the control circuit TC may have the function of transmitting the above-mentioned control signal or clock signal as a synchronization signal to two or more selected circuits from among the circuits included in the processing device PRC and the circuits included in the display device DSP in order to synchronize these two or more selected circuits.

[0352] <Example of Operation of Display System> Next, an example of operation of the display system DSYSA shown in FIG. 14 will be described.

[0353] Fig. 15 is a flowchart showing an example of the operation of the display system DSYSA in Fig. 14. The flowchart in Fig. 15 shows two operations: steps SP1 to SP14 showing an operation (hereinafter referred to as a first operation) of rewriting an image of a t-1th frame (t is an integer of 3 or more) pre-displayed in the pixel array unit PXA with an image of a tth frame, and steps SQ1 to SQ14 showing an operation (hereinafter referred to as a second operation) of rewriting an image of a tth frame with an image of a t+1th frame.

[0354] 15, the first and second operations are not performed separately, and part of the first operation may overlap with part of the second operation in timing. In other words, part of the first operation and part of the second operation may be performed simultaneously.

[0355] The memory circuit FM1 stores image data D （ｔ−１） [1] to Image Data D （ｔ−１） [M] is stored in the memory circuit FM2 in advance as the image of the t-2th frame. （ｔ−２） [1] to Image Data D （ｔ−２） It is assumed that [M] is held.

[0356] First, steps SP1 to SP14 of the first operation will be described.

[0357] In step SP1, as an example, i, which is a variable of the row number of the pixel array unit PXA, is set to 1. In steps SP1 to SP7, i is a variable that satisfies 1 to M.

[0358] In step SP2, for example, image data D （ｔ） Step SP2 also includes an operation of transmitting image data D[i] to the memory circuit LM2. （ｔ） The operation in which [i] is written is also included.

[0359] In step SP3, for example, the image data D of the i-th row of the t-1-th frame is read from the memory circuit FM1. （ｔ−１） [i] is read out and transmitted to the memory circuit LM1. Also, step SP3 includes an operation of reading out the image data D （ｔ−１） The operation in which [i] is written is also included.

[0360] Note that steps SP2 and SP3 may be performed simultaneously.

[0361] In step SP4, for example, image data D （ｔ−１） [i] is read out and transmitted to the processing circuit SGPR. Also, step SP4 includes an operation of reading out the image data D from the memory circuit LM2. （ｔ） [i] is read and sent to the processing circuit SGPR and the memory circuit FM2.

[0362] In step SP4, as an example, the image data D （ｔ） At this time, the image data D[i] stored in the memory circuit FM2 is written. （ｔ−２） [i] is the image data D read out from the memory circuit LM2 （ｔ） The operation of rewriting to [i] is performed.

[0363] In step SP5, for example, the processing circuit SGPR （ｔ−１） [i] and image data D （ｔ） In addition, step SP5 includes an operation of comparing the image data D （ｔ−１） [i] and image data D （ｔ） If [i] matches, the processing circuit SGPR outputs the comparison data C containing the logic of "0". （ｔ） Step SP5 also includes an operation of transmitting the image data D （ｔ−１） [i] and image data D （ｔ） If [i] do not match, the processing circuit SGPR outputs the comparison data C （ｔ） The operation includes transmitting [i] to the memory circuit FGM2.

[0364] In step SP5, for example, the comparison data C （ｔ） The operation in which [i] is written is also included.

[0365] In step SP6, it is determined whether i has reached M. If i has not reached M, the process proceeds from step SP6 to step SP7. If i has reached M, the process proceeds from step SP6 to step SP8.

[0366] Step SP7 includes the operation of adding 1 to i. After adding 1 to i, the process returns to step SP2.

[0367] In step SP8, as an example, k is defined as a variable representing the row number of the pixel array unit PXA. In step SP8, k is set to 1. In steps SP8 to SP14, k is a variable that satisfies the range of 1 to M.

[0368] In step SP9, for example, comparison data C （ｔ） [k] is read out and sent to the signal processing circuit PG.

[0369] In step SP10, for example, the signal processing circuit PG generates a pulse signal whose logic is "1" and a comparison data C （ｔ） [k] and the comparison data C （ｔ） Step SP10 includes an operation of generating a control signal including information [k]. Step SP10 also includes, as an example, an operation of transmitting the control signal to the drive circuit GD and the drive circuit SD.

[0370] In step SP11, the image data D held in the memory circuit FM2 is （ｔ） [k] is read out and input to the drive circuit SD.

[0371] Step SP12 includes an operation in which the drive circuit GD performs a logical operation on the selection signal (logic "1") sent to the k-th row of the pixel array unit PXA and the control signal generated in step SP10. （ｔ）When the logic of [k] is "0", the selection signal is converted into a non-selection signal (logic "0") as a result of the logical operation and is sent to the wiring GL[k]. （ｔ） When the logic of [k] is "1", the selection signal is not converted into a non-selection signal as a result of the logical operation, and a signal with a logic of "1" is sent to the wiring GL[k]. Note that, at this time, it is preferable to regard the non-selection signal (logic "0") as a signal with a low level potential, and the selection signal (logic "1") as a signal with a high level potential.

[0372] In step SP12, the drive circuit SD determines whether or not to set the output of the drive circuit SD to high impedance in response to the control signal generated by the signal processing circuit PG. （ｔ） When the logic of [k] is "0", the driving circuit SD sets its output to high impedance, and the image data D （ｔ） [k] is not output. （ｔ） When the logic of [k] is "1", the driving circuit SD （ｔ） [k] is output.

[0373] In step SP13, it is determined whether k has reached M. If k has not reached M, the process proceeds from step SP13 to step SP14. If k has reached M, the present operation example ends.

[0374] Step SP14 includes the operation of adding 1 to k. After adding 1 to k, the process returns to step SP9.

[0375] Next, steps SQ1 to SQ14 of the second operation will be described.

[0376] In addition, the operation of comparing the image of the tth frame with the image of the t+1th frame in the second operation to generate comparison data is performed, for example, between steps SP9 and SP14 in the first operation.

[0377] In step SQ1, as an example, a variable h representing the row number of the pixel array unit PXA is set to 1. In steps SQ1 to SQ7, h is a variable that satisfies the range of 1 to M.

[0378] In step SQ2, for example, image data D of the h-th row of the t+1th frame is input from the outside of the processing device PRC to the memory circuit LM1. （ｔ＋１） Step SQ2 also includes an operation of transmitting image data D[h] to the memory circuit LM1. （ｔ＋１） This also includes the operation of writing [h].

[0379] In step SQ3, for example, the image data D of the h-th row of the t-th frame is read from the memory circuit FM2. （ｔ） Step SQ3 also includes an operation of reading out [h] and transmitting it to the memory circuit LM2. （ｔ） This also includes the operation of writing [h].

[0380] Note that steps SQ2 and SQ3 may be performed simultaneously.

[0381] Preferably, steps SQ2 and SQ3 are performed during the operation of step SP9 or step SP10. In step SP9 or step SP10, no write or read operation is performed in the memory circuit FM2, so that the read operation of step SQ3 can be performed on the memory circuit FM2 during this period.

[0382] In step SQ3, the image data D read out from the memory circuit FM2 （ｔ） [h] is the image data D read out from the memory circuit FM2 in step SP11. （ｔ） That is, when k=h, the image data D read from the memory circuit FM2 （ｔ） [h] may be sent to the memory circuit LM2 and the drive circuit SD simultaneously.

[0383] In step SQ4, for example, image data D （ｔ）Step SQ4 also includes an operation of reading out image data D[h] from the memory circuit LM1 and transmitting it to the processing circuit SGPR. （ｔ＋１） [h] is read and sent to the processing circuit SGPR and the memory circuit FM1.

[0384] In step SQ4, for example, the image data D （ｔ＋１） At this time, the image data D[h] stored in the memory circuit FM1 is written. （ｔ−１） [h] is the image data D read out from the memory circuit LM1 （ｔ＋１） The operation of rewriting to [h] is performed.

[0385] Furthermore, it is preferable that steps SQ3 and SQ4 are performed during the operation of step SP11 or step SP12. In step SP11 or step SP12, the write operation and read operation in the memory circuit FM1 are not performed, so the write operation in step SQ4 can be performed in the memory circuit FM1 during this period.

[0386] In step SQ5, for example, the processing circuit SGPR （ｔ） [h] and image data D （ｔ＋１） Step SQ5 also includes an operation of comparing image data D （ｔ） [h] and image data D （ｔ＋１） If [h] match, the processing circuit SGPR outputs the comparison data C containing logic "0". （ｔ） [h] is transmitted to the memory circuit FGM1. （ｔ） [h] and image data D （ｔ＋１） If [h] do not match, the processing circuit SGPR outputs the comparison data C containing logic "1". （ｔ＋１） The operation includes transmitting [h] to the memory circuit FGM1.

[0387] In step SQ5, for example, the comparison data C （ｔ＋１） This also includes the operation of writing [h].

[0388] In step SQ6, it is determined whether h has reached M. If h has not reached M, the process proceeds from step SQ6 to step SQ7. If h has reached M, the process proceeds from step SQ6 to step SQ8.

[0389] Step SQ7 includes the operation of adding 1 to h. After adding 1 to h, the process returns to step SQ2.

[0390] In step SQ8, as an example, g is defined as a variable representing the row number of the pixel array unit PXA. Also, in step SQ8, g is set to 1. In steps SQ8 to SQ14, g is a variable that satisfies the range of 1 to M.

[0391] In step SQ9, for example, comparison data C （ｔ＋１） [g] is read and sent to the signal processing circuit PG.

[0392] In step SQ10, as an example, a pulse signal whose logic is "1" and comparison data C are input to the signal processing circuit PG. （ｔ＋１） A logical operation is performed with [g] to obtain the comparison data C （ｔ＋１） Step SQ10 includes an operation of generating a control signal including information [g]. Step SQ10 also includes, as an example, an operation of transmitting the control signal to the drive circuit GD and the drive circuit SD.

[0393] In step SQ11, the image data D held in the memory circuit FM1 is （ｔ＋１） The operation includes reading out [g] and inputting it to the drive circuit SD.

[0394] Step SQ12 includes an operation in which a logical operation is performed in the drive circuit GD on the selection signal (logic "1") sent to the gth row of the pixel array unit PXA and the control signal generated in step SQ10. （ｔ＋１） When the logic of [g] is "0", the selection signal is converted into a non-selection signal (logic "0") as a result of the logical operation and is sent to the wiring GL[g]. （ｔ＋１）When the logic of [g] is "1", the selection signal is not converted into a non-selection signal as a result of the logical operation, and a signal with a logic of "1" is sent to the wiring GL[g] as is. Note that, at this time, it is preferable to regard the non-selection signal (logic "0") as a signal with a low level potential, and the selection signal (logic "1") as a signal with a high level potential.

[0395] In step SQ12, the drive circuit SD determines whether or not to set the output of the drive circuit SD to high impedance in response to the control signal generated by the signal processing circuit PG. （ｔ＋１） When the logic of [g] is "0", the driving circuit SD makes its output high impedance, （ｔ＋１） [g] is not output. （ｔ＋１） When the logic of [g] is "1", the driving circuit SD （ｔ＋１） [g] is output.

[0396] In step SQ13, it is determined whether g has reached M. If g has not reached M, the process proceeds from step SQ13 to step SQ14. If g has reached M, the present operation example ends.

[0397] Step SQ14 includes the operation of adding 1 to g. After adding 1 to g, the process moves to step SQ9 again.

[0398] After the first operation is completed, a new image of the (t+2)th frame can be input to the processing device PRC between steps SQ8 and SQ14. At this time, the image of the (t+1)th frame and the image of the (t+2)th frame can be compared to generate comparison data, just as in steps SP1 to SP7 of the first operation. Thereafter, image data can be input to the display device DSP just like in steps SP8 to SP14 of the first operation.

[0399] By operating the display system DSYSA of Fig. 14 according to the operation method shown in the flowchart of Fig. 15, the t-th frame image can be displayed on the display device DSP while the processing device PRC compares the t-th frame image with the t+1-th frame image. In other words, since the images can be compared and displayed simultaneously, the display system DSYSA can be operated efficiently. This also prevents a decrease in the frame frequency of the display device DSP.

[0400] <Configuration Example of Each Circuit in Display System> Next, a configuration example of each circuit included in the display system DSYSA shown in FIG. 14 will be described.

[0401] In this configuration example, an operation is shown in which an image of the t-1th frame (t is an integer of 2 or more) that is pre-displayed on the pixel array unit PXA is rewritten with an image of the tth frame.

[0402] The memory circuit FM1 stores image data D （ｔ−１） [1] to Image Data D （ｔ−１） [M] is stored in the memory circuit FM2 in advance as the t-th frame image. （ｔ） [1] to Image Data D （ｔ） It is assumed that [M] is held.

[0403] [Memory Circuit LM1] Fig. 16 is a block diagram showing an example of the configuration of the memory circuit LM1. In Fig. 16, the processing circuit SGPR and the memory circuit FM1 are also shown to show the connection configuration between the memory circuit LM1 and its peripheral circuits. In Fig. 16, the image data for the i-th row transmitted from outside the memory device LM1 is indicated as D[i].

[0404] 16 can have the same configuration as the memory circuit LM1 described in Fig. 3. Therefore, for the memory circuit LM1 in Fig. 16, the description of the memory circuit LM1 in Fig. 3 can be referred to.

[0405] Note that the wirings WBLF1[1] to WBLF1[N] shown in FIG. 16 can be the wirings WBLF[1] to WBLF[N] in FIG.

[0406] [Memory Circuit LM2] Fig. 17 is a block diagram showing an example of the configuration of the memory circuit LM2. In Fig. 17, the processing circuit SGPR and the memory circuit FM2 are also shown to show the connection configuration between the memory circuit LM2 and its peripheral circuits. In Fig. 17, the image data for the i-th row transmitted from outside the memory device LM2 is indicated as D[i].

[0407] The memory circuit LM2 shown in Fig. 17 can be configured, for example, similarly to the memory circuit LM1 described in Fig. 3. Specifically, the memory circuit LM2 in Fig. 17 has a drive circuit WBD2, a drive circuit WWD2, a drive circuit RWD2, a drive circuit RBD2, and an output unit OPT2, and for the drive circuit WBD2 in Fig. 17, refer to the description of the drive circuit WBD1 in Fig. 3, for the drive circuit WWD2 in Fig. 17, refer to the description of the drive circuit WWD1 in Fig. 3, for the drive circuit RWD2 in Fig. 17, refer to the description of the drive circuit RWD1 in Fig. 3, for the drive circuit RBD2 in Fig. 17, refer to the description of the drive circuit RBD1 in Fig. 3, and for the output unit OPT2 in Fig. 17, refer to the description of the output unit OPT1 in Fig. 3.

[0408] 17 has N sense amplifiers SA2, and for the sense amplifiers SA2, the description of the sense amplifiers SA1 included in the drive circuit RBD1 in FIG. 3 can be referred to.

[0409] For the wirings WBL2[1] to WBL2[N] shown in FIG. 17, the description of the wirings WBL1[1] to WBL1[N] in FIG. 3 can be referred to. For the wiring WWL2 shown in FIG. 17, the description of the wiring WWL1 in FIG. 3 can be referred to. For the wiring RWL2 shown in FIG. 17, the description of the wiring RWL1 in FIG. 3 can be referred to. For the wirings RBL2[1] to RBL2[N] shown in FIG. 17, the description of the wirings RBL1[1] to RBL1[N] in FIG. 3 can be referred to. For the wiring SWL2A shown in FIG. 17, the description of the wiring SWL1A in FIG. 3 can be referred to. For the wiring SWL2B shown in FIG. 17, the description of the wiring SWL1B in FIG. 3 can be referred to. 17, the description of the wirings OL1[1] to OL1[N] in FIG. 3 can be referred to. The description of the wirings WBLF[1] to WBLF[N] in FIG. 3 can be referred to.

[0410] 17 can have the same configuration as the memory circuit LM1 described in Fig. 3, for example. Therefore, the description of the memory circuit LM1 in Fig. 3 can be referred to for the memory circuit LM2 in Fig. 17.

[0411] 18 is a block diagram showing a configuration example of the memory circuit FM1 or the memory circuit FM2. Note that the memory circuit FM1 and the memory circuit FM2 can have the same configuration, and therefore are shown as FM1 (FM2) in FIG. 18. In the following, the memory circuit FM1 will be described. However, in the description of the memory circuit FM1, the memory circuit LM1 will be replaced with the memory circuit LM2, the wirings WBLF1[1] to WBLF1[N] will be replaced with the wirings WBLF2[1] to WBLF2[N], the wirings WBL1[1] to WBL1[N] will be replaced with the wirings WBL2[1] to WBL2[N], and the image data D （ｔ） [i] is image data D （ｔ＋１） By replacing it with [i], it can be regarded as a description of the memory circuit FM2.

[0412] In order to show the connection configuration between the memory circuit FM1 and its peripheral circuits, FIG. 18 also illustrates the memory circuit LM1 and the drive circuit SD included in the display device DSP.

[0413] The memory circuit FM1 in Figure 18 is a configuration example in which the memory circuit FM shown in Figure 4 has been modified, and differs from the memory circuit FM shown in Figure 4 in that wirings WBL1[1] to WBL1[N] that transmit signals from the output section OPTF are connected to the memory circuit LM1.

[0414] The wirings WBL1[1] to WBL1[N] that transmit signals from the output unit OPTF are connected to the memory circuit LM1, whereby the image data D （ｔ） [i] (image data D （ｔ＋１） [i]) can be transmitted to the memory circuit LM1.

[0415] For other configurations of the memory circuit FM1 in FIG. 18, the description of the memory circuit FM in FIG. 4 can be referred to.

[0416] [Processing Circuit SGPR] Fig. 19 is a block diagram showing a configuration example of the processing circuit SGPR. In Fig. 19, in order to show the connection configuration between the processing circuit SGPR and its peripheral circuits, the memory circuits LM1, LM2, FGM1, and FGM2 are also shown.

[0417] The processing circuit SGPR shown in FIG. 19 is, as an example, a modified example of the processing circuit SGPR of FIG. 6, and differs from the processing circuit SGPR of FIG. 6 in that it has an output unit OPTP.

[0418] In the processing circuit SGPR of FIG. 19, the output part OPTP has a switch SWPA and a switch SWPB.

[0419] A first terminal of the switch SWPA and a first terminal of the switch SWPB are connected to the output terminal of the logic circuit LGMP, a second terminal of the switch SWPA is connected to the wiring WBLG1, and a second terminal of the switch SWPB is connected to the wiring WBLG2. In addition, a control terminal of the switch SWPA is connected to the wiring SWLPA, and a control terminal of the switch SWPB is connected to the wiring SWLPB.

[0420] The switches SWPA and SWPB can be, for example, switches that can be applied to the switches SW1A and SW1B of the memory circuit LM1 in Fig. 3. Therefore, unless otherwise specified, the description of the switches SWPA and SWPB can refer to the description of the switches SW1A and SW1B of the memory circuit LM1 in Fig. 3.

[0421] The wiring SWLPA functions as a wiring for switching the switch SWPA included in the processing circuit SGPR between an on state and an off state. Therefore, for example, a high-level potential or a low-level potential is supplied to the wiring SWLPA as a signal for switching the switch SWPA. Similarly, the wiring SWLPB functions as a wiring for switching the switch SWPB included in the processing circuit SGPR between an on state and an off state. Therefore, for example, a high-level potential or a low-level potential is supplied to the wiring SWLPB as a signal for switching the switch SWPB.

[0422] For example, the wiring WBLG1 is a wiring connected to the memory circuit FGM1, and the wiring WBLG2 is a wiring connected to the memory circuit FGM2. Note that each of the wiring WBLG1 and the wiring WBLG2 can be the wiring WBLG in the memory circuit FGM in FIG.

[0423] [Memory Circuit FGM1 and Memory Circuit FGM2] As an example, the memory circuit FGM illustrated in Fig. 6 can be applied to each of the memory circuit FGM1 and memory circuit FGM2 included in the processing device PRC in Fig. 14. Therefore, for configuration examples of each of the memory circuit FGM1 and memory circuit FGM2, the description of the memory circuit FGM in Fig. 6 can be referred to.

[0424] 6 is applied to each of the memory circuits FGM1 and FGM2, the wiring SWLG extending to the memory circuit FGM1 and the wiring SWLG extending to the memory circuit FGM2 are preferably separate wirings. This makes it possible to turn on only one of the switches SWG functioning as output units of the memory circuits FGM1 and FGM2. Since the processing device PRC in FIG. 14 is configured to read comparison data from one of the memory circuits FGM1 and FGM2 and transmit it to the signal processing circuit PG, as described above, it is preferable that the switches SWG of the memory circuits FGM1 and FGM2 are controlled by different wirings.

[0425] [Signal Processing Circuit PG] The signal processing circuit PG shown in Fig. 9A can be applied as an example to the signal processing circuit PG included in the processing device PRC in Fig. 14. Therefore, for a configuration example of the signal processing circuit PG, the description of the signal processing circuit PG in Fig. 9A can be referred to.

[0426] [Driver Circuit GD] As an example, any one of the drive circuits GD illustrated in each of Fig. 10A to Fig. 10D can be applied to the drive circuit GD included in the display device DSP of Fig. 14. Therefore, for configuration examples of the drive circuit GD, refer to the descriptions of the drive circuits GD in each of Fig. 10A to Fig. 10D.

[0427] [Driver Circuit SD] The driver circuit SD shown in Fig. 12 can be applied as an example to the driver circuit SD included in the processing device PRC in Fig. 14. Therefore, for a configuration example of the driver circuit SD, the description of the driver circuit SD in Fig. 12 can be referred to.

[0428] As described above, by configuring the display system DSYSA, similar to the display system DSYS of Figure 1, when the image displayed on the display device DSP does not change, the supply of charge according to image data to each of the wirings SL[1] to SL[N] can be eliminated, thereby reducing power consumption in the display system DSYSA.

[0429] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes.

[0430] Embodiment 3 In this embodiment, a display system according to one embodiment of the present invention, which has a different structure from the display systems described in Embodiments 1 and 2, will be described.

[0431] <Example of display system configuration> The display system DSYS described in embodiment 1 performs a comparison operation between the image signal and the image signal of the previous frame each time an image signal is sent to the display system DSYS. Therefore, depending on the processing time of the comparison operation, it may be difficult to increase the frame frequency of the display device DSP.

[0432] Furthermore, the configuration of the display system DSYSA described in embodiment 2 uses two line memories (memory circuits LM1 and LM2), two frame memories (memory circuits FM1 and FM2), and two flag memories (memory circuits FGM1 and FGM2), and is configured to input the image signal of the nth frame to the display device while performing a comparison operation between the image signals of the nth frame and the (n+1)th frame; however, the circuit scale of the display system DSYSA is likely to be larger than that of the display system DSYS.

[0433] Therefore, in this embodiment, a configuration of a display system that can reduce the circuit area and easily increase the frame frequency of the display device DSP or can prevent a decrease in the frame frequency will be described.

[0434] 20 is a block diagram illustrating a configuration example of a display system according to one embodiment of the present invention. In particular, a display system DSYSB illustrated in FIG. 20 is a modification of the display system DSYS illustrated in FIG. 1 , and differs from the display system DSYS in that the display system DSYS includes a memory circuit FMA having a different configuration from the memory circuit FM and does not include the memory circuits LM1 and LM2.

[0435] Therefore, in this specification, for the configuration of part of the display system DSYSB in Fig. 20, the description of the display system DSYSB in Fig. 1 can be referred to. Also, in this specification, in the description of the display system DSYSB in Fig. 20, the description of parts that overlap with the content of the display system DSYS in Fig. 1 may be omitted.

[0436] 1 can be referred to for the pixel array portion PXA included in the display device DSP in Fig. 20. In addition, the descriptions of the wirings SL[1] to SL[N] and the wirings GL[1] to GL[M] in Fig. 1 can be referred to for the wirings SL[1] to SL[N] and the wirings GL[1] to GL[M].

[0437] For the driver circuit SD and driver circuit GD included in the display device DSP of FIG. 20, the description of the driver circuit SD and driver circuit GD of FIG. 1 can be referred to.

[0438] For the processing circuit SGPR included in the processing device PRC in Fig. 20, the description of the processing circuit SGPR in Fig. 1 can be referred to. Furthermore, for the memory circuit FGM included in the processing device PRC in Fig. 20, the description of the memory circuit FGM in Fig. 1 can be referred to. Furthermore, for the signal processing circuit PG included in the processing device PRC in Fig. 20, the description of the signal processing circuit PG in Fig. 1 can be referred to.

[0439] The memory circuit FMA functions as a frame memory, for example. Specifically, the memory circuit FMA temporarily stores image data for all rows of an image to be displayed in the pixel array unit PXA. In particular, unlike the memory circuit FM of FIG. 1, the memory circuit FMA temporarily stores image data for two consecutive frames. In some cases, the memory circuit FMA may store image data for two non-consecutive frames.

[0440] Further, the memory circuit FMA stores, as an example, image data D of the t-th frame transmitted to each of the first to M-th rows of the pixel array unit PXA. （ｔ） [1] to Image Data D （ｔ）The memory circuit FMA has a function of acquiring the image data D [M] from outside the processing device PRC. （ｔ） [1] to Image Data D （ｔ） The signal processing circuit 100 has a function of sequentially reading out each of [M] and transmitting them to the driver circuit SD.

[0441] The memory circuit FMA is configured to be capable of simultaneously reading out two frames of image data, and preferably configured to read out one of the two frames of image data while writing the other of the two frames of image data.

[0442] Furthermore, since the memory circuit FMA can temporarily hold image data for two consecutive frames, the memory circuit FMA stores, for example, image data D （ｔ） [1] to Image Data D （ｔ） [M] and the image data D of the t+1th frame （ｔ＋１） [1] to Image Data D （ｔ＋１） It is possible to hold image data for two frames [M] and [M].

[0443] The control circuit TC included in the processing device PRC in FIG. 20 has, as an example, a function to control each circuit included in the processing device PRC and each circuit included in the display device DSP. For example, the control circuit TC has a function to send command signals to the drive circuits included in the memory circuit FMA and the memory circuit FGM to perform write operations, read operations, etc. The control circuit TC also has a function to send command signals to the drive circuits SD and the drive circuit GD to perform write operations, read operations, etc. The control circuit TC also has, as an example, a function to send command signals to control the switching between the on and off states of the switching elements included in the memory circuit FMA, the memory circuit FGM, and the processing circuit SGPR. The control circuit TC also has, as an example, a function to generate clock signals to be supplied to each circuit included in the processing device PRC and each circuit included in the display device DSP.

[0444] In addition, the control circuit TC may have the function of transmitting the above-mentioned clock signal or the like as a synchronization signal to two or more selected circuits from among the circuits included in the processing device PRC and the circuits included in the display device DSP in order to synchronize these two or more selected circuits.

[0445] <Example of Operation of Display System> Next, an example of operation of the display system DSYSB shown in FIG. 20 will be described.

[0446] Fig. 21 is a flowchart showing an example of the operation of the display system DSYSB in Fig. 20. The flowchart in Fig. 21 shows two operations: steps SR1 to SR16 showing an operation (hereinafter referred to as a first operation) of displaying images from the t-2th frame (t is an integer of 3 or more) to the t-1th frame in the pixel array unit PXA and also displaying images from the t-1th frame to the t-th frame, and steps SS1 to SS16 showing an operation (hereinafter referred to as a second operation) of rewriting the image of the t-th frame with the image of the t+1th frame.

[0447] 21, the first and second operations are not performed separately, and part of the first operation may overlap with part of the second operation in timing. In other words, part of the first operation and part of the second operation may be performed simultaneously.

[0448] The memory circuit FMA stores image data D （ｔ−１） [1] to Image Data D （ｔ−１） The memory circuit FGM stores the image data D of the t-2th frame in advance. （ｔ−２） [1] to Image Data D （ｔ−２） [M] and the image data D of the t-1th frame （ｔ−１） [1] to Image Data D （ｔ−１） Comparison data C with [M] （ｔ−１） [1] to Comparison Data C （ｔ−１） It is assumed that [M] is held.

[0449] First, steps SR1 to SR16 of the first operation will be described.

[0450] In step SR1, as an example, i, which is a variable of the row number of the pixel array unit PXA, is set to 1. In steps SR1 to SR4, i is a variable that satisfies the range of 1 to M.

[0451] In step SR2, for example, image data D of the i-th row of the t-th frame is input from the outside of the processing device PRC to the memory circuit FMA. （ｔ） Step SR2 also includes an operation of transmitting image data D[i] to the memory circuit FMA. （ｔ） The operation in which [i] is written is also included.

[0452] The memory circuit FMA stores image data D （ｔ） While writing [i], image data D （ｔ−１） At this time, the read image data D （ｔ−１） [i] is sent to the driver circuit SD.

[0453] In step SR3, it is determined whether i has reached M. If i has not reached M, the process proceeds from step SR3 to step SR4. If i has reached M, the process proceeds from step SR3 to step SR5.

[0454] Step SR4 includes the operation of adding 1 to i. After adding 1 to i, the process returns to step SR2.

[0455] In step SR5, as an example, h is defined as a variable representing the row number of the pixel array unit PXA. In step SR5, h is set to 1. In steps SR5 to SR9, h is a variable that satisfies the range of 1 to M.

[0456] In step SR6, for example, image data D is read from the memory circuit FMA. （ｔ−１） [h] and image data D （ｔ） [h] are simultaneously read out and sent to the processing circuit SGPR.

[0457] In step SR7, for example, the processing circuit SGPR （ｔ−１）[h] and image data D （ｔ） Step SR7 also includes an operation of comparing image data D （ｔ−１） [h] and image data D （ｔ） If [h] matches, the processing circuit SGPR outputs the comparison data C containing the logic of "0". （ｔ） [h] to the memory circuit FGM. （ｔ−１） [h] and image data D （ｔ） If [h] do not match, the processing circuit SGPR outputs the comparison data C （ｔ） The operation includes transmitting [h] to the memory circuit FGM.

[0458] In step SR7, for example, the comparison data C （ｔ） This also includes the operation of writing [h].

[0459] In step SR8, it is determined whether h has reached M. If h has not reached M, the process proceeds from step SR8 to step SR9. If h has reached M, the process proceeds from step SR8 to step SR10.

[0460] Step SR9 includes the operation of adding 1 to h. After adding 1 to h, the process returns to step SR6.

[0461] In step SR10, as an example, k is defined as a variable representing the row number of the pixel array unit PXA. In step SR10, k is set to 1. In steps SR10 to SR16, k is a variable that satisfies the range of 1 to M.

[0462] In step SR11, for example, comparison data C （ｔ） [k] is read out and sent to the signal processing circuit PG.

[0463] In step SR12, for example, a pulse signal whose logic is "1" and comparison data C are input to the signal processing circuit PG. （ｔ） [k] and the comparison data C （ｔ）Step SR12 includes an operation of generating a control signal including information [k]. Step SR12 also includes, as an example, an operation of transmitting the control signal to the drive circuit GD and the drive circuit SD.

[0464] In step SR13, the image data D held in the memory circuit FMA is （ｔ） [k] is read out and input to the drive circuit SD.

[0465] Step SR14 includes an operation in which a logical operation is performed in the drive circuit GD on the selection signal (logic "1") transmitted to the k-th row of the pixel array unit PXA and the control signal generated in step SR12. （ｔ） When the logic of [k] is "0", the selection signal is converted into a non-selection signal (logic "0") as a result of the logical operation and is sent to the wiring GL[k]. （ｔ） When the logic of [k] is "1", the selection signal is not converted into a non-selection signal as a result of the logical operation, and a signal with a logic of "1" is sent to the wiring GL[k]. Note that, at this time, it is preferable to regard the non-selection signal (logic "0") as a signal with a low level potential, and the selection signal (logic "1") as a signal with a high level potential.

[0466] In step SR14, the drive circuit SD determines whether or not to set the output of the drive circuit SD to high impedance in response to the control signal generated by the signal processing circuit PG. （ｔ） When the logic of [k] is "0", the driving circuit SD sets its output to high impedance, and the image data D （ｔ） [k] is not output. （ｔ） When the logic of [k] is "1", the driving circuit SD （ｔ） [k] is output.

[0467] In step SR15, it is determined whether k has reached M. If k has not reached M, the process proceeds from step SR15 to step SR16. If k has reached M, the first operation ends.

[0468] Step SR16 includes the operation of adding 1 to k. After adding 1 to k, the process returns to step SR11.

[0469] Next, steps SS1 to SS16 of the second operation will be described.

[0470] In step SS1, as an example, a variable g representing the row number of the pixel array unit PXA is set to 1. In steps SS1 to SS4, g is a variable that satisfies the range of 1 to M.

[0471] In step SS2, for example, the image data D of the gth row of the t+1th frame is input from the outside of the processing device PRC to the memory circuit FMA. （ｔ＋１） Step SS2 also includes an operation of transmitting image data D[g] to the memory circuit FMA. （ｔ＋１） This also includes the action of writing [g].

[0472] In step SS3, it is determined whether g has reached M. If g has not reached M, the process proceeds from step SS3 to step SS4. If g has reached M, the process proceeds from step SS3 to step SS5.

[0473] Step SS4 includes the operation of adding 1 to g. After adding 1 to g, the process returns to step SS2.

[0474] Also, step SS2 is preferably performed during steps SR11 to SR14 of the first operation. In particular, in step SR13, image data D is read from the memory circuit FMA. （ｔ） A read operation of [k] is performed, but by configuring the memory circuit FMA to be able to perform write and read operations simultaneously, steps SS2 and SR13 can be executed simultaneously.

[0475] In addition, in this case, in the memory circuit FMA, the row address to be written in step SS2 may be the same as the row address to be read in step SR13. In other words, with k=g, steps SS2 to SS4 and steps SR11 to SR16 may be performed simultaneously.

[0476] For the operations of steps SS5 to SS16, the explanation of steps SR5 to SR16 in the first operation can be referred to. In this case, in the explanation of steps SR5 to SR16, （ｔ） [h] is image data D （ｔ＋１） [h] and image data D （ｔ−１） [h] is image data D （ｔ） By replacing it with [h], it can be regarded as an explanation of steps SS5 to SS16.

[0477] By operating the display system DSYSB in Fig. 20 according to the operation method shown in the flowchart in Fig. 21, the memory circuit FMA of the processing device PRC can simultaneously read out the t-th frame image and write in the t+1-th frame image, thereby enabling the display system DSYSB to operate efficiently, and thus preventing a decrease in the frame frequency of the display device DSP.

[0478] <Configuration Example of Each Circuit in Display System> Next, a configuration example of each circuit included in the display system DSYSB shown in FIG. 20 will be described.

[0479] In this configuration example, an operation is shown in which an image of the t-1th frame (t is an integer of 3 or more) that is pre-displayed on the pixel array unit PXA is rewritten with an image of the tth frame.

[0480] The memory circuit FMA stores image data D （ｔ−２） [1] to Image Data D （ｔ−２） [M] and image data D as the image of the t-1th frame. （ｔ−１） [1] to Image Data D （ｔ−１）[M] and are assumed to be held.

[0481] [Memory Circuit FMA] Fig. 22 is a block diagram showing an example of the configuration of the memory circuit FMA. Fig. 22 also shows a processing circuit SGPR to show the connection configuration between the memory circuit FMA and its peripheral circuits.

[0482] The memory circuit FMA shown in FIG. 22 includes, as an example, a drive circuit WBDF, a drive circuit WWDFX, a drive circuit WWDFY, a drive circuit RWDF, a drive circuit RBDF, a memory cell unit MCAA, an input unit IPTF, and an output unit OPTF.

[0483] The memory cell unit MCAA has, as an example, a plurality of memory cells MCX and a plurality of memory cells MCY. In particular, in the memory cell unit MCAA of Fig. 22, as an example, the plurality of memory cells MCX and the plurality of memory cells MCY are arranged alternately in each column. Specifically, in the memory cell unit MCAA of Fig. 22, the plurality of memory cells MCX and the plurality of memory cells MCY are arranged in a matrix of M rows and 2 x N columns, and in particular, among the first column to the 2 x Nth column, the memory cells MCX are arranged in the odd-numbered columns and the memory cells MCY are arranged in the even-numbered columns.

[0484] Note that [x, y] attached to memory cell MCX indicates the address of memory cell MCX when only memory cell MCX is focused (memory cell MCY is ignored) in the memory cell section MCAA of Fig. 22. Similarly, [x, y] attached to memory cell MCY indicates the address of memory cell MCY when only memory cell MCY is focused (memory cell MCX is ignored) in the memory cell section MCAA of Fig. 22. For example, although not shown in Fig. 22, memory cell MCX[i, j] means that it is located in row i, column j when memory cell MCX is focused, and similarly, memory cell MCY[i, j] means that it is located in row i, column j when memory cell MCY is focused.

[0485] Furthermore, unless otherwise specified, the description of memory cell MC1 of memory circuit LM1 in Figure 3 can be referred to for memory cells MCX[1,1] to MCX[M,N] and memory cells MCY[1,1] to MCY[M,N].

[0486] The memory cells MCX[i,1] to MCX[i,N] store, for example, image data D[i] of the i-th row transmitted from outside the processing device PRC. The image data D[i] of the i-th row stored in the memory cells MCX[i,1] to MCX[i,N] is transmitted to, for example, the processing circuit SGPR and the pixel circuits PX[i,1] to PX[i,N] of the i-th row of the pixel array unit PXA.

[0487] Similarly, the memory cells MCY[i,1] to MCY[i,N] store image data D[i] of the i-th row transmitted from outside the processing device PRC. The image data D[i] of the i-th row stored in the memory cells MCY[i,1] to MCY[i,N] is transmitted to the processing circuit SGPR and the pixel circuits PX[i,1] to PX[i,N] of the i-th row of the pixel array unit PXA, for example.

[0488] In particular, memory cells MCX[i,1] to MCX[i,N] store image data D[i] of one of the odd-numbered or even-numbered frames, and memory cells MCY[i,1] to MCY[i,N] store image data D[i] of the other of the odd-numbered or even-numbered frames.

[0489] For example, memory cell MCX[i,j] is connected to wiring WBLFX[j], wiring RBLFX[j], wiring WWLFX[i], and wiring RWLF[i]. Also, memory cell MCY[i,j] is connected to wiring WBLFY[j], wiring RBLFY[j], wiring WWLFY[i], and wiring RWLF[i].

[0490] For example, the wiring WBLFX functions as a write data line, a write bit line, etc. in the memory cell MCX. Also, for example, the wiring WBLFY functions as a write data line, a write bit line, etc. in the memory cell MCY.

[0491] For example, the wiring RBLFX functions as a read data line, a read bit line, etc. in the memory cell MCX. Also, for example, the wiring RBLFY functions as a read data line, a read bit line, etc. in the memory cell MCY.

[0492] For example, the wiring WWLFX functions as a write word line in the memory cell MCX, and the wiring WWLFY functions as a write word line in the memory cell MCY.

[0493] The wiring RWLF functions as a read word line for the memory cells MCX and MCY. Note that the wiring RWLF may also function as a wiring for transmitting a write selection signal in addition to a read selection signal.

[0494] For example, the driver circuit WBDF has a function of acquiring image data transmitted from outside the memory circuit FMA and transmitting data included in the image data to the wirings WBLFX[1] to WBLFX[N] or the wirings WBLFY[1] to WBLFY[N]. In other words, for example, the driver circuit WBDF has a function as a write bit line driver circuit in the memory cell unit MCAA.

[0495] The input unit IPTF has a function of, for example, selecting one of the memory cells MCX and MCY and transmitting image data transmitted from the driving circuit WBDF to that one. Specifically, the input unit IPTF has a function of, for example, bringing the driving circuit WBDF and one of the wirings WBLFX and WBLFY into a conductive state, and bringing the driving circuit WBDF and the other of the wirings WBLFX and WBLFY into a non-conductive state.

[0496] The input unit IPTF may have, for example, N switching circuits SWCI. In this configuration, each of the N switching circuits SWCI has a switch SW1X and a switch SW1Y.

[0497] The switches SW1X and SW1Y can be, for example, switches that can be applied to the switch SW1A or the switch SW1B of the memory circuit LM1 described in Embodiment 1. Therefore, for the switches SW1X and SW1Y, the description of the switches SW1A or SW1B of the memory circuit LM1 can be referred to unless otherwise specified.

[0498] In the j-th column, the first terminal of the switch SW1X is connected to the first terminal of the switch SW1Y and the drive circuit WBDF. The second terminal of the switch SW1X is connected to the wiring WBLFX[j]. The control terminal of the switch SW1X is connected to the wiring SWLF1X. The second terminal of the switch SW1Y is connected to the wiring WBLFY[j]. The control terminal of the switch SW1Y is connected to the wiring SWLF1Y.

[0499] The wiring SWLF1X has a function as a wiring for switching the on state and the off state of the switch SW1X included in the switching circuit SWCI. Therefore, for example, a high-level potential or a low-level potential is supplied to the wiring SWLF1X as a signal for the switching.

[0500] The wiring SWLF1Y functions as a wiring for switching the switch SW1Y included in the switching circuit SWCI between an on state and an off state. Therefore, for example, a high-level potential or a low-level potential is supplied to the wiring SWL1Y as a signal for switching, similar to the wiring SWLF1X.

[0501] Incidentally, the input unit IPTF may be included in the driving circuit WBDF, for example.

[0502] For example, the driver circuit WWDFX has a function of transmitting a write selection signal or a non-selection signal to the wiring WWLFX when writing image data to the memory cell MCX. For example, transmitting a write selection signal to the wiring WWLFX[i] turns on the write transistors included in each of the memory cells MCX[i,1] to MCX[i,N] in the i-th row, allowing the memory cells MCX[i,1] to MCX[i,N] to acquire the image data transmitted to the wirings WBLFX[1] to WBLFX[N]. After that, the driver circuit WWDFX transmits a non-selection signal to the wiring WWLFX[i], turning off the write transistors included in each of the memory cells MCX[i,1] to MCX[i,N], allowing the memory cells MCX[i,1] to MCX[i,N] to retain the image data. That is, the drive circuit WWDFX has a function as a write word line driver circuit for the memory cells MCX included in the memory cell unit MCAA, for example. Also, from the above, the drive circuit WWDFX may be called a selection circuit.

[0503] For example, the image data D in the i-th row of the s-th frame is transmitted from the driver circuit WBDF to the memory cells MCX[i,1] to MCX[i,N] in the i-th row via the input unit IPTF. （ｓ） The case where [i] is written will be described.

[0504] At this time, while the driver circuit WWDFX transmits a write selection signal to the wiring WWLFX[i] and a non-selection signal to the wirings WWLFX[1] to WWLFX[M] other than the wiring WWLFX[i], the switch SW1X is turned on and the switch SW1Y is turned off, and the driver circuit WBDF transmits the image data D to the wirings WBLFX[1] to WBLFX[N]. （ｓ） By transmitting [i], the image data D is stored in the memory cells MCX[i,1] to MCX[i,N] in the i-th row of the memory cell unit MCAA. （ｓ） [i] can be written.

[0505] For example, the driver circuit WWDFY has a function of transmitting a write selection signal or a non-selection signal to the wiring WWLFY when writing image data to the memory cell MCY. For example, when a write selection signal is transmitted to the wiring WWLFY[i], the write transistors included in each of the memory cells MCY[i,1] to MCY[i,N] in the i-th row are turned on, so that the memory cells MCY[i,1] to MCY[i,N] can acquire the image data D[i] transmitted to the wirings WBLFY[1] to WBLFY[N]. After that, the driver circuit WWDFY transmits a non-selection signal to the wiring WWLFY[i], so that the write transistors included in each of the memory cells MCY[i,1] to MCY[i,N] are turned off, so that the memory cells MCY[i,1] to MCY[i,N] can acquire the image data D[i] transmitted to the wirings WBLFY[1] to WBLFY[N]. （ｔ） [i]. That is, the drive circuit WWDFY has a function as a write word line driver circuit for the memory cell MCY included in the memory cell unit MCAA, for example. Also, from the above, the drive circuit WWDFY may be called a selection circuit.

[0506] For example, the image data D of the i-th row of the s-th frame is transmitted from the driver circuit WBDF to the memory cells MCY[i,1] to MCY[i,N] of the i-th row via the input unit IPTF. （ｓ） The case where [i] is written will be described.

[0507] At this time, while the driver circuit WWDFY transmits a write selection signal to the wiring WWLFY[i] and transmits a non-selection signal to the wirings WWLFY[1] to WWLFY[M] other than the wiring WWLFY[i], the switch SW1X is turned off and the switch SW1Y is turned on, and the driver circuit WBDF transmits the image data D to the wirings WBLFY[1] to WBLFY[N]. （ｓ） By transmitting [i], the image data D is stored in the memory cells MCY[i,1] to MCY[i,N] in the i-th row of the memory cell unit MCAA. （ｓ） [i] can be written.

[0508] For example, the driver circuit RWDF has a function of transmitting a read selection signal to the wiring RWLF[i] when reading image data from each of the memory cells MCX[i,1] to MCX[i,N] and the memory cells MCY[i,1] to MCY[i,N] in the i-th row of the memory cell unit MCAA. The driver circuit RWDF also has a function of transmitting a non-selection signal to the wirings RWLF[1] to RWLF[M] excluding the wiring RWLF[i] so as to prevent reading from each of the memory cells MCX[1,1] to MCX[M,N] and the memory cells MCY[1,1] to MCY[M,N] in rows other than the i-th row of the memory cell unit MCAA. Furthermore, by sequentially transmitting selection signals to the wirings RWLF[1] to RWLF[M], the memory cells MCX[1,1] to MCX[M,N] and the memory cells MCY[1,1] to MCY[M,N] included in the memory cell unit MCAA can be sequentially selected row by row as the source of image data. That is, the driver circuit RWDF functions as a read word line driver circuit in the memory cell unit MCAA, for example. The driver circuit RWDF may also be referred to as a selection circuit from the above.

[0509] For example, the image data D of the t-2-th frame is stored in the memory cells MCX[i,1] to MCX[i,N] of the i-th row. （ｔ−２） [i] is read out, and the image data D of the t-1-th frame is read out from the memory cells MCY[i,1] to MCY[i,N] of the i-th row. （ｔ−１） The case where [i] is read will be described.

[0510] At this time, the driver circuit RWDF transmits a read selection signal to the wiring RWLF[i] and transmits a non-selection signal to the wirings RWLF[1] to RWLF[M] other than the wiring RWLF[i], thereby transmitting image data D from the memory cells MCX[i,1] to MCX[i,N] in the i-th row of the memory cell unit MCAA to the wirings RBLFX[1] to RBLFX[N], respectively. （ｔ−２）At the same time, the image data D is output from the memory cells MCY[i,1] to MCY[i,N] in the i-th row of the memory cell unit MCAA to the wirings RBLFY[1] to RBLFY[N], respectively. （ｔ−１） A read potential according to [i] can be output.

[0511] For example, the driver circuit RBDF has a function of amplifying the read potentials output from the memory cells MCX and MCY to the wirings RBLFX and RBLFY, respectively, to a level at which the read potentials can be treated as digital data. This allows the image data read from the memory cells MCX[i,1] to MCX[i,N] in the i-th row to be transmitted as digital data to the driver circuit SD or the processing circuit SGPR. In other words, for example, the driver circuit RBDF functions as a read circuit in the memory cell unit MCAA.

[0512] For example, as shown in FIG. 22 , the driver circuit RBDF can be configured to include N sense amplifiers SAX and N sense amplifiers SAY. In this configuration, each of the wirings RBLFX[1] to RBLFX[N] is connected to a sense amplifier SAX, and each of the wirings RBLFY[1] to RBLFY[N] is connected to a sense amplifier SAY. The N sense amplifiers SAX can amplify read potentials corresponding to image data read from the memory cells MCX[i,1] to MCX[i,N] in the i-th row to a level at which the read potentials can be treated as digital data. Similarly, the N sense amplifiers SAY can amplify read potentials corresponding to image data read from the memory cells MCY[i,1] to MCY[i,N] in the i-th row to a level at which the read potentials can be treated as digital data.

[0513] The output unit OPTF has a function of switching the output destination of the image data read from each of the memory cells MCX and MCY, for example. Specifically, the output unit OPTF transmits the image data read from each of the memory cells MCX and MCY to the processing circuit SGPR, or selects one of the image data read from each of the memory cells MCX and MCY and transmits it to the drive circuit SD.

[0514] For example, the output unit OPTF can be configured to have N switching circuits SWCO as shown in Fig. 22. In this configuration, each of the N switching circuits SWCO has a switch SW2X, a switch SW2Y, a switch SW3X, and a switch SW3Y.

[0515] The switches SW2X, SW2Y, SW3X, and SW3Y can be, for example, switches that can be applied to the switch SW1A or the switch SW1B of the memory circuit LM1 described in Embodiment 1. Therefore, for the switches SW2X, SW2Y, SW3X, and SW3Y, the description of the switch SW1A or the switch SW1B of the memory circuit LM1 can be referred to unless otherwise specified.

[0516] Furthermore, for example, the output unit OPTF can be configured to have a switching circuit MX as shown in Fig. 22. The switching circuit MX in Fig. 22 functions as a multiplexer, similar to the switching circuit MX described in Fig. 4. Therefore, for the switching circuit MX in Fig. 22, the description of the switching circuit MX in Fig. 4 can be referred to. As a result, the switching circuit MX in Fig. 22 can sequentially output image data read from the memory cells MCX or memory cells MCY to the wiring PDL column by column by sequentially switching the input terminal that is brought into a conductive state with the output terminal.

[0517] In the jth column, the sense amplifier SAX is connected to the first terminal of the switch SW2X and the first terminal of the switch SW3X, and the sense amplifier SAY is connected to the first terminal of the switch SW2Y and the first terminal of the switch SW3Y. The second terminal of the switch SW2X and the second terminal of the switch SW2Y are each connected to one of the N input terminals of the switching circuit MX. The second terminal of the switch SW3X is connected to a line OLX[j] (not shown), and the second terminal of the switch SW3Y is connected to a line OLY[j] (not shown). The control terminal of the switch SW2X is connected to a line SWLF2X, the control terminal of the switch SW2Y is connected to a line SWLF2Y, and the control terminals of the switches SW3X and SW3Y are each connected to a line SWLF3.

[0518] The wiring OLX[j] and the wiring OLY[j] are connected to the processing circuit SGPR. The output terminal of the switching circuit MX is connected to the drive circuit SD included in the display device DSP via a wiring PDL.

[0519] The wiring SWLF2X functions as a wiring for switching the switch SW2X included in the switching circuit SWCO between an on state and an off state. Therefore, for example, a high-level potential or a low-level potential is supplied to the wiring SWLF2X as a signal for switching. Furthermore, the wiring SWLF2Y functions as a wiring for switching the switch SW2Y included in the switching circuit SWCO between an on state and an off state. Therefore, for example, a high-level potential or a low-level potential is supplied to the wiring SWLF2Y as a signal for switching, similar to the wiring SWLF2X.

[0520] The wiring SWLF3 functions as a wiring for switching between an on state and an off state of each of the switches SW3X and SW3Y included in the switching circuit SWCO. Therefore, for example, a high-level potential or a low-level potential is supplied to the wiring SWLF3 as a signal for switching, similar to the wirings SWLF2X and SWLF2Y.

[0521] 22, the wirings OLX[1] to OLX[N] and the wirings OLY[1] to OLY[N] are shown as wirings for transmitting image data from the memory circuit FMA to the processing circuit SGPR, and the wiring PDL is shown as wiring for transmitting image data from the memory circuit FMA to the driver circuit SD.

[0522] 22, the memory circuit FMA and the driver circuit SD are connected using the wiring PDL, but the output unit OPTF may not be provided with a switching circuit MX, and the second terminals of the plurality of switches SW2X and the second terminals of the plurality of switches SW2Y may be directly connected to the driver circuit SD. This allows the image data to be transmitted all at once, thereby reducing the time required to transmit the image data.

[0523] <<Example of Operation of Memory Circuit FMA>> Next, an example of operation of the memory circuit FMA will be described.

[0524] Fig. 23 is a circuit diagram showing a configuration focusing on one column of the memory cell unit MCAA in the memory circuit FMA of Fig. 22. Also, in Fig. 23, the memory cell MCX and memory cell MCY of the memory cell unit MCAA each have the configuration of a memory cell having two transistors and one capacitive element shown in Fig. 32A described in embodiment 5. Therefore, for the specific configuration and operation of the memory cell MCX and memory cell MCY shown in Fig. 23, the description of Fig. 32A described in embodiment 5 can be referred to.

[0525] 23, the connection point between the first terminal of the switch SW1X and the first terminal of the switch SW1Y in the switching circuit SWCI is indicated as a node NW. Also, in Fig. 23, the connection point between the second terminal of the switch SW2X, the second terminal of the switch SW2Y, and the input terminal of the switching circuit MX in the switching circuit SWCO is indicated as a node NO.

[0526] 23 includes a transistor M1, a transistor M2, and a capacitance element C1. The transistor M1 functions as a write transistor in the memory cell, and the transistor M2 functions as a read transistor. The capacitance element C1 holds a potential corresponding to image data.

[0527] In memory cell MCX, a first terminal of transistor M1 is connected to the gate of transistor M2 and a first terminal of capacitance element C1. A second terminal of transistor M1 is connected to wiring WBLFX, and a gate of transistor M1 is connected to wiring WWLFX. A first terminal of transistor M2 is connected to wiring RBLFX, and a second terminal of transistor M2 is connected to wiring SLX. A second terminal of capacitance element C1 is connected to wiring RWLF.

[0528] In memory cell MCY, the first terminal of transistor M1 is connected to the gate of transistor M2 and the first terminal of capacitance element C1. The second terminal of transistor M1 is connected to wiring WBLFY, and the gate of transistor M1 is connected to wiring WWLFY. The first terminal of transistor M2 is connected to wiring RBLFY, and the second terminal of transistor M2 is connected to wiring SLY. The second terminal of capacitance element C1 is connected to wiring RWLF.

[0529] For example, the wiring SLX functions as a wiring for supplying a potential required when image data is read from the memory cell MCX, and the wiring SLY functions as a wiring for supplying a potential required when image data is read from the memory cell MCY, similar to the wiring SLX.

[0530] When writing image data to memory cell MCX, for example, the driver circuit WWDFX first applies a high-level potential to the wiring WWLFX as a selection signal, turning on the transistor M1 of memory cell MCX and establishing electrical continuity between the wiring WBLFX and the first terminal of the capacitance element C1. Then, the driver circuit RWDF applies a high-level potential to the wiring RWLF as a selection signal, and the driver circuit WBDF then transmits image data to the wiring WBLFX via the switch SW1X, thereby writing the image data to memory cell MCX. Then, the driver circuit WWDFX applies a low-level potential to the wiring WWLFX as a non-selection signal, turning off the transistor M1 of memory cell MCX and maintaining a voltage corresponding to the image data between the first and second terminals of the capacitance element C1. After turning off the transistor M1, the driver circuit RWDF applies a low-level potential to the wiring RWLF as a non-selection signal. As a result, the potential of the first terminal of the capacitive element C1 drops due to capacitive coupling by the capacitive element C1, so that the transistor M2 of the memory cell MCX can be turned off. Note that since the first terminal of the capacitive element C1 is in a floating state, even if the potential of the first terminal of the capacitive element C1 drops, the voltage corresponding to the image data between the first terminal and the second terminal of the capacitive element C1 is maintained.

[0531] Furthermore, when reading image data from memory cell MCX, for example, a high-level potential is first supplied to line SLX, and a low-level potential is precharged to line RBLFX. Then, when drive circuit RWDF applies a high-level potential to line RWLF as a selection signal, the potential of the first terminal of capacitive element C1 rises due to capacitive coupling of capacitive element C1. At this time, transistor M2 of memory cell MCX turns on, current flows from line SLX to line RBLFX, and the potential of line RBLFX rises. The potential that line RBLFX ultimately reaches is determined by the potential of the gate of transistor M2 of memory cell MCX, i.e., the potential corresponding to the image data. Then, the potential of line RBLFX is amplified by drive circuit RBDF, allowing image data to be read from memory cell MCX.

[0532] When writing image data to memory cell MCY, for example, the driver circuit WWDFY first applies a high-level potential to the wiring WWLFY as a select signal, turning on the transistor M1 of memory cell MCY and establishing electrical continuity between the wiring WBLFY and the first terminal of the capacitance element C1. Then, the driver circuit RWDF applies a high-level potential to the wiring RWLF as a select signal, and the driver circuit WBDF then transmits image data to the wiring WBLFY via the switch SW1Y, thereby writing the image data to memory cell MCY. Then, the driver circuit WWDFY applies a low-level potential to the wiring WWLFY as a non-select signal, turning off the transistor M1 of memory cell MCY and maintaining a voltage corresponding to the image data between the first and second terminals of the capacitance element C1. After turning off the transistor M1, the driver circuit RWDF applies a low-level potential to the wiring RWLF as a non-select signal. As a result, the potential of the first terminal of the capacitive element C1 drops due to capacitive coupling by the capacitive element C1, so that the transistor M2 of the memory cell MCY can be turned off. Note that since the first terminal of the capacitive element C1 is in a floating state, even if the potential of the first terminal of the capacitive element C1 drops, the voltage corresponding to the image data between the first and second terminals of the capacitive element C1 is maintained.

[0533] Furthermore, when reading image data from the memory cell MCY, for example, a high-level potential is first supplied to the line SLY, and a low-level potential is precharged to the line RBLFY. Then, the drive circuit RWDF applies a high-level potential to the line RWLF as a selection signal, causing the capacitive coupling of the capacitive element C1 to increase the potential of the first terminal of the capacitive element C1. At this time, the transistor M2 of the memory cell MCY is turned on, causing a current to flow from the line SLY to the line RBLFY, increasing the potential of the line RBLFY. The potential that the line RBLFY ultimately reaches is determined by the potential of the gate of the transistor M2 of the memory cell MCY, i.e., the potential corresponding to the image data. Then, the potential of the line RBLFY is amplified by the drive circuit RBDF, allowing image data to be read from the memory cell MCY.

[0534] As described above, the memory circuit FMA is provided with the wiring WWLFX as the write word line for the memory cell MCX and the wiring WWLFY as the write word line for the memory cell MCY, so that image data can be written to each of the memory cells MCX and MCY independently.

[0535] On the other hand, the memory cells MCX and MCY share the wiring RWLF that functions as a read word line, so that the memory cells MCX and MCY can simultaneously perform read operations. As described above, the wiring RWLF also functions as a write word line, so that when a write operation or a read operation is performed on one of the memory cells MCX and MCY, a selection signal is sent to the wiring RWLF.

[0536] Therefore, for example, by transmitting a select signal to the wiring WWLFX, a non-select signal to the wiring WWLFY, and a select signal to the wiring RWLF, a write operation is performed in the memory cell MCX and a read operation is performed in the memory cell MCY. Also, for example, by transmitting a non-select signal to the wiring WWLFX, a select signal to the wiring WWLFY, and a select signal to the wiring RWLF, a read operation is performed in the memory cell MCX and a write operation is performed in the memory cell MCY. Also, for example, by transmitting a non-select signal to the wiring WWLFX, a non-select signal to the wiring WWLFY, and a select signal to the wiring RWLF, a read operation is performed in each of the memory cells MCX and MCY.

[0537] 24 is a timing chart showing an example of a write operation and an example of a read operation of each of the memory cells MCX and MCY in the j-th column of the memory cell unit MCAA of the memory circuit FMA in FIG. 23. The timing chart also shows, as an example, an operation example of the memory circuit FMA in steps SR13 and SS2 of the flowchart in FIG. 21. That is, the timing chart shows an operation example of simultaneously reading out image frames held in the memory cells MCX and MCY. The timing chart also shows an operation example of writing to the memory cells MCX or MCY.

[0538] The timing chart shows changes in the potential of the wirings SWLF1X, SWLF1Y, WWLFX[1], WWLFY[1], WWLFX[2], WWLFY[2], WWLFX[M], WWLFY[M], RWLF[1], RWLF[2], RWLF[M], SWLF2X, SWLF2Y, and SWLF3 before time T1, from time T1 to time T14, and after time T14. The timing chart also shows image data transmitted to the nodes NW and NO before time T1, from time T1 to time T14, and after time T14.

[0539] Further, the image data D of the t-1th frame is stored in a plurality of memory cells MCY of the memory cell unit MCAA of the memory circuit FMA. （ｔ−１） [1] to D （ｔ−１） It is assumed that [M] is held.

[0540] Between time T1 and time T7, a high-level potential is applied to the wiring SWLF1X, and a low-level potential is applied to the wiring SWLF1Y. As a result, in the input portion IPTF of the memory circuit FMA, the switch SW1X is turned on and the switch SW1Y is turned off. Also, between time T1 and time T7, a low-level potential is applied to the wiring SWLF2X, a high-level potential is applied to the wiring SWLF2Y, and a low-level potential is applied to the wiring SWLF3. As a result, in the output portion OPTF of the memory circuit FMA, the switch SW2X is turned off, the switch SW2Y is turned on, and the switches SW3X and SW3Y are both turned off.

[0541] In addition, during the period from time T2 to time T6, the image data D of the t-th frame is input from the driving circuit WBDF to the input unit IPTF. （ｔ） [1] to D （ｔ） In the timing chart of FIG. 24, D （ｔ） [1] is input to the input unit IPTF, and D （ｔ） [2] is input to the input unit IPTF, and D （ｔ） [M] is input to the input unit IPTF. Note that between time T4 and time T5, （ｔ） [3] to D （ｔ） [M-1] are sequentially input to the input unit IPTF.

[0542] Between time T2 and time T3, a high-level potential is input to the wiring RWLF[1], i.e., a high-level potential is input to the second terminal of the capacitive element C1 of each of the memory cells MCX[1,j] and MCY[1,j].

[0543] Also, while a high-level potential is input to the wiring RWLF[1], a high-level potential is input to the wiring WWLFX[1]. That is, the high-level potential is applied to the gate of the transistor M1 of the memory cell MCX[1,j], turning the transistor M1 on, and electrical continuity is established between the first terminal of the capacitance element C1, the gate of the transistor M2, and the wiring WBLFX. As a result, a high-level potential is applied to the first terminal of the capacitance element C1 of the memory cell MCX[1,j]. （ｔ） Then, a low-level potential is input to the wiring RWLF[1], a low-level potential is applied to the gate of the transistor M1, and the transistor M1 is turned off. As a result, the first terminal of the capacitance element C1 of the memory cell MCX[1, j] is brought into a floating state, and the memory cell MCX[1, j] is charged with D （ｔ） The data in the jth column of [1] is held.

[0544] Then, by transitioning the potential of the wiring RWLF[1] from a high level potential to a low level potential, the potential of the first terminal of the capacitive element C1 of the memory cell MCX[1,j] drops due to capacitive coupling, which turns off the transistor M2 of the memory cell MCX[1,j], causing a non-conduction state between the wiring SLX and the wiring RBLFX, and preventing image data from being read from the memory cell MCX[1,j].

[0545] Furthermore, from time T2 to time T3, a low-level potential is always input to the wiring WWLFY[1], so that the low-level potential is applied to the gate of the transistor M1 of the memory cell MCY[1,j]. As a result, from time T2 to time T3, the transistor M1 is in an off state, and the first terminal of the capacitive element C1 of the memory cell MCY[1,j] is in a floating state. Here, when a high-level potential is input to the wiring RWLF[1], the potential of the first terminal of the capacitive element C1 of the memory cell MCY[1,j] rises due to capacitive coupling. As a result, the transistor M2 of the memory cell MCY[1,j] is turned on, so that the wiring SLY and the wiring RBLFY are electrically connected, and the D of the t-1-th frame is transferred from the memory cell MCY[1,j] to the wiring RBLFY. （ｔ−１）A potential according to the image data of the jth column of [1] is output.

[0546] Also, D of the t-1th frame output from the memory cell MCY[1, j] （ｔ−１） The potential corresponding to the image data of the j-th column in [1] is amplified by the sense amplifier SAY of the drive circuit RBDF via the wiring RBLFY and output to the output unit OPTF. Note that in the output unit OPTF, the switch SW2X is in the OFF state, the switch SW2Y is in the ON state, the switch SW3X is in the OFF state, and the switch SW3Y is in the OFF state. Therefore, the D （ｔ−１） The image data of the j-th column in [1] is output to the wiring PDL via the node NO and the switching circuit MX.

[0547] As described above, between time T2 and time T3, in the first row of the memory cell unit MCAA, the D of the t-th frame is stored in the memory cell MCX[1,j]. （ｔ） While writing the image data of the j-th column of [1], the D of the t-1-th frame from the memory cell MCY[1,j] （ｔ−１） The image data of the j-th column in [1] can be read out and transmitted to the wiring PDL.

[0548] Between time T3 and time T4, a high-level potential is input to the wiring RWLF[2]. Also, while a high-level potential is input to the wiring RWLF[2], a high-level potential is input to the wiring WWLFX[2]. As a result, the D of the t-th frame is input to the memory cell MCX[2,j], just like the memory cell MCX[1,j] between time T2 and time T3. （ｔ） The image data of the j-th column of [2] is written, and similarly to the memory cell MCY[1, j] between time T2 and time T3, the image data of the D of the t-1-th frame is written from the memory cell MCY[2, j]. （ｔ−１） The image data in the j-th column of [2] is read out.

[0549] Furthermore, from time T5 to time T6, a high-level potential is input to the wiring RWLF[M]. Furthermore, while a high-level potential is input to the wiring RWLF[M], a high-level potential is input to the wiring WWLFX[M]. As a result, the D of the t-th frame is input to the memory cell MCX[M,j], similar to the memory cell MCX[1,j] from time T2 to time T3. （ｔ） The image data of the j-th column of [M] is written, and similarly to the memory cell MCY[1, j] between time T2 and time T3, the D （ｔ−１） The image data in the j-th column of [M] is read out.

[0550] Between time T7 and time T8, for example, the operations of steps SR5 to SR9 described in the flowchart of FIG. 21 are performed. （ｔ−１） [h] and image data D （ｔ） [h] are simultaneously read out and transmitted to the processing circuit SGPR. （ｔ−１） [h] and image data D （ｔ） The operation of simultaneously reading out [h] and [h] and the operation of transmitting them to the processing circuit SGPR will be explained later with reference to the timing chart of FIG.

[0551] Between time T8 and time T14, a low-level potential is applied to the wiring SWLF1X, and a high-level potential is applied to the wiring SWLF1Y. As a result, in the input portion IPTF of the memory circuit FMA, the switch SW1X is turned off and the switch SW1Y is turned on. Also, between time T8 and time T14, a high-level potential is applied to the wiring SWLF2X, a low-level potential is applied to the wiring SWLF2Y, and a low-level potential is applied to the wiring SWLF3. As a result, in the output portion OPTF of the memory circuit FMA, the switch SW2X is turned on, the switch SW2Y is turned off, and the switches SW3X and SW3Y are both turned off.

[0552] Also, during the period from time T9 to time T13, the image data D of the t+1th frame is input from the driving circuit WBDF to the input unit IPTF. （ｔ＋１） [1] to D （ｔ＋１） In the timing chart of FIG. 24, D （ｔ＋１） [1] is input to the input unit IPTF, and D （ｔ＋１） [2] is input to the input unit IPTF, and D （ｔ＋１） [M] is input to the input unit IPTF. Note that between time T11 and time T12, （ｔ＋１） [3] to D （ｔ＋１） [M-1] are sequentially input to the input unit IPTF.

[0553] Between time T9 and time T10, a high-level potential is input to the wiring RWLF[1], i.e., a high-level potential is input to the second terminal of the capacitance element C1 of each of the memory cells MCX[1,j] and MCY[1,j].

[0554] Furthermore, while a high-level potential is input to the wiring RWLF[1], a high-level potential is input to the wiring WWLFY[1]. That is, the high-level potential is applied to the gate of the transistor M1 of the memory cell MCY[1,j], turning the transistor M1 on, and electrical continuity is established between the first terminal of the capacitance element C1, the gate of the transistor M2, and the wiring WBLFY. As a result, at the first terminal of the capacitance element C1 of the memory cell MCY[1,j], （ｔ−１） From the jth column data of [1] D （ｔ＋１） After that, a low-level potential is input to the wiring RWLF[1], a low-level potential is applied to the gate of the transistor M1, and the transistor M1 is turned off. As a result, the first terminal of the capacitor C1 of the memory cell MCY[1, j] is brought into a floating state, and the memory cell MCY[1, j] is charged with D （ｔ＋１） The data in the jth column of [1] is held.

[0555] Then, by transitioning the potential of the wiring RWLF[1] from a high level potential to a low level potential, the potential of the first terminal of the capacitive element C1 of the memory cell MCY[1,j] drops due to capacitive coupling, which turns off the transistor M2 of the memory cell MCY[1,j], causing a non-conduction state between the wiring SLY and the wiring RBLFY, and preventing image data from being read from the memory cell MCY[1,j].

[0556] Furthermore, from time T9 to time T10, a low-level potential is always input to the wiring WWLFX[1], and this low-level potential is applied to the gate of the transistor M1 of the memory cell MCX[1,j]. As a result, from time T9 to time T10, the transistor M1 is in an off state, and the first terminal of the capacitance element C1 of the memory cell MCX[1,j] is in a floating state. Here, when a high-level potential is input to the wiring RWLF[1], the potential of the first terminal of the capacitance element C1 of the memory cell MCX[1,j] rises due to capacitive coupling. As a result, the transistor M2 of the memory cell MCX[1,j] is turned on, and therefore the wiring SLX and the wiring RBLFX are electrically connected, and the D of the t-th frame is transferred from the memory cell MCX[1,j] to the wiring RBLFX. （ｔ） A potential according to the image data of the jth column of [1] is output.

[0557] Also, the D of the t-th frame output from the memory cell MCX[1,j] （ｔ） The potential corresponding to the image data of the j-th column in [1] is amplified by the sense amplifier SAX of the driving circuit RBDF via the wiring RBLFX and output to the output unit OPTF. In the output unit OPTF, the switch SW2X is in the ON state, the switch SW2Y is in the OFF state, the switch SW3X is in the OFF state, and the switch SW3Y is in the OFF state. Therefore, the D （ｔ） The image data of the j-th column in [1] is output to the wiring PDL via the node NO and the switching circuit MX.

[0558] As described above, between time T9 and time T10, in the first row of the memory cell unit MCAA, the D of the t+1th frame is stored in the memory cell MCY[1, j].（ｔ＋１） While writing the image data of the j-th column of [1], the D of the t-th frame from the memory cell MCX[1,j] （ｔ） The image data of the j-th column in [1] can be read out and transmitted to the wiring PDL.

[0559] Between time T10 and time T11, a high-level potential is input to the wiring RWLF[2]. While a high-level potential is being input to the wiring RWLF[2], a high-level potential is input to the wiring WWLFY[2]. As a result, the D of the t+1th frame is input to the memory cell MCY[2,j], similar to the memory cell MCY[1,j] between time T9 and time T10. （ｔ＋１） The image data of the j-th column of [2] is written, and similarly to the memory cell MCX[1, j] between time T9 and time T10, the D of the t-th frame is written from the memory cell MCX[2, j]. （ｔ） The image data in the j-th column of [2] is read out.

[0560] Furthermore, from time T12 to time T13, a high-level potential is input to the wiring RWLF[M]. Furthermore, while a high-level potential is input to the wiring RWLF[M], a high-level potential is input to the wiring WWLFX[M]. As a result, the D of the t+1th frame is input to the memory cell MCY[M,j], similar to the memory cell MCY[1,j] from time T9 to time T10. （ｔ＋１） The image data of the j-th column of [M] is written, and similarly to the memory cell MCX[1, j] between time T9 and time T10, the D of the t-th frame is written from the memory cell MCX[M, j]. （ｔ） The image data in the j-th column of [M] is read out.

[0561] As described above, the memory circuit FMA can perform one of a write operation and a read operation on a plurality of memory cells MCX, and can also perform the other of a write operation and a read operation on a plurality of memory cells MCY.

[0562] Fig. 25 is a timing chart showing an example of the read operation of each of the memory cells MCX and MCY in the j-th column of the memory cell unit MCAA of the memory circuit FMA in Fig. 23. The timing chart also shows, as an example, an operation example of the memory circuit FMA in step SR6 or step SS6 of the flowchart in Fig. 21. That is, the timing chart shows an operation example of simultaneously reading out image frames held in each of the memory cells MCX and MCY.

[0563] The timing chart shows changes in the potential of the wirings SWLF1X, SWLF1Y, WWLFX[1], WWLFY[1], WWLFX[2], WWLFY[2], WWLFX[M], WWLFY[M], RWLF[1], RWLF[2], RWLF[M], SWLF2X, SWLF2Y, and SWLF3 before time T21, from time T21 to time T27, and after time T27. The timing chart also shows image data transmitted to the node NW, the wiring OLX, and the wiring OLY before time T21, from time T21 to time T27, and after time T27.

[0564] Further, the image data D of the t-th frame is stored in a plurality of memory cells MCX of the memory cell unit MCAA of the memory circuit FMA. （ｔ） [1] to D （ｔ） [M] is held in the memory cells MCY of the memory cell unit MCAA of the memory circuit FMA. （ｔ−１） [1] to D （ｔ−１） It is assumed that [M] is held.

[0565] Between time T21 and time T27, a low-level potential is applied to the wirings SWLF1X and SWLF1Y. As a result, in the input portion IPTF of the memory circuit FMA, the switches SW1X and SW1Y are turned off. Also, between time T21 and time T27, a low-level potential is applied to the wirings SWLF2X and SWLF2Y, and a high-level potential is applied to the wiring SWLF3. As a result, in the output portion OPTF of the memory circuit FMA, the switches SW2X and SW2Y are turned off, and the switches SW3X and SW3Y are turned on.

[0566] 25 , a high-level potential is applied to the wiring RWLF[1] to the wiring RWLF[M] sequentially from time T21 to time T27. In the timing chart of FIG. 25 , a high-level potential is applied to the wiring RWLF[1] from time T22 to time T23, a high-level potential is applied to the wiring RWLF[2] from time T23 to time T24, and a high-level potential is applied to the wiring RWLF[M] from time T25 to time T26. In addition, a high-level potential is applied to the wirings RWLF[3] to RWLF[M-1] sequentially from time T24 to time T25.

[0567] Between time T22 and time T23, a high-level potential is input to the wiring RWLF[1]. That is, a high-level potential is input to the second terminal of the capacitance element C1 of each of the memory cells MCX[1,j] and MCY[1,j]. Furthermore, while a high-level potential is input to the wiring RWLF[1], a low-level potential is input to each of the wirings WWLFX[1] and WWLFY[1]. As a result, between time T22 and time T23, the transistors M1 of each of the memory cells MCX[1,j] and MCY[1,j] are in an off state, and the first terminals of the capacitance elements C1 of each of the memory cells MCX[1,j] and MCY[1,j] are in a floating state. Here, the input of a high-level potential to the wiring RWLF[1] increases the potential of the first terminals of the capacitance elements C1 of each of the memory cells MCX[1,j] and MCY[1,j] due to capacitive coupling.

[0568] As a result, the transistor M2 of the memory cell MCX[1, j] is turned on, so that the line SLX and the line RBLFX are electrically connected, and the D （ｔ） A potential corresponding to the image data of the j-th column of the memory cell MCX[1,j] is output. （ｔ） The potential corresponding to the image data of the j-th column in [1] is amplified by the sense amplifier SAX of the driving circuit RBDF via the wiring RBLFX and output to the output unit OPTF. In addition, since the switch SW2X is in the OFF state and the switch SW3X is in the ON state, the potential amplified by the sense amplifier SAX (the D （ｔ） The image data of the j-th column in [1] is output to the wiring OLX.

[0569] Furthermore, since the transistor M2 of the memory cell MCY[1, j] is turned on, the wiring SLY and the wiring RBLFY are electrically connected, and the D （ｔ−１）A potential corresponding to the image data of the j-th column of the memory cell MCY[1,j] is output. （ｔ−１） The potential corresponding to the image data of the j-th column in [1] is amplified by the sense amplifier SAY of the drive circuit RBDF via the wiring RBLFY and output to the output unit OPTF. In addition, since the switch SW2Y is in the OFF state and the switch SW3Y is in the ON state, the potential amplified by the sense amplifier SAY (D （ｔ−１） The image data of the j-th column in [1] is output to the wiring OLY.

[0570] As described above, between time T22 and time T23, in the first row of the memory cell unit MCAA, the D of the t-th frame held in the memory cell MCX[1, j] （ｔ） The image data of the j-th column of [1] and the D of the t-1-th frame stored in the memory cell MCY[1, j] （ｔ−１） The image data of the j-th column in [1] can be simultaneously read out and transmitted to the wiring OLX and the wiring OLY, respectively.

[0571] Between time T23 and time T24, a high-level potential is input to the wiring RWLF[2]. As a result, similar to the memory cells MCX[1,j] and MCY[1,j] between time T22 and time T23, the D （ｔ） The image data of the j-th column of [2] is read out, and the D of the t-1-th frame is read out from the memory cell MCY[2, j]. （ｔ−１） The image data in the j-th column of [2] is read out.

[0572] Furthermore, from time T25 to time T26, a high-level potential is input to the wiring RWLF[M]. As a result, similar to the memory cells MCX[1,j] and MCY[1,j] from time T22 to time T23, the D （ｔ） The image data of the j-th column of [M] is read out, and the D of the t-1-th frame is read out from the memory cell MCY[M, j]. （ｔ−１） The image data in the j-th column of [M] is read out.

[0573] As described above, the memory circuit FMA can simultaneously perform a read operation on the memory cells MCX and MCY located in the same row.

[0574] [Processing Circuit SGPR] Fig. 26 is a block diagram showing an example of the configuration of the processing circuit SGPR. Fig. 26 also shows the memory circuits FMA, FGM, and signal processing circuit PG to show the connection configuration between the processing circuit SGPR and its peripheral circuits.

[0575] The processing circuit SGPR shown in Fig. 26 has, as an example, the same configuration as the processing circuit SGPR shown in Fig. 6. Therefore, the processing circuit SGPR shown in Fig. 26 has a comparison circuit CPA and a logic circuit LGMP, similar to the processing circuit SGPR in Fig. 6. Furthermore, the comparison circuit CPA has, as an example, comparators CPAa[1] to CPAa[N].

[0576] Furthermore, for the configurations of the comparators CPAa[1] to CPAa[N] and the logic circuit LGMP, reference can be made to the description of the comparators CPAa[1] to CPAa[N] and the logic circuit LGMP included in the processing circuit SGPR in Figure 6.

[0577] In the j-th column, the first input terminal of the comparator CPAa[j] is connected to the wiring OLX[j], the second input terminal of the comparator CPAa[j] is connected to the wiring OLY[j], and the output terminal of the comparator CPAa[j] is connected to the j-th input terminal of the logic circuit LGMP.

[0578] The output terminal of the logic circuit LGMP is connected to a wiring WBLG, which will be described later. Note that in Fig. 26, the wiring WBLG is shown as a wiring for transmitting the comparison data C[i] from the processing circuit SGPR to the memory circuit FGM.

[0579] Next, an example of the operation of the processing circuit SGPR will be described. For example, in the memory circuit FMA, image data is simultaneously read from the memory cells MCX and MCY. In this way, the memory circuit FMA receives the D （ｔ）[i], and transmits the image data of the t-1-th frame via wiring OLY[1] to wiring OLY[N]. （ｔ−１） Consider the case where image data [i] is transmitted. In this case, in the processing circuit SGPR, the comparison circuit CPA （ｔ） [i] and D （ｔ−１） [i] is compared with [i]. Then, a logical operation is performed by the logic circuit LGMP based on the comparison results output from each output terminal of the comparison circuit CPA. As a result, the processing circuit SGPR obtains the comparison data C, which is the result of the logical operation of the logic circuit LGMP. （ｔ） [i] is output to the wiring WBLG.

[0580] Furthermore, for example, in the memory circuit FMA, by simultaneously reading image data from the memory cells MCX and MCY, the memory circuit FMA receives the D （ｔ） [i], and transmits the image data of the t+1th frame via wiring OLY[1] to wiring OLY[N]. （ｔ＋１） When the image data [i] is transmitted, the same operation as above is performed, and as a result, the processing circuit SGPR receives the comparison data C （ｔ＋１） [i] is output to the wiring WBLG.

[0581] [Memory Circuit FGM] The block diagram of the memory circuit FGM shown in Figure 26 shows a configuration example that can be applied to the memory circuit FGM included in the processing device PRC of Figure 20. Note that the memory circuit FGM shown in Figure 26 has, as an example, the same configuration as the memory circuit FGM shown in Figure 6. Therefore, for the configuration of the memory circuit FGM in Figure 26, the description of the memory circuit FGM in Figure 6 can be referred to.

[0582] For example, the comparison data C （ｔ） When [i] is transmitted, the drive circuit WWDG applies a high-level potential to the wiring WWLG[i] as a selection signal, thereby storing the comparison data C （ｔ）Thereafter, the driver circuit WWDG applies a low-level potential as a non-selection signal to the wiring WWLG[i], thereby writing the comparison data C to the memory cell MCG[i]. （ｔ） [i] can be held.

[0583] Also, for example, the comparison data C （ｔ） When transmitting the comparison data C[i], the drive circuit RWDG applies a high-level potential to the wiring RWLG[i] as a selection signal, thereby transmitting the comparison data C[i] from the memory cell MCG[i]. （ｔ） A potential corresponding to [i] can be output to the wiring RBLG. At this time, the potential is amplified by the sense amplifier SAG to a level that can be handled by other circuits. After that, by turning on the switch SWG, the comparison data C （ｔ） [i] can be transmitted to the signal processing circuit PG via the wiring FOL.

[0584] [Signal Processing Circuit PG] The signal processing circuit PG shown in Fig. 26 can be, for example, the signal processing circuit PG in Fig. 9A described in embodiment 1. Therefore, for the signal processing circuit PG in Fig. 26, the description of the signal processing circuit PG in Fig. 9A can be referred to.

[0585] For example, the comparison data C （ｔ） [1] to Comparison Data C （ｔ） [M] are sequentially read out and input to a first input terminal of the logic circuit CPB via the wiring FOL, and a clock signal generated by the pulse signal generating circuit PWG based on a signal sent to the wiring PWIL is input to a second input terminal of the logic circuit CPB, whereby the logic circuit CPB outputs the comparison data C （ｔ） [1] to Comparison Data C （ｔ） The driver circuit 102 generates a pulse signal (which can be a control signal sent to the driver circuit GD, for example) that reflects the logic of each of the signals [M], and outputs the pulse signal to the wiring PWCL.

[0586] [Driver Circuit GD] For each of the drive circuits GD included in the drive circuit unit DRA of the display device DSP in Fig. 20, reference can be made to the description of the drive circuit GD of the drive circuit unit DRA of the display device DSP shown in Fig. 1 described in embodiment 1. Therefore, any one of the drive circuits GD shown in Fig. 10A to Fig. 10D can be applied to the drive circuit GD included in the drive circuit unit DRA of the display device DSP in Fig. 20.

[0587] For this reason, the driving circuit GD receives a control signal from the signal processing circuit PG, for example, to generate the comparison data C （ｔ） [1] to Comparison Data C （ｔ） Based on [M], a non-selection signal can be sent to the wiring GL of the row of the pixel array unit PXA where the image data does not change between the t-th frame and the t-1-th frame, and a selection signal can be sent to the wiring GL of the row of the pixel array unit PXA where the image data changes between the t-th frame and the t-1-th frame.

[0588] [Driver Circuit SD] For the driver circuit SD included in the driver circuit unit DRA of the display device DSP in Fig. 20, reference can be made to the description of the driver circuit SD of the driver circuit unit DRA of the display device DSP shown in Fig. 1 described in embodiment 1. Therefore, the driver circuit SD shown in Fig. 12 can be applied to the driver circuit SD included in the driver circuit unit DRA of the display device DSP in Fig. 20.

[0589] For this reason, by receiving a control signal from the signal processing circuit PG, the driver circuit SD can turn off the switches SWS[1] to SWS[N] at the timing of transmitting image data of the t-th frame to the pixel circuits PX arranged in rows in which the image data does not change between the t-th frame and the t-1-th frame. As a result, the outputs from the driver circuit SD to the wirings SL[1] to SL[N] have high impedance, and the image data of the row in the t-th frame output from the digital-analog conversion circuits DAC[1] to DAC[N] is no longer output to the wirings SL[1] to SL[N], thereby reducing the power consumption of the digital-analog conversion circuits DAC[1] to DAC[N].

[0590] As described in this embodiment, by using the display system DSYSB of FIG. 20 , the memory circuit FMA can acquire separate image data from outside the processing device PRC at the same time as reading out image data to be displayed in the pixel array unit PXA of the display device DSP. This reduces the number of operational steps compared to the display system DSYS of FIG. 1 and the display system DSYSA of FIG. 14 . This prevents a reduction in the frame frequency of the display device DSP. Furthermore, the memory circuit FMA can simultaneously read out image data held in a plurality of memory cells MCX and image data held in a plurality of memory cells MCY, allowing the processing circuit SGPR to generate comparison data that is a comparison result of these image data.

[0591] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes.

[0592] Fourth Embodiment In this embodiment, a modification of the display system described in the third embodiment will be described.

[0593] 27 is a block diagram illustrating a configuration example of a display system according to one embodiment of the present invention. In particular, the display system DSYSC illustrated in FIG. 27 is a modified example of the display system DSYSB illustrated in FIG. 20 and differs from the display system DSYSB in that the memory circuit FGM is replaced with a memory circuit FGM1 and a memory circuit FGM2.

[0594] Therefore, in this specification, for the configuration of part of the display system DSYSC in Fig. 27, the description of the display system DSYSB in Fig. 20 can be referred to. Also, in this specification, in the description of the display system DSYSC in Fig. 27, the description of parts that overlap with the content of the display system DSYSB in Fig. 20 may be omitted.

[0595] 27, the pixel array portion PXA included in the display device DSP can be referred to in the description of the pixel array portion PXA in Fig. 1. In addition, the wirings SL[1] to SL[N] and the wirings GL[1] to GL[M] can be referred to in the description of the wirings SL[1] to SL[N] and the wirings GL[1] to GL[M] in Fig. 1.

[0596] For the driver circuit SD and driver circuit GD included in the display device DSP of FIG. 27, the description of the driver circuit SD and driver circuit GD of FIG. 1 can be referred to.

[0597] For the processing circuit SGPR included in the processing device PRC in Fig. 27, the description of the processing circuit SGPR in Fig. 1 can be referred to. Also, for the memory circuit FMA included in the processing device PRC in Fig. 27, the description of the memory circuit FMA in Fig. 20 can be referred to. Also, for the signal processing circuit PG included in the processing device PRC in Fig. 20, the description of the signal processing circuit PG in Fig. 1 can be referred to.

[0598] 27 includes a function of holding the comparison data C[i] transmitted from the processing circuit SGPR, and may be referred to as a flag memory, similar to the memory circuit FGM of the processing circuit PRC in FIG. 1. Each of the memory circuits FGM1 and FGM2 can hold the comparison data C[1] to C[M] for the number of rows in the pixel array unit PXA. Each of the memory circuits FGM1 and FGM2 also has a function of reading out the comparison data C[i] and transmitting it to the signal processing circuit PG.

[0599] Furthermore, it is preferable that the memory circuit FGM1 holds comparison data different from the comparison data held in the memory circuit FGM2. For example, it is preferable that one of the memory circuit FGM1 and the memory circuit FGM2 holds comparison data of the image data of the t-1th frame and the tth frame, and the other of the memory circuit FGM1 and the memory circuit FGM2 holds comparison data of the image data of the tth frame and the t+1th frame.

[0600] The control circuit TC included in the processing device PRC in FIG. 27 has, as an example, a function to control each circuit included in the processing device PRC and each circuit included in the display device DSP. For example, the control circuit TC has a function to send command signals to the drive circuits included in the memory circuit FMA, memory circuit FGM1, and memory circuit FGM2 to perform write operations, read operations, etc. The control circuit TC also has a function to send command signals to the drive circuits SD and drive circuit GD to perform write operations, read operations, etc. The control circuit TC also has, as an example, a function to send command signals to control the on / off switching of switching elements included in the memory circuit FMA, memory circuit FGM1, memory circuit FGM2, and processing circuit SGPR. The control circuit TC also has, as an example, a function to generate clock signals to be supplied to each circuit included in the processing device PRC and each circuit included in the display device DSP.

[0601] In addition, the control circuit TC may have the function of transmitting the above-mentioned clock signal or the like as a synchronization signal to two or more selected circuits from among the circuits included in the processing device PRC and the circuits included in the display device DSP in order to synchronize these two or more selected circuits.

[0602] <Example of Operation of Display System> Next, an example of operation of the display system DSYSC shown in FIG. 27 will be described.

[0603] Fig. 28 is a flowchart showing an example of the operation of the display system DSYSC in Fig. 27. The flowchart in Fig. 28 shows two operations: steps SU1 to SU9 showing an operation (hereinafter referred to as a third operation) of displaying images from the t-1th frame (t is an integer equal to or greater than 3) to the tth frame in the pixel array unit PXA, and steps SV1 to SV7 showing an operation (hereinafter referred to as a fourth operation) of rewriting the image of the tth frame with the image of the t+1th frame.

[0604] 28, it should be noted that the third and fourth operations are not performed separately, and that part of the third operation may overlap with part of the fourth operation in timing. In other words, part of the third operation and part of the fourth operation may be performed simultaneously.

[0605] The memory circuit FMA stores image data D as the t-1th frame image in advance. （ｔ−１） [1] to Image Data D （ｔ−１） In addition, one of the memory circuits FGM1 and FGM2 stores image data D of the t-2th frame in advance. （ｔ−２） [1] to Image Data D （ｔ−２） [M] and the image data D of the t-1th frame （ｔ−１） [1] to Image Data D （ｔ−１） Comparison data C with [M] （ｔ−１） [1] to Comparison Data C （ｔ−１） It is assumed that [M] is held.

[0606] First, steps SU1 to SU9 of the third operation will be described.

[0607] In step SU1, as an example, i, which is a variable of the row number of the pixel array unit PXA, is set to 1. In steps SU1 to SU4, i is a variable that satisfies the range of 1 to M.

[0608] In step SU2, for example, image data D of the i-th row of the t-th frame is input from the outside of the processing device PRC to the memory circuit FMA. （ｔ） Step SU2 also includes an operation of transmitting image data D[i] to the memory circuit FMA. （ｔ） The operation in which [i] is written is also included.

[0609] In step SR2 of the first operation described in the third embodiment, the image data D （ｔ） At the timing when [i] is written, the image data D is written from the memory circuit FMA. （ｔ−１） In step SU2, the image data D[i] is read from the memory circuit FMA. （ｔ−１） [i] is not read out.

[0610] In step SU3, it is determined whether i has reached M. If i has not reached M, the process proceeds from step SU3 to step SU4. If i has reached M, the process proceeds from step SU3 to step SU5.

[0611] Step SU4 includes the operation of adding 1 to i. After adding 1 to i, the process returns to step SU2.

[0612] In step SU5, as an example, h is defined as a variable representing the row number of the pixel array unit PXA. Also, in step SU5, h is set to 1. In steps SU5 to SU9, h is a variable that satisfies the range of 1 to M.

[0613] In step SU6, for example, image data D is read from the memory circuit FMA. （ｔ−１） [h] and image data D （ｔ） [h] are simultaneously read out and sent to the processing circuit SGPR.

[0614] In step SU7, for example, the processing circuit SGPR （ｔ−１） [h] and image data D （ｔ） Also, step SU7 includes an operation of comparing image data D （ｔ−１） [h] and image data D （ｔ） If [h] matches, the processing circuit SGPR outputs the comparison data C containing the logic of "0". （ｔ） Step SU7 also includes an operation of transmitting image data D （ｔ−１） [h] and image data D （ｔ） If [h] do not match, the processing circuit SGPR outputs the comparison data C （ｔ） The operation includes transmitting [h] to the other of the memory circuits FGM1 and FGM2.

[0615] In step SU7, for example, the comparison data C is stored in the other of the memory circuits FGM1 and FGM2. （ｔ） This also includes the operation of writing [h].

[0616] In step SU8, it is determined whether i has reached M. If i has not reached M, the process proceeds from step SU8 to step SU9. If i has reached M, the third operation ends.

[0617] Step SU9 includes the operation of adding 1 to h. After adding 1 to h, the process returns to step SU6.

[0618] Next, steps SV1 to SV7 of the fourth operation will be described.

[0619] It is preferable that steps SV1 to SV7 are performed during steps SU5 to SU9 of the third operation.

[0620] In step SV1, as an example, g, which is a variable of the row number of the pixel array unit PXA, is set to 1. Note that in steps SV1 to SV7, g is a variable that satisfies the range of 1 to M.

[0621] In particular, it is preferable that step SV1 be performed simultaneously with step SU5 of the third operation described above. Alternatively, step SV1 and step SU5 may be the same operation. For example, the operations may be performed by setting the variable g, which is the row number of the pixel array unit PXA used in steps SV2 to SV7, to the same value as the variable h, which is the row number of the pixel array unit PXA used in steps SU6 to SU9.

[0622] Furthermore, by treating the variable g handled in steps SV2 to SV7 and the variable h handled in steps SU6 to SU9 as the same value, the rows of the pixel array unit PXA handled in the operations of steps SV2 to SV7 can be aligned with the rows of the pixel array unit PXA handled in the operations of steps SU6 to SU9.

[0623] In step SV2, as an example, image data D （ｔ−１） [g] is read and sent to the driver circuit SD.

[0624] In particular, it is preferable that step SV2 be performed simultaneously with step SU6 of the third operation described above. （ｔ） Image data D read simultaneously with [g] (g=h) （ｔ−１） Preferably, the device operates to transmit [g] to the driver circuit SD as well as to the processing circuit SGPR.

[0625] In step SV3, for example, comparison data C is read from one of the memory circuits FGM1 and FGM2. （ｔ−１） The operation includes reading out [g] (g=h) and sending it to the signal processing circuit PG.

[0626] In step SV4, for example, a pulse signal whose logic is "1" and comparison data C are generated in the signal processing circuit PG. （ｔ−１） A logical operation is performed with [g] to obtain the comparison data C （ｔ−１） Step SV4 includes an operation of generating a control signal including information [g]. Step SV4 also includes, as an example, an operation of transmitting the control signal to the drive circuit GD and the drive circuit SD.

[0627] Step SV5 includes an operation in which the drive circuit GD performs a logical operation on the selection signal (logic "1") sent to the gth row of the pixel array unit PXA and the control signal generated in step SV3. （ｔ−１） When the logic of [g] is "0", the selection signal is converted into a non-selection signal (logic "0") as a result of the logical operation and is sent to the wiring GL[g]. （ｔ−１） When the logic of [g] is "1", the selection signal is not converted into a non-selection signal as a result of the logical operation, and a signal with a logic of "1" is sent to the wiring GL[g] as is. Note that, at this time, it is preferable to regard the non-selection signal (logic "0") as a signal with a low level potential, and the selection signal (logic "1") as a signal with a high level potential.

[0628] In step SV5, the drive circuit SD performs an operation of determining whether or not to make the output of the drive circuit SD high impedance in response to the control signal generated by the signal processing circuit PG. （ｔ−１） When the logic of [g] is "0", the driving circuit SD makes its output high impedance, （ｔ−１） [g] is not output. （ｔ−１） When the logic of [g] is "1", the driving circuit SD （ｔ−１） [g] is output.

[0629] It is preferable that step SV5 be performed before step SU7 of the third operation is completed.

[0630] In step SV6, it is determined whether g has reached M. If g has not reached M, the process moves from step SV6 to step SV7. If g has reached M, the fourth operation ends.

[0631] Note that step SV6 can be made the same operation as step SU8 of the third operation by setting the variables g and h to the same value.

[0632] Step SV7 includes the operation of adding 1 to g. After adding 1 to g, the process moves to step SV2 again.

[0633] Similarly, step SV7 can be made the same as step SU9 of the third operation by setting the variables g and h to the same value.

[0634] By operating the display system DSYSC of FIG. 27 in the operation method shown in the flowchart of FIG. 28, the image data D is stored in the processing circuit SGPR in the memory circuit FMA of the processing device PRC. （ｔ−１） [h] and image data D （ｔ） At the timing of transmitting [h], image data D （ｔ−１） [h] can also be transmitted to the drive circuit SD. In addition, since the display system DSYSC has the memory circuits FGM1 and FGM2, comparison data C of the image data of the t-1th frame and the tth frame can be stored in the other of the memory circuits FGM1 and FGM2. （ｔ） [1] to Comparison Data C （ｔ） While [M] is being written, comparison data C of the image data of the t-2th frame and the t-1th frame, which are held in one of the memory circuits FGM1 and FGM2, （ｔ−１） [1] to Comparison Data C （ｔ−１） [M] can be read out and transmitted to the signal processing circuit PG. The other of the memory circuits FGM1 and FGM2 performs the write operation of the comparison data, and one of the memory circuits FGM1 and FGM2 performs the read operation of the comparison data, thereby enabling the display system DSYSC to operate efficiently. This also makes it possible to prevent a decrease in the frame frequency of the display device DSP.

[0635] <Configuration Example of Each Circuit in Display System> Next, a configuration example of each circuit included in the display system DSYSC shown in FIG. 27 will be described.

[0636] [Memory Circuit FMA] For the memory circuit FMA shown in Fig. 27, for example, a circuit applicable to the memory circuit FMA of the display system DSYSB described in embodiment 3 can be used. Specifically, the memory circuits FMA shown in Fig. 22 and Fig. 23 can be applied to the memory circuit FMA shown in Fig. 27. Therefore, for the memory circuit FMA in Fig. 27, the description of the memory circuit FMA shown in Fig. 22 or Fig. 23 can be referred to.

[0637] [Processing Circuit SGPR] Fig. 29 is a block diagram showing a configuration example of the processing circuit SGPR. Fig. 29 also shows memory circuits FMA, FGM1, and FGM2 to explain the connection configuration between the processing circuit SGPR and its peripheral circuits.

[0638] The processing circuit SGPR shown in Fig. 29 includes, as an example, a comparison circuit CPA and a logic circuit LGMP, similar to the processing circuit SGPR shown in Fig. 6. The processing circuit SGPR also includes a switching circuit SWCP.

[0639] The comparator circuit CPA includes, for example, comparators CPAa[1] to CPAa[N]. Note that for the configurations of the comparators CPAa[1] to CPAa[N] and the logic circuit LGMP, the description of the comparators CPAa[1] to CPAa[N] and the logic circuit LGMP included in the processing circuit SGPR in FIG. 6 can be referred to.

[0640] The switching circuit SWCP has a switch SWP1 and a switch SWP2.

[0641] For the switches SWP1 and SWP2, for example, switches applicable to the switches SW1A or SW1B of the memory circuit LM1 shown in Fig. 3 can be used. Therefore, for the switches SWP1 and SWP2, unless otherwise specified, the description of the switches SW1A or SW1B of the memory circuit LM1 can be referred to.

[0642] In the j-th column, a first input terminal of a comparator CPAa[j] (not shown) is connected to a wiring OLX[j] (not shown), a second input terminal of the comparator CPAa[j] is connected to a wiring OLY[j] (not shown), and an output terminal of the comparator CPAa[j] is connected to the j-th input terminal of the logic circuit LGMP.

[0643] The output terminal of the logic circuit LGMP is connected to a first terminal of a switch SWP1 and a first terminal of a switch SWP2. The second terminal of the switch SWP1 is connected to a memory circuit FGM1 via a wiring WBLG1, and the second terminal of the switch SWP2 is connected to a memory circuit FGM2 via a wiring WBLG2. The control terminal of the switch SWP1 is connected to a wiring SWLP1, and the control terminal of the switch SWP2 is connected to a wiring SWLP2.

[0644] The wiring SWLP1 functions as a wiring for switching the on state and the off state of the switch SWP1 included in the switching circuit SWCP. For this reason, for example, a high-level potential or a low-level potential is supplied to the wiring SWLP1 as a signal for the switching.

[0645] Similarly, the wiring SWLP2 functions as a wiring for switching the on state and the off state of the switch SWP2 included in the switching circuit SWCP. For this reason, for example, a high-level potential or a low-level potential is supplied to the wiring SWLP2 as a signal for the switching.

[0646] Next, an example of the operation of the processing circuit SGPR will be described. For example, in the memory circuit FMA, image data is simultaneously read from the memory cells MCX and MCY. In this way, the memory circuit FMA receives the D （ｔ） [i], and transmits the image data of the t-1-th frame via wiring OLY[1] to wiring OLY[N]. （ｔ−１） Consider the case where image data [i] is transmitted. In this case, in the processing circuit SGPR, the comparison circuit CPA （ｔ） [i] and D （ｔ−１）[i] is compared with [i]. Then, based on the comparison results output from each output terminal of the comparison circuit CPA, a logical operation is performed by the logic circuit LGMP. As a result, the processing circuit SGPR outputs the comparison data C, which is the result of the logical operation of the logic circuit LGMP. （ｔ） [i] is output.

[0647] Furthermore, for example, in the memory circuit FMA, by simultaneously reading image data from the memory cells MCX and MCY, the memory circuit FMA receives the D （ｔ） [i], and transmits the image data of the t+1th frame via wiring OLY[1] to wiring OLY[N]. （ｔ＋１） When the image data [i] is transmitted, the same operation as above is performed, and as a result, the processing circuit SGPR outputs the comparison data C （ｔ＋１） [i] is output.

[0648] Furthermore, the comparison data C output from the logic circuit LGMP （ｔ） [i] is, for example, transmitted to one of the memory circuits FGM1 and FGM2, and is also the comparison data C output from the logic circuit LGMP. （ｔ＋１） [i] is transmitted to the other of the memory circuits FGM1 and FGM2, for example. （ｔ） [i] or comparison data C （ｔ＋１） For example, when transmitting [i] to the memory circuit FGM1, it is preferable to apply a high-level potential to the wiring SWLP1 and a low-level potential to the wiring SWLP2 to turn on the switch SWP1 and turn off the switch SWP2. （ｔ） [i] or comparison data C （ｔ＋１） For example, when transmitting [i] to the memory circuit FGM2, it is preferable to apply a low-level potential to the wiring SWLP1 and a high-level potential to the wiring SWLP2 to turn off the switch SWP1 and turn on the switch SWP2.

[0649] [Memory Circuit FGM1 and Memory Circuit FGM2] The block diagram of the memory circuit FGM1 and the memory circuit FGM2 shown in Fig. 30 shows a configuration example that can be applied to the memory circuit FGM1 and the memory circuit FGM2 shown in Fig. 27. Note that Fig. 30 also shows a signal processing circuit PG in order to explain the connection configuration between the memory circuit FGM1 and the memory circuit FGM2 and their peripheral circuits.

[0650] 30 has the same circuit configuration as the memory circuit FGM shown in FIG. 26 described in Embodiment 3. That is, the circuit configuration of the memory circuit FGM shown in FIG. 26 can be applied to each of the memory circuit FGM1 and the memory circuit FGM2 shown in FIG.

[0651] 30, the memory circuit FGM1 includes, for example, a memory cell unit MCAG1, a driver circuit WWDG1, a driver circuit RWDG1, a sense amplifier SAG1, and a switch SWG1. The memory cell unit MCAG1 includes memory cells MCG1[1] to MCG1[M]. The memory circuit FGM2 includes, for example, a memory cell unit MCAG2, a driver circuit WWDG2, a driver circuit RWDG2, a sense amplifier SAG2, and a switch SWG2. The memory cell unit MCAG2 includes memory cells MCG2[1] to MCG2[M].

[0652] For each of the memory cell units MCAG1 and MCAG2, refer to the description of the memory cell unit MCAG in the memory circuit FGM of Figure 26; for each of the drive circuits WWDG1 and WWDG2, refer to the description of the drive circuit WWDG in the memory circuit FGM of Figure 26; for each of the drive circuits RWDG1 and RWDG2, refer to the description of the drive circuit RWDG in the memory circuit FGM of Figure 26; for each of the sense amplifiers SAG1 and SAG2, refer to the description of the sense amplifier SAG in the memory circuit FGM of Figure 26; and for the switches SWG1 and SWG2, refer to the description of the switches SWG in the memory circuit FGM of Figure 26.

[0653] Furthermore, for the wiring WWLG1 extending in the row direction of the memory cell unit MCAG1 and the wiring WWLG2 extending in the row direction of the memory cell unit MCAG2, the description of the wiring WWLG in the memory circuit FGM in Fig. 26 can be referred to. For the wiring RWLG1 extending in the row direction of the memory cell unit MCAG1 and the wiring RWLG2 extending in the row direction of the memory cell unit MCAG2, the description of the wiring RWLG in the memory circuit FGM in Fig. 26 can be referred to. For the wiring WBLG1 extending in the column direction of the memory cell unit MCAG1 and the wiring WBLG2 extending in the column direction of the memory cell unit MCAG2, the description of the wiring WBLG in the memory circuit FGM in Fig. 26 can be referred to. For the wiring RBLG1 extending in the column direction of the memory cell unit MCAG1 and the wiring RBLG2 extending in the column direction of the memory cell unit MCAG2, the description of the wiring RBLG in the memory circuit FGM in Fig. 26 can be referred to. For the wiring SWLG1 and wiring SWLG2 shown in Fig. 30, the description of the wiring SWLG in the memory circuit FGM in Fig. 26 can be referred to.

[0654] A first terminal of the switch SWG1 is connected to the sense amplifier SAG1, a second terminal of the switch SWG1 is connected to the signal processing circuit PG via the wiring FOL, and a control terminal of the switch SWG1 is connected to the wiring SWLG1. A first terminal of the switch SWG2 is connected to the sense amplifier SAG2, a second terminal of the switch SWG2 is connected to the signal processing circuit PG via the wiring FOL, and a control terminal of the switch SWG2 is connected to the wiring SWLG2.

[0655] In the above configuration, by turning on one of the switches SWG1 and SWG2 and turning off the other, one of the memory circuits FGM1 and FGM2 can be selected, and the comparison data C[1] to C[M] stored in one of the memory circuits FGM1 and FGM2 can be transmitted to the signal processing circuit PG.

[0656] During the above operation, the other of the storage circuits FGM1 and FGM2 can obtain comparison data from the processing circuit SGPR and write it into the other of the storage circuits FGM1 and FGM2.

[0657] Therefore, by configuring the memory circuits FGM1 and FGM2 shown in FIG. 30, step SU6 of the third operation and step SV3 of the fourth operation described with reference to FIG. 28 can be executed simultaneously.

[0658] 27 and 30 may be integrated into one memory circuit. For example, the memory circuits FGM1 and FGM2 may be integrated into one memory circuit, which is the memory circuit FGM illustrated in FIG.

[0659] The memory circuit FGM in Figure 31 is configured by combining memory cells MCG1[1] to MCG1[M] and memory cells MCG2[1] to MCG2[M] into a memory cell unit MCAG, and combining driver circuits RWDG1 and RWDG2 into a driver circuit RWDG.

[0660] Note that, since the drive circuits RWDG1 and RWDG2 are combined into the drive circuit RWDG, the wirings RWLG1 and RWLG2 in the same row are combined into the wiring RWLG. For example, in the i-th row, the wiring RWLG[i] is connected to the memory cell MCG1[i] and the memory cell MCG2[i].

[0661] From the above, the configuration of the memory cell section MCAG, drive circuit WWDG1, drive circuit WWDG2, drive circuit RWDG, sense amplifier SAG1, and sense amplifier SAG2 of the memory circuit FGM shown in Figure 31 can be considered as the configuration of one column of the memory cell section MCAA, drive circuit WWDFX, drive circuit WWDFY, drive circuit RWDF, sense amplifier SAX, and sense amplifier SAY of the memory circuit FMA shown in Figures 22 and 23.

[0662] In other words, it can be said that a part of the memory circuit FGM shown in Fig. 31 has a circuit configuration in which a part of the memory circuit FMA shown in Fig. 22 and Fig. 23 is applied. Therefore, like the memory circuit FMA shown in Fig. 22 and Fig. 23, the memory circuit FGM in Fig. 31 can perform a write operation on one of the memory cells MCG1 and MCG2, and simultaneously perform a read operation on the other of the memory cells MCG1 and MCG2.

[0663] Therefore, the memory circuit FGM shown in Figure 31, like the memory circuit FGM1 and memory circuit FGM2 of Figure 30, can simultaneously execute step SU6 of the third operation described in Figure 28 and step SV3 of the fourth operation.

[0664] Furthermore, in the memory circuit FGM of FIG. 31, the driver circuits RWDG1 and RWDG2 are integrated into one driver circuit RWDG, and therefore the circuit area can be reduced compared to the memory circuits FGM1 and FGM2 of FIG.

[0665] As described in this embodiment, by using the display system DSYSC of FIG. 27 , it is possible to read out, from the memory circuit FMA, image data to be displayed in the pixel array unit PXA of the display device DSP, in accordance with the timing at which the two image data are read out. Furthermore, at this time, comparison data of the two image data is stored in one of the memory circuits FGM1 and FGM2, and the comparison data is read out from the other of the memory circuits FGM1 and FGM2 to generate a selection signal or non-selection signal to be transmitted to the pixel array unit PXA of the display device DSP. Furthermore, the display system DSYSC of FIG. 27 can reduce the number of operation steps compared to the display system DSYS of FIG. 1 and the display system DSYSA of FIG. 14 . This makes it possible to prevent a reduction in the frame frequency of the display device DSP.

[0666] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes.

[0667] Embodiment 5 In this embodiment, a memory cell included in each of the memory circuits described in Embodiments 1 to 4 will be described.

[0668] 32A is a circuit diagram showing a configuration example of a memory cell having two transistors and one capacitance element (sometimes referred to as a 2Tr1C type memory cell). The memory cell MC shown in FIG. 32A can be applied to, for example, a memory cell MC1 included in memory circuit LM1, a memory cell MC2 included in memory circuit LM2, a memory cell MCF included in each of memory circuits FM, FM1, and FM2, and a memory cell MCG included in memory circuit FGM.

[0669] The memory cell MC in FIG. 32A includes, as an example, a transistor M1, a transistor M2, and a capacitance element C1.

[0670] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element C1 and a gate of the transistor M2. A second terminal of the transistor M1 is connected to a wiring WBL, and a gate of the transistor M1 is connected to a wiring WWL. A second terminal of the capacitance element C1 is connected to a wiring RWL. A first terminal of the transistor M2 is connected to a wiring SL, and a second terminal of the transistor M2 is connected to a wiring RBL.

[0671] 32A, transistors M1 and M2 are illustrated as n-channel transistors, but one or both of transistors M1 and M2 may be p-channel transistors. Furthermore, n-channel transistors illustrated in this specification, including the memory cell MC of FIG. 32A, may be replaced with p-channel transistors. Conversely, p-channel transistors illustrated in this specification may be replaced with n-channel transistors.

[0672] 32A can be a Si transistor containing silicon in a channel formation region. Silicon can be, for example, amorphous silicon, microcrystalline silicon, polycrystalline silicon, or single crystal silicon. One or both of the transistors M1 and M2 can be an OS transistor. OS transistors are described in detail in this embodiment and Embodiment 7. Examples of transistors other than OS transistors and Si transistors include a transistor containing germanium or the like in a channel formation region, a transistor containing a compound semiconductor such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium in a channel formation region, a transistor containing a carbon nanotube in a channel formation region, or a transistor containing an organic semiconductor in a channel formation region.

[0673] In particular, in an OS transistor, the metal oxide contained in the channel formation region is preferably an oxide containing one or more selected from the group consisting of indium, an element M (examples of the element M include aluminum, gallium, yttrium, tin, copper, vanadium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and antimony), and zinc. Furthermore, the off-state current of an OS transistor containing the metal oxide in the channel formation region is preferably 10 aA (1×10) per 1 μm of channel width. −１７ A) or less, preferably 1 aA (1×10 −１８ A) or less, and more preferably 10 zA (1×10 −２０ A) or less, more preferably 1zA (1×10 −２１ A) or less, more preferably 100 yA (1×10 −２２ A) or less. Furthermore, since the carrier concentration of the metal oxide in the OS transistor is low, the off-state current of the OS transistor remains low even when the temperature of the OS transistor changes. For example, even when the temperature of the OS transistor is 150° C., the off-state current of the OS transistor can be 100 zA per 1 μm of channel width.

[0674] When an OS transistor is used as the transistor M1, a memory circuit including the memory cell MC illus...

Claims

A first line memory, a second line memory, a frame memory, a processing circuit, and a storage circuit, the first line memory has a function of acquiring data of a first row of the first image data and storing the data of the first row; the frame memory has a function of storing second image data; the second line memory has a function of acquiring data of a second row of the second image data read from the frame memory and holding the data of the second row; the processing circuit has a function of comparing the first row data read from the first line memory with the second row data read from the second line memory, and outputting comparison data including a comparison result; the first line memory has a function of acquiring the comparison data from the processing circuit, and outputting the data of the first row to the frame memory when the comparison data includes the comparison result that the data of the first row and the data of the second row do not match; the frame memory has a function of rewriting the data of the second row held therein with the data of the first row transmitted from the first line memory; The memory circuit has a function of acquiring the comparison data from the processing circuit and storing the comparison data. Processing unit. 　 In claim 1, the processing circuit includes N exclusive NOR circuits (N is an integer equal to or greater than 1) and a NAND circuit including N input terminals; one of the N exclusive NOR circuits has a function of performing a first logical operation using a value of a j-th column (j is an integer between 1 and N) of the first row data read from the first line memory and a value of a j-th column of the second row data read from the second line memory, and outputting a result of the first logical operation; the NAND circuit has a function of acquiring N results of the first logical operation from the N input terminals, respectively, and performing a second logical operation using the N results of the first logical operation to generate the comparison data. Processing unit. 　 A display device and the processing device according to claim 1, the display device includes a first drive circuit, a second drive circuit, and a pixel circuit; The processing device includes a signal processing circuit, the signal processing circuit has a function of acquiring the comparison data read from the storage circuit and generating a control signal using the comparison data; the first drive circuit has a function of performing a third logical operation using the control signal transmitted from the signal processing circuit and a selection signal for selecting the pixel circuit, and transmitting a result of the third logical operation to the pixel circuit; the second driving circuit has a function of determining whether or not to transmit the data of the first row or the data of the second row to the pixel circuit in response to the control signal transmitted from the signal processing circuit. Display system. 　 In claim 3, the first driving circuit includes a decoder and a logical AND circuit; the decoder has a function of generating the selection signal and transmitting the selection signal to a first input terminal of the AND circuit; the signal processing circuit has a function of transmitting the control signal to a second input terminal of the AND circuit; the logical product circuit performs the third logical operation using the control signal and the selection signal, and outputs a result of the third logical operation. Display system. 　 In claim 3, the second drive circuit includes a holding circuit, a digital-to-analog conversion circuit, and a switch; an output terminal of the holding circuit is electrically connected to an input terminal of the digital-to-analog conversion circuit; a first terminal of the switch is electrically connected to an output terminal of the digital-to-analog conversion circuit; A second terminal of the switch is electrically connected to the pixel circuit, A control terminal of the switch is electrically connected to a wiring through which the control signal is transmitted, the frame memory has a function of transmitting the first row data or the second row data to an input terminal of the holding circuit; Display system. 　 A processing device and a display device, the processing device includes a first line memory, a second line memory, a first frame memory, a second frame memory, a processing circuit, and a storage circuit; the first line memory has a function of acquiring data of a first row of the first image data and storing the data of the first row; the first frame memory has a function of acquiring the data of the first row read out from the first line memory and holding the data of the first row; the second frame memory has a function of holding second image data and a function of reading out data of a second row of the second image data and transmitting the data to the second line memory and the display device; the second line memory has a function of acquiring the data of the second row read out from the second frame memory and holding the data of the second row; the processing circuit has a function of comparing the first row data read from the first line memory with the second row data read from the second line memory, and outputting comparison data including a comparison result; The memory circuit has a function of acquiring the comparison data from the processing circuit and storing the comparison data. Display system. 　 In claim 6, the processing circuit includes N exclusive NOR circuits (N is an integer equal to or greater than 1) and a NAND circuit including N input terminals; one of the N exclusive NOR circuits has a function of performing a first logical operation using a value of a j-th column (j is an integer between 1 and N) of the first row data read from the first line memory and a value of a j-th column of the second row data read from the second line memory, and outputting a result of the first logical operation; the NAND circuit has a function of performing a second logical operation using the N results of the first logical operations from the N input terminals, respectively, to generate the comparison data. Display system. 　 In claim 6, the display device includes a first drive circuit, a second drive circuit, and a pixel circuit; The processing device includes a signal processing circuit, the signal processing circuit has a function of acquiring the comparison data read from the storage circuit and generating a control signal using the comparison data; the first drive circuit has a function of performing a third logical operation using the control signal transmitted from the signal processing circuit and a selection signal for selecting the pixel circuit, and transmitting a result of the third logical operation to the pixel circuit; the second driving circuit has a function of determining whether or not to transmit the data of the first row or the data of the second row to the pixel circuit in response to the control signal transmitted from the signal processing circuit. Display system. 　 In claim 8, the first driving circuit includes a decoder and a logical AND circuit; the decoder has a function of generating the selection signal and transmitting the selection signal to a first input terminal of the AND circuit; the signal processing circuit has a function of transmitting the control signal to a second input terminal of the AND circuit; the logical product circuit performs the third logical operation using the control signal and the selection signal, and outputs a result of the third logical operation. Display system. 　 In claim 8, the second drive circuit includes a holding circuit, a digital-to-analog conversion circuit, and a switch; an output terminal of the holding circuit is electrically connected to an input terminal of the digital-to-analog conversion circuit; a first terminal of the switch is electrically connected to an output terminal of the digital-to-analog conversion circuit; a second terminal of the switch electrically connected to the pixel circuit; A control terminal of the switch is electrically connected to a wiring through which the control signal is transmitted, the first frame memory has a function of transmitting the data of the first row or the data of the second row to an input terminal of the holding circuit; Display system. 　 A frame memory, a storage circuit, and a processing circuit, the frame memory includes a first memory cell and a second memory cell; The frame memory includes: A function of overlapping a write operation on one of the first memory cell and the second memory cell and a read operation on the other of the first memory cell and the second memory cell; a function of overlapping a read operation in the first memory cell and a read operation in the second memory cell; the processing circuit has a function of comparing first image data read from the first memory cell with second image data read from the second memory cell, and outputting comparison data including a comparison result; The memory circuit has a function of acquiring the comparison data from the processing circuit and storing the comparison data. Processing unit. 　 In claim 11, the frame memory includes a first selection circuit, a second selection circuit, and a third selection circuit; each of the first memory cell and the second memory cell includes a first transistor, a second transistor, and a capacitive element; In each of the first memory cell and the second memory cell, one of a source and a drain of the first transistor is electrically connected to one of a pair of terminals of the capacitive element and a gate of the second transistor; the first selection circuit is electrically connected to a gate of the first transistor of the first memory cell; the second selection circuit is electrically connected to the gate of the first transistor of the second memory cell; the third selection circuit is electrically connected to the other of the pair of terminals of the capacitive element of the first memory cell and the other of the pair of terminals of the capacitive element of the second memory cell; Processing unit. 　 In claim 12, the processing circuit includes N exclusive NOR circuits (N is an integer equal to or greater than 1) and a NAND circuit including N input terminals; one of the N exclusive NOR circuits has a function of performing a first logical operation using a value of a j-th column (j is an integer between 1 and N) of the first image data read from the first memory cell and a value of a j-th column of the second image data read from the second memory cell, and outputting a result of the first logical operation; the NAND circuit has a function of acquiring N results of the first logical operation from the N input terminals, respectively, and performing a second logical operation using the N results of the first logical operation to generate the comparison data. Processing unit. 　 A display device and a processing device according to claim 11, the display device includes a first drive circuit, a second drive circuit, and a pixel circuit; The processing device includes a signal processing circuit, the signal processing circuit has a function of acquiring the comparison data read from the storage circuit and generating a control signal using the comparison data; the first drive circuit has a function of performing a third logical operation using the control signal transmitted from the signal processing circuit and a selection signal for selecting the pixel circuit, and transmitting a result of the third logical operation to the pixel circuit; the frame memory has a function of reading out the first image data from the first memory cell and transmitting the first image data to the second driving circuit while the second image data held in the second memory cell is being rewritten with third image data; the second driving circuit has a function of determining whether or not to transmit the first image data to the pixel circuit in response to the control signal transmitted from the signal processing circuit; Display system. 　 In claim 14, the first driving circuit includes a decoder and a logical AND circuit; the decoder has a function of generating the selection signal and transmitting the selection signal to a first input terminal of the AND circuit; the signal processing circuit has a function of transmitting the control signal to a second input terminal of the AND circuit; the logical product circuit has a function of performing the third logical operation using the control signal and the selection signal, and outputting a result of the third logical operation. Display system. 　 In claim 14, the second drive circuit includes a holding circuit, a digital-to-analog conversion circuit, and a switch; an output terminal of the holding circuit is electrically connected to an input terminal of the digital-to-analog conversion circuit; a first terminal of the switch is electrically connected to an output terminal of the digital-to-analog conversion circuit; a second terminal of the switch electrically connected to the pixel circuit; A control terminal of the switch is electrically connected to a wiring through which the control signal is transmitted, the frame memory has a function of transmitting the first image data to an input terminal of the holding circuit; Display system. The image processing device includes a frame memory, a first storage circuit, a second storage circuit, and a processing circuit, the frame memory includes a first memory cell and a second memory cell; The frame memory includes: A function of overlapping a write operation on one of the first memory cell and the second memory cell and a read operation on the other of the first memory cell and the second memory cell; a function of overlapping a read operation in the first memory cell and a read operation in the second memory cell; the processing circuit has a function of comparing first image data read from the first memory cell with second image data read from the second memory cell, and outputting first comparison data including a comparison result; one of the first storage circuit and the second storage circuit has a function of acquiring the first comparison data from the processing circuit and storing the first comparison data; Processing unit. 　 In claim 17, the frame memory includes a first selection circuit, a second selection circuit, and a third selection circuit; each of the first memory cell and the second memory cell includes a first transistor, a second transistor, and a capacitive element; In each of the first memory cell and the second memory cell, one of a source and a drain of the first transistor is electrically connected to one of a pair of terminals of the capacitive element and a gate of the second transistor; the first selection circuit is electrically connected to a gate of the first transistor of the first memory cell; the second selection circuit is electrically connected to the gate of the first transistor of the second memory cell; the third selection circuit is electrically connected to the other of the pair of terminals of the capacitive element of the first memory cell and the other of the pair of terminals of the capacitive element of the second memory cell; Processing unit. 　 In claim 18, the processing circuit includes N exclusive NOR circuits (N is an integer equal to or greater than 1) and a NAND circuit including N input terminals; one of the N exclusive NOR circuits has a function of performing a first logical operation using a value of a j-th column (j is an integer between 1 and N) of the first image data read from the first memory cell and a value of a j-th column of the second image data read from the second memory cell, and outputting a result of the first logical operation; the NAND circuit has a function of acquiring N results of the first logical operation from the N input terminals, respectively, and performing a second logical operation using the N results of the first logical operation to generate the first comparison data. Processing unit. 　 A display device and a processing device according to claim 17, the display device includes a first drive circuit, a second drive circuit, and a pixel circuit; The processing device includes a signal processing circuit, the signal processing circuit has a function of acquiring the first comparison data read from one of the first storage circuit and the second storage circuit, and generating a control signal using the first comparison data; the first drive circuit has a function of performing a third logical operation using the control signal transmitted from the signal processing circuit and a selection signal for selecting the pixel circuit, and transmitting a result of the third logical operation to the pixel circuit; the frame memory has a function of reading the first image data from the first memory cell while writing third image data to the second memory cell, and transmitting the first image data to the second driving circuit; the second driving circuit has a function of determining whether or not to transmit the first image data to the pixel circuit in response to the control signal transmitted from the signal processing circuit; Display system. 　 In claim 20, the processing circuit has a function of comparing the first image data read from the first memory cell with the third image data read from the second memory cell, and outputting second comparison data including a comparison result; the other of the first storage circuit and the second storage circuit has a function of acquiring the second comparison data from the processing circuit and storing the second comparison data. Display system.

22. In claim 21, the first driving circuit includes a decoder and a logical AND circuit; the decoder has a function of generating the selection signal and transmitting the selection signal to a first input terminal of the AND circuit; the signal processing circuit has a function of transmitting the control signal to a second input terminal of the AND circuit; the logical product circuit performs the third logical operation using the control signal and the selection signal, and outputs a result of the third logical operation. Display system.

22. In claim 21, the second drive circuit includes a holding circuit, a digital-to-analog conversion circuit, and a switch; an output terminal of the holding circuit is electrically connected to an input terminal of the digital-to-analog conversion circuit; a first terminal of the switch is electrically connected to an output terminal of the digital-to-analog conversion circuit; a second terminal of the switch electrically connected to the pixel circuit; A control terminal of the switch is electrically connected to a wiring through which the control signal is transmitted, the frame memory has a function of transmitting the first image data to an input terminal of the holding circuit; Display system.

Images