Chip packaging structure and preparation method therefor, and storage system and electronic device

Abstract

The present disclosure relates to the technical field of semiconductor chips, and aims to reduce the size of a device. Provided are a chip packaging structure and a preparation method therefor, and a storage system and an electronic device. The chip packaging structure comprises a first chip, a second chip and a third chip, which are arranged in a stacked mode, wherein the first chip at least comprises a peripheral circuit, and the peripheral circuit comprises a first transistor; the second chip at least comprises a column decoder, and the column decoder comprises a second transistor; and the third chip at least comprises a control circuit, and the control circuit comprises a third transistor, the length of a trench of the first transistor, the length of a trench of the second transistor and the length of a trench of the third transistor being different from each other. The chip packaging structure is applied to a storage system, so as to realize data reading and writing operations.

Description

Chip packaging structure and preparation method thereof, storage system, and electronic equipment Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a chip packaging structure and a preparation method thereof, a storage system, and an electronic device. Background Art

[0002] As the feature size of memory cells approaches the process limit, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate.

[0004] In the existing 3D NAND packaging structure, how to reduce the size of the device has become an urgent problem to be solved in the field.

[0005] Summary of the Invention

[0006] Embodiments of the present disclosure provide a chip packaging structure and a manufacturing method thereof, a storage system, and an electronic device, aiming to reduce the size of a device.

[0007] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0008] In one aspect, a chip package structure is provided, comprising a first chip, a second chip, and a third chip arranged in a stacked arrangement, wherein the first chip includes at least a peripheral circuit, the peripheral circuit including a first transistor; the second chip includes at least a column decoder, the column decoder including a second transistor; and the third chip includes at least a control circuit, the control circuit including a third transistor. The channel lengths of the first transistor, the second transistor, and the third transistor are all different.

[0009] The chip packaging structure provided by the above-mentioned embodiments of the present disclosure includes a first chip, a second chip, and a third chip arranged in a stacked manner. The first chip includes at least a peripheral circuit, which includes a first transistor. That is, the circuit using the first transistor is integrated into the first chip. The second chip includes at least a column decoder, which includes a second transistor. That is, the circuit using the second transistor is integrated into the second chip. The third chip includes at least a control circuit, which includes a third transistor. That is, the circuit using the third transistor is integrated into the third chip.

[0010] Multiple circuits on the same chip use the same transistors, and the parameters of the manufacturing process for these multiple circuits are the same. Therefore, the same process can be used to form multiple circuits on the same chip. Furthermore, the process parameters used to manufacture different chips vary, resulting in different channel lengths for the first transistor, the second transistor, and the third transistor, and thus different operating voltages for the circuits on different chips.

[0011] Compared with arranging multiple chips horizontally, by stacking the first chip, the second chip and the third chip with different process parameters, the size of the chip packaging structure in the horizontal direction can be reduced, thereby reducing the size of the storage system using the chip packaging structure.

[0012] In some embodiments, the peripheral circuit includes at least a word line driver and a page buffer, each of which includes a first transistor. The second chip also includes a power management circuit, which includes a second transistor. The third chip also includes an I / O interface circuit, which includes a third transistor.

[0013] In some embodiments, the first transistor, the second transistor, and the third transistor are all CMOS transistors, and the column decoder further includes a fourth transistor and a fifth transistor. The fourth transistor is a bipolar transistor, and the fifth transistor is a DMOS transistor.

[0014] In some embodiments, the second chip further includes a power management circuit, and the power management circuit includes a fourth transistor and a fifth transistor.

[0015] In some embodiments, the chip packaging structure further includes a fourth chip, the fourth chip includes a volatile memory, and the fourth chip is stacked with the first chip, the second chip, and the third chip.

[0016] In some embodiments, the first chip, the second chip, and the third chip form a stacked structure, which is arranged in parallel with the fourth chip along a first direction. The first chip includes a first surface close to or away from the second chip, and the first direction is parallel to the first surface.

[0017] In some embodiments, among multiple chips stacked together, one of two adjacent chips includes a first dielectric layer located on the chip surface and a first conductive pattern extending through the first dielectric layer, and the other includes a second dielectric layer located on the chip surface and a second conductive pattern extending through the second dielectric layer, the first conductive pattern is bonded to the second conductive pattern, and the first dielectric layer is bonded to the second dielectric layer.

[0018] In some embodiments, the chip packaging structure further includes a connection structure, and the first conductive pattern is electrically connected to the second conductive pattern through the connection structure.

[0019] In some embodiments, the connection structure includes any one of a solder ball, a solder bump, or a copper pillar.

[0020] In some embodiments, the orthographic projection of the connection structure on the first surface of the first chip is a circle, and a diameter of the circle ranges from 1 μm to 10 μm.

[0021] In some embodiments, the plurality of connection structures are arranged in an array along a direction parallel to the first surface of the first chip, and a distance between two adjacent connection structures ranges from 1 μm to 10 μm.

[0022] In some embodiments, the chip packaging structure further includes a fifth chip, the fifth chip includes a three-dimensional memory array, the fifth chip is stacked with the first chip, the second chip and the third chip, and the fifth chip is adjacent to the first chip.

[0023] In some embodiments, the channel length of the first transistor ranges from 40 nm to 180 nm, the channel length of the second transistor is greater than or equal to 130 nm, and the channel length of the third transistor ranges from 14 nm to 40 nm.

[0024] In another aspect, a method for fabricating a chip package structure is provided, the method comprising: forming a first chip, a second chip, and a third chip, and stacking the first, second, and third chips. The first chip includes at least a peripheral circuit, which includes a first transistor. The second chip includes at least a column decoder, which includes a second transistor. The third chip includes at least a control circuit, which includes a third transistor. The channel lengths of the first transistor, the second transistor, and the third transistor are all different.

[0025] The preparation method provided by the above-mentioned embodiment of the present disclosure classifies the same process conditions (for example, process parameters) during the preparation of multiple circuits of the storage system, and circuits with the same process (with the same process parameters) can be prepared on the same chip.

[0026] For example, multiple circuits (at least including peripheral circuits) including transistors of the same type (first transistors) are prepared on a first chip, multiple circuits (at least including column decoders) including transistors of the same type (second transistors) are prepared on a second chip, and multiple circuits (at least including control circuits) including transistors of the same type (third transistors) are prepared on a third chip, which simplifies the chip preparation process and reduces the process cost.

[0027] Moreover, stacking the first chip, the second chip, and the third chip can reduce the horizontal size of the chip packaging structure compared to arranging multiple chips flatly in the horizontal direction, thereby reducing the size of the storage system using the chip packaging structure.

[0028] In some embodiments, the first chip, the second chip, and the third chip each include multiple circuits. The same process can be used to form the multiple circuits of the same chip, and the process parameters for forming different chips are different.

[0029] In some embodiments, the method for preparing the chip packaging structure further includes: stacking a fourth chip with the first chip, the second chip, and the third chip, wherein the fourth chip includes a volatile memory.

[0030] In some embodiments, a bonding process is used to connect the surfaces of two adjacent chips.

[0031] In some embodiments, a connection structure is used to connect two adjacent chips.

[0032] In some embodiments, before stacking the first, second, and third chips, a bonding process is used to connect the surface of the fifth chip to the surface of the first chip to form a bonding structure. The bonding structure, the second, and third chips are then stacked.

[0033] On the other hand, a storage system is provided, comprising: the chip packaging structure as described above, and a circuit board, wherein the chip packaging structure is electrically connected to the circuit board.

[0034] On the other hand, an electronic device is provided, which includes the storage system as described above.

[0035] It can be understood that the beneficial effects achieved by the storage system and electronic device provided by the above embodiments of the present disclosure can be referred to the beneficial effects of the chip packaging structure described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and do not limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, etc. involved in the embodiments of the present disclosure.

[0037] FIG1 is a block diagram of an electronic device provided in some embodiments of the present disclosure;

[0038] FIG2 is a block diagram of a storage system provided by some embodiments of the present disclosure;

[0039] FIG3 is a structural diagram of a storage system provided by some embodiments of the present disclosure;

[0040] FIG4 is a block diagram of a first chip provided in some embodiments of the present disclosure;

[0041] FIG5 is a block diagram of a second chip provided in some embodiments of the present disclosure;

[0042] FIG6 is a block diagram of a third chip provided in some embodiments of the present disclosure;

[0043] FIG7 is a structural diagram of a transistor in a chip provided by some embodiments of the present disclosure;

[0044] 8A and 8B are structural diagrams of several other storage systems provided by some embodiments of the present disclosure;

[0045] FIG9 is a schematic diagram of a connection between chips provided by some embodiments of the present disclosure;

[0046] FIG10 is a cross-sectional view of the structure of FIG9 along section line AA';

[0047] FIG11 is a schematic diagram of a connection between chips provided by some embodiments of the present disclosure;

[0048] FIG12 is a flow chart of preparing a chip packaging structure according to some embodiments of the present disclosure;

[0049] 13A to 13G are diagrams showing steps of preparing a chip packaging structure according to some embodiments of the present disclosure;

[0050] FIG14 is a structural diagram of another storage system provided by some embodiments of the present disclosure;

[0051] 15A to 15B are diagrams showing steps of another method for preparing a chip packaging structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0052] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0053] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0054] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0055] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0056] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0057] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0058] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0059] As used herein, “approximately” includes the stated value and an average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0060] In the context of this disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers, and “over” or “over” means not only “over” or “above” something, but also includes “over” or “above” something with no intervening features or layers (i.e., directly on something).

[0061] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0062] Some embodiments of the present disclosure provide an electronic device. FIG1 is a block diagram of the electronic device provided by some embodiments of the present disclosure.

[0063] 1 , the electronic device 1 includes a storage system 2 and a processor 3 . The processor 3 may be a central processing unit (CPU). The processor 3 is electrically connected to the storage system 2 to control the operation of the storage system 2 .

[0064] The electronic device 1 can be any one of a mobile phone, desktop computer, tablet computer, laptop computer, server, vehicle-mounted device, wearable device (such as smart watch, smart bracelet, smart glasses, etc.), mobile power supply, game console, digital multimedia player, etc.

[0065] The storage system 2 can be integrated into various types of storage devices, such as a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package. Furthermore, the storage system 2 can be used in various types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage.

[0066] FIG2 is a block diagram of a storage system provided by some embodiments of the present disclosure.

[0067] 2 , the memory system 2 includes a three-dimensional memory array 21 , a word line driver (also called a row decoder) 22 , a page buffer 23 , a power management circuit (Power Management IC, PMIC for short) 24 , a control circuit 25 , a column decoder 26 , and an I / O (Input / Output) interface circuit 27 .

[0068] The three-dimensional memory array 21 may include multiple memory blocks, each of which may include multiple memory cells. The multiple memory cells may be connected to a word line driver 22 via string select lines, word lines, and ground select lines, and may be connected to a page buffer 23 via bit lines.

[0069] For example, a plurality of memory cells arranged along the same row may be connected to the same word line, and a plurality of memory cells arranged along the same column may be connected to the same bit line.

[0070] The word line driver 22 can decode the input address to generate and send one or more driving signals, such as word line voltage signals. The word line driver 22 can provide the word line voltage signals generated by the power management circuit 24 to one or more selected word lines among the plurality of word lines. Under the control of the control circuit 25, unselected word lines among the plurality of word lines can receive another word line voltage signal.

[0071] Page buffer 23 can be connected to the three-dimensional memory array 21 via bit lines to read or sense data stored in the memory cells. Depending on the operating mode of memory system 2, page buffer 23 can also be used to temporarily store data to be written or programmed into the memory cells. Page buffer 23 is also connected to column decoder 26, which can selectively activate the bit lines of the three-dimensional memory array 21.

[0072] The power management circuit 24 may use external voltages to generate voltages required for internal operations, such as a program voltage, a read voltage, an erase voltage, etc. The voltages generated by the power management circuit 24 may be transmitted to the three-dimensional memory array 21 through the word line driver 22 .

[0073] The control circuit 25 may control the overall operation of the word line driver 22 and the page buffer 23, may receive control signals and external voltages sent from an external entity, may operate depending on the received control signals, and may also control read, write, and / or erase operations in response to the control signals.

[0074] I / O interface circuit 27 may receive write data and send the write data to page buffer 23 during a program operation, may output read data received from page buffer 23 to an external entity during a read operation, and may send input addresses or instructions to control circuit 25 .

[0075] Exemplarily, the storage system 2 also includes a volatile memory 28, which can be, for example, a dynamic random access memory (DRAM) or registers. This volatile memory 28 can be used as a cache for the control circuit 25 to store control programs. When the control circuit 25 is operating, high-speed data transmission is performed between the control circuit 25 and the memory to quickly access the control program.

[0076] In some embodiments, the storage system 2 includes a three-dimensional storage array 21. In this case, the storage system 2 may be a memory card.

[0077] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0078] In some other embodiments, the storage system 2 includes a plurality of three-dimensional storage arrays 21. In this case, the storage system 2 may be a solid state drive (SSD).

[0079] In the storage system 2, the control circuit 25 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0080] Alternatively, the control circuit 25 is configured to operate in a high duty cycle environment SSD or eMMC, which are used for data storage in mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0081] In some embodiments, the storage system also includes a circuit board and a chip packaging structure arranged on the circuit board. The chip packaging structure includes multiple chips. The multiple chips can be, for example, three-dimensional storage arrays, power management circuits, control circuits, and memory chips. The multiple chips are arranged flatly along the surface of the circuit board, resulting in a larger size of the storage system.

[0082] Among the multiple chips mentioned above, as the size of the three-dimensional storage array decreases, other chips cannot be reduced in size due to limitations in process accuracy and cannot match the size reduction of the three-dimensional storage array. This restricts the size reduction of the storage system. Based on this, how to reduce the size of the device has become an urgent problem to be solved in the field.

[0083] To solve the above problems, some embodiments of the present disclosure provide a storage system. Figure 3 is a structural diagram of a storage system provided by some embodiments of the present disclosure; Figure 4 is a block diagram of a first chip provided by some embodiments of the present disclosure; Figure 5 is a block diagram of a second chip provided by some embodiments of the present disclosure; Figure 6 is a block diagram of a third chip provided by some embodiments of the present disclosure; and Figure 7 is a structural diagram of transistors in a chip provided by some embodiments of the present disclosure.

[0084] 3 , the storage system 2 includes a circuit board 4 and a chip packaging structure 5 disposed on the circuit board 4 . The chip packaging structure 5 includes a first chip 51 , a second chip 52 , and a third chip 53 that are stacked.

[0085] 4 , the first chip 51 includes at least a peripheral circuit. The peripheral circuit may include, for example, the aforementioned word line driver 22 and page buffer 23 . Both the word line driver 22 and the page buffer 23 may include a first transistor.

[0086] In the storage system 2, the word line driver 22 and the page buffer 23 both include a first transistor, and both include transistors of the same type. In addition, the operating voltage ranges of the word line driver 22 and the page buffer 23 are roughly equal, for example, the operating voltage ranges of the two are 2.5V to 30V. Therefore, the same process can be used to prepare the word line driver 22 and the page buffer 23 on the first chip 51, thereby realizing modularization of the circuit, simplifying the preparation process of the word line driver 22 and the page buffer 23, and having a lower process cost.

[0087] Illustratively, the first transistor is a CMOS (Complementary Metal Oxide Semiconductor) transistor, and the first transistor can be manufactured using a MOS process to manufacture the circuit on the first chip 51 .

[0088] 5 , the second chip 52 includes at least the aforementioned column decoder 26, which includes a second transistor. The second chip 52 may also include the aforementioned power management circuit 24, which also includes a second transistor.

[0089] In the storage system 2, the column decoder 26 and the power management circuit 24 both include second transistors, and both include transistors of the same type. In addition, the operating voltage ranges of the column decoder 26 and the power management circuit 24 are approximately the same, for example, the operating voltage ranges of the column decoder 26 and the power management circuit 24 are 3.3V to 30V. Therefore, the column decoder 26 and the power management circuit 24 can be manufactured on the second chip 52 using the same process, thereby achieving circuit modularization, simplifying the manufacturing process of the column decoder 26 and the power management circuit 24, and reducing the process cost.

[0090] Exemplarily, the second transistor is a CMOS transistor. In addition, the column decoder 26 and the power management circuit 24 also include bipolar transistors and DMOS (double-diffused metal oxide semiconductor) transistors. The bipolar transistors, CMOS transistors and DMOS transistors can be prepared using the BCD process to prepare the circuit on the second chip 52.

[0091] 6 , the third chip 53 includes at least the aforementioned control circuit 25, which includes a third transistor. The third chip 53 may also include the aforementioned I / O interface circuit 27, which also includes a third transistor.

[0092] In the storage system 2, the control circuit 25 and the I / O interface circuit 27 both include a third transistor, and both include transistors of the same type. In addition, the operating voltages of the control circuit 25 and the I / O interface circuit 27 are roughly equal, for example, the operating voltages of the two are about 1.1V. Therefore, the same process can be used to prepare the control circuit 25 and the I / O interface circuit 27 on the third chip 53, thereby realizing the modularization of the circuit, simplifying the preparation process of the control circuit 25 and the I / O interface circuit 27, and having a low process cost.

[0093] Exemplarily, the third transistor is a CMOS transistor, and the third transistor can be manufactured using a MOS process to manufacture the circuit on the third chip 53 .

[0094] Referring to FIG7 , the trench length L of a transistor is a critical parameter that affects transistor performance. During the fabrication of the first chip 51, the second chip 52, and the third chip 53, process parameters are adjusted to vary between the chips. This results in different channel lengths for the first transistor, the second transistor, and the third transistor, leading to different operating voltages for the circuits in the different chips.

[0095] Exemplarily, the channel length of the first transistor ranges from 40 nm to 180 nm, for example, the channel length of the first transistor is 40 nm, 75 nm, 110 nm, 145 nm, or 180 nm. The channel length of the second transistor ranges from 130 nm and above, for example, the channel length of the second transistor is 130 nm, 140 nm, 150 nm, 160 nm, or 170 nm. The channel length of the third transistor ranges from 14 nm to 40 nm, for example, the channel length of the third transistor is 14 nm, 20 nm, 27 nm, 28 nm, or 40 nm.

[0096] In the memory system 2 provided by the above-described embodiment of the present disclosure, the chip package structure 5 includes a first chip 51, a second chip 52, and a third chip 53, which are stacked. The first chip 51 includes at least a peripheral circuit, which includes a first transistor. That is, the circuit using the first transistor is integrated into the first chip 51. The second chip 52 includes at least a column decoder 26, which includes a second transistor. That is, the circuit using the second transistor is integrated into the second chip 52. The third chip 53 includes at least a control circuit 25, which includes a third transistor. That is, the circuit using the third transistor is integrated into the third chip 53.

[0097] Multiple circuits on the same chip use the same transistors, and the parameters of the manufacturing process for these multiple circuits are the same. Therefore, the same process can be used to form multiple circuits on the same chip. Furthermore, the process parameters used to manufacture different chips vary, resulting in different channel lengths for the first transistor, the second transistor, and the third transistor, and thus different operating voltages for the circuits on different chips.

[0098] Compared with laying multiple chips flat in the horizontal direction, by stacking the first chip 51, the second chip 52 and the third chip 53 with different process parameters, the size of the chip packaging structure 5 in the horizontal direction can be reduced. For example, the size of the chip packaging structure 5 can be reduced by more than 50%, thereby reducing the size of the storage system 2 using the chip packaging structure 5.

[0099] In some embodiments, referring to FIG. 3 , the chip package structure 5 further includes a fourth chip 54 , and the fourth chip 54 includes the aforementioned volatile memory 28 .

[0100] The fourth chip 54 can be stacked with the first chip 51, the second chip 52 and the third chip 53 so that the fourth chip 54 is directly connected to the third chip 53, which is conducive to high-speed transmission of signals between the volatile memory 28 in the fourth chip 54 and the control circuit 25 in the third chip 53, and can reduce the horizontal size of the chip packaging structure 5, thereby reducing the size of the storage system 2.

[0101] For example, as shown in FIG3 , when the first chip 51 , the second chip 52 and the third chip 53 are stacked in sequence, the fourth chip 54 may be disposed on a side of the third chip 53 away from the first chip 51 .

[0102] 8A and 8B are structural diagrams of several other storage systems provided in some embodiments of the present disclosure.

[0103] When the first chip 51, the second chip 52, and the third chip 53 are stacked in sequence, as shown in FIG8A , the fourth chip 54 may also be disposed between the first chip 51 and the second chip 52. Alternatively, as shown in FIG8B , the fourth chip 54 may also be disposed between the second chip 52 and the third chip 53.

[0104] In addition, the first chip 51 , the second chip 52 and the third chip 53 may not be stacked in sequence, and the stacking order of the three may be adjusted according to design requirements.

[0105] In some embodiments, referring to Figures 8A and 8B, the chip packaging structure 5 also includes a fifth chip 55, and the fifth chip 55 includes the aforementioned three-dimensional storage array 21. The fifth chip 55 can be stacked with the first chip 51, the second chip 52 and the third chip 53, which can reduce the size of the chip packaging structure 5 in the horizontal direction, thereby reducing the size of the storage system 2.

[0106] Illustratively, a memory cell of the three-dimensional memory array 21 may include a plurality of transistors for storage, for example, each memory cell includes at least 500 transistors.

[0107] As previously described, the first chip 51 includes peripheral circuits, such as a wordline driver 22 and a page buffer 23. The wordline driver 22 and the page buffer 23 each perform high-speed signal transmission with the three-dimensional memory array 21. Therefore, the fifth chip 55 is positioned adjacent to the first chip 51 to facilitate interconnection and ensure efficient signal transmission between the two.

[0108] FIG9 is a schematic diagram of a connection between chips provided by some embodiments of the present disclosure; FIG10 is a cross-sectional view of the structure in FIG9 along section line AA′.

[0109] 9 , among the multiple chips stacked, taking the case where a first chip 51 and a second chip 52 are adjacent to each other as an example, the first chip 51 and the second chip 52 can be interconnected through a connection structure 56 .

[0110] It is understandable that among the multiple chips arranged in a stack, any two adjacent chips can be interconnected through the connection structure 56, and the embodiments of the present application are not limited to this.

[0111] Illustratively, the first chip 51 includes a first dielectric layer 61 on its surface and a first conductive pattern 62 extending through the first dielectric layer 61. The second chip 52 includes a second dielectric layer 71 on its surface and a second conductive pattern 72 extending through the second dielectric layer 71. The first conductive pattern 62 of the first chip 51 is electrically connected to the second conductive pattern 72 of the second chip 52 via a connecting structure 56. The chip interconnection achieved via the connecting structure 56 is relatively simple and has low process difficulty and cost.

[0112] In addition, among the multiple chips stacked together, the chips directly connected to the circuit board 4 can also be interconnected using the connection structure 56 .

[0113] For example, the connection structure 56 includes any one of a solder ball, a solder bump, or a Cu pillar.

[0114] In some embodiments, referring to Figures 9 and 10 , first chip 51 includes a surface P on a side close to or away from second chip 52. The orthographic projection of connection structure 56 on surface P is a circle, and the diameter D of the circle ranges from 1 μm to 10 μm. For example, the diameter D of the circle is 1 μm, 3 μm, 5.5 μm, 8 μm, or 10 μm. Compared to the size of the connection structures in currently mass-produced products, the diameter D of the projection of connection structure 56 is on the micron level, reducing the area occupied by connection structure 56 and facilitating device miniaturization.

[0115] In the case where the connection structure 56 is a solder bump, since the projected diameter of the connection structure 56 is in the micrometer order, the connection structure 56 is also referred to as a micro bump.

[0116] In some embodiments, referring to Figures 9 and 10, a plurality of connection structures 56 are arranged in an array along a direction parallel to the surface P, i.e., along the plane XY, and the spacing E between two adjacent connection structures 56 ranges from 1 μm to 10 μm. For example, the spacing E between two adjacent connection structures 56 is 1 μm, 4 μm, 5.5 μm, 7 μm or 10 μm.

[0117] Compared with the spacing of the connection structures in currently mass-produced products, the connection structures 56 in the embodiment of the present application are smaller in size, which is beneficial to reducing the spacing E of the connection structures 56 and thus facilitating miniaturization of the device.

[0118] FIG11 is a schematic diagram of a connection between chips provided in some embodiments of the present disclosure.

[0119] 11 , taking the case where a first chip 51 and a second chip 52 are adjacent to each other as an example, the two adjacent chips can be interconnected by hybrid bonding.

[0120] It is understandable that among the multiple chips arranged in a stack, any two adjacent chips can be interconnected by hybrid bonding, and the embodiments of the present application are not limited to this.

[0121] For example, the first dielectric layer 61 of the first chip 51 is bonded to the second dielectric layer 71 of the second chip 52, and the first conductive pattern 62 of the first chip 51 is bonded to the second conductive pattern 72 of the second chip 52. By hybrid bonding, the conductive patterns of the two chips are in contact, which is conducive to high-speed transmission of signals between the chips.

[0122] In the memory system 2, the wordline driver 22 and page buffer 23 are each connected to the three-dimensional memory array 21 and require high-speed signal transmission. Therefore, connecting the fifth chip 55 to the first chip 51 through hybrid bonding facilitates high-speed signal transmission between the wordline driver 22 and page buffer 23 in the first chip 51 and the three-dimensional memory array 21 in the fifth chip 55.

[0123] Moreover, in the storage system 2, high-speed signal transmission is also required between the volatile memory 28 and the control circuit 25. Therefore, connecting the fourth chip 54 and the third chip 53 by hybrid bonding is beneficial to high-speed signal transmission between the volatile memory 28 in the fourth chip 54 and the control circuit 25 in the third chip 53.

[0124] Some embodiments of the present disclosure also provide a method for preparing the chip packaging structure shown in Figure 3, Figure 12 is a flow chart of preparing the chip packaging structure provided by some embodiments of the present disclosure; Figures 13A to 13G are diagrams of the steps of preparing a chip packaging structure provided by some embodiments of the present disclosure.

[0125] 12 , the method for preparing the chip packaging structure includes the following steps S10 to S20 :

[0126] S10: Referring to FIG. 13A to FIG. 13C , a first chip 51, a second chip 52, and a third chip 53 are formed. First chip 51 includes at least a peripheral circuit, which includes a first transistor. Second chip 52 includes at least a column decoder 26, which includes a second transistor. Third chip 53 includes at least a control circuit 25, which includes a third transistor.

[0127] Exemplarily, the first chip 51, the second chip 52 and the third chip 53 each include multiple circuits. For example, the peripheral circuit of the first chip 51 includes a word line driver 22 and a page buffer 23, the second chip 52 includes a column decoder 26 and a power management circuit 24, and the third chip 53 includes a control circuit 25 and an I / O interface circuit 27.

[0128] Based on this, the same process can be used to form multiple circuits on the same chip, which simplifies the chip preparation process and reduces the process cost.

[0129] Moreover, during the preparation of the first chip 51, the second chip 52 and the third chip 53, the process parameters are adjusted so that the process parameters of different chips are different, so that the length of the channel of the first transistor, the length of the channel of the second transistor and the length of the channel of the third transistor in the chip are all different, so that the operating voltages of the circuits in different chips are different.

[0130] 13D and 13E , the method for preparing the chip package structure further includes forming a fourth chip 54 and a fifth chip 55 , wherein the fourth chip 54 includes a volatile memory 28 , and the fifth chip 55 includes a three-dimensional memory array 21 .

[0131] Referring to Figure 13F, in order to ensure that the fifth chip 55 can transmit signals at high speed with the first chip 51, before stacking the first chip 51, the second chip 52 and the third chip 53, the surface of the fifth chip 55 can be bonded to the surface of the first chip 51 to form a bonding structure, and then the bonding structure can be connected to the second chip 52.

[0132] S20 : ​​Referring to FIG. 13G , the first chip 51 , the second chip 52 and the third chip 53 are stacked.

[0133] For example, the fourth chip 54 can be connected to the circuit board 4 first, then the third chip 53 can be connected to the fourth chip 54, the second chip 52 can be connected to the third chip 53, and finally the fifth chip 55 and the bonding structure of the first chip 51 can be connected to the second chip 52, and the first chip 51 and the second chip 52 can be directly connected.

[0134] For example, a bonding process, such as a hybrid bonding process, may be used to connect the surfaces of two adjacent chips. Alternatively, a connection structure 56 may be used to connect the two adjacent chips.

[0135] The preparation method provided by the above-mentioned embodiment of the present disclosure classifies the same process conditions (for example, process parameters) during the preparation of multiple circuits of the storage system 2, and circuits of the same process (with the same process parameters) can be prepared on the same chip.

[0136] For example, the peripheral circuits include word line drivers 22 and page buffers 23, both of which include the same type of transistors (first transistors). Therefore, word line drivers 22 and page buffers 23 can be fabricated on first chip 51. Column decoders 26 and power management circuits 24 include the same type of transistors (second transistors). Therefore, column decoders 26 and power management circuits 24 can be fabricated on second chip 52. Control circuits 25 and I / O interface circuits 27 include the same type of transistors (third transistors). Therefore, control circuits 25 and I / O interface circuits 27 can be fabricated on third chip 53, simplifying the chip fabrication process and reducing process costs.

[0137] Moreover, stacking the first chip 51, the second chip 52 and the third chip 53 can reduce the horizontal size of the chip packaging structure 5 compared to arranging multiple chips flatly in the horizontal direction, thereby reducing the size of the storage system 2 using the chip packaging structure 5.

[0138] FIG14 is a structural diagram of another storage system provided by some embodiments of the present disclosure.

[0139] 14 , the chip packaging structure 5 further includes a fourth chip 54 . The first chip 51 , the second chip 52 and the third chip 53 form a stacking structure 50 . The fourth chip 54 and the stacking structure 50 are arranged in parallel along a first direction X. The first direction X is parallel to the surface P of the first chip 51 .

[0140] Exemplarily, the fourth chip 54 and the stack structure 50 are arranged side by side on the circuit board 4 and are arranged flat along the surface of the circuit board 4. The fourth chip 54 and the stack structure 50 are both connected to the circuit board 4 via a connection structure 56.

[0141] Compared with the three-dimensional storage array, power management circuit, control circuit and storage circuit and other chips arranged flatly along the surface of the circuit board, in the above-mentioned embodiment of the present disclosure, the fourth chip 54 and the stacking structure 50 are arranged in parallel, and the chip packaging structure 5 has an area only the size of two chips. The area of ​​the chip packaging structure 5 along the plane XY is small, thereby reducing the area occupied by the chip packaging structure 5 on the circuit board 4, which is conducive to reducing the area of ​​the storage system 2 and realizing the miniaturization of the device.

[0142] Moreover, the process of connecting the fourth chip 54 and the stacked structure 50 to the circuit board 4 is simple. The fourth chip 54 is electrically connected to the third chip 53 through the circuit board 4, so that the volatile memory 28 in the fourth chip 54 is electrically connected to the control circuit 25 in the third chip 53.

[0143] Some embodiments of the present disclosure further provide a method for preparing the chip packaging structure shown in FIG. 14 . FIG. 15A to FIG. 15B are diagrams showing the steps of preparing another chip packaging structure provided by some embodiments of the present disclosure.

[0144] Similar to the above-mentioned preparation method, the first chip 51, the second chip 52, the third chip 53, the fourth chip 54 and the fifth chip 55 are first formed, and then the surface of the fifth chip 55 is bonded to the surface of the first chip 51 to form a bonding structure.

[0145] 15A , a first chip 51 , a second chip 52 , and a third chip 53 are stacked.

[0146] For example, the third chip 53 can be connected to the circuit board 4 first, the second chip 52 can be connected to the third chip 53, and finally the bonding structure of the fifth chip 55 and the first chip 51 can be connected to the second chip 52, and the first chip 51 and the second chip 52 can be directly connected.

[0147] 15B , the fourth chip 54 is connected to the circuit board 4 . This step may be performed before or after the first chip 51 , the second chip 52 and the third chip 53 are stacked. The embodiment of the present disclosure does not limit this.

[0148] In the preparation method provided by the above-mentioned embodiment of the present disclosure, the fourth chip 54 is not stacked with the first chip 51, the second chip 52 and the third chip 53, but the fourth chip 54 is connected to the circuit board 4 separately. The process of connecting the fourth chip 54 to the circuit board 4 is simple, which is conducive to reducing process costs.

[0149] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A chip packaging structure, characterized in that: include: A first chip, a second chip, and a third chip are stacked; The first chip at least includes a peripheral circuit, and the peripheral circuit includes a first transistor; the second chip at least includes a column decoder, and the column decoder includes a second transistor; the third chip at least includes a control circuit, and the control circuit includes a third transistor; The length of the channel of the first transistor, the length of the channel of the second transistor, and the length of the channel of the third transistor are all different.

2. The chip packaging structure according to claim 1, characterized in that: The peripheral circuit includes at least a word line driver and a page buffer, and the word line driver and the page buffer each include the first transistor; The second chip further includes a power management circuit, and the power management circuit includes the second transistor; The third chip further includes an I / O interface circuit, and the I / O interface circuit includes the third transistor.

3. The chip packaging structure according to claim 1 or 2, characterized in that: The first transistor, the second transistor and the third transistor are all CMOS transistors; The column decoder further includes a fourth transistor and a fifth transistor, wherein the fourth transistor is a bipolar transistor and the fifth transistor is a DMOS transistor.

4. The chip packaging structure according to claim 3, characterized in that: The second chip further includes a power management circuit, and the power management circuit includes the fourth transistor and the fifth transistor.

5. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a fourth chip, wherein the fourth chip includes a volatile memory; The fourth chip is stacked with the first chip, the second chip and the third chip.

6. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a fourth chip, wherein the fourth chip includes a volatile memory; The stacked structure formed by the first chip, the second chip and the third chip is arranged in parallel with the fourth chip along the first direction; The first chip includes a first surface close to or far from a side of the second chip, and the first direction is parallel to the first surface.

7. The chip packaging structure according to any one of claims 1 to 6, characterized in that: Among the multiple chips stacked, one of the two adjacent chips includes a first dielectric layer located on the chip surface and a first conductive pattern penetrating the first dielectric layer; the other includes a second dielectric layer located on the chip surface and a second conductive pattern penetrating the second dielectric layer; The first conductive pattern is bonded to the second conductive pattern, and the first dielectric layer is bonded to the second dielectric layer.

8. The chip packaging structure according to any one of claims 1 to 6, characterized in that: Among the multiple chips stacked, one of the two adjacent chips includes a first dielectric layer located on the chip surface and a first conductive pattern penetrating the first dielectric layer; the other includes a second dielectric layer located on the chip surface and a second conductive pattern penetrating the second dielectric layer; The chip packaging structure further includes a connection structure, and the first conductive pattern is electrically connected to the second conductive pattern through the connection structure.

9. The chip packaging structure according to claim 8, characterized in that: The connection structure includes any one of a solder ball, a solder bump or a copper column.

10. The chip packaging structure according to claim 8 or 9, characterized in that: The first chip comprises a first surface close to or away from a side of the second chip; The orthographic projection of the connection structure on the first surface is a circle, and the diameter of the circle ranges from 1 μm to 10 μm.

11. The chip packaging structure according to any one of claims 8 to 10, characterized in that: The first chip comprises a first surface close to or away from a side of the second chip; Along a direction parallel to the first surface, a plurality of the connection structures are arranged in an array; The distance between two adjacent connection structures ranges from 1 μm to 10 μm.

12. The chip packaging structure according to any one of claims 1 to 11, characterized in that: The chip packaging structure further includes a fifth chip, wherein the fifth chip includes a three-dimensional storage array; The fifth chip is stacked with the first chip, the second chip and the third chip; The fifth chip is disposed adjacent to the first chip.

13. The chip packaging structure according to any one of claims 1 to 12, characterized in that: The channel length of the first transistor ranges from 40 nm to 180 nm; The channel length of the second transistor is greater than or equal to 130 nm; The channel length of the third transistor is in the range of 14 nm to 40 nm.

14. A method for preparing a chip packaging structure, characterized in that: include: forming a first chip, a second chip, and a third chip; Stacking the first chip, the second chip and the third chip; The first chip at least includes a peripheral circuit, and the peripheral circuit includes a first transistor; the second chip at least includes a column decoder, and the column decoder includes a second transistor; the third chip at least includes a control circuit, and the control circuit includes a third transistor; The length of the channel of the first transistor, the length of the channel of the second transistor, and the length of the channel of the third transistor are all different.

15. The preparation method according to claim 14, characterized in that: The first chip, the second chip and the third chip each include a plurality of circuits; The forming of the first chip, the second chip and the third chip comprises: Using the same process to form multiple circuits on the same chip; and / or, The process parameters for forming different chips are different.

16. The preparation method according to claim 14 or 15, characterized in that: The preparation method further comprises: A fourth chip is stacked with the first chip, the second chip and the third chip; the fourth chip includes a volatile memory.

17. The preparation method according to any one of claims 14 to 16, characterized in that: The surfaces of two adjacent chips are connected using a bonding process.

18. The preparation method according to any one of claims 14 to 16, characterized in that: A connection structure is used to connect two adjacent chips.

19. The preparation method according to any one of claims 14 to 18, characterized in that: Before stacking the first chip, the second chip and the third chip, the method further includes: Using a bonding process, the surface of a fifth chip is connected to the surface of the first chip to form a bonding structure; the fifth chip includes a three-dimensional storage array; The stacking of the first chip, the second chip and the third chip comprises: The bonding structure, the second chip and the third chip are stacked.

20. A storage system, characterized in that: include: The chip packaging structure according to any one of claims 1 to 13; A circuit board, the chip packaging structure is electrically connected to the circuit board.

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