Three-dimensional integrated device and forming method therefor

Abstract

The present invention relates to a three-dimensional integrated device and a forming method therefor. The three-dimensional integrated device comprises a stack body formed by stacking at least two layers of chips and a carrier piece bonded to a first surface of the stack body, the first surface of the stack body being provided with a heat-conducting groove, the carrier piece being provided with a first through hole and a second through hole, the first through hole and the second through hole respectively exposing a first end and a second end of the heat-conducting groove, the first through hole being an inlet for a cooling liquid, and the second through hole being an outlet for the cooling liquid. The three-dimensional integrated device can use the flow of the cooling liquid within the heat-conducting groove to take away heat for cooling, so as to achieve the purpose of cooling the device, achieving higher heat-conducting efficiency and greater cooling capability, thus reducing the risk of heat accumulation inside the three-dimensional integrated device, and helping to improve the performance of the three-dimensional integrated device.

Description

Three-dimensional integrated device and method for forming the same Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a three-dimensional integrated device and a method for forming the same. Background Art

[0002] With the growing demand for big data processing capabilities of integrated circuits, Moore's Law is approaching its limit, and device size reduction is becoming increasingly difficult. Three-dimensional integration technology has become an effective solution to continue to improve PPAC (performance, power, area, cost) in the post-Moore era.

[0003] For 3D integrated devices, as the number of stacked layers increases, the heat generated during operation increases dramatically. If the heat cannot be removed in a timely manner, the accumulated heat will seriously affect the performance of the device.

[0004] In the prior art, when manufacturing a three-dimensional integrated device, multiple chips are first stacked and the resulting stacked structure is bonded to a circuit substrate. A thermally conductive layer is then formed on the surface of the stacked structure away from the circuit substrate, and a heat-dissipating metal sheet is placed on the thermally conductive layer. The goal is to conduct heat generated within the device through the thermally conductive layer to the metal heat sink, where it is then dissipated through heat exchange between the metal heat sink and the air. Heat exchange between the metal heat sink and the air can dissipate heat naturally, or it can be achieved through "forced air cooling" by accelerating air flow. However, both natural and forced air cooling methods, due to their low thermal conductivity and limited heat dissipation capacity, can still lead to heat accumulation within the three-dimensional integrated device, hindering its normal operation.

[0005] Summary of the Invention

[0006] In order to improve the heat dissipation capability of a three-dimensional integrated device, the present invention provides a three-dimensional integrated device and a method for forming the three-dimensional integrated device.

[0007] On the one hand, the present invention provides a three-dimensional integrated device, which includes a stack formed by stacking at least two layers of chips and a carrier, the stack having a first surface and a second surface opposite to each other, wherein the first surface is formed with a heat-conducting groove, and the length direction of the heat-conducting groove is parallel to the first surface; the carrier is bonded to the first surface of the stack, and the carrier has a first through hole and a second through hole, the first through hole exposes the first end of the heat-conducting groove, and the second through hole exposes the second end of the heat-conducting groove, wherein the first through hole is the inlet of the heat dissipation liquid, and the second through hole is the outlet of the heat dissipation liquid.

[0008] Optionally, the opening of the first through hole facing away from the stacking body is not higher than the surface of the carrier around the first through hole; the opening of the second through hole facing away from the stacking body is not higher than the surface of the carrier around the second through hole.

[0009] Optionally, a solder bump is formed on the second surface, and the solder bump is connected to a circuit inside the stacked body.

[0010] Optionally, the three-dimensional integrated device further includes a circuit substrate having pads, wherein the stacked body is bonded to the circuit substrate by soldering the solder bumps to corresponding pads.

[0011] Optionally, the stack includes a first chip layer including a first substrate and electronic components formed on a front surface of the first substrate, wherein the heat conduction groove is formed on a back surface of the first substrate opposite to the front surface.

[0012] Optionally, the electronic components include logic devices and / or memory devices.

[0013] Optionally, one or more channel paths are provided between the first end and the second end of the heat conductive groove.

[0014] Optionally, in the stack, each chip layer includes at least one chip.

[0015] In one aspect, the present invention provides a method for forming a three-dimensional integrated device, the method comprising:

[0016] stacking at least two layers of chips to form a stacked body, wherein the stacked body has a first surface and a second surface opposite to each other;

[0017] forming a heat conducting groove on the first surface, wherein the length direction of the heat conducting groove is parallel to the first surface, and the heat conducting groove has a first end and a second end in the length direction;

[0018] forming a first groove and a second groove on a surface of a carrier;

[0019] Bonding the stack to the carrier, wherein the first groove is opposite to the first end of the heat conducting groove, and the second groove is opposite to the second end of the heat conducting groove;

[0020] The bottoms of the first groove and the second groove are removed to form a first through hole in the first groove and a second through hole in the second groove, wherein the first through hole exposes the first end of the heat conductive groove and the second through hole exposes the second end of the heat conductive groove, wherein the first through hole is an inlet for heat dissipation liquid and the second through hole is an outlet for heat dissipation liquid.

[0021] Optionally, the bottoms of the first groove and the second groove are removed by thinning or etching the carrier.

[0022] Optionally, before removing the bottom of the first groove and the second groove, the formation method also includes: forming a solder bump on the second surface, the solder bump being connected to the circuit inside the stack; and joining the stack to a circuit substrate, the circuit substrate having a pad, wherein the solder bump is welded to the corresponding pad.

[0023] The three-dimensional integrated device provided by the present invention includes a stack formed by at least two layers of chips and a carrier bonded to the first surface of the stack. A heat-conducting groove is formed on the first surface of the stack, and the carrier has a first through-hole and a second through-hole. The first through-hole exposes the first end of the heat-conducting groove, and the second through-hole exposes the second end of the heat-conducting groove. The first through-hole serves as an inlet for a heat-dissipating liquid, and the second through-hole serves as an outlet for the heat-dissipating liquid. Compared to the prior art heat dissipation method of attaching a metal heat sink, the three-dimensional integrated device can dissipate heat by utilizing the flow of heat-dissipating liquid in the heat-conducting groove to remove heat, thereby achieving device cooling. This method has higher thermal conductivity and stronger heat dissipation capacity, reduces the risk of heat accumulation within the three-dimensional integrated device, and helps improve the performance of the three-dimensional integrated device.

[0024] The method for forming the three-dimensional integrated device provided by the present invention has the same concept as the three-dimensional integrated device of the present invention and has the same or similar advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG1 is a schematic flow chart of a method for forming a three-dimensional integrated device according to an embodiment of the present invention.

[0026] FIG2 is a schematic cross-sectional view of a stacked body in a method for forming a three-dimensional integrated device according to an embodiment of the present invention.

[0027] 3 is a schematic cross-sectional view of a method for forming a three-dimensional integrated device after forming a heat conduction trench on the first surface of a stacked body according to an embodiment of the present invention.

[0028] 4 is a simulated plan view of a heat conduction trench formed on a first surface of a stacked body in a method for forming a three-dimensional integrated device according to an embodiment of the present invention.

[0029] FIG5 is a schematic cross-sectional view of a method for forming a three-dimensional integrated device according to an embodiment of the present invention after forming a first groove and a second groove on the surface of a carrier.

[0030] FIG6 is a simulated plan view of a first groove and a second groove formed on a surface of a carrier wafer in a method for forming a three-dimensional integrated device according to an embodiment of the present invention.

[0031] 7 is a schematic cross-sectional view of a stacked body and a carrier after bonding in a method for forming a three-dimensional integrated device according to an embodiment of the present invention.

[0032] 8 is a simulated cross-sectional view of a stacked body, a carrier wafer, and a heat conducting trench after bonding in a method for forming a three-dimensional integrated device according to an embodiment of the present invention.

[0033] 9 is a schematic cross-sectional view of a method for forming a three-dimensional integrated device after forming a solder bump on the second surface of the stacked body according to an embodiment of the present invention.

[0034] 10 is a cross-sectional view of a method for forming a three-dimensional integrated device according to an embodiment of the present invention after the stacked body is bonded to a circuit substrate.

[0035] 11 is a schematic cross-sectional view of a method for forming a three-dimensional integrated device according to an embodiment of the present invention after the bottoms of the first groove and the second groove are removed.

[0036] FIG12 is a schematic cross-sectional view of a three-dimensional integrated device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The following is a further detailed description of the three-dimensional integrated device of the present invention and its formation method in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be understood that the drawings in the specification are all in a very simplified form and are all in non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order for performing these steps, some of the steps described may be omitted and / or some other steps not described herein may be added to the method. It should be understood that spatial relative terms are intended to include different orientations in use or operation in addition to the orientation of the device described in the figure. For example, if the structure in the figure is inverted or positioned in other different ways (such as rotated), the exemplary term "on..." may also include "under..." and other orientation relationships.

[0038] The following first describes the method for forming a three-dimensional integrated device of the present invention through an embodiment.

[0039] 1 and 2 , in the embodiment of the present invention, step S1 includes: stacking at least two layers of chips to form a stack 100 , wherein the stack 100 has a first surface 100 a and a second surface 100 b opposite to each other.

[0040] The method for forming a three-dimensional integrated device according to an embodiment of the present invention can utilize three-dimensional integration technology to stack at least two layers of chips to form the stack 100. In three-dimensional integration technology, multiple active devices, passive devices, MEMS devices, or discrete chips (such as optoelectronic chips, biochips, memory chips, logic chips, computing chips) with different functions or prepared using different processes are assembled together in three-dimensional directions (such as the X direction, Y direction, and Z direction of an orthogonal coordinate system) to form a complete circuit system. Each layer of chips can be formed separately by a separate wafer-level process. At least two layers of chips can be stacked to form the stack 100 by a wafer-level process, a chip-level process, or a chip-to-wafer process. In the stack 100, each layer of chips (or chip layer) is, for example, a wafer, or each layer of chips (or chip layer) is a chip (or die). Depending on the design, or at least one layer is a wafer and at least one layer is a chip, the number of chip layers stacked in the stack 100 can be different.

[0041] Each layer of chips in the stack 100 may include a semiconductor substrate and electronic components, interconnect layers, dielectric layers, etc. fabricated based on the semiconductor substrate. To stack at least two layers of chips, the chip layers may be superimposed together by bonding or bonding (e.g., hybrid bonding). For example, the chip layers may be bonded or bonded with the semiconductor substrates facing each other, or bonded or bonded with the semiconductor substrates facing away from each other (as shown in FIG. 2 ). Alternatively, the semiconductor substrate of one chip layer may be bonded or bonded to the dielectric layer of another chip layer.

[0042] For example, as shown in FIG2 , a logic wafer W1 and a memory wafer W2 are stacked together to form a stack 100 through step S1. The logic wafer W1, for example, includes a first substrate 101 and logic devices formed on a surface of the first substrate 101. The side with the logic devices formed thereon is referred to herein as the front side of the first substrate 101, and the side opposite to the front side is referred to as the back side of the first substrate 101. The logic wafer W1 may further include a first interconnect structure 102 formed on the front side of the first substrate 101. The memory wafer W2, for example, includes a second substrate 103 and memory devices (such as dynamic random access memory (DRAM) or static random access memory (SRAM)) formed on a surface of the second substrate 103. The side with the memory devices formed thereon is referred to herein as the front side of the second substrate 103, and the side opposite to the front side is referred to as the back side of the second substrate 103. The memory wafer W2 may further include a second interconnect structure 104 formed on the front side of the second substrate 103. The first interconnect structure 102 and the second interconnect structure 104 can be multi-layer electrical interconnect structures, for example, including multiple layers of patterned conductive layers and conductive plugs separated by dielectric materials. These conductive layers and conductive plugs provide connectivity between various doped regions, circuits, and input / outputs of the logic wafer W1 or the memory wafer W2. It should be understood that the components and positions of the first interconnect structure 102 and the second interconnect structure 104 are only schematically illustrated in the figures and may vary in practice based on design requirements. For clarity, FIG2 only shows a portion of the conductive layers and conductive plugs in the first interconnect structure 102 and the second interconnect structure 104.

[0043] As an example, in step S1, the front sides of the first substrate 101 and the second substrate 103 are bonded, the first surface 100a of the stack 100 serves as the back side of the first substrate 101, and the second surface 100b serves as the back side of the second substrate 103. The present invention is not limited thereto. For example, in another embodiment, a plurality of memory wafers and a logic wafer may be stacked to form a corresponding stack, or a plurality of memory chips and a logic chip may be stacked to form a corresponding stack.

[0044] 1 and 3 to 5 , in an embodiment of the present invention, step S2 includes forming a heat conducting trench TR on the first surface 100 a of the stack 100 , wherein the length direction of the heat conducting trench TR is parallel to the first surface 100 a , and the heat conducting trench TR has a first end TR1 and a second end TR2 in the length direction.

[0045] The production of the thermal conductive trench TR, for example, includes the following process: forming an imaged mask layer (such as a photoresist or a hard mask) on the first surface 100a of the stack 100 to expose the area of ​​the first surface 100a where the thermal conductive trench TR is to be formed, and then etching the first surface 100a by dry etching or wet etching to form a groove of a preset depth in the stack 100 as the thermal conductive trench TR.

[0046] As an example, in this embodiment, the stack 100 includes a stacked logic wafer W1 and a memory wafer W2. The thermally conductive trench TR is used to allow heat dissipation liquid to flow within the first surface 100a to remove heat generated within the three-dimensional integrated device. The thermally conductive trench TR can extend within the first surface 100a as needed. The thermally conductive trench TR extends within the first surface 100a along its length. The first end TR1 and the second end TR2 of the thermally conductive trench TR are located at different positions along the length. Subsequently, the first end TR1 serves as the location where heat dissipation liquid flows into the thermally conductive trench TR, and the second end TR2 serves as the location where heat dissipation liquid flows out of the thermally conductive trench TR.

[0047] It should be noted that the formation of the thermal conductive groove TR on the first surface 100a of the stack 100, i.e., the back side of the first substrate 101 in the logic wafer W1, as shown in FIG2 is used as an example for explanation here, but the present invention is not limited to this. In other embodiments, as needed, a thermal conductive groove can also be formed on one side of the storage wafer in the stack.

[0048] Figure 4 shows an exemplary simulated planar pattern of the heat-conducting trenches TR formed on the first surface 100a of the stack 100. Referring to Figure 4 , the first end TR1 and the second end TR2 of the heat-conducting trench TR are, for example, the two ends of the heat-conducting trench TR that are farther apart. That is, from the first end TR1 to the second end TR2, the heat dissipation fluid needs to flow a greater distance within the heat-conducting trench TR. However, this is not intended to be limiting. The planar arrangement of the heat-conducting trenches TR shown in Figure 4 is merely an example. Those skilled in the art can customize the planar arrangement of the heat-conducting trenches TR and the first and second ends TR1 and TR2 of the heat-conducting trench TR as needed.

[0049] As shown in FIG4 , the heat conducting trench TR may have multiple (e.g., two, three, or four) channel paths between the first end TR1 and the second end TR2, so that the heat conducting trench TR can be distributed over a larger area of ​​the first surface 100a. However, the present invention is not limited thereto. The heat conducting trench TR may have only one channel path between the first end TR1 and the second end TR2, and this channel path may be a straight line or a curve.

[0050] 1 and 5 , in the embodiment of the present invention, step S3 includes: forming a first groove U1 and a second groove U2 on a surface of a carrier wafer 200 .

[0051] The carrier 200 may be a semiconductor substrate, a glass substrate, a ceramic substrate, or a polymer substrate. After the carrier 200 is subsequently bonded to the stack 100, the first groove U1 and the second groove U2 are positioned opposite the first end TR1 and the second end TR2 of the thermally conductive trench TR, respectively. Therefore, the positions of the first groove U1 and the second groove U2 can be determined based on the arrangement of the thermally conductive trench TR in the stack 100. The cross-sectional area of ​​the first groove U1 can be larger or smaller than the area of ​​the first end TR1 of the thermally conductive trench TR opposite to it, and the cross-sectional area of ​​the second groove U2 can be larger or smaller than the area of ​​the second end TR2 of the thermally conductive trench TR opposite to it.

[0052] The formation of the first groove U1 and the second groove U2 on the surface of the carrier 200 includes, for example, the following process: forming a patterned mask layer (such as a photoresist or a hard mask) on the surface of the carrier 200 to expose the area where the first groove U1 and the second groove U2 are to be formed, and then etching the carrier 200 by dry etching or wet etching to form the first groove U1 and the second groove U2 in the carrier 200. Figure 6 shows an exemplary simulated planar pattern of the first groove U1 and the second groove U2 formed on the surface of the carrier 200. Referring to Figure 6, illustratively, the cross-section of the first groove U1 and the second groove U2 is rectangular, but is not limited thereto. In other embodiments, the first groove U1 and the second groove U2 may also have a circular, elliptical, triangular, square, pentagonal, hexagonal or other cross-sectional shape.

[0053] Referring to Figures 1 and 7 , in this embodiment of the present invention, step S4 includes bonding the stack 100 to the carrier 200, wherein the first groove U1 is opposite the first end TR1 of the thermally conductive trench TR, and the second groove U2 is opposite the second end TR2 of the thermally conductive trench TR. Figure 8 shows a simulated cross-section of the stack 100, carrier 200, and thermally conductive trench TR after bonding.

[0054] The stack 100 and the wafer 200 are bonded together using, for example, fusion bonding. After bonding, the first groove U1 covers the first end TR1 of the thermally conductive trench TR, thereby communicating with the first end TR1. The second groove U2 covers the second end TR2 of the thermally conductive trench TR, thereby communicating with the second end TR2.

[0055] Figure 9 is a schematic cross-sectional view of a method for forming a three-dimensional integrated device according to an embodiment of the present invention, after solder bumps are formed on the second surface of the stack. Referring to Figure 9 , in this embodiment, to connect the stack 100 to the circuit substrate, solder bumps 110 are also formed on the second surface 100b of the stack 100. These solder bumps 110 are connected to the circuitry within the stack 100.

[0056] Specifically, referring to FIG9 , after bonding the stack 100 and the carrier 200, the method for forming a three-dimensional integrated device according to an embodiment of the present invention may further include: using the carrier 200 for support, forming a first back dielectric layer 105 on the back side of the second substrate 103, and etching the first back dielectric layer 105 and the second substrate 103 to form a silicon through hole penetrating the second substrate 103, so that the silicon through hole exposes the second interconnect structure 104; depositing a metal material (such as copper) to form a silicon conductive hole corresponding to the silicon through hole. The back surface 100b is then formed by depositing a second back dielectric layer 107 and etching the second back dielectric layer 107 to form a through hole exposing the back surface interconnect layer 106. A metal material (such as copper) is deposited to form a conductive via corresponding to the through hole connected to the back surface interconnect layer 106, and a pad 108 is formed. A passivation layer 109 is deposited and etched to form a through hole exposing the pad 108. A solder bump 110 is formed in the through hole to connect to the pad 108. One or more solder bumps 110 may be formed on the second surface 100b, and the specific arrangement may depend on the integration requirements of the stack 100 and the circuit substrate.

[0057] 10 shows a cross-section after the stacked body 100 is bonded to the circuit substrate 300. Referring to FIG10, the stacked body 100 can then be bonded to a circuit substrate 300 so that the circuit inside the stacked body 100 is connected to the circuit substrate 300.

[0058] The circuit substrate 300 may include electronic components (such as logic elements) and interconnect structures, which can provide further interconnection and support in the three-dimensional integrated device. The circuit substrate 300 may have solder pads (not shown) formed on its surface. When the stack 100 and the circuit substrate 300 are joined, each solder bump 110 formed on the stack 100 can be soldered to the corresponding solder pad on the circuit substrate 300.

[0059] The circuit substrate 300 may be an intermediate substrate, such as a DCB board (ceramic-based copper-clad laminate, also known as a DBC board), an AMB board (active metal brazing carrier), a DPC board (direct plate copper), an HTCC board (high-temperature co-fired ceramic), or an LTCC board (low-temperature co-fired ceramic). After the stack 100 is bonded to one side of the intermediate substrate, the intermediate substrate may be connected to a PCB substrate from the other side of the intermediate substrate, but the present invention is not limited thereto. The circuit substrate 300 may also be a PCB substrate.

[0060] 1 and 11 , in an embodiment of the present invention, step S5 includes removing the bottoms of the first groove U1 and the second groove U2, thereby forming a first through hole U1a in the first groove U1 and a second through hole U2a in the second groove U2. For example, the bottoms of the first groove U1 and the second groove U2 can be removed by thinning the substrate 200 (e.g., by mechanical grinding, chemical mechanical polishing, laser grinding, or other processes) or etching (e.g., by dry etching or wet etching). The first through hole U1a exposes the first end TR1 of the heat-conducting trench TR, and the second through hole U2a exposes the second end TR2 of the heat-conducting trench TR. As indicated by the dotted arrows, the first through hole U1a serves as an inlet for the heat dissipation liquid, and the second through hole U2a serves as an outlet for the heat dissipation liquid.

[0061] In this embodiment, after the bottoms of the first groove U1 and the second groove U2 are removed by thinning or etching the slide 200, the opening of the first through hole U1a facing away from the stack 100 (i.e., the liquid inlet of the first through hole U1a) is no higher than the surface of the slide 200 surrounding the first through hole U1a; and the opening of the second through hole U2a facing away from the stack 100 (i.e., the liquid outlet of the second through hole U2a) is no higher than the surface of the slide 200 surrounding the second through hole U2a. As shown in Figure 11, as an example, the liquid inlet of the first through hole U1a and the liquid outlet of the second through hole U2a are substantially flush with the surface of the slide 200 on the same side.

[0062] In the method for forming a three-dimensional integrated device described in the above embodiment, a heat-conducting groove TR is formed on the surface of the stack 100. In addition, a first through hole U1a connected to the first end TR1 of the heat-conducting groove TR and a second through hole U2a connected to the second end TR2 of the heat-conducting groove TR are formed in the carrier 200 bonded to the stack 100. When the three-dimensional integrated device is working, a heat-dissipating liquid (such as water, liquid nitrogen, ethanol, silicone oil, Freon or special coolant, etc.) can be introduced into the heat-conducting groove TR from the first through hole U1a, and the heat-dissipating liquid is made to flow out from the second through hole U2a. This can promptly take away the heat generated by the chip in the stack 100 when it is working, thereby achieving the purpose of cooling the device. The heat conduction efficiency is higher and the heat dissipation capacity is stronger. Compared with the heat dissipation method of attaching a metal heat sink adopted in the prior art, the risk of heat accumulation inside the three-dimensional integrated device can be reduced, which helps to improve the performance of the three-dimensional integrated device.

[0063] The embodiments of the present invention further relate to a three-dimensional integrated device, which can be manufactured using the method for forming a three-dimensional integrated device described in the above embodiments.

[0064] Referring to Figure 11, according to an embodiment of the present invention, a three-dimensional integrated device includes a stacked body 100 formed by stacking at least two layers of chips and a carrier 200, wherein the stacked body 100 has a first surface 100a and a second surface 100b opposite to each other, wherein the first surface 100a is formed with a heat-conducting groove TR, and the length direction of the heat-conducting groove TR is parallel to the first surface 100a, the carrier 200 is bonded to the first surface 100a of the stacked body 100, and the carrier 200 has a first through hole U1a and a second through hole U2a, wherein the first through hole U1a exposes the first end TR1 of the heat-conducting groove TR, and the second through hole U2a exposes the second end TR2 of the heat-conducting groove TR, wherein the first through hole U1a is the inlet of the heat dissipation liquid, and the second through hole U2a is the outlet of the heat dissipation liquid.

[0065] The opening of the first through hole U1a facing away from the stack 100 (i.e., the liquid inlet of the first through hole U1a) is, for example, no higher than the surface of the slide 200 surrounding the first through hole U1a; the opening of the second through hole U2a facing away from the stack 100 (i.e., the liquid outlet of the second through hole U2a) is, for example, no higher than the surface of the slide 200 surrounding the second through hole U2a. As shown in FIG11 , as an example, the liquid inlet of the first through hole U1a and the liquid outlet of the second through hole U2a are substantially flush with the surface of the slide 200 on the same side.

[0066] The thermal conductive groove TR is formed on the first surface 100 a of the stack 100 . The first surface 100 a is, for example, the surface of the semiconductor substrate in the stack 100 , but is not limited thereto. In another embodiment, the thermal conductive groove TR may also be formed on the surface of the dielectric layer in the stack 100 .

[0067] 2 to 11 , one or more channels may be formed between the first end TR1 and the second end TR2 of the heat conducting trench TR. Optionally, a solder bump 110 is formed on the second surface 100 b of the stack 100 , and the solder bump 110 is connected to a circuit inside the stack 100 .

[0068] In some embodiments, the three-dimensional integrated device further includes a circuit substrate 300 having pads, wherein the stacked body 100 is bonded to the circuit substrate 300 by soldering the solder bumps 110 to corresponding pads.

[0069] 11 , in some embodiments, the stack 100 includes a first chip layer (e.g., a logic wafer W1), the first chip layer including a first substrate 101 and electronic components formed on the front side of the first substrate 101, wherein the heat conduction groove TR is formed on the back side of the first substrate 101 opposite to the front side. The electronic components may include logic devices and / or memory devices. Specifically, the first chip layer may be a logic wafer, a logic chip, a memory wafer, or a memory chip, or the first chip layer may be a wafer containing both logic devices and memory devices or a chip containing both logic devices and memory devices.

[0070] In the stack 100, each layer of chips may include one or more chips. As an example, the stack 100 is formed by stacking a logic wafer W1 and a storage wafer W2. However, it is not limited to this. According to the design of the three-dimensional integrated device, the stack 100 may include more than two chip layers, and each chip layer may have a wafer-level size or a chip-level size. Referring to Figure 12, in another embodiment, the stack 100 includes a logic wafer W1 and two or more storage wafers (for example, a storage wafer W3 and a storage wafer W4 as an example), and the stack 100 is bonded to the circuit substrate 300 on one side of the logic wafer W1 and to the carrier 200 on the side of the storage wafer W3, and a thermal conductive groove TR is formed on the surface of the storage wafer W3.

[0071] A three-dimensional integrated device according to an embodiment of the present invention includes a stack 100 formed by stacking at least two layers of chips, and a carrier 200 bonded to a first surface 100a of the stack 100. A heat-conducting trench TR is formed on the first surface 100a of the stack 100. The carrier 200 has a first through-hole U1a and a second through-hole U2a. The first through-hole U1a exposes a first end TR1 of the heat-conducting trench TR, while the second through-hole U2a exposes a second end TR2 of the heat-conducting trench TR. The first through-hole U1a serves as an inlet for a heat-dissipating liquid, while the second through-hole U2a serves as an outlet for the heat-dissipating liquid. Compared to the prior art heat dissipation method of attaching a metal heat sink, the three-dimensional integrated device utilizes the flow of heat-dissipating liquid in the heat-conducting trench TR to remove heat and dissipate heat, thereby cooling the device. This method offers higher thermal conductivity and stronger heat dissipation capabilities, reduces the risk of heat accumulation within the three-dimensional integrated device, and helps improve the performance of the three-dimensional integrated device.

[0072] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The relevant parts can be understood by reference.

[0073] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A three-dimensional integrated device, characterized in that: include: A stacked body formed by stacking at least two layers of chips, the stacked body having a first surface and a second surface opposite to each other, wherein a heat conduction groove is formed on the first surface, and the length direction of the heat conduction groove is parallel to the first surface; and A carrier is bonded to the first surface of the stack, and the carrier has a first through hole and a second through hole, wherein the first through hole exposes the first end of the heat-conducting groove, and the second through hole exposes the second end of the heat-conducting groove, wherein the first through hole is the inlet of the heat dissipation liquid, and the second through hole is the outlet of the heat dissipation liquid.

2. The three-dimensional integrated device according to claim 1, characterized in that: An opening of the first through hole facing away from the stacked body is not higher than the surface of the wafer around the first through hole; an opening of the second through hole facing away from the stacked body is not higher than the surface of the wafer around the second through hole.

3. The three-dimensional integrated device according to claim 1, characterized in that: A solder bump is formed on the second surface, and the solder bump is connected to a circuit inside the stacked body.

4. The three-dimensional integrated device according to claim 3, characterized in that: Also includes: The circuit substrate has pads, wherein the stacked body is bonded to the circuit substrate by soldering the solder bumps to the corresponding pads.

5. The three-dimensional integrated device according to claim 1, characterized in that: The stacked body includes a first chip layer, the first chip layer includes a first substrate and electronic components formed on a front surface of the first substrate, wherein the heat conduction groove is formed on a back surface of the first substrate opposite to the front surface.

6. The three-dimensional integrated device according to claim 5, characterized in that: The electronic components include logic devices and / or memory devices.

7. The three-dimensional integrated device according to any one of claims 1 to 6, characterized in that: The thermally conductive trench has one or more channel paths between the first end and the second end.

8. The three-dimensional integrated device according to any one of claims 1 to 6, characterized in that: In the stack, each chip layer includes at least one chip.

9. A method for forming a three-dimensional integrated device, characterized in that: include: Stacking at least two layers of chips to form a stacked body, wherein the stacked body has a first surface and a second surface opposite to each other; A heat conducting groove is formed on the first surface, wherein the length direction of the heat conducting groove is parallel to the first surface, and the heat conducting groove has a first end and a second end in the length direction; Forming a first groove and a second groove on a surface of a carrier; Bonding the stack to the carrier, wherein the first groove is opposite to the first end of the heat conducting groove, and the second groove is opposite to the second end of the heat conducting groove; and The bottoms of the first groove and the second groove are removed to form a first through hole in the first groove and a second through hole in the second groove, wherein the first through hole exposes the first end of the heat conductive groove and the second through hole exposes the second end of the heat conductive groove, wherein the first through hole is an inlet for heat dissipation liquid and the second through hole is an outlet for heat dissipation liquid.

10. The forming method according to claim 9, characterized in that: The bottoms of the first groove and the second groove are removed by thinning or etching the carrier.

11. The forming method according to claim 9, characterized in that: Before removing the bottoms of the first groove and the second groove, the forming method further includes: forming a solder bump on the second surface, wherein the solder bump is connected to a circuit inside the stack; and The stacked body is bonded to a circuit substrate having pads, wherein the solder bumps are soldered to the corresponding pads.

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