Memory cell structure and manufacturing method therefor, and memory cell array structure

Abstract

Disclosed are a memory cell structure and a manufacturing method therefor, and a memory cell array structure. The memory cell structure comprises: a first transistor, a storage region and a second transistor which are sequentially connected in a first direction; the first transistor comprises a first doped region, a second doped region and a third doped region which are sequentially connected in a second direction; the second transistor comprises a fourth doped region, a fifth doped region and a sixth doped region which are sequentially connected in the second direction; the storage region has a first side and a second side which are opposite to each other in the first direction, the second doped region is connected to the first side, and the fifth doped region is connected to the second side; the first, third, fourth and sixth doped regions are doped with first doping ions; and the second doped region, the storage region, and the fifth doped region are doped with second doping ions.

Description

Memory cell structure and manufacturing method thereof, memory cell array structure

[0001] Cross-references

[0002] This application claims priority to Chinese patent application number 202310921681.4, filed on July 24, 2023, entitled “Memory cell structure, manufacturing method thereof, memory cell array structure”, which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a memory cell structure and a manufacturing method thereof, and a memory cell array structure. Background Art

[0004] Common dynamic random access memory (DRAM) is a 1T1C type, where a single transistor source or drain is electrically connected to a capacitor to form a single memory cell. This structure uses capacitors to store data, but reading data consumes the capacitor's charge, and the capacitor itself leaks electricity, requiring constant refreshing. This results in high DRAM power consumption and unstable electrical performance. Furthermore, the large area required to manufacture the capacitor makes scaling down the capacitor challenging.

[0005] To overcome the difficulties brought by capacitors, capacitor-free memory cell structures are used, but the electrical performance of capacitor-free memory cell structures remains to be studied.

[0006] Summary of the Invention

[0007] The embodiments of the present disclosure provide a memory cell structure and a manufacturing method thereof, and a memory cell array structure, which are at least beneficial to improving the electrical performance of the memory cell structure.

[0008] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a storage cell structure, including: a first transistor, a storage area, and a second transistor that are contacted and connected in sequence along a first direction; wherein, the first transistor includes a first doping area, a second doping area, and a third doping area that are contacted and connected in sequence along a second direction, and the second transistor includes a fourth doping area, a fifth doping area, and a sixth doping area that are contacted and connected in sequence along the second direction, and the storage area has a first side and a second side opposite to each other along the first direction, the second doping area is contacted and connected to the first side, and the fifth doping area is contacted and connected to the second side, and the first direction and the second direction intersect; the first doping area, the third doping area, the fourth doping area, and the sixth doping area are all doped with first doping ions, and the second doping area, the storage area, and the fifth doping area are all doped with second doping ions, and one of the first doping ion and the second doping ion is an N-type doping ion, and the other is a P-type doping ion.

[0009] In some embodiments, the doping concentration of the second doping ions in the second doping region is greater than the doping concentration in the storage region, and the doping concentration of the second doping ions in the second doping region is greater than the doping concentration in the fifth doping region.

[0010] In some embodiments, the doping concentration of the second doping ion in the second doping region is in the range of 1×10 18 atom / cm 3 ~1×10 19 atom / cm 3 The doping concentration of the second doping ion in the storage region is in the range of 1×10 16 atom / cm 3 ~8×10 17 atom / cm 3 , and / or, the doping concentration of the second doping ion in the fifth doping region is in the range of 1×10 16 atom / cm 3 ~8×10 17 atom / cm 3 .

[0011] In some embodiments, the first doping region and the third doping region are further doped with the second doping ions, the doping concentration of the second doping ions in the first doping region is lower than the doping concentration of the first doping ions in the first doping region, and the doping concentration of the second doping ions in the third doping region is lower than the doping concentration of the first doping ions in the third doping region.

[0012] In some embodiments, the fourth doping region and the sixth doping region are further doped with the second doping ions, the doping concentration of the second doping ions in the fourth doping region is lower than the doping concentration of the first doping ions in the fourth doping region, and the doping concentration of the second doping ions in the sixth doping region is lower than the doping concentration of the first doping ions in the sixth doping region.

[0013] In some embodiments, the first transistor comprises a triode.

[0014] In some embodiments, the second transistor includes a metal-oxide semiconductor field-effect transistor; the metal-oxide semiconductor field-effect transistor further includes: a gate dielectric layer located on a side of the fifth doping region along the first direction away from the storage region; and a gate located on a side of the gate dielectric layer along the first direction away from the fifth doping region.

[0015] In some embodiments, the memory cell structure further includes: a first electrical connection layer located on a side of the first doping region away from the second doping region along the second direction, and the first electrical connection layer is in contact with the first doping region and the fourth doping region respectively.

[0016] In some embodiments, the memory cell structure further includes: a second electrical connection layer located on a side of the third doping region away from the second doping region along the second direction, and the second electrical connection layer is in contact with the third doping region and the sixth doping region respectively.

[0017] In some embodiments, the memory cell structure further includes: a dielectric layer located between the first doping region and the fourth doping region, and between the third doping region and the sixth doping region, and a sidewall surrounding the memory region and extending along the first direction.

[0018] In some embodiments, the dielectric layer includes a first dielectric layer and a second dielectric layer, the second dielectric layer surrounds the sidewall of the storage area extending along the first direction; the first dielectric layer is located on the sidewall of the second dielectric layer away from the storage area.

[0019] In some embodiments, taking a plane perpendicular to the first direction as a reference plane, the orthographic projection of the second doped region on the reference plane is located in the orthographic projection of the storage region on the reference plane; and / or, the orthographic projection of the fifth doped region on the reference plane is located in the orthographic projection of the storage region on the reference plane.

[0020] In some embodiments, taking a plane perpendicular to the first direction as a reference plane, the orthographic projection of the first doped region on the reference plane coincides with the orthographic projection of the fourth doped region on the reference plane; and / or, the orthographic projection of the third doped region on the reference plane coincides with the orthographic projection of the sixth doped region on the reference plane.

[0021] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a method for manufacturing a memory cell structure, comprising: providing a substrate; performing doping and patterning on different regions of the substrate to form a first transistor comprising a first doping region, a second doping region, and a third doping region sequentially connected in contact along a second direction, and forming a memory region located on a side of the second doping region away from the remaining substrate; forming a dielectric layer, the dielectric layer surrounding sidewalls of the memory region extending in the first direction and covering a side of the first doping region and the third doping region away from the remaining substrate; forming a second transistor, the second transistor being located on a side of the dielectric layer and the memory region away from the first transistor; wherein the second transistor comprises a fourth doping region, a fifth doping region, and a sixth doping region sequentially connected in contact along the second direction, the fifth doping region being in contact with the memory region, the first direction and the second direction intersecting, the first doping region, the third doping region, the fourth doping region, and the sixth doping region being doped with first doping ions, the second doping region, the memory region, and the fifth doping region being doped with second doping ions, one of the first doping ions and the second doping ions being N-type doping ions and the other being P-type doping ions.

[0022] In some embodiments, the steps of forming the first transistor and the storage area include: using two different doping processes to dope the second doping ions into the substrate to form an initial first doping area and an initial second doping area, and the remaining substrate is a substrate, the initial second doping area is located on the side of the substrate away from the initial first doping area, and the doping concentration of the second doping ions in the initial second doping area is less than the doping concentration in the initial first doping area; graphing the initial second doping area to form the storage area; using a third doping process to dope the first doping ions into the initial first doping area that is not blocked by the storage area to form the first doping area and the third doping area, and the remaining initial first doping area that is not doped with the first doping ions is the second doping area.

[0023] In some embodiments, the steps of forming the first transistor and the storage area include: using a fourth doping process to dope the second doping ions into the substrate to form an initial third doping area; forming a mask layer with an opening on a side of the initial third doping area away from the remaining substrate; using a fifth doping process to dope the first doping ions into the initial third doping area exposed by the opening to form the first doping area and the third doping area, and the remaining initial third doping area not doped with the first doping ions is the second doping area; and forming the storage area on a side of the second doping area away from the remaining substrate.

[0024] In some embodiments, the step of forming the second transistor includes: forming an initial fourth doping region doped with the second doping ions, the initial fourth doping region being located on a side of the dielectric layer and the storage region away from the first transistor; forming a gate dielectric layer and a gate stacked along the first direction, the gate dielectric layer being located on a side of the initial fourth doping region away from the storage region, and the gate being opposite the storage region; and using a sixth doping process to dope the first doping ions into the initial fourth doping region not blocked by the gate dielectric layer to form the fourth doping region and the sixth doping region, and the remaining initial fourth doping region not doped with the first doping ions is the fifth doping region.

[0025] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a memory cell array structure, comprising: a plurality of memory cell structures as described in any one of the above items; the plurality of memory cell structures are arranged at intervals along the first direction and / or the third direction, and the first direction, the second direction and the third direction intersect with each other.

[0026] In some embodiments, a plurality of the memory cell structures are arranged at intervals along the first direction, a first electrical connection layer and a second electrical connection layer both extend along the first direction, the first electrical connection layer is in contact and connected with the plurality of the memory cell structures arranged at intervals along the first direction, and the second electrical connection layer is also in contact and connected with the plurality of the memory cell structures arranged at intervals along the first direction.

[0027] In some embodiments, the second transistor further includes: a gate dielectric layer located on a side of the fifth doping region along the first direction away from the storage region; a gate located on a side of the gate dielectric layer along the first direction away from the fifth doping region; a plurality of the storage cell structures are arranged at intervals along the third direction, the gate extends along the third direction, and the gate corresponds to the plurality of the storage cell structures arranged at intervals along the third direction.

[0028] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0029] The storage region is not only in contact with the second doped region in the first transistor, but also in contact with the fifth doped region in the second transistor. Thus, charge can be stored in the storage region simultaneously with the aid of the first transistor and the second transistor, thereby improving the charge storage efficiency of the memory cell structure, that is, improving the efficiency of write operations on the memory cell structure, thereby improving the electrical performance of the memory cell structure. Furthermore, the first transistor, the storage region, and the second transistor are stacked along a first direction, which helps reduce the layout area of ​​the memory cell structure in a plane perpendicular to the first direction. Compared to a 1T1C type memory cell structure, the memory cell structure provided in the embodiments of the present disclosure helps reduce its own size. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] 1 to 3 are three-dimensional schematic diagrams of a storage unit structure provided in an embodiment of the present disclosure;

[0032] 4 and 5 are schematic diagrams of two cross-sectional structures of a memory cell structure provided in an embodiment of the present disclosure;

[0033] 6 to 14 are schematic cross-sectional views corresponding to steps in a method for manufacturing a memory cell structure according to another embodiment of the present disclosure;

[0034] FIG15 is a schematic diagram of three circuit structures corresponding to a read / write control method for a memory cell structure provided in another embodiment of the present disclosure;

[0035] 16 and 17 are two three-dimensional structural schematic diagrams of a memory cell array structure provided in yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] As known from the background art, the electrical performance of the capacitor-free memory cell structure needs to be improved.

[0037] The present disclosure provides a memory cell structure, a manufacturing method thereof, and a memory cell array structure. In the memory cell structure, a storage region is in contact and connected not only with the second doped region in the first transistor, but also with the fifth doped region in the second transistor. Thus, charge can be stored in the storage region simultaneously with the aid of the first and second transistors, thereby improving the charge storage efficiency of the memory cell structure, that is, improving the efficiency of write operations on the memory cell structure, thereby improving the electrical performance of the memory cell structure. Furthermore, the first transistor, the storage region, and the second transistor are stacked along a first direction, which helps reduce the layout area of ​​the memory cell structure in a plane perpendicular to the first direction. Compared to a 1T1C type memory cell structure, the memory cell structure provided in the present disclosure helps reduce its own size.

[0038] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0039] An embodiment of the present disclosure provides a memory cell structure. The memory cell structure provided by an embodiment of the present disclosure is described in detail below with reference to the accompanying drawings. Figures 1 to 3 are schematic diagrams of three three-dimensional structures of the memory cell structure provided by an embodiment of the present disclosure; Figures 4 and 5 are schematic diagrams of two cross-sectional structures of the memory cell structure provided by an embodiment of the present disclosure.

[0040] 1 to 5 , the memory cell structure 100 includes: a first transistor 101, a storage region SN, and a second transistor 102 that are sequentially connected in contact along a first direction X; wherein the first transistor 101 includes a first doping region 111, a second doping region 121, and a third doping region 131 that are sequentially connected in contact along a second direction Y; the second transistor 102 includes a fourth doping region 112, a fifth doping region 122, and a sixth doping region 132 that are sequentially connected in contact along the second direction Y; the storage region SN has a first side a and a second side b opposite to each other along the first direction X; the second doping region 121 is in contact with the first side a, and the fifth doping region 122 is in contact with the second side b; the first direction X and the second direction Y intersect; the first doping region 111, the third doping region 131, the fourth doping region 112, and the sixth doping region 132 are all doped with first doping ions, and the second doping region 121, the storage region SN, and the fifth doping region 122 are all doped with second doping ions, one of the first doping ions and the second doping ions is an N-type doping ion, and the other is a P-type doping ion.

[0041] It can be understood that the storage region SN is not only in contact with and connected to the second doped region 121 in the first transistor 101, but also in contact with and connected to the fifth doped region 122 in the second transistor 102. Therefore, charge can be stored in the storage region SN simultaneously with the help of the first transistor 101 and the second transistor 102, thereby facilitating the improvement of the charge storage efficiency of the memory cell structure 100, that is, improving the efficiency of the write operation on the memory cell structure 100, thereby improving the electrical performance of the memory cell structure 100. Moreover, the first transistor 101, the storage region SN, and the second transistor 102 are stacked along the first direction X, which helps to reduce the layout area of ​​the memory cell structure 100 in a plane perpendicular to the first direction X. Compared with the 1T1C type memory cell structure, the memory cell structure 100 provided in the embodiment of the present disclosure helps to reduce its own size.

[0042] In some embodiments, the first doping ion is an N-type ion, and the second doping ion is a P-type ion. In some embodiments, the N-type ion may include at least one of arsenic ions, phosphorus ions, or antimony ions; the P-type ion may include at least one of boron ions, indium ions, or gallium ions. In other embodiments, the first doping ion may be a P-type ion, and the second doping ion may be an N-type ion.

[0043] It should be noted that the following description will be given illustratively with the first doping ion being an N-type ion and the second doping ion being a P-type ion.

[0044] The embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0045] In some embodiments, referring to FIG1 to FIG5 , the first transistor 101 may be a triode, where the first doped region 111 serves as the emitter of the triode, the second doped region 121 serves as the base of the triode, and the third doped region 131 serves as the collector of the triode.

[0046] It is understood that the first transistor 101 can be viewed as two diodes connected together with a common anode. The first transistor 101 can be an NPN bipolar transistor. In normal operation of the first transistor 101, the PN junction formed by the base and emitter, i.e., the emitter junction, is in a forward biased state, while the PN junction formed by the base and collector, i.e., the collector junction, is in a reverse biased state.

[0047] Furthermore, the transistor has a current amplification function, meaning that a small current input to the base is amplified, generating a larger current flowing from the collector to the emitter. Thus, when the first transistor 101 is used as a read transistor in the memory cell structure 100, a smaller amount of charge can be stored in the storage region SN. That is, when the current provided by the storage region SN to the second doped region 121 is smaller, a larger current can be read from the third doped region 131 of the first transistor 101 by utilizing the current amplification function of the first transistor 101. This helps improve the current sensitivity of the memory cell structure 100, enabling the storage and reading of data at a logic level 1 in the memory cell structure 100 using a smaller current, thereby improving the electrical performance of the memory cell structure 100.

[0048] In some embodiments, referring to Figures 1 to 5, the second transistor 102 includes a metal-oxide semiconductor field-effect transistor; the metal-oxide semiconductor field-effect transistor may further include: a gate dielectric layer 142, located on a side of the fifth doping region 122 along the first direction X away from the storage region SN; and a gate 152, located on a side of the gate dielectric layer 142 along the first direction X away from the fifth doping region 122.

[0049] In this way, one of the fourth doping region 112 and the sixth doping region 132 can serve as the source of the second transistor 102, and the other can serve as the drain of the second transistor 102. Part of the fifth doping region 122 serves as the channel region of the second transistor 102 when the second transistor 102 is turned on.

[0050] It is understandable that gate-induced drain leakage (GIDL) exists in the second transistor 102. The working principle of the memory cell structure 100 is described below using an example where the second transistor 102 is an NMOS transistor and the first transistor is a triode.

[0051] The first transistor 101 serves as a read transistor of the memory cell structure 100 , the second transistor 102 serves as a write transistor of the memory cell structure 100 , the fourth doped region 112 serves as a source of the second transistor 102 , and the sixth doped region 132 serves as a drain of the second transistor 102 .

[0052] If a logic level 1 is written to the memory cell structure 100, a large negative voltage is applied to the gate 152, causing the second transistor 102 to be in the off state. A large GIDL is generated in the second transistor 102, flowing from the sixth doping region 132 to the fifth doping region 122. Furthermore, a large GIDL flows from the fifth doping region 122 to the storage region SN. At this time, the voltage at the storage region SN is large, and the first transistor 101 is in a strong electric field environment, resulting in impact ionization. That is, the free carriers inside the first transistor 101 are accelerated to a sufficiently high energy under the action of the strong electric field, and collision excitation generates multiplication. In this way, charge is stored by utilizing both the GIDL phenomenon of the second transistor 102 and the impact ionization phenomenon of the first transistor 101. On the one hand, this is beneficial to increase the amount of charge stored in the storage region SN, and on the other hand, it is beneficial to improve the charge storage efficiency of the memory cell structure 100, so as to complete the writing of the logic level 1 and improve the electrical performance of the memory cell structure 100. It should be noted that the negative voltage is a voltage less than 0V.

[0053] If a logic level 0 is written to the memory cell structure 100 , the gate 152 is grounded to prevent GIDL from being generated in the second transistor 102 , and the first transistor 101 is controlled to be in a non-operating state to prevent current from flowing in the storage area SN to complete the writing of the logic level 0.

[0054] If a read operation is performed on the memory cell structure 100, a small negative voltage is applied to the gate 152 to avoid GIDL in the second transistor 102 and to control the first transistor 101 to be in a normal working state. In this way, if the amount of charge stored in the storage area SN is large, that is, there is a large current in the storage area SN, the current amplification effect of the first transistor 101 can be used to read a larger current from the third doping area 131 of the first transistor 101 to complete the reading of the logic level 1; if the amount of charge stored in the storage area SN is small or even there is no current in the storage area SN, the current amplification effect of the first transistor 101 can be used to read a smaller current from the third doping area 131 of the first transistor 101 or the current read from the third doping area 131 is 0 to complete the reading of the logic level 0. It should be noted that the larger and smaller in the above description are all relative and can be flexibly adjusted according to actual conditions.

[0055] In the above embodiment, the doping concentration of the second doping ions in the second doping region 121 may be greater than the doping concentration in the storage region SN, and the doping concentration of the second doping ions in the second doping region 121 is greater than the doping concentration in the fifth doping region 122 .

[0056] It can be understood that among the second doping region 121, the storage region SN and the fifth doping region 122, the doping concentration of the second doping ions in the second doping region 121 is the largest. This is beneficial to increasing the number of majority carriers in the second doping region 121, so as to increase the collision ionization rate in the first transistor 101, thereby helping to further increase the amount of charge stored in the storage region SN, and further improve the charge storage efficiency of the storage cell structure 100.

[0057] In practical applications, on the premise that the doping concentration of the second doping ions in the second doping region 121 is the largest among the second doping region 121, the doping concentration of the second doping ions in the storage region SN and the fifth doping region 122 may be consistent; or, the doping concentration of the second doping ions in the second doping region 121, the storage region SN and the fifth doping region 122 may all be consistent.

[0058] In some embodiments, the doping concentration of the second doping ions in the second doping region 121 may be in the range of 1×10 18 atom / cm 3 ~1×10 19 atom / cm 3 The doping concentration of the second doping ion in the storage region SN may be in the range of 1×10 16 atom / cm 3 ~8×10 17 atom / cm 3 , and / or, the doping concentration of the second doping ion in the fifth doping region 122 may be in the range of 1×10 16 atom / cm 3 ~8×10 17 atom / cm 3 It should be noted that the doping concentration of the second doping ion in either the storage region SN or the fifth doping region 122 is in the range of 1×10 16 atom / cm 3 ~8×10 17 atom / cm 3 That is, it is not necessary for the second doping ion to have a doping concentration range of 1×10 16 atom / cm 3 ~8×10 17 atom / cm 3 .

[0059] In some embodiments, in addition to being doped with the first doping ions, the first doping region 111 and the third doping region 131 are also doped with a small amount of second doping ions, that is, the doping concentration of the second doping ions in the first doping region 111 is much lower than the doping concentration of the first doping ions in the first doping region 111, and the doping concentration of the second doping ions in the third doping region 131 is much lower than the doping concentration of the first doping ions in the third doping region 131.

[0060] In some embodiments, in addition to being doped with the first doping ions, the fourth doping region 112 and the sixth doping region 132 are also doped with a small amount of second doping ions, that is, the doping concentration of the second doping ions in the fourth doping region 112 is much lower than the doping concentration of the first doping ions in the fourth doping region 112, and the doping concentration of the second doping ions in the sixth doping region 132 is much lower than the doping concentration of the first doping ions in the sixth doping region 132.

[0061] In some embodiments, referring to Figures 2 to 4, the memory cell structure 100 may further include: a first electrical connection layer 103, located on a side of the first doping region 111 away from the second doping region 121 along the second direction Y, and the first electrical connection layer 103 is in contact and connected with the first doping region 111 and the fourth doping region 112 respectively.

[0062] In other embodiments, referring to Figure 5, the memory cell structure 100 may further include: a first electrical connection layer 103, along the second direction Y, the first electrical connection layer 103 penetrates the fourth doping region 112 and penetrates at least part of the thickness of the first doping region 111 to achieve contact connection between the first electrical connection layer 103 and the first doping region 111 and the fourth doping region 112 respectively.

[0063] In this way, the examples shown in Figures 2 to 5 are conducive to using the same first electrical connection layer 103 to control the first doping region 111 and the fourth doping region 112 in the memory cell structure 100, so as to reduce the degree of control of the first transistor 101 and the second transistor 102 in the memory cell structure 100, and simplify the preparation process for forming the memory cell structure 100.

[0064] In some embodiments, referring to Figures 2 to 4, the memory cell structure 100 may further include: a second electrical connection layer 104, located on a side of the third doping region 131 away from the second doping region 121 along the second direction Y, and the second electrical connection layer 104 is in contact and connected with the third doping region 131 and the sixth doping region 132 respectively.

[0065] In other embodiments, referring to Figure 5, the memory cell structure 100 may further include: a second electrical connection layer 104, along the second direction Y, the second electrical connection layer 104 penetrates the sixth doping region 132 and penetrates at least part of the thickness of the third doping region 131 to achieve contact connection between the second electrical connection layer 104 and the third doping region 131 and the sixth doping region 132 respectively.

[0066] In this way, the examples shown in Figures 2 to 5 are conducive to using the same second electrical connection layer 104 to control the third doping region 131 and the sixth doping region 132 in the memory cell structure 100, so as to reduce the degree of control of the first transistor 101 and the second transistor 102 in the memory cell structure 100, and simplify the preparation process for forming the memory cell structure 100.

[0067] In some embodiments, referring to FIG. 2 to FIG. 5 , the memory cell structure 100 may further include a dielectric layer 105 located between the first doping region 111 and the fourth doping region 112 , and between the third doping region 131 and the sixth doping region 132 , as well as sidewalls surrounding the memory region SN and extending along the first direction X. This facilitates electrical insulation between the first doping region 111 and the fourth doping region 112 , between the third doping region 131 and the sixth doping region 132 , and between the memory region SN and the first electrical connection layer 103 and the second electrical connection layer 104 , through the dielectric layer 105 .

[0068] In some embodiments, referring to Figures 3 to 5 , the dielectric layer 105 includes a first dielectric layer 115 and a second dielectric layer 125 , wherein the first dielectric layer 115 surrounds the sidewalls of the storage region SN extending along the first direction X; the second dielectric layer 125 is located on the sidewalls of the first dielectric layer 115 away from the storage region SN, as well as on portions of the sidewalls of the first electrical connection layer 103 extending along the first direction X and portions of the sidewalls of the second electrical connection layer 104 extending along the first direction X. In this manner, while achieving the aforementioned electrical insulation, the first dielectric layer 115 can also support the storage region SN, preventing deformation or even collapse of the storage region SN, thereby improving the structural stability of the memory cell structure 100 and further enhancing the electrical performance of the memory cell structure 100 .

[0069] In some embodiments, the material of the first dielectric layer 115 includes at least one of silicon nitride and silicon oxynitride, and the material of the second dielectric layer 125 includes at least silicon oxide.

[0070] In some embodiments, referring to Figures 1 to 5, taking a plane perpendicular to the first direction X as a reference plane, the orthographic projection of the second doping region 121 on the reference plane is located in the orthographic projection of the storage region SN on the reference plane. This is beneficial to increasing the contact area between the storage region SN and the second doping region 121, so as to reduce the contact resistance between the storage region SN and the second doping region 121, and reduce the probability of carrier recombination in the storage region SN and the second doping region 121, thereby helping to improve the charge storage efficiency of the storage region SN.

[0071] In some embodiments, referring to Figures 1 to 5, the orthographic projection of the fifth doping region 122 on the reference plane is located in the orthographic projection of the storage region SN on the reference plane. This is beneficial to increasing the contact area between the storage region SN and the fifth doping region 122, so as to reduce the contact resistance between the storage region SN and the fifth doping region 122, and reduce the probability of carrier recombination in the storage region SN and the fifth doping region 122, thereby helping to improve the charge storage efficiency of the storage region SN.

[0072] In some embodiments, referring to Figures 1 to 5, the orthographic projection of the first doped region 111 on the reference plane and the orthographic projection of the fourth doped region 112 on the reference plane can overlap. This is beneficial to improving the structural regularity of the first transistor 101 and the second transistor 102, so that the surface of the first electrical connection layer 103 extending along the first direction X is flat, thereby helping to reduce the complexity of preparing the memory cell structure 100.

[0073] In some embodiments, referring to Figures 1 to 5, the orthographic projection of the third doping region 131 on the reference plane and the orthographic projection of the sixth doping region 132 on the reference plane can overlap. This is beneficial to improving the structural regularity of the first transistor 101 and the second transistor 102, so that the surface of the second electrical connection layer 104 extending along the first direction X is flat, thereby helping to reduce the complexity of preparing the memory cell structure 100.

[0074] In some embodiments, referring to Figures 1 to 5, the orthographic projection of the storage region SN on the reference plane and the orthographic projection of the gate 152 on the reference plane can overlap, which is beneficial to improving the structural regularity of the first transistor 101 and the second transistor 102, so as to reduce the complexity of preparing the memory cell structure 100.

[0075] In summary, the storage region SN is not only in contact with and connected to the second doped region 121, but also in contact with and connected to the fifth doped region 122. Therefore, charge can be stored simultaneously in the storage region SN with the aid of the first transistor 101 and the second transistor 102, thereby facilitating improved charge storage efficiency of the memory cell structure 100, that is, improved efficiency of write operations on the memory cell structure 100, thereby improving the electrical performance of the memory cell structure 100. Furthermore, the first transistor 101, the storage region SN, and the second transistor 102 are stacked along the first direction X, which facilitates reducing the layout area of ​​the memory cell structure 100 in a plane perpendicular to the first direction X. Compared to a 1T1C type memory cell structure, the memory cell structure 100 provided in one embodiment of the present disclosure facilitates reduced size.

[0076] Another embodiment of the present disclosure further provides a method for manufacturing a memory cell structure, which is used to form the memory cell structure provided in the above embodiment. The method for manufacturing a memory cell structure provided in another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Figures 6 to 14 are schematic cross-sectional views corresponding to each step in the method for manufacturing a memory cell structure provided in another embodiment of the present disclosure. It should be noted that the parts that are identical or corresponding to the above embodiment will not be described in detail here.

[0077] 1 to 14 , a method for manufacturing a memory cell structure 100 includes: providing a substrate 110; performing doping and patterning on different regions of the substrate 110 to form a first transistor 101 including a first doping region 111, a second doping region 121, and a third doping region 131 that are sequentially contacted and connected along a second direction Y, and forming a storage region SN located on a side of the second doping region 121 away from the remaining substrate 110; forming a dielectric layer 105, the dielectric layer 105 surrounding a sidewall of the storage region SN extending along the first direction X and covering a side of the first doping region 111 and the third doping region 131 away from the remaining substrate 110; forming a second transistor 102, the second transistor 102 Located on a side of the dielectric layer 105 and the storage region SN away from the first transistor 101; wherein the second transistor 102 includes a fourth doping region 112, a fifth doping region 122 and a sixth doping region 132 that are sequentially contacted and connected along the second direction Y, the fifth doping region 122 is in contact and connected to the storage region SN, the first direction X and the second direction Y intersect, the first doping region 111, the third doping region 131, the fourth doping region 112, and the sixth doping region 132 are all doped with first doping ions, the second doping region 121, the storage region SN and the fifth doping region 122 are all doped with second doping ions, one of the first doping ions and the second doping ions is an N-type doping ion, and the other is a P-type doping ion.

[0078] It is understandable that the manufacturing method of the memory cell structure 100 provided in another embodiment of the present disclosure is not unique. Another embodiment of the present disclosure will be described in more detail below using the accompanying drawings as a main example.

[0079] In some embodiments, referring to FIG. 6 to FIG. 8 , forming the first transistor 101 and the storage region SN may include the following steps:

[0080] Referring to Figure 6, two different doping processes are used to dope the second doping ions into the substrate 110 to form an initial first doping region 120 and an initial second doping region 130. The remaining substrate 110 is the substrate 140. The initial second doping region 130 is located on the side of the substrate 140 away from the initial first doping region 120, and the doping concentration of the second doping ions in the initial second doping region 130 is less than the doping concentration in the initial first doping region 120.

[0081] It is understood that the initial first doping region 120 is subsequently used to form the first transistor 101, and the initial second doping region 130 is subsequently used to form the storage region SN. The doping concentration of the second doping ions in the initial second doping region 130 is lower than the doping concentration in the initial first doping region 120, so that the subsequent doping concentration of the second doping ions in the storage region SN can be lower than the doping concentration in the second doping region 121. In practical applications, the doping concentrations of the second doping ions in the initial first doping region 120 and the initial second doping region 130 can also be consistent, that is, the subsequent doping concentrations of the second doping ions in the second doping region 121 and the storage region SN can also be consistent.

[0082] In some embodiments, along the second direction Y, the substrate 140 includes a stacked semiconductor layer 170 and an isolation layer 180. The semiconductor layer 170 may be made of an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material may be silicon or germanium; the crystalline inorganic compound semiconductor material may be silicon carbide, silicon germanium, gallium arsenide, or indium gallium; and the isolation layer 180 may be made of at least one isolation material selected from silicon oxide, silicon nitride, or silicon oxynitride.

[0083] In some embodiments, the steps of forming the initial first doping region 120 and the initial second doping region 130 include: forming the initial first doping region 120 in the substrate 110 using a first doping process; and forming the initial second doping region 130 in the substrate 110 using a second doping process. The process parameters of the first doping process are controlled to be different from the process parameters of the second doping process. For example, both the first doping process and the second doping process are ion implantation processes, and the power of the first doping process is controlled to be greater than the power of the second doping process, so that the depth of the second doping ions implanted into the substrate 110 in the first doping process is greater than the depth of the second doping ions implanted into the substrate 110 in the second doping process, thereby forming the initial first doping region 120 in contact with the substrate 140 and the initial second doping region 130 located on a side of the substrate 140 away from the initial first doping region 120. It should be noted that another embodiment of the present disclosure does not limit the order of forming the initial first doping region 120 and the initial second doping region 130. The initial first doping region 120 can be formed by the first doping process first, and then the initial second doping region 130 can be formed by the second doping process. Alternatively, the initial second doping region 130 can be formed by the second doping process first, and then the initial first doping region 120 can be formed by the first doping process.

[0084] 6 and 7 , the initial second doping region 130 is patterned to form a storage region SN.

[0085] 7 and 8 , the first doping ions are doped into the unblocked initial first doping region 120 of the storage region SN using a third doping process to form a first doping region 111 and a third doping region 131. The remaining initial first doping region 120 not doped with the first doping ions serves as the second doping region 121. Thus, in addition to being doped with the first doping ions, the first doping region 111 and the third doping region 131 are also doped with a small amount of the second doping ions.

[0086] In some other embodiments, referring to FIG. 9 and FIG. 8 , forming the first transistor 101 and the storage region SN may include the following steps:

[0087] 9 , a fourth doping process is used to dope the substrate 110 with second doping ions to form an initial third doping region 150 ; a mask layer 106 having an opening 116 is formed on a side of the initial third doping region 150 away from the remaining substrate 110 .

[0088] 9 and 8 , a fifth doping process is used to dope the first doping ions into the initial third doping region 150 exposed by the opening 116 to form a first doping region 111 and a third doping region 131 , and the remaining initial third doping region 150 not doped with the first doping ions is the second doping region 121 .

[0089] 8 , a storage region SN is formed on a side of the second doping region 121 away from the remaining substrate 110 .

[0090] It should be noted that parts identical or corresponding to the above embodiments are not described in detail here.

[0091] In some further embodiments, forming the first transistor and the storage region may include the following steps: using different doping processes to dope different dopant ions into different regions of the substrate to form the first transistor, for example, performing a seventh doping process on the substrate used to form the first and third doping regions to form the first and third doping regions, and performing an eighth doping process on the substrate used to form the second doping region to form the second doping region. The seventh doping process dopes the substrate with the first dopant ions, while the eighth doping process dopes the substrate with the second dopant ions; and forming a storage region doped with the second dopant ions on a side of the second doping region away from the remaining substrate.

[0092] In some embodiments, after forming the first transistor 101 and before forming the second transistor 102, the manufacturing method further includes the following steps:

[0093] 10 , a first dielectric film 135 is formed to cover the exposed surface of the storage region SN, that is, to cover the top surface of the storage region SN away from the substrate 140 and to cover the sidewalls of the storage region SN extending along the first direction X. A second dielectric film 145 is formed to cover the exposed surface of the first dielectric film 135, that is, to cover the top surface of the first dielectric film 135 away from the substrate 140 and to cover the sidewalls of the first dielectric film 135 extending along the first direction X.

[0094] It should be noted that the structural schematic diagrams corresponding to the steps shown in the subsequent Figures 11 to 13 are based on the example of forming the storage cell structure 100 shown in Figure 5. In actual applications, the storage cell structure 100 shown in Figure 4 can also be formed based on the structural schematic diagram shown in Figure 10.

[0095] In some embodiments, to ultimately form the memory cell structure 100 shown in FIG5 , with reference to FIG10 and FIG11 , the first dielectric film 135 and the second dielectric film 145 are etched back to expose the top surface of the storage region SN away from the substrate 140, leaving the first dielectric film 135 as the first dielectric layer 115. It should be noted that, in order to subsequently form the first electrical connection layer 103 (see FIG5 ) and the second electrical connection layer 104 (see FIG5 ), the remaining second dielectric film 145 and the first doped region 111 and the third doped region 131 formed in FIG8 will also be etched.

[0096] In other embodiments, to ultimately form the memory cell structure 100 shown in FIG. 4 , with reference to FIG. 10 and FIG. 11 , the first dielectric film 135 and the second dielectric film 145 are etched back to expose the top surface of the storage region SN away from the substrate 140. The remaining first dielectric film 135 serves as the first dielectric layer 115, and the remaining second dielectric film 145 serves as the second dielectric layer 125. The first dielectric layer 115 and the second dielectric layer 125 constitute the dielectric layer 105. Subsequently, a first electrical connection layer 103 (see FIG. 4 ) is formed on the side of the dielectric layer 105, the first doped region 111, and the fourth doped region 112 (see FIG. 4 ) away from the storage region SN. A second electrical connection layer 104 (see FIG. 4 ) is formed on the side of the dielectric layer 105, the third doped region 131, and the sixth doped region 132 (see FIG. 4 ) away from the storage region SN.

[0097] In some embodiments, referring to FIG. 12 and FIG. 13 , forming the second transistor 102 may include the following steps:

[0098] 12 , an initial fourth doping region 160 doped with second doping ions is formed. The initial fourth doping region 160 is located on a side of the dielectric layer 105 and the storage region SN away from the first transistor 101 .

[0099] It is understood that the initial fourth doping region 160 is subsequently used to form the fourth doping region 112, the fifth doping region 122, and the sixth doping region 132. In some examples, the doping concentration of the second doping ions in the initial fourth doping region 160 is lower than the doping concentration in the initial first doping region 120, so that the subsequent doping concentration of the second doping ions in the fifth doping region 122 can be lower than the doping concentration in the second doping region 121. In practical applications, the doping concentrations of the second doping ions in the initial fourth doping region 160 and the initial first doping region 120 can also be consistent, that is, the subsequent doping concentrations of the second doping ions in the fifth doping region 122 and the second doping region 121 can also be consistent.

[0100] 12 , a gate dielectric layer 142 and a gate 152 are stacked along the first direction X. The gate dielectric layer 142 is located on a side of the initial fourth doped region 160 away from the storage region SN, and the gate 152 faces the storage region SN.

[0101] In some embodiments, after forming the gate 152 and before forming the fourth doping region 112 , the fifth doping region 122 , and the sixth doping region 132 , referring to FIG. 13 , the manufacturing method may further include forming a protective layer 155 to cover sidewalls of the gate dielectric layer 142 and the gate 152 extending along the first direction X. This prevents damage to the gate dielectric layer 142 and the gate 152 during the subsequent formation of the fourth doping region 112 , the fifth doping region 122 , and the sixth doping region 132 .

[0102] Continuing with FIG13 , the first doping ions are doped into the initial fourth doping region 160 not blocked by the gate dielectric layer 142 using the sixth doping process to form the fourth doping region 112 and the sixth doping region 132. The remaining initial fourth doping region 160 not doped with the first doping ions serves as the fifth doping region 122. Thus, in addition to being doped with the first doping ions, the fifth doping region 122 and the sixth doping region 132 are also doped with a small amount of the second doping ions.

[0103] In other embodiments, forming the second transistor may include the following steps: forming an initial fifth doping region doped with second doping ions; forming a mask layer having an opening on a side of the initial fifth doping region away from the remaining substrate; doping the initial fifth doping region exposed by the opening with first doping ions using a ninth doping process to form a fourth doping region and a sixth doping region, with the remaining initial fifth doping region not doped with the first doping ions serving as the fifth doping region; and forming a gate dielectric layer and a gate electrode on a side of the fifth doping region away from the remaining storage region. Portions identical or corresponding to those in the above embodiments are not further described herein.

[0104] In some further embodiments, forming the second transistor may include the following steps: forming an initial semiconductor layer, and doping different regions of the initial semiconductor layer with different doping ions using different doping processes to form a fourth doping region, a fifth doping region, and a sixth doping region. For example, the initial semiconductor layer used to form the fourth and sixth doping regions is subjected to a seventh doping process to form the fourth and sixth doping regions, and the initial semiconductor layer used to form the fifth doping region is subjected to an eighth doping process to form the fifth doping region. The seventh doping process dopes the initial semiconductor layer with the first doping ions, while the eighth doping process dopes the initial semiconductor layer with the second doping ions; and forming a gate dielectric layer and a gate electrode on a side of the fifth doping region away from the remaining storage region.

[0105] It should be noted that, no matter whether the memory cell structure 100 shown in FIG. 5 or the memory cell structure 100 shown in FIG. 4 is formed, the above three methods can be used to form the second transistor.

[0106] In some embodiments, forming the first electrical connection layer 103 and the second electrical connection layer 104 may include the following steps:

[0107] 13 and 14 , the first doped region 111 and the third doped region 131 formed in FIG. 8 , the fourth doped region 112 and the sixth doped region 132 formed in FIG. 13 , and the remaining second dielectric film 145 are further patterned to form a first contact hole 113 and a second contact hole 114 .

[0108] With reference to FIG14 and FIG5 , a first electrical connection layer 103 is formed to completely fill the first contact hole 113, and a second electrical connection layer 104 is formed to completely fill the second contact hole 114. It should be noted that another embodiment of the present disclosure does not limit the order of forming the first electrical connection layer 103 and the second electrical connection layer 104. The first electrical connection layer 103 may be formed first, followed by the second electrical connection layer 104, or the second electrical connection layer 104 may be formed first, followed by the first electrical connection layer 103.

[0109] In summary, in the memory cell structure 100 formed by the method for manufacturing a memory cell structure provided in another embodiment of the present disclosure, the storage region SN is not only in contact with and connected to the second doped region 121, but also in contact with and connected to the fifth doped region 122. Therefore, charge can be stored simultaneously in the storage region SN by means of the first transistor 101 and the second transistor 102, thereby facilitating improved charge storage efficiency of the memory cell structure 100, that is, improved efficiency of write operations on the memory cell structure 100, thereby improving the electrical performance of the memory cell structure 100. Furthermore, the first transistor 101, the storage region SN, and the second transistor 102 are stacked along the first direction X, which facilitates reducing the layout area of ​​the memory cell structure 100 in a plane perpendicular to the first direction X. Compared to a 1T1C type memory cell structure, the memory cell structure 100 provided in the embodiment of the present disclosure facilitates reduced size.

[0110] Another embodiment of the present disclosure further provides a read / write control method for a memory cell structure, for controlling the memory cell structure provided by the above-described embodiment or the memory cell structure formed by the manufacturing method of the memory cell structure provided by the above-described embodiment. Figure 15 is a schematic diagram of three circuit structures corresponding to the read / write control method for the memory cell structure provided by another embodiment of the present disclosure. It should be noted that the parts that are identical or corresponding to the above-described embodiments are not repeated here.

[0111] The following describes in detail the read and write control method of the memory cell structure 100 with reference to FIG15 and FIG4.

[0112] With reference to 15a in reference Figure 15 and Figure 4, if the memory cell structure 100 is written to logic level 1, a first negative voltage, for example -0.5V, is applied to the gate 152, so that the first transistor 101 is in the off state; the first electrical connection layer 103 is grounded, that is, the voltage at the first electrical connection layer 103 is 0V, so that the voltages at the first doping region 111 and the fourth doping region 112 are both 0V; a first positive voltage, for example 2V, is applied to the second electrical connection layer 104, so that the voltages at the third doping region 131 and the sixth doping region 132 are both 2V.

[0113] In this way, due to the large voltage difference between the gate 152 and the sixth doping region 132, the second transistor 102 is in the off state, and a large GIDL is generated in the second transistor 102, flowing from the sixth doping region 132 to the fifth doping region 122. Furthermore, a large GIDL flows from the fifth doping region 122 to the storage region SN. At this time, the voltage at the storage region SN is large, and the first transistor 101 is in a strong electric field environment, which causes impact ionization. That is, the free carriers inside the first transistor 101 are accelerated to a sufficiently high energy under the action of the strong electric field, and collision excitation causes multiplication. In this way, the GIDL phenomenon of the second transistor 102 and the impact ionization phenomenon of the first transistor 101 are both utilized to store charge. On the one hand, this is beneficial for increasing the amount of charge stored in the storage region SN, and on the other hand, it is beneficial for improving the charge storage efficiency of the memory cell structure 100, thereby completing the writing of the logic level 1 and improving the electrical performance of the memory cell structure 100.

[0114] With reference to 15b in reference Figure 15 and Figure 4, if the memory cell structure 100 is written to logic level 0, the gate 152 is grounded, so that the voltage at the gate 152 is 0V; the first electrical connection layer 103 is grounded, so that the voltage at the first electrical connection layer 103 is 0V, so that the voltages at the first doping region 111 and the fourth doping region 112 are both 0V; a second positive voltage, for example 0.5V, is applied to the second electrical connection layer 104, so that the voltages at the third doping region 131 and the sixth doping region 132 are both 0.5V.

[0115] As such, since the voltage difference between the gate 152 and the sixth doped region 132 is small, the second transistor 102 is in an off state, and GIDL is prevented from occurring in the second transistor 102. Furthermore, the voltage difference between the first doped region 111 and the third doped region 131 in the first transistor 101 is small, thereby controlling the first transistor 101 to be in a non-operating state and extracting hole carriers in the memory cell structure to prevent current from flowing in the memory region SN, thereby completing the writing of a logic level 0.

[0116] With reference to 15c in reference Figure 15 and Figure 4, if a read operation is performed on the memory cell structure 100, a second negative voltage, for example -0.1V, is applied to the gate 152, so that the first transistor 101 is in an off state, and; the first electrical connection layer 103 is grounded, that is, the voltage at the first electrical connection layer 103 is 0V, so that the voltages at the first doping region 111 and the fourth doping region 112 are both 0V; a third positive voltage, for example 1V, is applied to the second electrical connection layer 104, so that the voltages at the third doping region 131 and the sixth doping region 132 are both 1V.

[0117] As such, since the voltage difference between the gate 152 and the sixth doping region 132 is relatively small, the second transistor 102 is in an off state, and GIDL is prevented from being generated in the second transistor 102 .

[0118] If the amount of charge stored in the storage region SN is large, that is, there is a large current in the storage region SN, the voltage at the second doping region 121 is greater than the voltage at the first doping region 111, and the PN junction formed by the two is in a forward biased state. The voltage at the third doping region 131 is greater than the voltage at the second doping region 121, and the PN junction formed by the two is in a reverse biased state, that is, the first transistor 101 is in a normal working state. The current amplification effect of the first transistor 101 can be used to read a larger current from the third doping region 131 of the first transistor 101 to complete the reading of the logic level 1.

[0119] If the amount of charge stored in the storage area SN is small or even there is no current in the storage area SN, the first transistor 101 is in a non-operating state, and the current read from the third doping region 131 is 0, or the voltage at the second doping region 121 is slightly greater than the voltage at the first doping region 111, so that the transistor 101 is in a normal operating state, but the current read from the third doping region 131 of the first transistor 101 by the current amplification effect of the first transistor 101 is small, so as to complete the reading of the logic level 0.

[0120] It should be noted that the first negative voltage and the second negative voltage are both voltages less than 0V, and the absolute value of the first negative voltage is greater than the absolute value of the second negative voltage. The first positive voltage, the second positive voltage, and the third positive voltage are all voltages greater than 0V, and the first positive voltage is greater than the third positive voltage, and the third positive voltage is greater than the second positive voltage. In addition, the numerical values ​​of the first negative voltage, the second negative voltage, the first positive voltage, the second positive voltage, and the third positive voltage illustrated in FIG15 are all reference values, and the ground voltage in the above-mentioned write and read operations is also a reference value. In actual applications, it is only necessary to make the ground voltage greater than the negative voltage and / or less than the positive voltage in the corresponding operation. The positive voltage here is one of the first positive voltage, the second positive voltage, and the third positive voltage, and the negative voltage here is one of the first negative voltage and the second negative voltage.

[0121] It is understandable that, in the above-mentioned writing operation and reading operation, the voltage at each conductive structure can be flexibly adjusted according to actual conditions.

[0122] In summary, the memory cell structure 100 can simultaneously store charge in the storage region SN by means of the first transistor 101 and the second transistor 102, thereby improving the charge storage efficiency of the memory cell structure 100, that is, improving the efficiency of writing operations to the memory cell structure 100, thereby improving the electrical performance of the memory cell structure 100. Moreover, the first transistor 101 has a current amplification function. Thus, the current amplification function of the first transistor 101 can be utilized to read a large current from the third doped region 131 of the first transistor 101, thereby increasing the current sensing sensitivity of the memory cell structure 100, thereby facilitating improved electrical performance of the memory cell structure 100.

[0123] Another embodiment of the present disclosure further provides a memory cell array structure, which will be described in detail below in conjunction with the accompanying drawings. Figures 16 and 17 are schematic diagrams of two three-dimensional structures of a memory cell array structure provided in another embodiment of the present disclosure. It should be noted that parts that are identical or corresponding to the aforementioned embodiments are not repeated here.

[0124] 16 , the memory cell array structure may include: a plurality of memory cell structures 100 as provided in the foregoing embodiments or a plurality of memory cell structures 100 manufactured using the manufacturing method provided in the foregoing embodiments; the plurality of memory cell structures 100 are arranged at intervals along the first direction X.

[0125] In some embodiments, continuing to refer to Figure 16, the first electrical connection layer 103 and the second electrical connection layer 104 both extend along the first direction X, the first electrical connection layer 103 is in contact with and connected to a plurality of storage cell structures 100 arranged at intervals along the first direction X, and the second electrical connection layer 104 is also in contact with and connected to a plurality of storage cell structures 100 arranged at intervals along the first direction X.

[0126] It can be understood that the first electrical connection layer 103 is in contact with the multiple memory cell structures 100 arranged at intervals along the first direction X, which means that the first electrical connection layer 103 is in contact with the first doping region 111 and the fourth doping region 112 in the multiple memory cell structures 100; the second electrical connection layer 104 is also in contact with the multiple memory cell structures 100 arranged at intervals along the first direction X, which means that the second electrical connection layer 104 is in contact with the third doping region 131 and the sixth doping region 132 of the multiple memory cell structures.

[0127] It should be noted that, in FIG16 , the number of memory cell structures 100 arranged at intervals along the first direction X is 2 as an example. In actual applications, the number of memory cell structures 100 arranged at intervals along the first direction X can be 3, 4, 5 or 10, etc., that is, another embodiment of the present disclosure does not limit the number of memory cell structures 100 arranged at intervals along the first direction X in the memory cell array structure.

[0128] In other embodiments, referring to Figure 17, the memory cell array structure may include: a plurality of memory cell structures 100 as provided in the aforementioned embodiments or a plurality of memory cell structures 100 manufactured by the manufacturing method provided in the aforementioned embodiments; the plurality of memory cell structures 100 are arranged at intervals along the third direction Z, and the first direction X, the second direction Y and the third direction Z intersect with each other.

[0129] 17 , in some embodiments, the gate 152 extends along the third direction Z, and the gate 152 corresponds to a plurality of memory cell structures 100 spaced apart along the third direction Z. It will be understood that the gate 152 corresponding to the plurality of memory cell structures 100 spaced apart along the third direction Z means that the gate 152 is in contact with and connected to the gate dielectric layer 142 in the plurality of memory cell structures 100 spaced apart along the third direction Z.

[0130] In some other embodiments, in addition to the gate 152 extending along the third direction Z, the gate dielectric layer 142 also extends along the third direction Z. The gate 152 corresponding to the plurality of memory cell structures 100 spaced apart along the third direction Z means that the gate 152 corresponds to the fifth doped regions 122 in the plurality of memory cell structures 100 spaced apart along the third direction Z, and the gate dielectric layer 142 is in contact with and connected to the fifth doped regions 122 in the plurality of memory cell structures 100 spaced apart along the third direction Z.

[0131] It should be noted that FIG17 uses the example of two memory cell structures 100 arranged at intervals along the third direction Z. In actual applications, the number of memory cell structures 100 arranged at intervals along the third direction Z can be 3, 4, 5, or 10, etc., that is, another embodiment of the present disclosure does not limit the number of memory cell structures 100 arranged at intervals along the third direction Z in the memory cell array structure. In addition, to facilitate clear illustration of each memory cell structure 100, FIG17 uses a perspective drawing method for the gate 152.

[0132] In yet other embodiments, with reference to FIG16 and FIG17 , a memory cell array structure may include: a plurality of memory cell structures 100 as provided in the aforementioned embodiments, or a plurality of memory cell structures 100 manufactured using the manufacturing methods provided in the aforementioned embodiments; the plurality of memory cell structures 100 are arranged at intervals along the first direction X and the third direction Z, and the first direction X, the second direction Y, and the third direction Z intersect with each other. Portions identical or corresponding to the aforementioned embodiments are not further described herein.

[0133] In actual applications, multiple storage cell structures 100 can also be arranged at intervals only along the second direction Y; or, multiple storage cell structures 100 can also be arranged at intervals along the first direction X and the second direction Y; or, multiple storage cell structures 100 can also be arranged at intervals along the third direction Z and the second direction Y; or, multiple storage cell structures 100 can also be arranged at intervals along the first direction X, the second direction Y and the third direction Z.

[0134] In the above embodiment, referring to Figures 16 and 17, the second transistor 102 may further include: a gate dielectric layer 142, located on a side of the fifth doping region 122 along the first direction X away from the storage region SN; and a gate 152, located on a side of the gate dielectric layer 142 along the first direction X away from the fifth doping region 122.

[0135] It should be noted that the read / write control method for the memory cell array structure is similar to the read / write control method for the memory cell structure 100, with the difference being that the memory cell structures 100 that require read / write control in the memory cell array structure are subjected to read / write control as in the aforementioned embodiment, while the memory cell structures 100 that do not require read / write control in the memory cell array structure are simply controlled to be in a non-operating state. Furthermore, the manufacturing method for the memory cell array structure is similar to the manufacturing method for the memory cell structure 100, with the difference being that when forming each individual structure, multiple individual components need to be formed. Furthermore, portions that are identical or corresponding to those in the aforementioned embodiment are not further described here.

[0136] In summary, in the memory cell structure 100, the first transistor 101, the storage region SN, and the second transistor 102 are stacked along the first direction X, which helps reduce the layout area of ​​the memory cell structure 100 in a plane perpendicular to the first direction X and reduces its own size. This helps increase the number of memory cell structures 100 in the memory cell array structure per unit volume, that is, helps improve the integration density of the memory cell array structure. In addition, the improved electrical performance of the memory cell structure 100 helps improve the electrical performance of the memory cell array structure.

[0137] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A storage unit structure (100), comprising: A first transistor (101), a storage region (SN) and a second transistor (102) that are sequentially contact-connected along a first direction (X); wherein the first transistor (101) comprises a first doping region (111), a second doping region (121) and a third doping region (131) which are sequentially contacted and connected along a second direction (Y); the second transistor (102) comprises a fourth doping region (112), a fifth doping region (122) and a sixth doping region (132) which are sequentially contacted and connected along the second direction (Y); the storage region (SN) has a first side (a) and a second side (b) which are opposite to each other along the first direction (X); the second doping region (121) is contacted and connected to the first side (a); the fifth doping region (122) is contacted and connected to the second side (b); and the first direction (X) and the second direction (Y) intersect; The first doping region (111), the third doping region (131), the fourth doping region (112), and the sixth doping region (132) are all doped with first doping ions, and the second doping region (121), the storage region (SN), and the fifth doping region (122) are all doped with second doping ions, and one of the first doping ions and the second doping ions is an N-type doping ion, and the other is a P-type doping ion.

2. The memory cell structure (100) according to claim 1, wherein: The doping concentration of the second doping ions in the second doping region (121) is greater than the doping concentration in the storage region (SN), and the doping concentration of the second doping ions in the second doping region (121) is greater than the doping concentration in the fifth doping region (122).

3. The memory cell structure (100) according to claim 1 or 2, wherein: The doping concentration of the second doping ion in the second doping region (121) is in the range of 1×10 18 atom / cm 3 ~1×10 19 atom / cm 3 ; The doping concentration of the second doping ion in the storage region (SN) is in the range of 1×10 16 atom / cm 3 ~8×10 17 atom / cm 3 , and / or, the doping concentration of the second doping ion in the fifth doping region (122) is in the range of 1×10 16 atom / cm 3 ~8×10 17 atom / cm 3 .

4. The memory cell structure (100) according to claim 1, wherein: The first doping region (111) and the third doping region (131) are also doped with the second doping ions, the doping concentration of the second doping ions in the first doping region (111) is lower than the doping concentration of the first doping ions in the first doping region (111), and the doping concentration of the second doping ions in the third doping region (131) is lower than the doping concentration of the first doping ions in the third doping region (131).

5. The memory cell structure (100) according to claim 1, wherein: The fourth doping region (112) and the sixth doping region (132) are also doped with the second doping ions, the doping concentration of the second doping ions in the fourth doping region (112) is lower than the doping concentration of the first doping ions in the fourth doping region (112), and the doping concentration of the second doping ions in the sixth doping region (132) is lower than the doping concentration of the first doping ions in the sixth doping region (132).

6. The memory cell structure (100) according to any one of claims 1 to 5, wherein: The first transistor (101) comprises a triode.

7. The memory cell structure (100) according to any one of claims 1 to 5, wherein: The second transistor (102) comprises a metal-oxide semiconductor field effect transistor; The metal-oxide semiconductor field effect transistor further comprises: A gate dielectric layer (142) is located on a side of the fifth doping region (122) away from the storage region (SN) along the first direction (X); The gate (152) is located on a side of the gate dielectric layer (142) away from the fifth doping region (122) along the first direction (X).

8. The memory cell structure (100) according to any one of claims 1 to 5, further comprising: A first electrical connection layer (103) is located on a side of the first doping region (111) away from the second doping region (121) along the second direction (Y), and the first electrical connection layer (103) is in contact with and connected to the first doping region (111) and the fourth doping region (112), respectively.

9. The memory cell structure (100) according to any one of claims 1 to 5, further comprising: The second electrical connection layer (104) is located on a side of the third doping region (131) away from the second doping region (121) along the second direction (Y), and the second electrical connection layer (104) is in contact with and connected to the third doping region (131) and the sixth doping region (132), respectively.

10. The memory cell structure (100) according to any one of claims 1 to 5, further comprising: A dielectric layer (105) is located between the first doping region (111) and the fourth doping region (112), between the third doping region (131) and the sixth doping region (132), and surrounds the side wall of the storage region (SN) extending along the first direction (X).

11. The memory cell structure (100) according to claim 10, wherein: The dielectric layer (105) comprises a first dielectric layer (115) and a second dielectric layer (125), wherein the second dielectric layer (125) surrounds the side wall of the storage area (SN) extending along the first direction (X); and the first dielectric layer (115) is located on the side wall of the second dielectric layer (125) away from the storage area (SN).

12. The memory cell structure (100) according to claim 1, wherein: Taking a plane perpendicular to the first direction (X) as a reference plane, an orthographic projection of the second doping region (121) on the reference plane is located in an orthographic projection of the storage region (SN) on the reference plane; And / or, the orthographic projection of the fifth doping region (122) on the reference plane is located in the orthographic projection of the storage region (SN) on the reference plane.

13. The memory cell structure (100) according to claim 1, wherein: Taking a plane perpendicular to the first direction (X) as a reference plane, an orthographic projection of the first doped region (111) on the reference plane coincides with an orthographic projection of the fourth doped region (112) on the reference plane; and / or an orthographic projection of the third doped region (131) on the reference plane coincides with an orthographic projection of the sixth doped region (132) on the reference plane.

14. A method for manufacturing a memory cell structure (100), comprising: Providing a substrate (110); Performing doping and patterning on different regions of the substrate (110) to form a first transistor (101) comprising a first doping region (111), a second doping region (121) and a third doping region (131) that are sequentially contacted and connected along a second direction (Y), and forming a storage region (SN) located on a side of the second doping region (121) away from the rest of the substrate (110); forming a dielectric layer (105), wherein the dielectric layer (105) surrounds the side wall of the storage region (SN) extending along the first direction (X) and covers the first doping region (111) and the third doping region (131) on a side away from the remaining substrate (110); forming a second transistor (102), wherein the second transistor (102) is located on a side of the dielectric layer (105) and the storage area (SN) away from the first transistor (101); The second transistor (102) comprises a fourth doping region (112), a fifth doping region (122) and a sixth doping region (132) which are sequentially contacted and connected along the second direction (Y), the fifth doping region (122) is contacted and connected with the storage region (SN), the first direction (X) and the second direction (Y) intersect, the first doping region (111), the third doping region (131), the fourth doping region (112) and the sixth doping region (132) are all doped with first doping ions, the second doping region (121), the storage region (SN) and the fifth doping region (122) are all doped with second doping ions, and the first doping ions and the first doping ions are connected to each other. One of the two doping ions is an N-type doping ion, and the other is a P-type doping ion.

15. The manufacturing method according to claim 14, wherein: The steps of forming the first transistor (101) and the storage area (SN) include: The second doping ions are doped into the substrate (110) using two different doping processes to form an initial first doping region (120) and an initial second doping region (130), the remaining substrate (110) being a substrate (140), the initial second doping region (130) being located on a side of the substrate (140) away from the initial first doping region (120), and the doping concentration of the second doping ions in the initial second doping region (130) being lower than the doping concentration in the initial first doping region (120); Performing a patterning process on the initial second doping region (130) to form the storage region (SN); The first doping ions are doped into the initial first doping region (120) not blocked by the storage region (SN) using a third doping process to form the first doping region (111) and the third doping region (131); the remaining initial first doping region (120) not doped with the first doping ions is the second doping region (121).

16. The manufacturing method according to claim 14, wherein: The steps of forming the first transistor (101) and the storage area (SN) include: Using a fourth doping process to dope the second doping ions into the substrate (110) to form an initial third doping region (150); forming a mask layer (106) having an opening (116) on a side of the initial third doping region (150) away from the remaining substrate (110); Using a fifth doping process to dope the first doping ions into the initial third doping region (150) exposed by the opening (116) to form the first doping region (111) and the third doping region (131), and the remaining initial third doping region (150) not doped with the first doping ions is the second doping region (121); The storage region (SN) is formed on a side of the second doping region (121) away from the remaining substrate (110).

17. The manufacturing method according to any one of claims 14 to 16, wherein: The step of forming the second transistor (102) comprises: forming an initial fourth doping region (160) doped with the second doping ions, wherein the initial fourth doping region (160) is located on a side of the dielectric layer (105) and the storage region (SN) away from the first transistor (101); forming a gate dielectric layer (142) and a gate electrode (152) stacked and arranged along the first direction (X), wherein the gate dielectric layer (142) is located on a side of the initial fourth doping region (160) away from the storage region (SN), and the gate electrode (152) is directly opposite to the storage region (SN); The first doping ions are doped into the initial fourth doping region (160) not blocked by the gate dielectric layer (142) using a sixth doping process to form the fourth doping region (112) and the sixth doping region (132); the remaining initial fourth doping region (160) not doped with the first doping ions serves as the fifth doping region (122).

18. A memory cell array structure, comprising: A plurality of memory cell structures (100) according to any one of claims 1 to 8; A plurality of the storage unit structures (100) are arranged at intervals along the first direction (X) and / or the third direction (Z), and the first direction (X), the second direction (Y) and the third direction (Z) intersect each other.

19. The memory cell array structure according to claim 18, wherein: The plurality of storage cell structures (100) are arranged at intervals along the first direction (X), the first electrical connection layer (103) and the second electrical connection layer (104) both extend along the first direction (X), the first electrical connection layer (103) is in contact with and connected to the plurality of storage cell structures (100) arranged at intervals along the first direction (X), and the second electrical connection layer (104) is also in contact with and connected to the plurality of storage cell structures (100) arranged at intervals along the first direction (X).

20. The memory cell array structure according to claim 18 or 19, wherein: The second transistor (102) further comprises: a gate dielectric layer (142) located on a side of the fifth doping region (122) away from the storage region (SN) along the first direction (X); and a gate (152) located on a side of the gate dielectric layer (142) away from the fifth doping region (122) along the first direction (X). The plurality of memory cell structures (100) are arranged at intervals along the third direction (Z), the gate (152) extends along the third direction (Z), and the gate (152) corresponds to the plurality of memory cell structures (100) arranged at intervals along the third direction (Z).

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