Gate drive unit and display apparatus

Abstract

A gate drive unit (10) and a display apparatus. The gate drive unit comprises a first frequency-division control line (FDL1), a second frequency-division control line (FDL2), and a plurality of gate drive circuits, wherein an output module (12) of each gate drive circuit is electrically connected to the first frequency-division control line (FDL1) or the second frequency-division control line (FDL2) and to a first node (P) and a second node (Q) in a stage shift module (11), so as to output a first frequency-division control signal (FD1) or a second frequency-division control signal (FD2) to a scan output end of the current-stage gate drive circuit according to signals of the first node (P) and the second node (Q).

Description

Gate driving unit and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving unit and a display device. Background Art

[0002] Display panels using variable-frequency technology can enter a low-frequency mode when in standby mode or when using specific applications. This saves power and helps improve the battery life of the display device. However, existing display panels enter low-frequency mode by switching to a full-screen low-frequency display module, which limits its use in certain scenarios. SUMMARY OF THE INVENTION

[0003] The embodiments of the present application provide a gate driving unit and a display device, which can facilitate frequency division driving of a display panel.

[0004] The present application provides a gate drive unit, comprising: a first frequency-division control line for transmitting a first frequency-division control signal, a second frequency-division control line for transmitting a second frequency-division control signal, and a plurality of cascaded gate drive circuits, each of the gate drive circuits comprising a level transmission module and an output module. The level transmission module receives a level transmission signal from an upper level, a first clock signal, and a second clock signal, and outputs the level transmission signal of the current level to the gate drive circuit of the lower level; the output module is electrically connected to the first frequency-division control line or the second frequency-division control line, a first node, and a second node in the level transmission module, and outputs the first frequency-division control signal or the second frequency-division control signal to a scan output terminal of the gate drive circuit of the current level based on the signals of the first node and the second node.

[0005] Embodiments of the present application also include a display device comprising any of the aforementioned gate drive units and a display panel. The display panel includes a plurality of sub-pixels and a plurality of first scan lines. The plurality of sub-pixels include light-emitting devices and a pixel drive circuit for driving the light-emitting devices to emit light. The pixel drive circuit includes at least one transistor. Gate control signals output by the plurality of gate drive circuits are transmitted via the plurality of first scan lines to control terminals of the transistors in the plurality of pixel drive circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] 1A and 1B are schematic structural diagrams of a gate driving unit provided in an embodiment of the present application;

[0007] 2A and 2B are timing diagrams corresponding to the gate driving unit provided in an embodiment of the present application;

[0008] 3A and 3B are schematic structural diagrams of a display device provided in an embodiment of the present application;

[0009] FIG4 is a schematic structural diagram of a pixel driving circuit provided in an embodiment of the present application;

[0010] 5A and 5B are timing diagrams corresponding to the display device provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0011] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0012] The present application provides a gate drive unit and a display device, including a first frequency-dividing control line, a second frequency-dividing control line, and a plurality of cascaded gate drive circuits. Each gate drive circuit includes a stage transmission module and an output module. The output module is electrically connected to the first frequency-dividing control line or the second frequency-dividing control line and the first node and the second node in the stage transmission module. The output module outputs a first frequency-dividing control signal or a second frequency-dividing control signal to a scan output terminal of the gate drive circuit at the corresponding stage according to signals at the first node and the second node. The level of the gate control signal output by the gate drive circuit via the scan output terminal is controlled by the level of the first frequency-dividing control signal or the second frequency-dividing control signal, thereby achieving control of the effective pulse of the gate control signal. Subsequently, when the gate drive circuit does not need to output an effective pulse so that a display panel using the gate drive circuit can achieve a frequency-dividing function, the level of the first frequency-dividing control signal or the second frequency-dividing control signal can be controlled to control whether the gate control signal has an effective pulse. This controls a transistor of a pixel drive circuit in the display panel using the gate drive circuit to be non-conductive, thereby preventing the corresponding sub-pixel from refreshing display data, thereby achieving the frequency-dividing function of the display panel.

[0013] Specifically, the present application implements the level transmission setting through the level transmission module included in the gate driving circuit, and makes the gate driving circuit include an output module, so that the output module outputs the first frequency division control signal and the second frequency division control signal through the scanning output end according to the signals of the first node and the second node in the level transmission module to generate a gate control signal.

[0014] 1A and 1B are schematic structural diagrams of a gate driving unit provided in an embodiment of the present application. The present application provides a gate driving unit 10 comprising a first frequency division control line FDL1, a second frequency division control line FDL2, and a plurality of cascaded gate driving circuits.

[0015] The first frequency-division control line FDL1 is configured to transmit a first frequency-division control signal FD1 .

[0016] The second frequency-division control line FDL2 is configured to transmit a second frequency-division control signal FD2 .

[0017] The plurality of cascaded gate driving circuits are configured to generate a plurality of gate control signals Scan. Optionally, each of the gate driving circuits includes a stage transmission module 11 and an output module 12.

[0018] The stage transmission module 11 receives an upper stage stage transmission signal Cas, a first clock signal CK1 and a second clock signal CK2, and outputs the current stage transmission signal Cas to the lower stage gate driving circuit.

[0019] The output module 12 is electrically connected to the first frequency-division control line FDL1 or the second frequency-division control line FDL2, the first node P and the second node Q in the stage transmission module 11. The output module 12 outputs the first frequency-division control signal FD1 or the second frequency-division control signal FD2 to the scan output end of the gate drive circuit of this stage according to the signals of the first node P and the second node Q, so that the level state of the gate control signal Scan output by the gate drive circuit through the scan output end is correspondingly controlled by the level state of the first frequency-division control signal FD1 or the second frequency-division control signal FD2, thereby realizing control of the effective pulse of the gate control signal Scan.

[0020] Optionally, the m-th level transmission signal Cas(m) output by the m-th level gate driving circuit through the level transmission output terminal is output to the m+A-th level gate driving circuit, the m+A-th level gate driving circuit receives the m-th level transmission signal Cas(m), the first clock signal CK1 and the second clock signal CK2, and outputs the m+A-th level transmission signal Cas(m+A). The m-th gate drive circuit is electrically connected to the first frequency-dividing control line FDL1 to output the first frequency-dividing control signal FD1 to the scan output terminal of the m-th gate drive circuit, so that the level of the m-th gate control signal Scan output by the m-th gate drive circuit via the scan output terminal is correspondingly controlled by the level of the first frequency-dividing control signal FD1; the m+A-th gate drive circuit is electrically connected to the second frequency-dividing control line FDL2 to output the second frequency-dividing control signal FD2 to the scan output terminal of the m+A-th gate drive circuit, so that the level of the m+A-th gate control signal Scan(m+A) output by the m+A-th gate drive circuit via the scan output terminal is correspondingly controlled by the level of the second frequency-dividing control signal FD2, thereby enabling the two cascaded gate drive circuits to generate corresponding gate control signals Scan according to the first frequency-dividing control signal FD1 and the second frequency-dividing control signal FD2, respectively. m ≥ 1, A ≥ 1.

[0021] Optionally, FIG. 2A to FIG. 2B are timing diagrams corresponding to the gate driving unit provided in an embodiment of the present application. In order to enable the display panel using the gate driving unit 10 to achieve frequency division display, the first frequency division control signal FD1 is partially identical to the second frequency division control signal FD2.

[0022] Optionally, the transistor to which the gate control signal Scan generated by the gate driving unit 10 is applied is a P-type transistor. Then, the first frequency-division control signal FD1 and the second frequency-division control signal FD2 have a period of time in the same high-level state, so that the gate control signal Scan generated by the gate driving unit 10 according to the first frequency-division control signal FD1 and the second frequency-division control signal FD2 has a corresponding high-level state, and then the transistor to which the gate control signal Scan is applied is not turned on, so that the corresponding sub-pixel does not refresh the display data, thereby enabling the display panel to achieve low-frequency display in the part corresponding to the sub-pixel.

[0023] Optionally, the transistor to which the gate control signal Scan generated by the gate driving unit 10 is applied is an N-type transistor. Then, the first frequency-division control signal FD1 and the second frequency-division control signal FD2 have a period in which they are both in a low-level state, so that the gate control signal Scan generated by the gate driving unit 10 according to the first frequency-division control signal FD1 and the second frequency-division control signal FD2 has a corresponding low-level state, and then the transistor to which the gate control signal Scan is applied is not turned on, so that the corresponding sub-pixel does not refresh the display data, thereby enabling the display panel to achieve low-frequency display in the portion corresponding to the sub-pixel.

[0024] Optionally, please continue to refer to FIG. 1B , the output module 12 includes a first output transistor Tso1 and a second output transistor Tso2 .

[0025] The control terminal of the first output transistor Tso1 is electrically connected to the first node P, the input terminal of the first output transistor Tso1 is electrically connected to the first voltage terminal VGH, and the output terminal of the first output transistor Tso1 is electrically connected to the scan output terminal.

[0026] A control terminal of the second output transistor Tso2 is electrically connected to the second node Q, an output terminal of the second output transistor Tso2 is electrically connected to the scan output terminal, and an input terminal of the second output transistor Tso2 is electrically connected to the first frequency division control line FDL1 or the second frequency division control line FDL2, so that when the second output transistor Tso2 is turned on according to the signal of the second node Q, the first frequency division control signal FD1 or the second frequency division control signal FD2 is output to the scan output terminal through the second output transistor Tso2.

[0027] Optionally, please continue to refer to FIG. 1B , the level transmission module 11 includes a first node control module, a second node control module and a level transmission output module.

[0028] The first node control module is electrically connected to the first node P. The first node control module receives the first clock signal CK1 or the second clock signal CK2 to control the signal of the first node P.

[0029] Optionally, the first node control module includes a first transistor T1 and a second transistor T2. The input terminal of the first transistor T1 is electrically connected to the second voltage terminal VGL; the control terminal of the second transistor T2 is electrically connected to the second node Q, the input terminal of the second transistor T2 is electrically connected to the control terminal of the first transistor T1, and the output terminal of the second transistor T2 is electrically connected to the output terminal of the first transistor T1. The control terminal of the first transistor T1 is electrically connected to the first clock signal line CKL1 or the second clock signal line CKL2.

[0030] The second node control module is electrically connected to the second node Q. The second node control module receives the first clock signal CK1, the second clock signal CK2 and the upper-level transmission signal to control the signal of the second node Q.

[0031] Optionally, the second node control module includes a third transistor T3, a fourth transistor T4, and a fifth transistor T5. The input end of the third transistor T3 receives the upper stage transmission signal, and the output end of the third transistor T3 is electrically connected to the second node Q; the control end of the fourth transistor T4 is electrically connected to the first node P, and the input end of the fourth transistor T4 is electrically connected to the first voltage end VGH; the input end of the fifth transistor T5 is electrically connected to the output end of the fourth transistor T4, and the output end of the fifth transistor T5 is electrically connected to the second node Q. The control end of the third transistor T3 is electrically connected to one of the first clock signal line CKL1 and the second clock signal line CKL2, and the control end of the fifth transistor T5 is electrically connected to the other of the first clock signal line CKL1 and the second clock signal line CKL2. Optionally, the control end of the third transistor T3 is electrically connected to the control end of the first transistor T1.

[0032] The stage transmission output module is electrically connected to the first node P, the second node Q and the stage transmission output end of the gate drive circuit. The stage transmission output module outputs the stage transmission signal to the next stage gate drive circuit through the stage transmission output end according to the signals of the first node P and the second node Q.

[0033] Optionally, the stage output module includes a first-stage output transistor T6, a second-stage output transistor T7, a first capacitor C1, and a second capacitor C2. The control terminal of the first-stage output transistor T6 is electrically connected to the first node P, the input terminal of the first-stage output transistor T6 is electrically connected to the first voltage terminal VGH, and the output terminal of the first-stage output transistor T6 is electrically connected to the stage output terminal; the control terminal of the second-stage output transistor T7 is electrically connected to the second node Q, and the output terminal of the second-stage output transistor T7 is electrically connected to the stage output terminal; the first capacitor C1 is connected in series between the input terminal of the first-stage output transistor T6 and the control terminal of the first-stage output transistor T6; and the second capacitor C2 is connected in series between the input terminal of the second-stage output transistor T7 and the control terminal of the second-stage output transistor T7.

[0034] Optionally, the input terminal of the second-stage transmission output transistor T7 may be electrically connected to the second voltage terminal VGL, and the input terminal of the second-stage transmission output transistor T7 may also be electrically connected to the first clock signal line CKL1 or the second clock signal line CKL2.

[0035] Optionally, the first-stage transmission output transistor T6 is a P-type transistor, and the voltage value supplied by the second voltage terminal VGL is smaller than the voltage value supplied by the first voltage terminal VGH.

[0036] Optionally, if the transistor to which the gate control signal Scan is applied is a P-type transistor, then the effective pulse of the gate control signal Scan corresponds to a low-level state; if the transistor to which the gate control signal Scan is applied is an N-type transistor, then the effective pulse of the gate control signal Scan corresponds to a high-level state.

[0037] Optionally, the stage transmission module 11 further includes a shielding module, the shielding module including a shielding transistor T8, the control terminal of the shielding transistor T8 being electrically connected to the third voltage terminal, the input terminal of the shielding transistor T8 being electrically connected to the output terminal of the third transistor T3 and the output terminal of the fifth transistor T5, and the output terminal of the shielding transistor T8 being electrically connected to the control terminal of the second-stage transmission output transistor T7. The second-stage transmission output transistor T7 is a P-type transistor, and the voltage value supplied by the third voltage terminal is equal to the voltage value supplied by the second voltage terminal VGL. The second-stage transmission output transistor T7 is an N-type transistor, and the voltage value supplied by the third voltage terminal is equal to the voltage value supplied by the first voltage terminal VGH.

[0038] Optionally, please continue to refer to Figure 1B. In the gate drive circuit of the mth level, the input end of the second output transistor Tso2 is electrically connected to the first frequency division control line FDL1; the first node control module receives the first clock signal CK1, the control end of the first transistor T1 and the control end of the third transistor T3 are electrically connected to the first clock signal line CKL1 that transmits the first clock signal CK1, and the control end of the fifth transistor T5 and the input end of the second-level transmission output transistor T7 are electrically connected to the second clock signal line CKL2 that transmits the second clock signal CK2. In the m+A-th level gate drive circuit, the input end of the second output transistor Tso2 is electrically connected to the second frequency-division control line FDL2; the first node control module receives the second clock signal CK2, the control end of the first transistor T1 and the control end of the third transistor T3 are electrically connected to the second clock signal line CKL2, and the control end of the fifth transistor T5 and the input end of the second-level transmission output transistor T7 are electrically connected to the first clock signal line CKL1, so that the m+A-th level gate drive circuit and the m-th level gate drive circuit that receive the m-th level transmission signal Cas(m) output by the m-th level gate drive circuit can generate corresponding gate control signals Scan according to the second frequency-division control signal FD2 and the first frequency-division control signal FD1 respectively.

[0039] Optionally, referring to Figures 2A and 2B , in order to enable the cascaded two-stage gate drive circuit to generate the corresponding gate control signal Scan based on the first frequency-divided control signal FD1 and the second frequency-divided control signal FD2, the second clock signal CK2 is partially identical to the first frequency-divided control signal FD1, and the first clock signal CK1 is partially identical to the second frequency-divided control signal FD2. That is, when the display panel using the gate drive unit 10 does not require frequency division display, the second clock signal CK2 is identical to the first frequency-divided control signal FD1 (i.e., both are low or high), and the first clock signal CK1 is identical to the second frequency-divided control signal FD2 (i.e., both are low or high). When the display panel using the gate drive unit 10 requires frequency division display, the second clock signal CK2 is different from the first frequency-divided control signal FD1, the first clock signal CK1 is different from the second frequency-divided control signal FD2, and the first frequency-divided control signal FD1 is identical to the second frequency-divided control signal FD2 (i.e., both are low or high).

[0040] Optionally, the m-th level gate driving circuit and the m+A-th level gate driving circuit may both be odd-level gate driving circuits (e.g., m is an odd number, A is also an even number; or m is an even number, A is also an odd number; the m-th level gate driving circuit and the m+A-th level gate driving circuit constitute an interlaced level transmission), so that the odd-level gate driving circuit generates a corresponding gate control signal Scan according to the first frequency-division control signal FD1 and the second frequency-division control signal FD2; the m-th level gate driving circuit and the m+A-th level gate driving circuit may both be even-level gate driving circuits (e.g., m is an odd number, A is also an odd number; or m is an even number, A is also an even number; the m-th level gate driving circuit and the m+A-th level gate driving circuit constitute an interlaced level transmission), so that the even-level gate driving circuit generates a corresponding gate control signal Scan according to the first frequency-division control signal FD1 and the second frequency-division control signal FD2. In addition, the m-th level gate drive circuit can be one of the odd-level gate drive circuit and the even-level gate drive circuit, and the m+A-th level gate drive circuit is the other of the odd-level gate drive circuit and the even-level gate drive circuit, so that the odd-level gate drive circuit and the even-level gate drive circuit respectively generate corresponding gate control signals Scan according to the first frequency division control signal FD1 and the second frequency division control signal FD2.

[0041] Optionally, in order to reduce the number of control signal lines used in the gate drive circuit, the first frequency division control line FDL1 can be electrically connected to the odd-numbered gate drive circuit, and the second frequency division control line FDL2 can be electrically connected to the even-numbered gate drive circuit, so that the odd-numbered gate drive circuit generates a corresponding gate control signal Scan according to the first frequency division control signal FD1, and the even-numbered gate drive circuit generates a corresponding gate control signal Scan according to the second frequency division control signal FD2.

[0042] Optionally, in the odd-numbered gate drive circuit, the input end of the second output transistor Tso2 is electrically connected to the first frequency division control line FDL1; the first node control module receives the first clock signal CK1, the control end of the first transistor T1 is electrically connected to the first clock signal line CKL1 that transmits the first clock signal CK1, the control end of the third transistor T3 is electrically connected to the first clock signal line CKL1 that transmits the first clock signal CK1, the control end of the fifth transistor T5 is electrically connected to the second clock signal line CKL2 that transmits the second clock signal CK2, and the input end of the second-stage transmission output transistor T7 is electrically connected to the second clock signal line CKL2. In the gate drive circuit of the even-numbered stage, the input end of the second output transistor Tso2 is electrically connected to the second frequency-division control line FDL2; the first node control module receives the second clock signal CK2, the control end of the first transistor T1 is electrically connected to the second clock signal line CKL2 that transmits the second clock signal CK2, the control end of the third transistor T3 is electrically connected to the second clock signal line CKL2, the control end of the fifth transistor T5 is electrically connected to the first clock signal line CKL1, and the input end of the second-stage transmission output transistor T7 is electrically connected to the first clock signal line CKL1.

[0043] Please continue to refer to Figures 1B and 2A. Taking the m-th level gate driving circuit electrically connected to the first frequency division control line FDL1, the m+A-th level gate driving circuit electrically connected to the second frequency division control line FDL2, the transistors included in the multiple gate driving circuits are P-type transistors, the transistors applying the gate control signal Scan are P-type transistors, the multiple gate driving circuits are transmitted row by row, and the display panel applying the gate driving unit 10 starts to implement frequency division display from the m+3 row as an example, the working principle of the gate driving unit 10 is explained.

[0044] The first stage t1: the first frequency division control signal FD1 and the second clock signal CK2 are high, the second frequency division control signal FD2 and the first clock signal CK1 are low, the upper-level stage transmission signal Cas(m-1) received by the m-th stage gate drive circuit is high, and the m+1-th stage gate drive circuit receives the m-th stage transmission signal Cas(m) output by the m-th stage gate drive circuit and is high.

[0045] In the m-th stage gate driving circuit, the first transistor T1 and the third transistor T3 are turned on according to the first clock signal CK1, the second voltage transmitted by the second voltage terminal VGL is transmitted to the first node P through the first transistor T1, the fourth transistor T4, the first-stage transfer output transistor T6 and the first output transistor Tso1 are turned on, the first voltage transmitted by the first voltage terminal VGH is transmitted to the stage transfer output terminal through the first-stage transfer output transistor T6, so that the m-th stage transfer signal Cas(m) output by the m-th stage gate driving circuit has a high level state; the first voltage transmitted by the first voltage terminal VGH is output to the scan output terminal through the first output transistor Tso1, so that the m-th stage gate control signal Scan(m) output by the m-th stage gate driving circuit has a high level state; the upper stage transfer signal Cas(m-1) received by the m-th stage gate driving circuit turns off the second transistor T2, the second-stage transfer output transistor T7 and the second output transistor Tso2; the fifth transistor T5 is turned off according to the second clock signal CK2.

[0046] In the m+1th-stage gate driving circuit, the first transistor T1 and the third transistor T3 are turned off according to the second clock signal CK2, the fourth transistor T4, the first-stage transmission output transistor T6, and the first output transistor Tso1 remain turned on, and the fifth transistor T5 is turned on according to the first clock signal CK1. The first voltage transmitted by the first voltage terminal VGH is transmitted to the second node Q via the fourth transistor T4 and the fifth transistor T5; the first voltage transmitted by the first voltage terminal VGH is transmitted to the stage transmission output terminal via the first-stage transmission output transistor T6, so that the m+1th-stage transmission signal Cas(m+1) output by the m+1th-stage gate driving circuit has a high level state; the first voltage transmitted by the first voltage terminal VGH is output to the scan output terminal via the first output transistor Tso1, so that the m+1th-stage gate control signal Scan(m+1) output by the m+1th-stage gate driving circuit has a high level state; the second transistor T2, the second-stage transmission output transistor T7, and the second output transistor Tso2 remain turned off.

[0047] Second stage t2: the second clock signal CK2 and the first frequency-dividing control signal FD1 are at low levels, and the first clock signal CK1, the second frequency-dividing control signal FD2 and the upstream stage transfer signal Cas(m-1) are at high levels.

[0048] In the m-th stage gate driving circuit, the first transistor T1 and the third transistor T3 are turned off according to the first clock signal CK1, the fourth transistor T4, the first-stage transmission output transistor T6, and the first output transistor Tso1 remain turned on, and the fifth transistor T5 is turned on according to the second clock signal CK2. The first voltage transmitted by the first voltage terminal VGH is transmitted to the second node Q via the fourth transistor T4 and the fifth transistor T5, and the first voltage transmitted by the first voltage terminal VGH is transmitted to the stage transmission output terminal via the first-stage transmission output transistor T6, so that the m-th stage transmission signal Cas(m) output by the m-th stage gate driving circuit has a high level state; the first voltage transmitted by the first voltage terminal VGH is output to the scan output terminal via the first output transistor Tso1, so that the m-th stage gate control signal Scan(m) output by the m-th stage gate driving circuit has a high level state; the second transistor T2, the second-stage transmission output transistor T7, and the second output transistor Tso2 remain turned off.

[0049] The (m+1)th stage gate driving circuit performs the same operation as the (m)th stage gate driving circuit in the first phase t1 .

[0050] In the third stage t3 , the second clock signal CK2 and the first frequency-dividing control signal FD1 are at high levels, and the first clock signal CK1 , the second frequency-dividing control signal FD2 and the upstream transfer signal Cas(m−1) are at low levels.

[0051] In the m-th stage gate driving circuit, the first transistor T1 and the third transistor T3 are turned on according to the first clock signal CK1, the second voltage transmitted by the second voltage terminal VGL is transmitted to the first node P through the first transistor T1, the fourth transistor T4, the first-stage transfer output transistor T6, and the first output transistor Tso1 are turned on, and the first voltage transmitted by the first voltage terminal VGH is transmitted to the stage transfer output terminal through the first-stage transfer output transistor T6, so that the m-th stage transfer signal Cas(m) output by the m-th stage gate driving circuit has a high level state; the upper stage transfer signal Cas(m-1) turns on the second transistor T2, the second-stage transfer output transistor T7, and the second output transistor Tso2, the first clock signal CK1 is transmitted to the first node P through the second transistor T2, the second clock signal CK2 is transmitted to the stage transfer output terminal through the second-stage transfer output transistor T7, the first frequency division control signal FD1 is output to the scan output terminal through the first output transistor Tso1, so that the m-th stage gate control signal Scan(m) output by the m-th stage gate driving circuit has a high level state; the fifth transistor T5 is turned off according to the second clock signal CK2.

[0052] The m+1th stage gate driving circuit performs the same operation as the mth stage gate driving circuit in the second phase t2 , and the m+2th stage gate driving circuit performs the same operation as the m+1th stage gate driving circuit in the second phase t2 .

[0053] Fourth stage t4: the second clock signal CK2 and the first frequency-dividing control signal FD1 are at low levels, and the first clock signal CK1, the second frequency-dividing control signal FD2 and the upstream stage transfer signal Cas(m-1) are at high levels.

[0054] In the m-th stage gate drive circuit, the first transistor T1 and the third transistor T3 are turned off according to the first clock signal CK1, and the second capacitor C2 maintains the second-stage transmission output transistor T7 on, so that the second clock signal CK2 jumps from a high level to a low level and is coupled to the second node Q through the second capacitor C2 to further lower the potential of the second node Q. The second transistor T2, the second-stage transmission output transistor T7, and the second output transistor Tso2 remain on, so that the first clock signal CK1 is transmitted to the first node P through the second transistor T2, so that the first-stage transmission output transistor T6 and the first output transistor Tso1 are turned off; the second clock signal CK2 is output to the stage transmission output terminal through the second-stage transmission output transistor T7, so that the m-th stage transmission signal Cas(m) output by the m-th stage gate drive circuit has a low level state; the first frequency division control signal FD1 is output to the scan output terminal through the second output transistor Tso2, so that the m-th stage gate control signal Scan(m) output by the m-th stage gate drive circuit has a low level state.

[0055] The m+1th level gate driving circuit performs the same operation as the mth level gate driving circuit in the third stage t3, the m+2th level gate driving circuit performs the same operation as the m+1th level gate driving circuit in the third stage t3, and the m+3th level gate driving circuit performs the same operation as the m+2th level gate driving circuit in the third stage t3.

[0056] Fifth stage t5: the second clock signal CK2 and the first frequency division control signal FD1 are high, the first clock signal CK1 and the second frequency division control signal FD2 are low, and the upstream stage transfer signal Cas(m-1) is high.

[0057] In the m-th stage gate driving circuit, the first transistor T1 and the third transistor T3 are turned on according to the first clock signal CK1, the second voltage transmitted by the second voltage terminal VGL is transmitted to the first node P through the first transistor T1, the fourth transistor T4, the first-stage transmission output transistor T6, and the first output transistor Tso1 are turned on, and the first voltage transmitted by the first voltage terminal VGH is transmitted to the stage transmission output terminal through the first-stage transmission output transistor T6, so that the m-th stage transmission signal Cas(m) output by the m-th stage gate driving circuit has a high level state; the first voltage transmitted by the first voltage terminal VGH is output to the scan output terminal through the first output transistor Tso1, so that the m-th stage gate control signal Scan(m) output by the m-th stage gate driving circuit has a high level state; the upper stage transmission signal Cas(m-1) turns off the second transistor T2, the second-stage transmission output transistor T7, and the second output transistor Tso2; the fifth transistor T5 is turned off according to the second clock signal CK2.

[0058] The m+1th level gate driving circuit performs the same operation as the mth level gate driving circuit in the fourth stage t4, the m+2th level gate driving circuit performs the same operation as the m+1th level gate driving circuit in the fourth stage t4, and the m+3th level gate driving circuit performs the same operation as the m+2th level gate driving circuit in the fourth stage t4.

[0059] The sixth stage t6: the second clock signal CK2 and the first frequency-dividing control signal FD1 are at a low level, and the first clock signal CK1, the second frequency-dividing control signal FD2 and the upstream stage transfer signal Cas(m-1) are at a high level.

[0060] The m-th level gate driving circuit performs the same operation as in the second stage t2, the m+1-th level gate driving circuit performs the same operation as in the fifth stage t5, the m+2-th level gate driving circuit performs the same operation as in the fifth stage t5, and the m+3-th level gate driving circuit performs the same operation as in the fifth stage t5.

[0061] Seventh stage t7: the second clock signal CK2, the first frequency division control signal FD1 and the second frequency division control signal FD2 are at high levels, and the first clock signal CK1 and the upstream stage transfer signal Cas(m-1) are at low levels.

[0062] The mth-stage gate driving circuit performs the same operation as in the first stage t1, the m+1th-stage gate driving circuit performs the same operation as in the sixth stage t6, and the m+2th-stage gate driving circuit performs the same operation as in the sixth stage t6.

[0063] In the (m+3)-th stage gate driving circuit, the first transistor T1 and the third transistor T3 are turned off according to the second clock signal CK2, and the second capacitor C2 maintains the second-stage transmission output transistor T7 on, so that the first clock signal CK1 transitions from a high level to a low level and is coupled to the second node Q via the second capacitor C2, thereby further lowering the potential of the second node Q. The second transistor T2, the second-stage transmission output transistor T7, and the second output transistor Tso2 remain on, so that the second clock signal CK2 is transmitted to the first node P via the second transistor T2, thereby turning off the first-stage transmission output transistor T6 and the first output transistor Tso1. The first clock signal CK1 is output to the stage transmission output terminal via the second-stage transmission output transistor T7, so that the (m+3)-th stage transmission signal Cas(m+3) output by the (m+3)-th stage gate driving circuit has a low level state. The first frequency division control signal FD1 is output to the scan output terminal via the second output transistor Tso2, so that the m-th stage gate control signal Scan(m+3) output by the (m+3)-th stage gate driving circuit has a high level state.

[0064] Therefore, the m+3-level gate driving circuit can still provide the m+3-level transmission signal Cas(m+3) to the lower-level gate driving circuit, and the gate control signal Scan(m+3) output by the m+3-level gate driving circuit does not have a valid pulse, so that the transistor electrically connected to the m+3-level gate driving circuit cannot be turned on. Subsequently, when the gate driving unit 10 is used in the display panel, the sub-pixels electrically connected to the m+3-level gate driving circuit will not refresh the display data, so that the display panel can achieve frequency division display in the corresponding area.

[0065] In the eighth stage t8 , the first frequency division control signal FD1 and the second frequency division control signal FD2 are maintained at a high level, and the second clock signal CK2 and the first clock signal CK1 transition between a low level state and a high level state.

[0066] The multi-stage gate drive circuits located after the (m+3)-th gate drive circuit (e.g., the (m+3)-th through (m+C)-th gate circuits) sequentially output multi-stage transfer signals Cas(m+3)-Cas(m+C) with valid pulses based on the first frequency-divided control signal FD1, the second frequency-divided control signal FD2, the second clock signal CK2, and the first clock signal CK1. The multi-stage gate drive circuits located after the (m+3)-th gate drive circuit (e.g., the (m+3)-th through (m+C)-th gate circuits) do not output gate control signals Scan(m+3)-Scan(m+C) with valid pulses. Where C is greater than or equal to 0.

[0067] Until at least one of the first frequency-dividing control signal FD1 and the second frequency-dividing control signal FD2 begins to transition from a high state to a low state, some gate drive circuits in the multi-stage gate drive circuit resume outputting valid pulses. As shown in the ninth stage t9 of Figure 3B , the second clock signal CK2 and the first frequency-dividing control signal FD1 are high, while the first clock signal CK1 and the second frequency-dividing control signal FD2 are low. The m+C+1th-stage gate circuit performs the same operations as the m-th-stage gate drive circuit in the fourth stage t4 during the ninth stage t9, ensuring that the m+C+1th-stage gate control signal Scan(m+C+1) output by the m+C+1th-stage gate circuit contains valid pulses.

[0068] Optionally, the upper stage transmission signal may be inverted, so that the corresponding gate control signal Scan valid pulse is in a high level state.

[0069] It can be understood that in the first gate driving circuit of the multi-stage gate driving circuit, the start signal STV can be used as the upper-stage transmission signal.

[0070] Figures 3A and 3B are structural schematic diagrams of the display device provided in an embodiment of the present application, Figure 4 is a structural schematic diagram of the pixel driving circuit provided in an embodiment of the present application, and Figures 5A and 5B are timing diagrams corresponding to the display device provided in an embodiment of the present application; the embodiment of the present application also includes a display device, including any of the above-mentioned gate driving units 10 and a display panel.

[0071] Optionally, the display panel includes a display area and a non-display area 100 a located outside the display area, wherein the gate driving unit 10 may be located in the non-display area 100 a.

[0072] The display panel includes a plurality of sub-pixels Pi and a plurality of first scan lines SL1. The plurality of sub-pixels Pi include light-emitting devices Di and pixel drive circuits for driving the light-emitting devices Di to emit light. The pixel drive circuits include at least one transistor. Gate control signals Scan output by the plurality of gate drive circuits are transmitted via the plurality of first scan lines SL1 to control terminals of the transistors in the plurality of pixel drive circuits, so that the display panel can control the plurality of sub-pixels Pi to achieve frequency-divided display within a display cycle according to the gate control signals Scan.

[0073] Optionally, when the display panel implements frequency division display, a display cycle includes a write frame WF and a hold frame HF. Within the write frame WF, the first frequency division control signal FD1 and the second frequency division control signal FD2 jump between a high level state and a low level state, so that the plurality of sub-pixels Pi can write display data within the write frame WF to achieve an image update.

[0074] If the transistors to which the multiple gate control signals Scan output by the gate driving unit 10 are applied are P-type transistors, then, in the blanking interval after the write frame WF or in at least one hold frame HF after the write frame WF, the first frequency division control signal FD1 and the second frequency division control signal FD2 may have a period of time in a high-level state, so that the sub-pixels Pi of the corresponding rows do not refresh the written data. If the transistors to which the multiple gate control signals Scan output by the gate driving unit 10 are applied are N-type transistors, then, in the blanking interval after the write frame WF or in at least one hold frame HF after the write frame WF, the first frequency division control signal FD1 and the second frequency division control signal FD2 may have a period of time in a low-level state, so that the sub-pixels Pi of the corresponding rows do not refresh the written data.

[0075] Optionally, the blanking interval includes a horizontal blanking interval and a vertical blanking interval.

[0076] Optionally, the number of times that the first frequency-division control signal FD1 and the second frequency-division control signal FD2 maintain the same level state in each holding frame HF can be the same or different, and the moments when the first frequency-division control signal FD1 and the second frequency-division control signal FD2 maintain the same level state in each holding frame HF can be the same or different, so that the display panel can have different display frequencies corresponding to different rows in a display cycle, thereby realizing frequency-division display at any position.

[0077] Optionally, the light emitting device Di includes an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, etc.

[0078] Optionally, the plurality of first scan lines SL1 are arranged along the second direction y, each first scan line SL1 extends along a first direction x crossing the second direction y, and the plurality of first scan lines SL1 are configured to transmit a plurality of gate control signals Scan.

[0079] 3A , the display panel includes a plurality of data lines DL electrically connected to a plurality of sub-pixels Pi. The plurality of data lines DL are arranged along a first direction x, and each data line DL extends along a second direction y. The plurality of data lines DL are configured to transmit a plurality of data signals.

[0080] Continuing to refer to FIG. 4 , the pixel driving circuit includes a driving transistor Tdr and a data transistor Tda.

[0081] The driving transistor Tdr and the light emitting device Di are connected in series between the first power line Vdd and the second power line Vss. The input end of the data transistor Tda is electrically connected to the corresponding data line DL, and the output end of the data transistor Tda is electrically connected to the input end of the driving transistor Tdr.

[0082] Optionally, the control end of the data transistor Tda of multiple sub-pixels Pi can be electrically connected to the gate driving unit 10 through the first scanning line SL1, so as to control the data transistor Tda of the multiple sub-pixels Pi to be turned on or off through the gate driving circuit, thereby controlling whether data is written into the control end of the driving transistor Tdr to determine whether the sub-pixel Pi performs a display data refresh operation.

[0083] Optionally, referring to FIG. 3A to FIG. 3B and FIG. 4 , the pixel driving circuit further includes a compensation transistor Tc, a reset transistor Ti1 , an initialization transistor Ti2 , a first light emission control transistor Ts1 , and a second light emission control transistor Ts2 .

[0084] The input and output terminals of the compensation transistor Tc are electrically connected between the control terminal of the driving transistor Tdr and the output terminal of the driving transistor Tdr. The compensation transistor Tc is configured to connect the driving transistor Tdr in a diode form. Optionally, the compensation transistor Tc includes an oxide transistor or a silicon transistor.

[0085] The input and output terminals of the reset transistor Ti1 are electrically connected between the first reset line and the control terminal of the drive transistor Tdr. The reset transistor Ti1 is configured to transmit a first reset signal VI1 transmitted by the first reset line to the control terminal of the drive transistor Tdr, thereby resetting the potential of the control terminal of the drive transistor Tdr. Optionally, the reset transistor Ti1 includes an oxide transistor or a silicon transistor.

[0086] The input end of the initial transistor Ti2 is electrically connected to the second reset line, and the output end of the initial transistor Ti2 is electrically connected to the light-emitting device Di. The initial transistor Ti2 is configured to transmit the second reset signal VI2 transmitted by the second reset line to the anode of the light-emitting device Di to initialize the anode potential of the light-emitting device Di.

[0087] The input and output ends of the first light-emitting control transistor Ts1 are electrically connected between the first power line Vdd and the input end of the driving transistor Tdr, and the input and output ends of the second light-emitting control transistor Ts2 are electrically connected between the light-emitting device Di and the output end of the driving transistor Tdr. The first light-emitting control transistor Ts1 and the second light-emitting control transistor Ts2 are configured to control the light-emitting moment of the light-emitting device Di.

[0088] Optionally, the pixel driving circuit of each sub-pixel Pi further includes a third capacitor Cst, and the third capacitor Cst is connected in series between the first power line Vdd and the control terminal of the driving transistor Tdr.

[0089] Optionally, the pixel driving circuit of each sub-pixel Pi further includes a fourth capacitor Cboost, and the fourth capacitor Cboost is connected in series between the control terminal of the driving transistor Tdr and the control terminal of the data transistor Tda.

[0090] Optionally, the pixel driving circuit of each sub-pixel Pi also includes a reset transistor Ti3, the input end of the reset transistor Ti3 is electrically connected to the third reset line, and the output end of the reset transistor Ti3 is electrically connected to the input end of the driving transistor Tdr; the control end of the reset transistor Ti3 is electrically connected to the control end of the initialization transistor Ti2, and the reset transistor Ti3 is configured to transmit the third reset signal VI3 transmitted by the third reset line to the input end of the driving transistor Tdr to reset the potential of the input end of the driving transistor Tdr.

[0091] Optionally, the gate driving unit 10 included in the display panel can also be electrically connected to the control end of at least one of the compensation transistor Tc, reset transistor Ti1, initial transistor Ti2, reset transistor Ti3, first light-emitting control transistor Ts1, and second light-emitting control transistor Ts2 of multiple sub-pixels Pi.

[0092] Optionally, the display panel further includes a plurality of emission control lines EML, a plurality of second scan lines SL2, a plurality of third scan lines SL3, and a plurality of reset control lines VL. The plurality of emission control lines EML, the plurality of second scan lines SL2, the plurality of third scan lines SL3, and the plurality of reset control lines are arranged along the second direction y and extend along the first direction x. The plurality of emission control lines EML are configured to transmit a plurality of emission control signals EMA, the plurality of second scan lines SL2 transmit a plurality of second scan signals Scan2, the plurality of third scan lines SL3 transmit a plurality of third scan signals Scan3, and the plurality of reset control lines VL transmit a reset control signal EMB. Among them, the control end of the data transistor Tda of the multiple sub-pixels Pi located in the same row is electrically connected to the corresponding first scan line SL1 to the gate driving unit 10, the control end of the compensation transistor Tc of the multiple sub-pixels Pi located in the same row is electrically connected to the corresponding second scan line SL2, the control end of the reset transistor Ti1 of the multiple sub-pixels Pi located in the same row is electrically connected to the corresponding third scan line SL3, the control end of the initialization transistor Ti2 of the multiple sub-pixels Pi located in the same row is electrically connected to the corresponding reset control line VL, and the control ends of the first light-emitting control transistor Ts1 and the second light-emitting control transistor Ts2 of the multiple sub-pixels Pi located in the same row are electrically connected to the corresponding light-emitting control line EML.

[0093] Taking the data transistor Tda, in which the control terminal is electrically connected to the gate driver unit 10 and the data transistor Tda is a P-type transistor, as an example, the frequency division display operating principle of the display panel during a display cycle is described. The write frame WF includes a first reset phase tim1, a second reset phase tim2, a data write phase tim3, and a light-emitting phase tim4.

[0094] During the write frame WF, to ensure that the control terminal data of the multiple drive transistors Tdr included in the display panel can be normally written, the first frequency-dividing control signal FD1 transmitted by the first frequency-dividing control line FDL1 electrically connected to the gate drive unit 10 has a transition between a high level state and a low level state, and the second frequency-dividing control signal FD2 transmitted by the second frequency-dividing control line FDL2 electrically connected to the gate drive unit 10 has a transition between a high level state and a low level state, thereby enabling the gate drive unit 10 to output multiple levels of gate control signals Scan with valid pulses during the write frame WF. Therefore, during the write frame WF, the sub-pixels Pi of each row correspondingly undergo a first reset phase tim1, a second reset phase tim2, a data write phase tim3, and a light-emitting phase tim4.

[0095] The working principles of each stage of writing a frame WF are described by taking a row of multiple sub-pixels Pi as an example, as shown in FIG5A .

[0096] In the first reset stage tim1, the initial transistor Ti2 and the reset transistor Ti3 are turned on according to the corresponding reset control signal EMB, and the compensation transistor Tc is turned on according to the corresponding second scan signal Scan2, so that the anode of the light-emitting device Di can be reset according to the second reset signal VI2, and the input end, output end and control end of the driving transistor Tdr can be reset according to the third reset signal VI3.

[0097] In the second reset phase tim2, the reset transistor Ti1 is turned on according to the corresponding third scan signal Scan3, and the compensation transistor Tc is turned on according to the corresponding second scan signal Scan2, so that the output terminal and the control terminal of the driving transistor Tdr are reset according to the second reset signal VI2.

[0098] In the data writing phase tim3 , the data transistor Tda is turned on according to the corresponding first scan signal Scan, and the compensation transistor Tc is turned on according to the corresponding second scan signal Scan2 , so that the control terminal of the driving transistor Tdr can be written with the data signal Vdata.

[0099] In the light emitting stage tim4 , the first light emitting control transistor Ts1 and the second light emitting control transistor Ts2 are turned on according to the light emitting control signal EMA, so that the driving transistor Tdr generates a driving current to drive the corresponding light emitting device Di to emit light.

[0100] Optionally, a third reset phase tin is included between the light-emitting phase tim4 and the data writing phase tim3. In the third reset phase tin, the initial transistor Ti2 and the reset transistor Ti3 are turned on according to the corresponding reset control signal EMB, so that the anode of the light-emitting device Di is reset according to the second reset signal VI2, and the input and output ends of the driving transistor Tdr are reset according to the third reset signal VI3.

[0101] Optionally, the first frequency division control signal FD1 and the second frequency division control signal FD2 are both in a high-level state starting at a first frequency division time tfd1 (if the transistor to which the gate control signal Scan is applied is an N-type, the first frequency division control signal FD1 and the second frequency division control signal FD2 are both in a low-level state starting at the first frequency division time tfd1), respectively transition between a high-level state and a low-level state starting at a second frequency division time tfd2, and are both in a high-level state again starting at a third frequency division time tfd3 (if the transistor to which the gate control signal Scan is applied is an N-type, the first frequency division control signal FD1 and the second frequency division control signal FD2 are both in a low-level state again starting at the third frequency division time tfd3). The first frequency division time tfd1 may correspond to a vertical blanking interval or a horizontal blanking interval, the second frequency division time tfd2 may correspond to a vertical blanking interval or a horizontal blanking interval, and the third frequency division time tfd3 may correspond to a vertical blanking interval or a horizontal blanking interval.

[0102] 5A and 5B , the operating principle of the display panel during a hold frame HF is described below, taking the example of a first frequency division instant tfd1 corresponding to a vertical blanking interval, a second frequency division instant tfd2 and a third frequency division instant tfd3 corresponding to a horizontal blanking interval, and the first frequency division instant tfd1, the second frequency division instant tfd2, and the third frequency division instant tfd3 all falling within the same hold frame HF. For ease of description, the multi-stage gate driving circuits within the first hold frame HF, which are located between the first frequency division instant tfd1 and the second frequency division instant tfd2 and correspond to both the first frequency division control signal FD1 and the second frequency division control signal FD2 being in a high-level state, are denoted as the first-stage gate driving circuit to the mth-stage gate driving circuit; the multi-stage gate driving circuits within the first hold frame HF1, which are located after the second frequency division instant tfd2 and correspond to transitions between the first frequency division control signal FD1 and the second frequency division control signal FD2 being in a high-level state and a low-level state, respectively, are denoted as the m+1th-stage gate driving circuit to the m+nth-stage gate driving circuit. After the third frequency division time tfd3 within the first hold frame HF1, and corresponding to the first frequency division control signal FD1 and the second frequency division control signal FD2 being both high again, the multi-stage first gate driver circuits are recorded as the (m+n+1)th to (z)th gate driver circuits. The plurality of sub-pixels Pi located in rows 1 to m in the display panel are electrically connected to the (1)th to (m)th gate driver circuits, the plurality of sub-pixels Pi located in rows (m+1) to (m+n)th are electrically connected to the (m+1)th to (m+n)th gate driver circuits, and the plurality of sub-pixels Pi located in rows (m+n+1) to (z)th are electrically connected to the (m+n+1)th to (z)th gate driver circuits.

[0103] Then, within the first hold frame HF1, the gate control signals Scan(1) to Scan(m) generated by the 1st-level gate drive circuit to the mth-level gate drive circuit do not output valid pulses, the data transistors Tda of the multiple sub-pixels Pi in the 1st-level mth row are turned off, and the multiple sub-pixels Pi located in the 1st-level mth row maintain the display image of the write frame WF. The gate control signals Scan(m+1) to Scan(m+n) generated by the m+1st-level gate drive circuit to the m+nth-level gate drive circuit have valid pulse outputs, and the multiple sub-pixels Pi located in the m+1st-level m+nth row undergo the various stages of the write frame WF within the first hold frame HF1, so that the multiple sub-pixels Pi located in the m+1th-level m+nth row display an image different from the image displayed in the write frame WF within the first hold frame HF1. The gate control signals Scan(m+n+1)~Scan(z) generated by the m+n+1th to zth-level gate driving circuits do not output valid pulses, and the data transistors Tda of the multiple sub-pixels Pi in the m+n+1th to zth rows are turned off in the first hold frame HF1. ​​The multiple sub-pixels Pi located in the m+n+1th to zth rows maintain the display screen of the write frame WF in the first hold frame HF1.

[0104] Please continue to refer to Figure 5A. Vgdb represents the gate-drain voltage difference of the driving transistor Tdr when the low-frequency display area in the prior art keeps refreshing the display data in the frame HF. Scanb represents the gate control signal applied by the low-frequency display area in the prior art when the low-frequency display area keeps refreshing the display data in the frame HF. Vgd represents the gate-drain voltage difference of the driving transistor Tdr in the low-frequency display area of ​​the present application when the low-frequency display area keeps refreshing the display data in the frame HF. Scan represents the gate control signal applied by the low-frequency display area of ​​the present application when the low-frequency display area keeps refreshing the display data in the frame HF. Since the voltage state of the gate-drain voltage difference of the driving transistor Tdr has an instantaneous bias on the driving transistor Tdr, the threshold value of the driving transistor Tdr is shifted. The positive gate-drain voltage difference of the driving transistor Tdr causes the threshold voltage of the driving transistor Tdr to be positively biased, as shown in ①③⑤⑦ in Figure 5A; the negative gate-drain voltage difference of the driving transistor Tdr causes the threshold voltage of the driving transistor Tdr to be negatively biased, as shown in ②④⑥ in Figure 5A. In the prior art, processes ④ and ⑥ are added to balance the bias effects of ② and ⑦ on the driving transistor Tdr. However, in the prior art, the low-frequency display area does not stop refreshing the display data in the holding frame HF (that is, in the prior art, the gate control signals Scan(1)~Scan(m) generated by the 1st-level gate driving circuit to the mth-level gate driving circuit still output valid pulses, and the gate control signals Scan(m+n+1)~Scan(z) generated by the m+n+1th-level gate driving circuit to the zth-level gate driving circuit still output valid pulses). Compared with the present application, in which the low-frequency display area stops refreshing the display data in the holding frame HF (such as the gate control signals Scan(1)~Scan(m) generated by the 1st-level gate driving circuit to the mth-level gate driving circuit do not output valid pulses, and the gate control signals Scan(m+n+1)~Scan(z) generated by the m+n+1th-level gate driving circuit to the zth-level gate driving circuit do not output valid pulses), the prior art has an additional process ⑤, and the addition of process ⑤ will weaken the effects of processes ④ and ⑥, thereby worsening the offset of the threshold voltage Vth and causing worsening of the flicker. However, the present application does not have process ⑤, and thus will not worsen the offset of the threshold voltage Vth. Therefore, the present application stops outputting the effective pulse of the gate control signal Scan in the corresponding low-frequency display area, which is beneficial to improving the flicker problem.

[0105] Alternatively, the first frequency division control signal FD1 and the second frequency division control signal FD2 may remain at the same high level after the third frequency division time tfd3, and may continue to remain at the same high level until the second hold frame HF2 following the first hold frame HF1. ​​Alternatively, the first frequency division control signal FD1 and the second frequency division control signal FD2 may remain at the same high level after the third frequency division time tfd3, and may continue to remain at the same high level until the vertical blanking interval.

[0106] Taking the example of the first and second frequency-division control signals FD1 and FD2 being in the same high-level state after the third frequency-division time tfd3 and continuing into the vertical blanking interval, within the second hold frame HF2, the first and second frequency-division control signals FD1 and FD2 are again in the same high-level state at the fourth frequency-division time tfd4. If, before the fourth frequency-division time tfd4, the multi-stage gate drive circuits corresponding to the high-level and low-level transitions of the first and second frequency-division control signals FD1 and FD2 are from the first to the m+nth stage gate drive circuits, and after the fourth frequency-division time tfd4, the multi-stage gate drive circuits corresponding to the first and second frequency-division control signals FD1 and FD2 being in the same high-level state are from the m+n+1th to the zth stage gate drive circuits.

[0107] Then, in the second hold frame HF2, the multiple sub-pixels Pi located in the 1st to m+nth rows are turned on by the valid pulses of the gate control signals Scan(1) to Scan(m+n) generated by the 1st-level gate driving circuit to the m+nth-level gate driving circuit, thereby causing the multiple sub-pixels Pi located in the 1st to m+nth rows to display a screen different from the screen displayed in the write frame WF in the second hold frame HF2. The gate control signals Scan(m+n+1) to Scan(z) generated by the m+n+1st-level gate driving circuit to the zth-level gate driving circuit do not have valid pulse outputs, causing the multiple sub-pixels Pi located in the m+n+1st-level to zth rows to maintain the display screen of the write frame WF.

[0108] Similarly, the working principle of a display cycle in the remaining holding frames HF can also be obtained.

[0109] Therefore, within a display cycle, multiple sub-pixels Pi in the 1st to mth rows can be used to display at a first frequency, multiple sub-pixels Pi in the m+1th to m+nth rows can be used to display at a second frequency, and multiple sub-pixels Pi in the m+n+1th to zth rows can be used to display at a third frequency.

[0110] Optionally, the first frequency may be greater than, less than, or equal to the second frequency, so that the first display area and the second display area can display images at different or the same frequencies within a display cycle. Optionally, the third frequency may be equal to the first frequency or the second frequency. Optionally, the third frequency may be different from both the first frequency and the second frequency.

[0111] Optionally, the first frequency may be 1Hz~360Hz, the second frequency may be 1Hz~360Hz, and the third frequency may be 1Hz~360Hz. Optionally, the first frequency may be 60Hz, so that the multiple sub-pixels Pi in the 1st to mth rows can be used to display a display screen with a lower refresh frequency (such as used to continuously display power information, time information, certain signal status information (such as wifi information, traffic information, Bluetooth information, etc.), and also used to display barrage messages, etc.). The second frequency may be 120Hz, so that the multiple sub-pixels Pi in the m+1th to m+nth rows can be used to display a display screen with a higher refresh frequency (such as movie screens, game screens, etc.). The third frequency may be 30Hz, so that the multiple sub-pixels Pi in the m+n+1th to zth rows can be used to display a display screen with a frequency different from that of the first display area and the second display area (such as information used to implement information input functions (such as keyboards, handwriting boxes, etc.), text boxes, comment areas, etc.), as shown in Figure 3B.

[0112] Among them, z can be less than or equal to the number of rows of sub-pixels Pi included in the display panel. In addition, m+n can also be less than or equal to the number of rows of sub-pixels Pi included in the display panel. That is, the number of sub-display areas with different display frequencies in the display panel is greater than or equal to 2. If m+n is equal to the number of rows of sub-pixels Pi included in the display panel, the display panel includes two sub-display areas with different display frequencies; if z is equal to the number of rows of sub-pixels Pi included in the display panel, the display panel includes three sub-display areas with different display frequencies; if z is less than the number of rows of sub-pixels Pi included in the display panel, the display panel includes at least four sub-display areas with different display frequencies. It can be understood that the multiple sub-pixels Pi included in a row can be used as a sub-display area, and the multiple sub-pixels Pi included in multiple consecutive rows can also be used as a sub-display area.

[0113] It is understandable that the number of sub-display areas corresponding to each display period of the display panel may be different, and the corresponding frequency division positions may also be different, so that the display panel is suitable for different application scenarios.

[0114] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A gate driving unit, wherein: include: A first frequency division control line for transmitting a first frequency division control signal, a second frequency division control line for transmitting a second frequency division control signal, and a plurality of cascaded gate drive circuits, each of the gate drive circuits comprising: A level transmission module, the level transmission module receives the upper level level transmission signal, the first clock signal and the second clock signal, and outputs the current level transmission signal to the lower level gate driving circuit; as well as An output module, wherein the output module is electrically connected to the first frequency division control line or the second frequency division control line, and the first node and the second node in the stage transmission module, and the output module outputs the first frequency division control signal or the second frequency division control signal to the scan output end of the gate drive circuit of this stage according to the signals of the first node and the second node.

2. The gate driving unit according to claim 1, wherein: The first frequency division control line is electrically connected to the gate driving circuit of the odd-numbered stages, and the second frequency division control line is electrically connected to the gate driving circuit of the even-numbered stages; The first frequency division control signal is partially identical to the second frequency division control signal.

3. The gate driving unit according to claim 2, wherein: The output module comprises: a first output transistor, wherein a control terminal of the first output transistor is electrically connected to the first node, an input terminal of the first output transistor is electrically connected to a first voltage terminal, and an output terminal of the first output transistor is electrically connected to the scan output terminal; and a second output transistor, wherein a control terminal of the second output transistor is electrically connected to the second node, and an output terminal of the second output transistor is electrically connected to the scan output terminal; Among them, the input end of the second output transistor in the odd-numbered gate driving circuit is electrically connected to the first frequency division control line, and the input end of the second output transistor in the even-numbered gate driving circuit is electrically connected to the second frequency division control line.

4. The gate driving unit according to claim 2, wherein: The level transmission module comprises: A first node control module, electrically connected to the first node, the first node control module receiving the first clock signal or the second clock signal to control a signal of the first node; a second node control module electrically connected to the second node, the second node control module receiving the first clock signal, the second clock signal and the upper level transmission signal to control the signal of the second node; and The level transmission output module is electrically connected to the first node, the second node and the level transmission output terminal of the gate driving circuit. The level transmission output module outputs the level transmission signal of the current level to the gate driving circuit of the next level through the level transmission output terminal according to the signals of the first node and the second node.

5. The gate driving unit according to claim 4, wherein: The first node control module in the odd-numbered gate driving circuit receives the first clock signal, and the first node control module in the even-numbered gate driving circuit receives the second clock signal; The first clock signal is partially identical to the second frequency-division control signal, and the second clock signal is partially identical to the first frequency-division control signal.

6. The gate driving unit according to claim 4, wherein: The first node control module includes: a first transistor, wherein an input terminal of the first transistor is electrically connected to a second voltage terminal; and a second transistor, wherein a control terminal of the second transistor is electrically connected to the second node, an input terminal of the second transistor is electrically connected to the control terminal of the first transistor, and an output terminal of the second transistor is electrically connected to the output terminal of the first transistor; Among them, the control end of the first transistor in the odd-numbered gate driving circuit is electrically connected to the first clock signal line that transmits the first clock signal, and the control end of the first transistor in the even-numbered gate driving circuit is electrically connected to the second clock signal line that transmits the second clock signal.

7. The gate driving unit according to claim 4, wherein: The second node control module includes: a third transistor, wherein an input terminal of the third transistor receives the upper-stage transmission signal, and an output terminal of the third transistor is electrically connected to the second node; a fourth transistor, wherein a control terminal of the fourth transistor is electrically connected to the first node, and an input terminal of the fourth transistor is electrically connected to the first voltage terminal; a fifth transistor, wherein an input terminal of the fifth transistor is electrically connected to an output terminal of the fourth transistor, and an output terminal of the fifth transistor is electrically connected to the second node; Among them, the control end of the third transistor in the odd-numbered gate driving circuit is electrically connected to the first clock signal line transmitting the first clock signal, and the control end of the fifth transistor is electrically connected to the second clock signal line transmitting the second clock signal; the control end of the third transistor in the even-numbered gate driving circuit is electrically connected to the second clock signal line, and the control end of the fifth transistor is electrically connected to the first clock signal line.

8. The gate driving unit according to claim 7, wherein: The level transmission output module comprises: a first-stage transmission output transistor, wherein a control terminal of the first-stage transmission output transistor is electrically connected to the first node, an input terminal of the first-stage transmission output transistor is electrically connected to the first voltage terminal, and an output terminal of the first-stage transmission output transistor is electrically connected to the first stage transmission output terminal; a second-stage transmission output transistor, wherein a control terminal of the second-stage transmission output transistor is electrically connected to the second node, and an output terminal of the second-stage transmission output transistor is electrically connected to the stage transmission output terminal; a first capacitor, the first capacitor being connected in series between the input terminal of the first-stage transmission output transistor and the control terminal of the first-stage transmission output transistor; and A second capacitor, the second capacitor is connected in series between the input terminal of the second-stage transmission output transistor and the control terminal of the second-stage transmission output transistor; Among them, the input end of the second-stage transmission output transistor in the odd-numbered gate driving circuit is electrically connected to the second clock signal line, and the input end of the second-stage transmission output transistor in the even-numbered gate driving circuit is electrically connected to the first clock signal line.

9. The gate driving unit according to claim 8, wherein: The level transmission module also includes: The shielding module comprises a shielding transistor, wherein the control end of the shielding transistor is electrically connected to the third voltage end, the input end of the shielding transistor is electrically connected to the output end of the third transistor and the output end of the fifth transistor, and the output end of the shielding transistor is electrically connected to the control end of the second-stage transmission output transistor.

10. A display device, wherein: include: A gate driving unit, comprising a first frequency division control line for transmitting a first frequency division control signal, a second frequency division control line for transmitting a second frequency division control signal, and a plurality of cascaded gate driving circuits, each of the gate driving circuits comprising a stage transmission module and an output module; The level transmission module receives the upper level transmission signal, the first clock signal and the second clock signal, and outputs the current level transmission signal to the lower level gate driving circuit; The output module is electrically connected to the first frequency division control line or the second frequency division control line, the first node and the second node in the stage transmission module, and the output module outputs the first frequency division control signal or the second frequency division control signal to the scan output terminal of the gate driving circuit of this stage according to the signals of the first node and the second node; as well as The display panel comprises a plurality of sub-pixels and a plurality of first scan lines, wherein the plurality of sub-pixels comprise light-emitting devices and a pixel driving circuit for driving the light-emitting devices to emit light, wherein the pixel driving circuit comprises at least one transistor; Wherein, the gate control signals output by the plurality of gate driving circuits are transmitted to the control ends of the transistors of the plurality of pixel driving circuits via the plurality of first scanning lines.

11. The display device according to claim 10, wherein: A display cycle of the display panel includes a write frame and a hold frame; in a blanking interval after the write frame of the display panel or in at least one hold frame after the write frame, the first frequency division control signal and the second frequency division control signal have a time period in which they are both in a high level state.

12. The display device according to claim 10, wherein: The pixel driving circuit includes a driving transistor and a data transistor, the driving transistor and the light emitting device are connected in series between a first power line and a second power line, an input end of the data transistor is electrically connected to a corresponding data line, and an output end of the data transistor is electrically connected to an input end of the driving transistor; Wherein, the control terminals of the data transistors of the plurality of sub-pixels are electrically connected to the gate driving unit through the first scanning line.

13. The display device according to claim 10, wherein: The first frequency division control line is electrically connected to the gate driving circuit of the odd-numbered stages, and the second frequency division control line is electrically connected to the gate driving circuit of the even-numbered stages; The first frequency division control signal is partially identical to the second frequency division control signal.

14. The display device according to claim 13, wherein: The output module comprises: a first output transistor, wherein a control terminal of the first output transistor is electrically connected to the first node, an input terminal of the first output transistor is electrically connected to a first voltage terminal, and an output terminal of the first output transistor is electrically connected to the scan output terminal; and a second output transistor, wherein a control terminal of the second output transistor is electrically connected to the second node, and an output terminal of the second output transistor is electrically connected to the scan output terminal; Among them, the input end of the second output transistor in the odd-numbered gate driving circuit is electrically connected to the first frequency division control line, and the input end of the second output transistor in the even-numbered gate driving circuit is electrically connected to the second frequency division control line.

15. The display device according to claim 13, wherein: The level transmission module comprises: A first node control module, electrically connected to the first node, the first node control module receiving the first clock signal or the second clock signal to control a signal of the first node; a second node control module electrically connected to the second node, the second node control module receiving the first clock signal, the second clock signal and the upper level transmission signal to control the signal of the second node; and The level transmission output module is electrically connected to the first node, the second node and the level transmission output terminal of the gate driving circuit. The level transmission output module outputs the level transmission signal of the current level to the gate driving circuit of the next level through the level transmission output terminal according to the signals of the first node and the second node.

16. The display device according to claim 15, wherein: The first node control module in the odd-numbered gate driving circuit receives the first clock signal, and the first node control module in the even-numbered gate driving circuit receives the second clock signal; The first clock signal is partially identical to the second frequency-division control signal, and the second clock signal is partially identical to the first frequency-division control signal.

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