Display panel and manufacturing method therefor, and display device

Abstract

A display panel and a manufacturing method therefor, and a display device. The display panel comprises a substrate (10), an array circuit layer (20), a pixel define layer (30), first capacitors (Cst1), and a plurality of sub-pixel units (PX); the array circuit layer (20) comprises a plurality of drive transistors (DT); each sub-pixel unit (PX) comprises a first electrode (40); each first capacitor (Cst1) comprises a first electrode plate (110) and a second electrode plate (120), the pixel define layer (30) covers the first electrode plates (110), the second electrode plates (120) are located on the side of the pixel define layer (30) away from the substrate (10), the orthographic projection of each first electrode plate (110) on the substrate (10) at least partially overlaps the orthographic projection of the corresponding second electrode plate (120) on the substrate (10), and the first electrode plates (110) are connected to the gates of the drive transistors (DT).

Description

Display panel, manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 26, 2023, with application number 202310938917.5. The entire contents of the above application are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of display technology, for example, to a display panel, a manufacturing method thereof, and a display device. Background Art

[0003] Organic Light Emitting Display (OLED) and flat-panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, power saving, thin body, and wide application range, becoming the mainstream display device.

[0004] However, the display effect of OLED display products in related technologies still needs to be improved.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide a display panel, a manufacturing method thereof, and a display device.

[0007] An embodiment of the present application provides a display panel, comprising:

[0008] substrate;

[0009] an array circuit layer, located on the substrate, the array circuit layer comprising a plurality of driving transistors;

[0010] A pixel definition layer and a plurality of sub-pixel units are located on a side of the array circuit layer away from the substrate, wherein the sub-pixel unit includes a first electrode;

[0011] A first capacitor includes a first plate and a second plate, wherein the first plate is arranged in the same layer as the first electrode, the pixel definition layer covers the first plate, the second plate is located on the side of the pixel definition layer away from the substrate, the orthographic projection of the first plate on the substrate and the orthographic projection of the second plate on the substrate at least partially overlap, and the first plate is connected to the gate of the driving transistor.

[0012] The present application also provides a display panel, including:

[0013] substrate;

[0014] an array circuit layer, located on the substrate, the array circuit layer comprising a plurality of driving transistors;

[0015] A pixel definition layer and a plurality of sub-pixel units are located on a side of the array circuit layer away from the substrate, wherein the sub-pixel unit includes a first electrode, and the pixel definition layer includes a pixel definition portion and an opening area formed by the pixel definition portion, wherein the opening area exposes the first electrode;

[0016] a first capacitor, comprising a first plate and a second plate, wherein an orthographic projection of the first plate on the substrate at least partially overlaps with an orthographic projection of the second plate on the substrate, and the first plate is connected to the gate of the driving transistor;

[0017] An isolation portion is located on one side of the substrate, the isolation portion is at least partially arranged around the opening area, the orthographic projection of the isolation portion on the substrate is at least partially overlapped with the orthographic projection of the first electrode on the substrate, and at least part of the isolation portion is reused as the second electrode.

[0018] The present application also provides a method for manufacturing a display panel, including:

[0019] providing a substrate;

[0020] forming an array circuit layer on the substrate, wherein the array circuit layer includes a plurality of driving transistors;

[0021] A first electrode and a first electrode in a sub-pixel unit are formed on a side of the array circuit layer facing away from the substrate, wherein the first electrode is connected to the gate of the driving transistor;

[0022] forming a pixel definition layer on a side of the first plate and the first electrode facing away from the substrate, wherein the pixel definition layer covers the first plate;

[0023] A second electrode plate is formed on the side of the pixel definition layer away from the substrate, the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the second electrode plate on the substrate at least partially overlap, and the first electrode plate and the second electrode plate constitute two electrodes of a first capacitor.

[0024] An embodiment of the present application further provides a display device, which includes the display panel described in any embodiment of the present application.

[0025] The display panel, its manufacturing method, and display device provided in the embodiments of the present application use a first capacitor to store the gate voltage of the driving transistor. For example, the first plate can be arranged in the same layer as the first electrode, and the second plate can be arranged on the side of the pixel definition layer away from the substrate. The first plate and the second plate can be insulated by the pixel definition layer. Using the pixel definition layer as a capacitor dielectric layer between the first plate and the second plate is beneficial to increasing the capacitance value of the first capacitor, thereby improving the stability of the gate voltage of the driving transistor and improving the display effect of the display panel.

[0026] In summary, the technical solution of the present application, by forming a first capacitor and using the first capacitor as a storage capacitor in the pixel circuit, is conducive to increasing the capacitance value of the storage capacitor, avoiding the high pixel density unit (Pixels Per Inch, PPI) design that restricts the capacitance value of the storage capacitor, and improving the stability of the gate voltage of the driving transistor, thereby improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG1 is a top view of a display panel provided in an embodiment of the present application;

[0028] FIG2 is a cross-sectional view of the display panel shown in FIG1 taken along section line BB′;

[0029] FIG3 is a schematic structural diagram of a pixel circuit provided in an embodiment of the present application;

[0030] FIG4 is another cross-sectional view of the display panel shown in FIG1 taken along section line BB′;

[0031] FIG5 is an enlarged view of the M region in the display panel shown in FIG1 ;

[0032] FIG6 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present application;

[0033] FIG7 is a schematic flow chart of a method for manufacturing a display panel provided in an embodiment of the present application;

[0034] FIG8 is a schematic structural diagram of a display panel formed in a portion of steps in a method for manufacturing a display panel according to an embodiment of the present application;

[0035] FIG9 is a schematic structural diagram of a display panel formed in another part of the steps in the method for manufacturing a display panel according to an embodiment of the present application;

[0036] FIG10 is a schematic structural diagram of a display panel formed in another part of the steps in the method for manufacturing a display panel according to an embodiment of the present application;

[0037] FIG11 is a schematic structural diagram of a display panel formed in another part of the steps in the method for manufacturing a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, in addition to the process, method, system, product or equipment comprising a series of steps or units shown in the embodiments of the present application, other processes, methods, systems, products or equipment of this series of steps or units not clearly listed may also be included, or other steps or units inherent to these processes, methods, systems, products or equipment.

[0039] In display panels with high pixel density (Pixels Per Inch, PPI), the limited area of ​​a single sub-pixel makes it difficult to increase the storage capacitor in the pixel circuit, affecting the stability of the gate voltage of the driving transistor in the pixel circuit. This can cause display anomalies such as flickering, bright spots on black screens, and other display issues on the display panel, restricting the improvement of the display effect.

[0040] An embodiment of the present application provides a display panel. FIG1 is a top view of a display panel provided by an embodiment of the present application; FIG2 is a cross-sectional view obtained by cutting the display panel shown in FIG1 along the section line BB'; FIG3 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present application. In conjunction with FIG1 to FIG3, the display panel includes: a substrate 10, an array circuit layer 20, a pixel definition layer 30, a first capacitor Cst1 and a plurality of sub-pixel units PX. The embodiment of the present application forms a first capacitor without adding an additional display panel film layer and a corresponding mask, and uses the first capacitor as a storage capacitor in the pixel circuit, thereby increasing the capacitance value of the storage capacitor, avoiding the high PPI design that restricts the capacitance value of the storage capacitor, improving the stability of the gate voltage of the driving transistor, and improving the display effect of the display panel.

[0041] The array circuit layer 20 is located on the substrate 10 and includes multiple pixel circuits, each of which includes a driving transistor DT. The pixel definition layer 30 and sub-pixel unit PX are located on the side of the array circuit layer 20 facing away from the substrate 10. The sub-pixel unit PX includes a first electrode 40. The first capacitor Cst1 includes a first plate 110 and a second plate 120. The first plate 110 and the first electrode 40 are arranged on the same layer. The pixel definition layer 30 covers the first plate 110. The second plate 120 is located on the side of the pixel definition layer 30 facing away from the substrate 10. The orthographic projection of the first plate 110 on the substrate 10 at least partially overlaps the orthographic projection of the second plate 120 on the substrate 10. The first plate 110 is connected to the gate 220 of the driving transistor DT.

[0042] The substrate 10 can provide protection and support for the display panel. The substrate 10 can be a flexible substrate made of materials such as polyimide (PI), polyethylene naphthalate (PEN), or polyethylene terephthalate (PET), or a mixture of these materials. The substrate 10 can also be a rigid substrate made of materials such as glass.

[0043] The display panel has a display area AA and a non-display area NAA. A plurality of sub-pixel units PX are provided in the display area AA. The sub-pixel units PX are located in the area defined by the pixel definition layer 30. The sub-pixel units PX have a first electrode 40. The pixel circuit is electrically connected to the first electrode 40 of the corresponding sub-pixel unit PX to drive the corresponding sub-pixel unit PX to emit light. Exemplarily, the sub-pixel unit PX includes a light-emitting device D0. The light-emitting device D0 can be an organic light-emitting diode OLED or a micron-sized light-emitting diode Micro-LED. The first electrode 40 is an electrode of the light-emitting device D0, such as an anode. The driving transistor DT and the light-emitting device D0 are connected between a first power line ELVDD and a second power line ELVSS. The driving transistor DT can generate a driving current based on its own gate voltage to drive the light-emitting device D0 to emit light, so that the display panel can display.

[0044] Since there is an overlapping area between the orthographic projection of the first electrode plate 110 on the substrate 10 and the orthographic projection of the second electrode plate 120 on the substrate 10, the pixel definition layer 30 covers the first electrode plate 110, and the second electrode plate 120 is located on the side of the pixel definition layer 30 away from the substrate 10, so that the first electrode plate 110 and the second electrode plate 120 are insulated by the pixel definition layer 30, and the first electrode plate 110 and the second electrode plate 120 can form a first capacitor Cst1. The first electrode plate 110 of the first capacitor Cst1 is connected to the gate 220 of the driving transistor DT, so that the first capacitor Cst1 can be used as a storage capacitor of the pixel circuit to store the gate voltage of the driving transistor DT through the first capacitor Cst1.

[0045] The technical solution of the embodiment of the present application uses the first capacitor Cst1 as a storage capacitor to store the gate voltage of the driving transistor DT. The first plate 110 is arranged in the same layer as the first electrode 40, and the second plate 120 is arranged on the side of the pixel definition layer 30 away from the substrate 10. The first plate 110 and the second plate 120 are insulated by the pixel definition layer 30. Since the dielectric constant of the material of the pixel definition layer 30 is large and its thickness is usually thin, using the pixel definition layer 30 as a capacitor dielectric layer between the first plate 110 and the second plate 120 is beneficial to increasing the capacitance value of the first capacitor Cst1, thereby improving the stability of the gate voltage of the driving transistor DT and improving the display effect of the display panel.

[0046] In summary, the technical solution of the embodiment of the present application can form a first capacitor without adding an additional display panel film layer and a corresponding mask plate. Using the first capacitor as a storage capacitor in the pixel circuit is beneficial to increasing the capacitance value of the storage capacitor and avoiding the high PPI design that restricts the capacitance value of the storage capacitor. By increasing the capacitance value of the storage capacitor, the stability of the gate voltage of the driving transistor is improved, thereby improving the display effect of the display panel.

[0047] There are many specific configuration methods for the first capacitor Cst1 , and several of them are exemplified below.

[0048] In conjunction with Figures 1 to 3, in one embodiment, the sub-pixel unit PX further includes a second electrode 60. The second electrode 60 is located on a side of the pixel definition layer 30 facing away from the substrate 10. The second plate 120 and the second electrode 60 are made of different materials. The second electrode 60 may be the cathode of the light-emitting device D0. The second plate 120 and the second electrode 60 are both located on a side of the pixel definition layer 30 facing away from the substrate 10. The second plate 120 and the second electrode 60 may both be made of a conductive material, and the light transmittance of the second electrode 60 is greater than the light transmittance of the second plate 120. Optionally, the second electrode 120 and the second electrode 60 may be disposed in different layers, that is, they are located in different layers. Although the second electrode 120 and the second electrode 60 are both located on the side of the pixel definition layer 30 facing away from the substrate 10, the second electrode 120 and the second electrode 60 are formed in different film layer manufacturing processes. For example, the second electrode 120 may be first formed on the side of the pixel definition layer 30 facing away from the substrate 10, and then the second electrode 60 may be formed on the side of the pixel definition layer 30 facing away from the substrate 10. By arranging that the second electrode 120 and the second electrode 60 include different materials and / or the second electrode 120 and the second electrode 60 are located in different layers, the second electrode 120 and the second electrode 60 form different structures rather than an integrated structure. The space on the side of the pixel definition layer 30 facing away from the substrate 10 is utilized to separately dispose the second electrode 120 and the second electrode 60, thereby achieving the aforementioned effects while avoiding an increase in the thickness of the display panel.

[0049] Optionally, the pixel definition layer 30 includes a pixel definition portion 310 and an opening area 320 enclosed by the pixel definition portion 310, wherein the opening area 320 exposes the first electrode 40. The pixel definition portion 310 covers the first electrode plate 110, and the second electrode plate 120 is located on the side of the pixel definition portion 310 facing away from the substrate 10. The pixel definition portion 310 separates the first electrode plate 110 and the second electrode plate 120 to insulate the first electrode plate 110 from the second electrode plate 120. The display panel also includes a light-emitting layer 50, which is disposed in the opening area 320 and is located on the side of the first electrode 40 facing away from the substrate 10. The second electrode 60 is located on the side of the light-emitting layer 50 facing away from the substrate 10. The second electrode 60 receives a power supply voltage, and the second electrode plate 120 contacts the second electrode 60 to receive the power supply voltage. The power supply voltage can be a fixed voltage or a variable voltage. For example, the power supply voltage remains constant within the same display cycle, but can vary in different display cycles.

[0050] The pixel definition portion 310 is made of an insulating material with a high dielectric constant and a relatively thin thickness. Using the pixel definition portion 310 as a capacitor dielectric layer between the first plate 110 and the second plate 120 helps increase the capacitance of the first capacitor Cst1, thereby improving the stability of the gate voltage of the drive transistor DT and enhancing the display quality of the display panel. The second electrode 60 is partially located on the side of the light-emitting layer 50 facing away from the substrate 10 and partially located on the side of the pixel definition portion 310 facing away from the substrate 10. The second plate 120 and the second electrode 60 are in contact and electrically connected. The second electrode 60, serving as the cathode of the light-emitting device D0, is connected to the second power line ELVSS. The second power line ELVSS inputs a power supply voltage. In other words, the second power line ELVSS transmits the power supply voltage to the second electrode 60, so that both the second electrode 60 and the second plate 120 receive the power supply voltage. By setting the second plate 120 in contact with the second electrode 60 to input the power supply voltage, the potential of the second plate 120 is fixed within the same display cycle, so that the gate voltage of the driving transistor DT is stored through the first capacitor Cst1. In this way, the power supply voltage can be reused as a fixed voltage that needs to be input to the second plate 120, and there is no need to provide a fixed voltage to the second plate 120 separately, which is beneficial to reducing the number of signal terminals and signal lines used to transmit voltage signals in the display panel, thereby simplifying the structure of the display panel.

[0051] FIG4 is another cross-sectional view of the display panel shown in FIG1 taken along section line BB'. In conjunction with FIG3 and FIG4, in another embodiment, the display panel includes: a substrate 10, an array circuit layer 20, a pixel definition layer 30, a first capacitor Cst1, an isolation portion 70, and a plurality of sub-pixel units PX. The array circuit layer 20 is located on the substrate 10 and includes a plurality of pixel circuits, each of which includes a drive transistor DT. The sub-pixel unit PX includes a first electrode 40. The pixel definition layer 30 and the first electrode 40 are located on a side of the array circuit layer 20 facing away from the substrate 10. The pixel definition layer 30 includes a pixel definition portion 310 and an opening 320 formed by the pixel definition portion 310, exposing the first electrode 40. The first capacitor Cst1 includes a first plate 110 and a second plate 120. The orthographic projection of the first plate 110 on the substrate 10 at least partially overlaps the orthographic projection of the second plate 120 on the substrate 10. The first plate 110 is connected to the gate 220 of the drive transistor DT. The isolation portion 70 is located on the substrate 10 , and the orthographic projection of the isolation portion 70 on the substrate 10 at least partially overlaps with the orthographic projection of the first electrode plate 110 on the substrate 10 . At least a portion of the isolation portion 70 is reused as the second electrode plate 120 .

[0052] The isolation portion 70 includes a conductive material, for example, the isolation portion 70 includes a metal material. The isolation portion 70 can be disposed on a side of the pixel definition layer 30 facing away from the substrate 10, for example, the isolation portion 70 is disposed at least partially around the opening area 320. Optionally, the first electrode 110 and the first electrode 40 are disposed in the same layer, the pixel definition layer 30 covers the first electrode 110, and the isolation portion 70 is located on a side of the pixel definition layer 30 facing away from the substrate 10, such that the first electrode 110 and the isolation portion 70 are insulated by the pixel definition layer 30. The sub-pixel unit PX may include a first electrode 40, a light-emitting layer 50, and a second electrode 60. The isolation portion 70 is located between adjacent sub-pixel units PX to isolate adjacent sub-pixel units PX. Since the first electrode 110 and the isolation part 70 are insulated by the pixel definition layer 30, and the orthographic projection of the isolation part 70 on the substrate 10 overlaps with the orthographic projection of the first electrode 110 on the substrate 10, the isolation part 70 is reused as the second electrode 120, and the first electrode 110 and the isolation part 70 can be used to form a first capacitor Cst1. The first capacitor Cst1 can be used as a storage capacitor. On the basis of achieving the above-mentioned effect, the existing isolation part 70 in the display panel is reused as the second electrode 120, and there is no need to set up the second electrode 120 additionally, which is conducive to simplifying the production process of the display panel.

[0053] Optionally, the isolation portion 70 that is multiplexed as the second plate 120 inputs a power supply voltage, so that the potential of the second plate 120 is fixed within the same display cycle, so as to store the gate voltage of the driving transistor DT through the first capacitor Cst1. In this way, the power supply voltage can be multiplexed as a fixed voltage that needs to be input to the second plate 120, and there is no need to provide a fixed voltage to the second plate 120 separately, which is beneficial to reducing the number of signal terminals and signal lines for transmitting voltage signals in the display panel, thereby simplifying the structure of the display panel.

[0054] Optionally, the isolation portion 70 is located on a side of the pixel defining portion 310 facing away from the substrate 10. The pixel defining portion 310 covers the first electrode 110, and the pixel defining portion 310 insulates the first electrode 110 from the isolation portion 70. The first electrode 40, the light-emitting layer 50, and the second electrode 60 located in the same opening region 320 represent the same sub-pixel unit PX. The light-emitting layer 50 of the sub-pixel unit PX has a gap on the side of the isolation portion 70. That is, the light-emitting layers 50 of multiple sub-pixel units PX are separated on the side of the isolation portion 70, and the light-emitting layers 50 of adjacent sub-pixel units PX are isolated by the isolation portion 70. The second electrode 60 overlaps the isolation portion 70.

[0055] In summary, the technical solution of the embodiment of the present application utilizes the first plate 110 to connect the gate of the driving transistor DT, so that the first plate 110 and the first electrode 40 are arranged in the same layer, the first plate 110 is used as one plate of the first capacitor Cst1, the isolation portion 70 is used as the other plate of the first capacitor Cst1, and the pixel definition portion 310 is used as the capacitor dielectric layer between the two plates. On the basis of achieving the above-mentioned effect, the isolation portion 70 is reused as the second plate 120, and the second electrode 60 is set to overlap the adjacent isolation portion 70 so that the isolation portion 70 inputs the power supply voltage. On the one hand, the power supply voltage can be reused as a fixed voltage that needs to be input to the second plate 120, so that the first capacitor Cst1 is t1 can store the gate voltage of the driving transistor DT, and there is no need to provide a fixed voltage to the isolation part 70 separately, which is beneficial to reducing the number of signal terminals and signal lines used to transmit voltage signals in the display panel, thereby simplifying the structure of the display panel. On the other hand, the second electrode 60 and the isolation part 70 are both input with the power supply voltage, so that the overall resistance of the second electrode 60 and the isolation part 70 is relatively small, so as to alleviate the influence of the voltage drop of the power supply voltage on the second electrode 60 on the power supply voltage, thereby reducing the difference in the power supply voltage input to different areas of the display panel, so as to avoid the sudden change of the power supply voltage and affect the amount of charge stored in the first capacitor Cst1, which helps to ensure the stability of the gate voltage of the driving transistor DT.

[0056] Continuing with FIG4 , the isolation portion 70 optionally includes a first sub-isolating portion 710, a second sub-isolating portion 720, and a third sub-isolating portion 730. The first sub-isolating portion 710, the second sub-isolating portion 720, and the third sub-isolating portion 730 are sequentially stacked and disposed on a side of the pixel defining portion 310 facing away from the substrate 10. Any one of the first sub-isolating portion 710, the second sub-isolating portion 720, and the third sub-isolating portion 730, or at least two adjacent ones, is a conductive isolation portion. The orthographic projection of the conductive isolation portion on the substrate 10 at least partially overlaps with the orthographic projection of the first electrode plate 110 on the substrate 10. At least a portion of the conductive isolation portion is reused as the second electrode plate 120 and inputs a power supply voltage.

[0057] Any of the first sub-isolating portion 710, the second sub-isolating portion 720, and the third sub-isolating portion 730 may be a conductive isolating portion, or the first sub-isolating portion 710 and the second sub-isolating portion 720 may be conductive isolating portions, or the second sub-isolating portion 720 and the third sub-isolating portion 730 may be conductive isolating portions, or the first sub-isolating portion 710, the second sub-isolating portion 720, and the third sub-isolating portion 730 may all be conductive isolating portions. The conductive isolating portion is made of a conductive material (e.g., a metal material). By providing at least a portion of the conductive isolating portion to be reused as the second electrode plate 120 and inputting a power supply voltage, while achieving the aforementioned effects, the conductive isolating portion is reused as the second electrode plate 120, eliminating the need for an additional second electrode plate 120, thereby simplifying the display panel manufacturing process.

[0058] Optionally, along the direction perpendicular to the substrate 10, the cross-sections of the first sub-isolating portion 710 and the third sub-isolating portion 730 are rectangular, and the cross-section of the second sub-isolating portion 720 is rectangular or trapezoidal. When the cross-section of the second sub-isolating portion 720 is trapezoidal, the lower base of the trapezoid is adjacent to the first sub-isolating portion 710, and the upper base of the trapezoid is adjacent to the third sub-isolating portion 720; the orthographic projection of the third sub-isolating portion 730 on the substrate 10 covers the orthographic projection of the first sub-isolating portion 710 on the substrate 10, and the orthographic projection of the third sub-isolating portion 730 on the substrate 10 covers the orthographic projection of the second sub-isolating portion 720 on the substrate 10.

[0059] Exemplarily, the length of the third sub-isolating portion 730 can be set to be greater than or equal to the length of the first sub-isolating portion 710, and the length of the third sub-isolating portion 730 can be greater than or equal to the length of the second sub-isolating portion 720. The length of the second sub-isolating portion 720 can be the length of the side close to the first sub-isolating portion 710 or the third sub-isolating portion 730, wherein the length of each sub-isolating portion refers to the dimension of the edge of each sub-isolating portion parallel to the first direction Y, and the first direction Y is parallel to the surface of the substrate 10 close to the isolation portion 70. In this way, the orthographic projection of the third sub-isolating portion 730 on the substrate 10 can cover the orthographic projection of the first sub-isolating portion 710 on the substrate 10, and the orthographic projection of the third sub-isolating portion 730 on the substrate 10 covers the orthographic projection of the second sub-isolating portion 720 on the substrate 10, that is, along the first direction Y, the third sub-isolating portion 730 is larger than the first sub-isolating portion 710. The edges on both sides of the first sub-isolating portion 710 are retracted relative to the edges on both sides of the third sub-isolating portion 730, and the edges on both sides of the second sub-isolating portion 720 are retracted relative to the edges on both sides of the third sub-isolating portion 730. In this way, when forming the second electrode 60, the second electrodes 60 of adjacent sub-pixel units PX can be separated by the first sub-isolating portion 710 in the isolation portion 70, so that the second electrode 60 is formed between adjacent isolation portions 70, and the second electrode 60 can also be overlapped with the first sub-isolating portion 710, or the second electrode 60 can be overlapped with both the first sub-isolating portion 710 and the second sub-isolating portion 720. When the first sub-isolating portion 710 is a conductive isolation portion, or the first sub-isolating portion 710 and the second sub-isolating portion 720 are both conductive isolation portions, the conductive isolation portion inputs the power supply voltage through the second electrode 60.

[0060] Continuing with FIG4 , the pixel definition portion 310 includes an inorganic insulating layer material. Optionally, the pixel definition portion 310 includes at least one of a silicon oxide layer and a silicon nitride layer. For example, the pixel definition portion 310 can be made of a silicon oxide material, i.e., the pixel definition portion 310 is a silicon oxide layer, or the pixel definition portion 310 can be made of a silicon nitride material, i.e., the pixel definition portion 310 is a silicon nitride layer. Alternatively, the pixel definition portion 310 can include at least one silicon oxide layer and at least one silicon nitride layer stacked together. Using inorganic insulating layer materials such as silicon oxide and / or silicon nitride to form the pixel definition portion 310 helps increase the dielectric constant of the pixel definition portion 310, thereby increasing the capacitance value of the first capacitor Cst1.

[0061] Optionally, the total thickness of the pixel defining portion 310 ranges from 100 nm to 1000 nm. For example, the total thickness of the pixel defining portion 310 may be 500 nm. This can make the thickness of the pixel defining portion 310 thinner, thereby further increasing the capacitance value of the first capacitor Cst1.

[0062] Figure 5 is an enlarged view of region M in the display panel shown in Figure 1 , showing only a portion of the display panel's film layers. In conjunction with Figures 4 and 5 , the first electrode plate 110 can optionally be insulated from the first electrode 40 and positioned between adjacent first electrodes 40. Utilizing the area between adjacent first electrodes 40 for positioning the first electrode plate 110 not only achieves the aforementioned effects but also improves the space utilization of the display panel.

[0063] Optionally, in one embodiment, the first electrode 110 is arranged around the first electrode 40, and the first electrode 110 can form a ring structure around the periphery of the first electrode 40, and the second electrode 120 is arranged around the opening area 320 of the pixel definition layer 30, and the overlapping area of ​​the orthographic projection of the first electrode 110 on the substrate 10 and the orthographic projection of the second electrode 120 on the substrate 10 surrounds the opening area 320. This can further improve the space utilization of the display panel, and at the same time help to increase the area of ​​the first electrode 110 and the second electrode 120, so as to increase the vertical overlapping area of ​​the first electrode 110 and the second electrode 120, thereby increasing the capacitance value of the first capacitor Cst1, further improving the gate voltage stability of the driving transistor DT, and thus improving the display effect.

[0064] In combination with Figures 3 to 5, optionally, the first plate 110 of the first capacitor Cst1 connected to the same pixel circuit is arranged around the first electrode 40 of the sub-pixel unit PX driven by the pixel circuit. Exemplarily, the sub-pixel unit PX includes a sub-pixel unit having a first color light-emitting layer 501, a sub-pixel unit having a second color light-emitting layer 502, and a sub-pixel unit having a third color light-emitting layer 503. The first color, the second color, and the third color are different. For example, the first color is red, the second color is green, and the third color is blue. The first plate 110 of the first capacitor Cst1 connected to each pixel circuit is arranged around the first electrode 40 of the sub-pixel unit PX driven by the pixel circuit, which can facilitate the connection of the first plate 110 to the driving transistor DT in the corresponding pixel circuit, thereby simplifying the manufacturing process of the display panel.

[0065] In conjunction with Figures 2 and 3, the display panel also includes a connecting electrode 250, which is arranged in the same layer as the source 230 or the drain 240 of the driving transistor DT. The connecting electrode 250 is electrically connected to the gate 220 of the driving transistor DT and the first electrode plate 110, respectively. The first electrode plate 110 is connected to the gate 220 of the driving transistor DT through the connecting electrode 250, and the orthographic projection of the connecting electrode 250 on the substrate 10 overlaps with the orthographic projection of the gate 220 of the driving transistor DT on the substrate 10.

[0066] Exemplarily, the transistor shown in Figure 3 can be a driving transistor DT. Since the orthographic projection of the first electrode 110 on the substrate 10 overlaps with the orthographic projection of the second electrode 120 on the substrate 10, the connecting electrode 250 is electrically connected to the gate 220 of the driving transistor DT and the first electrode 110, respectively, and the orthographic projection of the connecting electrode 250 on the substrate 10 overlaps with the orthographic projection of the gate 220 of the driving transistor DT on the substrate 10. The first capacitor Cst1 can also be equivalent to the capacitor formed by the gate 220 of the driving transistor DT and the second electrode 120, and the second electrode 120 inputs a fixed voltage to store the gate voltage of the driving transistor DT through the first capacitor Cst1, which is equivalent to increasing the vertical overlapping area between the gate 220 of the driving transistor DT and the second electrode 120, which is beneficial to increasing the capacitance value of the first capacitor Cst1.

[0067] FIG2 shows a case where the connecting electrode 250 is directly electrically connected to the first electrode plate 110. In conjunction with FIG3 and FIG4 , in another embodiment, the display panel further includes a connecting portion 260 connected between the first electrode plate 110 and the connecting electrode 250. The connecting portion 260 is located in the metal layer between the first electrode plate 110 and the connecting electrode 250 to electrically connect the first electrode plate 110 and the connecting electrode 250.

[0068] 3 and 4 , the array circuit layer 20 includes a plurality of metal layers, an insulating layer is provided between two adjacent metal layers, the plurality of metal layers include a first metal layer M1 and a second metal layer M2, the gate 220 of the driving transistor DT is located in the first metal layer M1, the array circuit layer 20 further includes a third electrode 130 located in the second metal layer M2, the orthographic projection of the third electrode 130 on the substrate 10 at least partially overlaps with the orthographic projection of the gate 220 of the driving transistor DT on the substrate 10, and the third electrode 130 and the gate 220 of the driving transistor DT constitute two plates of the second capacitor Cst2.

[0069] Exemplarily, the third plate 130 inputs a fixed voltage. For example, the third plate 130 is electrically connected to the first power line ELVDD so that the power voltage is transmitted to the third plate 130 via the first power line ELVDD. As the fixed voltage input to the third plate 130, the third plate 130 and the gate 220 of the driving transistor DT can form a second capacitor Cst2 to store the gate voltage of the driving transistor DT via the second capacitor Cst2. The first power line ELVDD inputs a first power voltage, and the second power line ELVSS inputs a second power voltage. That is, the second plate 120 contacts the second electrode 60 to input the second power voltage. The first power voltage and the second power voltage are different. For example, the voltage value of the first power voltage is a positive number, and the voltage value of the second power voltage is a negative number or 0. The technical solution of the embodiment of the present application, on the basis of achieving the aforementioned effects, uses the first capacitor Cst1 and the second capacitor Cst2 together as the storage capacitor of the pixel circuit. In this way, the total capacitance of the storage capacitor of the pixel circuit is the sum of the capacitance values ​​of the first capacitor Cst1 and the second capacitor Cst2. Even in a high PPI design, the capacitance value of the storage capacitor can be increased to further enhance the stability of the gate voltage of the driving transistor DT, thereby further improving the display effect of the display panel.

[0070] Continuing to refer to Figure 4, the array circuit layer 20 also includes an active layer 210, a third metal layer M3 and a fourth metal layer M4. The active layer 210, the first metal layer M1, the second metal layer M2, the third metal layer M3 and the fourth metal layer M4 are stacked in sequence on one side of the substrate 10. The source 230 and the drain 240 of the driving transistor DT and the connecting electrode 250 can all be set in the third metal layer M3, and the connecting portion 260 can be set in the fourth metal layer M4. Optionally, the display panel further includes a first encapsulation layer 810, a second encapsulation layer 820 and a third encapsulation layer 830, the first encapsulation layer 810 is formed on the side of the second electrode 60 and the isolation portion 70 facing away from the substrate 10, the first encapsulation layer 810 covers the second electrode 60 and at least part of the isolation portion 70, the second encapsulation layer 820 is formed on the side of the first encapsulation layer 810 and the isolation portion 70 facing away from the substrate 10, the second encapsulation layer 820 covers the first encapsulation layer 810 and the isolation portion 70, and the third encapsulation layer 830 is formed on the side of the second encapsulation layer 820 facing away from the substrate 10 and covers the second encapsulation layer 820.

[0071] FIG6 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application. Referring to FIG6 , the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a driving transistor DT, and also includes a first capacitor Cst1 and a second capacitor Cst2 in any of the above embodiments. Exemplarily, the working phases of the pixel circuit include an initialization phase, a data writing phase, and a light-emitting phase. In the initialization phase, the third transistor T3 and the fourth transistor T4 can be controlled to be turned on in response to the first scanning signal S1, and the initialization voltage input by the initialization signal line Vref is transmitted to the gate of the driving transistor DT through the third transistor T3 to initialize the gate voltage of the driving transistor DT, and the driving transistor DT is controlled to be turned on, and the initialization voltage input by the initialization signal line Vref is transmitted to the anode of the light-emitting device D0 through the fourth transistor T4 to initialize the anode voltage of the light-emitting device D0. During the data writing phase, the first transistor T1 and the second transistor T2 are controlled to be turned on in response to the second scan signal S2, so that the data voltage input from the data line Data can be transmitted to the gate of the driving transistor DT in sequence through the first transistor T1, the driving transistor DT, and the second transistor T2. This makes the gate voltage of the driving transistor DT correlated with both the data voltage and the threshold voltage of the driving transistor DT. Threshold voltage compensation is achieved while the data voltage is being written into the driving transistor DT, and the gate voltage of the driving transistor DT is stored by the first capacitor Cst1 and the second capacitor Cst2. During the light-emitting phase, the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on in response to the light-emitting control signal EM, and the first transistor T1 to the fourth transistor T4 are all turned off, forming a conductive path between the first power line ELVDD and the second power line ELVSS. The driving transistor DT can generate a driving current based on the voltage stored in the first capacitor Cst1 and the second capacitor Cst2, thereby driving the light-emitting device D0 to emit light.

[0072] The technical solution of the embodiment of the present application uses the first capacitor Cst1 and the second capacitor Cst2 together as the storage capacitor of the pixel circuit, which can increase the capacitance value of the storage capacitor to avoid the high PPI design restricting the capacitance value of the storage capacitor, and helps to improve the stability of the gate voltage of the driving transistor DT, thereby improving the display effect of the display panel.

[0073] The present application also provides a method for manufacturing a display panel, which is used to manufacture the display panel in any of the above embodiments. FIG7 is a flow chart of a method for manufacturing a display panel provided in an embodiment of the present application. Referring to FIG7 , the method specifically includes the following steps:

[0074] S110, providing a substrate.

[0075] S120 , forming an array circuit layer on the substrate, wherein the array circuit layer includes a plurality of driving transistors.

[0076] S130 , forming a first electrode and a first electrode in the sub-pixel unit on a side of the array circuit layer facing away from the substrate, wherein the first electrode is connected to the gate of the driving transistor.

[0077] Figures 8 to 11 are schematic diagrams of the structure of a display panel formed in the steps of a method for manufacturing a display panel provided in an embodiment of the present application. Referring to Figure 8 , a substrate 10 is provided, and an array circuit layer 20 is formed on substrate 10. Multiple pixel circuits are formed in array circuit layer 20, each of which includes a driver transistor DT. Exemplarily, array circuit layer 20 includes an active layer 210, a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4. The gate 220 of the driver transistor DT is located in the first metal layer M1, and the source 230 and drain 240 of the driver transistor DT are located in the third metal layer M3.

[0078] After the array circuit layer 20 is formed, a first electrode 40 and a first electrode plate 110 are formed on the side of the array circuit layer 20 facing away from the substrate 10. For example, the first electrode 40 and the first electrode plate 110 can be arranged on the side of the fourth metal layer M4 facing away from the substrate 10. The first electrode plate 110 can be connected to the gate 220 of the driving transistor through the connecting portion 260 in the fourth metal layer M4 and the connecting electrode 250 in the third metal layer M3.

[0079] S140 , forming a pixel definition layer on a side of the first plate and the first electrode facing away from the substrate, wherein the pixel definition layer covers the first plate.

[0080] S150, forming a second electrode plate on a side of the pixel definition layer away from the substrate, wherein the orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the second electrode plate on the substrate, and the first electrode plate and the second electrode plate constitute two electrodes of a first capacitor.

[0081] 9 , a pixel definition layer 30 is formed on the side of the first electrode 40 and the first electrode plate 110 facing away from the substrate 10. Referring to FIG10 , a second electrode plate 120 is formed on the side of the pixel definition layer 30 facing away from the substrate 10, such that the orthographic projection of the first electrode plate 110 on the substrate 10 and the orthographic projection of the second electrode plate 120 on the substrate 10 at least partially overlap. The first electrode plate 110 and the second electrode plate 120 constitute two plates of a first capacitor Cst1.

[0082] The technical solution of the embodiment of the present application can form a first capacitor without adding an additional display panel film layer and a corresponding mask plate. Using the first capacitor as a storage capacitor in the pixel circuit is beneficial to increasing the capacitance value of the storage capacitor and avoiding the high PPI design that restricts the capacitance value of the storage capacitor. By increasing the capacitance value of the storage capacitor, the stability of the gate voltage of the driving transistor is improved, thereby improving the display effect of the display panel.

[0083] Referring to Figure 10, optionally, step S150 specifically includes: forming an isolation portion 70 on the side of the pixel definition layer 30 facing away from the substrate 10, so that the orthographic projection of the isolation portion 70 on the substrate 10 and the orthographic projection of the first electrode 110 on the substrate 10 at least partially overlap, and reusing at least part of the isolation portion 70 as the second electrode 120.

[0084] Optionally, after step S150, the method further includes forming an opening area 320 in the pixel definition layer 30 to expose the first electrode plate 110, such that the pixel definition layer 30 is composed of a pixel definition portion 310 and the opening area 320 enclosed by the pixel definition portion 310, and the pixel definition portion 310 covers the first electrode plate 110. For example, after forming the isolation portion 70, the opening area 320 of the pixel definition layer 30 can be formed between the areas enclosed by the isolation portion 70, such that the isolation portion 70 is disposed around the opening area 320. In other embodiments, the opening area 320 of the pixel definition layer 30 can be formed first, and then step S150 can be performed. For example, the isolation portion 70 can be formed so that the isolation portion 70 is located on the side of the pixel definition portion 310 facing away from the substrate 10, and the isolation portion 70 is disposed around the opening area 320.

[0085] 11 , the method further includes S160: forming a light-emitting layer 50 of the sub-pixel unit PX in the opening area 320 so that the light-emitting layer 50 is located on the side of the first electrode 40 away from the substrate 10, isolating the light-emitting layers 50 of adjacent sub-pixel units PX by an isolation portion 70, and then forming a second electrode 60 on the side of the light-emitting layer 50 away from the substrate 10, so that the second electrodes 60 of adjacent sub-pixel units PX are separated by the isolation portion 70, the first electrode 40, the light-emitting layer 50 and the second electrode 60 of the same sub-pixel unit PX are located in the same opening area 320, and the light-emitting layers 50 and the second electrode 60 of different sub-pixel units PX are isolated by the isolation portion 70, so as to facilitate individual control of each sub-pixel unit PX, and in the manufacturing process of the display panel, there is no need to use an additional mask to isolate different sub-pixel units PX, which is beneficial to reducing the manufacturing cost of the display panel. Referring to Figure 4, after the second electrode 60 is formed, a first encapsulation layer 810 can be formed on the side of the second electrode 60 and the isolation portion 70 facing away from the substrate 10, so that the first encapsulation layer 810 covers the second electrode 60 and at least part of the isolation portion 70. Then, a second encapsulation layer 820 is formed on the side of the first encapsulation layer 810 and the isolation portion 70 facing away from the substrate 10, so that the second encapsulation layer 820 covers the first encapsulation layer 810 and the isolation portion 70. A third encapsulation layer 830 is formed on the side of the second encapsulation layer 820 facing away from the substrate 10, so that the third encapsulation layer 830 covers the second encapsulation layer 820. The encapsulation process of the display panel is completed, and the display panel shown in Figure 4 is obtained.

[0086] The present application also provides a display device, which includes the display panel of any of the above embodiments and thus has the corresponding functional structure and effects of the display panel, which will not be described in detail here. The display device can be a mobile phone, or it can be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc., which are not specifically limited in the present application.

Claims

1. A display panel, comprising: substrate; An array circuit layer, located on the substrate, the array circuit layer comprising a plurality of driving transistors; A pixel definition layer and a plurality of sub-pixel units are located on a side of the array circuit layer away from the substrate, and the sub-pixel unit includes a first electrode; A first capacitor includes a first electrode plate and a second electrode plate, wherein the first electrode plate is arranged in the same layer as the first electrode, the pixel definition layer covers the first electrode plate, the second electrode plate is located on the side of the pixel definition layer away from the substrate, the orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the second electrode plate on the substrate, and the first electrode plate is connected to the gate of the driving transistor.

2. The display panel according to claim 1, wherein: The sub-pixel unit further includes: The second electrode is located on a side of the pixel definition layer away from the substrate, and the second electrode plate and the second electrode are made of different materials.

3. The display panel according to claim 1 or 2, wherein: The second pole plate and the second electrode are arranged in different layers.

4. The display panel according to claim 1, further comprising: The isolation portion is located on the side of the pixel definition layer away from the substrate, the orthographic projection of the isolation portion on the substrate at least partially overlaps with the orthographic projection of the first electrode on the substrate, and at least part of the isolation portion is reused as the second electrode.

5. The display panel according to claim 4, wherein: The sub-pixel unit further includes a light-emitting layer and a second electrode stacked on a side of the first electrode away from the substrate. The light-emitting layer of the sub-pixel unit has a gap on a side of the isolation portion, and the second electrode overlaps the isolation portion.

6. The display panel according to claim 4, wherein: The isolation portion includes a first sub-isolation portion, a second sub-isolation portion and a third sub-isolation portion which are sequentially stacked and arranged on a side of the pixel definition layer away from the substrate; Any one of the first sub-isolation portion, the second sub-isolation portion and the third sub-isolation portion or at least two adjacent ones are conductive isolation portions, the orthographic projection of the conductive isolation portion on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate, and at least part of the conductive isolation portion is reused as the second electrode plate and set to the input power supply voltage.

7. The display panel according to claim 6, wherein: Along the direction perpendicular to the substrate, the cross-section of the second sub-isolating portion is rectangular or trapezoidal. When the cross-section of the second sub-isolating portion is trapezoidal, the lower base of the trapezoid is adjacent to the first sub-isolating portion, and the upper base of the trapezoid is adjacent to the third sub-isolating portion; the orthographic projection of the third sub-isolating portion on the substrate covers the orthographic projection of the first sub-isolating portion on the substrate, and the orthographic projection of the third sub-isolating portion on the substrate covers the orthographic projection of the second sub-isolating portion on the substrate.

8. The display panel according to claim 1, wherein: The pixel definition layer includes a pixel definition portion and an opening area surrounded by the pixel definition portion, wherein the opening area exposes the first electrode; The pixel definition portion covers the first electrode plate, the second electrode plate is located on a side of the pixel definition portion away from the substrate, and the pixel definition portion isolates the first electrode plate and the second electrode plate to insulate the first electrode plate and the second electrode plate.

9. The display panel according to claim 8, wherein: The pixel definition portion includes at least one of a silicon oxide layer and a silicon nitride layer.

10. The display panel according to claim 8, wherein: Along a direction perpendicular to the substrate, the thickness of the pixel definition portion ranges from 100 nm to 1000 nm.

11. The display panel according to claim 8, wherein: The sub-pixel unit further includes: A light-emitting layer is disposed in the opening area and is located on a side of the first electrode away from the substrate; The second electrode is located on a side of the light-emitting layer away from the substrate. The second electrode is configured to input a power supply voltage. The second electrode is in contact with the second electrode plate.

12. The display panel according to claim 8, wherein: The first electrode plate is insulated from the first electrode, and the first electrode plate is located between adjacent first electrodes; The first electrode plate is arranged around the first electrode; The second electrode plate is disposed around the opening area of ​​the pixel definition layer, and an overlapping area of ​​an orthographic projection of the first electrode plate on the substrate and an orthographic projection of the second electrode plate on the substrate surrounds the opening area.

13. The display panel according to claim 1 further includes a connecting electrode, which is arranged in the same layer as the source or drain of the driving transistor, and is electrically connected to the gate of the driving transistor and the first electrode plate respectively, and the orthographic projection of the connecting electrode on the substrate at least partially overlaps with the orthographic projection of the gate of the driving transistor on the substrate.

14. The display panel according to claim 1, wherein: The array circuit layer also includes a multi-layer metal layer and a third electrode plate; An insulating layer is provided between two adjacent metal layers, the multi-layer metal layers include a first metal layer and a second metal layer, and the gate of the driving transistor is located in the first metal layer; The third electrode plate is located in the second metal layer, and the orthographic projection of the third electrode plate on the substrate at least partially overlaps with the orthographic projection of the gate of the driving transistor on the substrate. The third electrode plate and the gate of the driving transistor constitute two electrodes of the second capacitor.

15. A display panel, comprising: substrate; An array circuit layer, located on the substrate, the array circuit layer comprising a plurality of driving transistors; A pixel definition layer and a plurality of sub-pixel units are located on a side of the array circuit layer away from the substrate, the sub-pixel unit comprises a first electrode, the pixel definition layer comprises a pixel definition portion and an opening area formed by the pixel definition portion, and the opening area exposes the first electrode; A first capacitor, comprising a first electrode plate and a second electrode plate, wherein an orthographic projection of the first electrode plate on the substrate at least partially overlaps an orthographic projection of the second electrode plate on the substrate, and the first electrode plate is connected to a gate of the driving transistor; An isolation portion is located on one side of the substrate, the isolation portion is at least partially arranged around the opening area, the orthographic projection of the isolation portion on the substrate is at least partially overlapped with the orthographic projection of the first electrode on the substrate, and at least part of the isolation portion is reused as the second electrode.

16. The display panel according to claim 15, wherein: The first plate is arranged in the same layer as the first electrode, the pixel definition layer covers the first plate, the isolation portion is located on a side of the pixel definition portion away from the substrate, and the isolation portion multiplexed as the second plate is set to input a power supply voltage.

17. The display panel according to claim 15, wherein: The sub-pixel unit further includes a light-emitting layer and a second electrode stacked on a side of the first electrode away from the substrate. The light-emitting layer of the sub-pixel unit has a gap on a side of the isolation portion, and the second electrode overlaps the isolation portion.

18. The display panel according to claim 15, wherein: The isolation portion includes a first sub-isolation portion, a second sub-isolation portion and a third sub-isolation portion which are sequentially stacked and arranged on a side of the pixel definition layer away from the substrate; Any one of the first sub-isolation part, the second sub-isolation part and the third sub-isolation part or at least two adjacent ones are conductive isolation parts, the orthographic projection of the conductive isolation part on the substrate overlaps at least partially with the orthographic projection of the first electrode plate on the substrate, and at least part of the conductive isolation part is set to input power supply voltage and reused as the second electrode plate; Along the direction perpendicular to the substrate, the length of the third sub-isolation portion is greater than or equal to the length of the first sub-isolation portion, and the cross-section of the second sub-isolation portion is rectangular or trapezoidal. When the cross-section of the second sub-isolation portion is trapezoidal, the lower base of the trapezoid is adjacent to the first sub-isolation portion, and the upper base of the trapezoid is adjacent to the third sub-isolation portion.

19. The display panel according to claim 15, wherein: The array circuit layer also includes a multi-layer metal layer and a third electrode plate; An insulating layer is provided between two adjacent metal layers, the multi-layer metal layers include a first metal layer and a second metal layer, and the gate of the driving transistor is located in the first metal layer; The third electrode plate is located in the second metal layer, and the orthographic projection of the third electrode plate on the substrate at least partially overlaps with the orthographic projection of the gate of the driving transistor on the substrate. The third electrode plate and the gate of the driving transistor constitute two electrodes of the second capacitor.

20. A method for manufacturing a display panel, comprising: providing a substrate; forming an array circuit layer on the substrate, wherein the array circuit layer includes a plurality of driving transistors; A first electrode and a first electrode in a sub-pixel unit are formed on a side of the array circuit layer away from the substrate, wherein the first electrode is connected to a gate of the driving transistor; forming a pixel definition layer on the first electrode plate and the first electrode side away from the substrate, wherein the pixel definition layer covers the first electrode plate; A second electrode plate is formed on the side of the pixel definition layer away from the substrate, the orthographic projection of the first electrode plate on the substrate at least partially overlaps the orthographic projection of the second electrode plate on the substrate, and the first electrode plate and the second electrode plate constitute two electrodes of a first capacitor.

21. A display device, comprising the display panel according to any one of claims 1 to 14, or comprising the display panel according to any one of claims 15 to 19.

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