Pixel driving circuit and driving method thereof, display substrate, and display apparatus

Abstract

The present disclosure provides a pixel driving circuit and a driving method thereof, a display substrate, and a display apparatus. The pixel driving circuit comprises a driving transistor and a control sub-circuit. The driving transistor comprises a first gate, a second gate, and an oxide active layer. The driving transistor is used for realizing a driving function under the control of a first control signal transmitted by the first gate and a second control signal transmitted by the second gate. The second gate of the driving transistor is coupled to the control sub-circuit. The control sub-circuit is used for providing at least two different second control signals for the second gate coupled to the control sub-circuit.

Description

Pixel driving circuit and driving method thereof, display substrate and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202310904327.0 filed in China on July 21, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, a display substrate, and a display device. Background Art

[0004] With the continuous development of display technology, the application fields of display products are becoming more and more extensive, the display quality requirements of display products are becoming higher and higher, and the corresponding structural complexity and production costs of display products are also receiving more and more attention.

[0005] A display product includes multiple sub-pixels, each of which includes a driver and a light-emitting portion. The driver provides a driving signal to the light-emitting portion, thereby driving the light-emitting portion to emit light. As the resolution of display products continues to increase, the layout space for sub-pixels is limited, the difficulty of sub-pixel layout continues to increase, and the manufacturing cost of display products continues to rise. To address these issues, the driver can adopt a driver circuit including oxide transistors. This can reduce the manufacturing cost and difficulty of display products while maintaining high resolution.

[0006] However, the data signal range that can be achieved by the driving circuit including the oxide transistor is very small, which places high precision requirements on the driving chip in the display product and may lead to poor image quality in low grayscale displays.

[0007] Summary of the Invention

[0008] The present disclosure aims to provide a pixel driving circuit and a driving method thereof, a display substrate and a display device.

[0009] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0010] A first aspect of the present disclosure provides a pixel driving circuit, comprising: a driving transistor and a control subcircuit;

[0011] The driving transistor includes: a first gate, a second gate and an oxide active layer, and the driving transistor is used to realize a driving function under the control of a first control signal transmitted by the first gate and a second control signal transmitted by the second gate;

[0012] The second gate of the driving transistor is coupled to the control subcircuit, and the control subcircuit is configured to provide at least two different second control signals to the second gate coupled thereto.

[0013] Optionally, the control subcircuit includes a first control unit, a second control unit and a first holding unit;

[0014] The first control unit is respectively coupled to the corresponding control signal line, the corresponding first signal line and the control end of the second control unit, and is used to control the conduction or disconnection of the electrical connection between the first signal line and the control end of the second control unit under the control of the corresponding control signal line;

[0015] The second control unit is further coupled to the corresponding second data line and the second gate respectively, and is used to switch on or off the electrical connection between the second data line and the second gate under the control of the signal received by the control end;

[0016] The first holding unit is coupled to the control terminal of the second control unit and the second data line respectively.

[0017] Optionally, the first control unit includes a first control transistor, the second control unit includes a second control transistor, and the first holding unit includes a first capacitor;

[0018] The gate of the first control transistor is coupled to the corresponding control signal line, the first electrode of the first control transistor is coupled to the first signal line, and the second electrode of the first control transistor is coupled to the gate of the second control transistor;

[0019] The first electrode of the second control transistor is coupled to the corresponding second data line, and the first electrode of the second control transistor is coupled to the second gate;

[0020] A first plate of the first capacitor is coupled to the gate of the second control transistor, and a second plate of the first capacitor is coupled to the second data line.

[0021] Optionally, the control subcircuit includes a third control unit and a second holding unit;

[0022] The third control unit is coupled to the corresponding control signal line, the corresponding second data line and the second gate respectively, and is used to control the electrical connection between the second data line and the second gate to be turned on or off under the control of the control signal line;

[0023] The second holding unit is coupled to the control signal line and the second data line respectively.

[0024] Optionally, the third control unit includes a third control transistor, a gate of the third control transistor is coupled to the corresponding control signal line, a first electrode of the third control transistor is coupled to the corresponding second data line, and a second electrode of the third control transistor is coupled to the second gate;

[0025] The second holding unit includes a second capacitor, a first plate of the second capacitor is coupled to the gate of the third control transistor, and a second plate of the second capacitor is coupled to the second data line.

[0026] Optionally, the pixel driving circuit further includes: a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a storage capacitor;

[0027] The gate of the first transistor is coupled to the corresponding first reset signal line, the first electrode of the first transistor is coupled to the corresponding first initialization signal line, and the second electrode of the first transistor is coupled to the first gate of the driving transistor;

[0028] The gate of the second transistor is coupled to the corresponding scan line, the first electrode of the second transistor is coupled to the second electrode of the driving transistor, and the second electrode of the second transistor is coupled to the first gate of the driving transistor;

[0029] The gate of the fourth transistor is coupled to the corresponding scan line, the first electrode of the fourth transistor is coupled to the corresponding first data line, and the second electrode of the fourth transistor is coupled to the first electrode of the driving transistor;

[0030] The gate of the fifth transistor is coupled to the corresponding light emitting control line, the first electrode of the fifth transistor is coupled to the corresponding power line, and the second electrode of the fifth transistor is coupled to the first electrode of the driving transistor;

[0031] The gate of the sixth transistor is coupled to the corresponding light emitting control line, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the anode of the corresponding light emitting element;

[0032] The gate of the seventh transistor is coupled to the corresponding second reset signal line, the first electrode of the seventh transistor is coupled to the corresponding second initialization signal line, and the second electrode of the seventh transistor is coupled to the anode of the corresponding light-emitting element;

[0033] The first plate of the storage capacitor is coupled to the second gate of the driving transistor, and the second plate of the storage capacitor is coupled to the corresponding power line.

[0034] Based on the technical solution of the above pixel driving circuit, the second aspect of the present disclosure provides a display substrate, including a base substrate and the above multiple pixel driving circuits, wherein the multiple pixel driving circuits are arrayed on the base substrate.

[0035] Optionally, in the driving transistor included in the pixel driving circuit, an orthographic projection of the oxide active layer on the base substrate at least partially overlaps with an orthographic projection of the first gate on the base substrate, and an orthographic projection of the oxide active layer on the base substrate at least partially overlaps with an orthographic projection of the second gate on the base substrate;

[0036] Along a direction away from the base substrate, the second gate, the oxide active layer and the first gate are stacked in sequence.

[0037] Optionally, the first electrode of the driving transistor and the electrode of the control transistor coupled to the second gate are provided in the same layer and made of the same material.

[0038] Optionally, the display substrate includes a light-shielding layer, and the second gate is provided in the same layer and with the same material as the light-shielding layer.

[0039] Optionally, the display substrate further includes a power line, and the power line is multiplexed as a first signal line coupled to the control sub-circuit in the pixel driving circuit.

[0040] Optionally, the display substrate further includes a reset signal line, and the reset signal line is multiplexed as a control signal line coupled to a control sub-circuit in the pixel driving circuit.

[0041] Optionally, the plurality of pixel driving circuits are divided into a plurality of rows of pixel driving circuits and a plurality of columns of pixel driving circuits;

[0042] The control sub-circuits in a row of pixel driving circuits are coupled to the same control signal line, and the control sub-circuits in a column of pixel driving circuits are coupled to the same second data line.

[0043] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate.

[0044] Based on the technical solution of the above pixel driving circuit, a third aspect of the present disclosure provides a driving method of the pixel driving circuit, for driving the above display substrate; the driving method comprises:

[0045] During the reset period, the control subcircuit in the pixel driving circuit provides a second control signal to the second gate of the driving transistor coupled thereto;

[0046] During the light emitting period, the driving transistor realizes a driving function under the control of a first control signal transmitted by the first gate and a second control signal transmitted by the second gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0048] FIG1 is a first structural diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0049] FIG2 is a second structural diagram of a pixel driving circuit provided in an embodiment of the present disclosure;

[0050] FIG3 is a third structural diagram of a pixel driving circuit provided in an embodiment of the present disclosure;

[0051] FIG4 is a cross-sectional schematic diagram of a driving transistor and a control transistor provided by an embodiment of the present disclosure;

[0052] FIG5 is a schematic diagram of a transfer curve in the related art;

[0053] FIG6 is a schematic diagram of a transfer curve provided by an embodiment of the present disclosure;

[0054] FIG7 is a schematic diagram of a film layer of a display substrate provided in an embodiment of the present disclosure;

[0055] FIG8 is a schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure using a 4T1C circuit structure;

[0056] FIG9 is a timing diagram of the operation of the pixel driving circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] In order to further illustrate the pixel driving circuit and driving method thereof, the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0058] 1 , 2 and 4 , an embodiment of the present disclosure provides a pixel driving circuit, including: a driving transistor T3 and a control subcircuit 10 ;

[0059] The driving transistor T3 includes: a first gate T3-g1, a second gate T3-g2 and an oxide active layer T3-o. The driving transistor T3 is used to realize a driving function under the control of a first control signal transmitted by the first gate T3-g1 and a second control signal transmitted by the second gate T3-g2;

[0060] The second gate T3 - g2 of the driving transistor T3 is coupled to the control sub-circuit 10 , and the control sub-circuit 10 is configured to provide at least two different second control signals to the second gate T3 - g2 coupled thereto.

[0061] Exemplarily, the pixel driving circuit is applied to an organic light-emitting diode (OLED) display device, but is not limited thereto.

[0062] Exemplarily, the driving transistor T3 includes a dual-gate oxide transistor, the driving transistor T3 includes a first gate T3-g1, a second gate T3-g2 and an oxide active layer T3-o, at least a portion of the oxide active layer T3-o is located between the first gate T3-g1 and the second gate T3-g2.

[0063] Exemplarily, the second control signal received by the second gate T3-g2 is a DC signal that can be regulated. The voltage value of the DC signal can be selected between -5V and +5V, for example, -5V, -4V, -3V, -2V, -1V, 0V, 1V, 2V, 3V, 4V, 5V, etc., but is not limited thereto.

[0064] More specifically, Figure 5 illustrates a transfer curve diagram corresponding to displaying five adjacent grayscale images in a conventional solution. These five grayscale images are achieved by selecting five Vgs values ​​on the transfer curve, specifically the Vgs values ​​corresponding to the five black dots in Figure 5. As can be seen from Figure 5, the ΔVgs between adjacent grayscale images is very small, which places high demands on the precision of the driver chip in the display product and may result in poor image quality at low grayscale levels.

[0065] In the technical solution provided by the embodiment of the present disclosure, second control signals with different potentials are set for the above-mentioned five grayscale images and are provided to the second gate T3-g2, for example: -2V, -1V, 0V, 1V and 2V. In this case, the transfer curve will move horizontally, as shown in FIG6 , as the five transfer curves L1, L2, L3, L4, and L5 that move horizontally. The above-mentioned five grayscale images correspond to the five black dots in FIG6 . This is equivalent to expanding the originally very small ΔVgs to form a new transfer curve Lx. It can be seen from the transfer curve Lx that the ΔVgs between adjacent grayscale images is large. This places lower requirements on the accuracy of the driver chip in the display product, facilitates the driver chip to provide signals to display images of different grayscales, improves the display fineness, and is conducive to improving the low grayscale display quality.

[0066] It should be noted that the second control signal provided by the control subcircuit 10 to the second gate T3-g2 can form a fixed electric field on the second gate T3-g2. The fixed electric field can affect the open state of the channel formed in the oxide active layer T3-o. At the same time, through the first control signal on the first gate T3-g1 and the input electrode of the driving transistor T3 (such as the source T3-s), the operating state of the driving transistor T3 is controlled to display different grayscale images. The gate-source voltage Vgs of the driving transistor T3 is mainly regulated by the first control signal on the first gate T3-g1 and the data signal received by the input electrode of the driving transistor T3. For example, Vgs=Vg-Vs, where Vg is the voltage value of the first control signal on the first gate T3-g1, and Vs is the voltage value of the data signal received by the input electrode of the driving transistor T3. The data signal is provided by the driver chip to the data line coupled to the pixel driving circuit and then transmitted to the input electrode of the driving transistor T3. The driving current Ids formed on the driving transistor T3 corresponds to the grayscale of the display image, that is, different Ids correspond to different grayscale images.

[0067] It is worth noting that when the pixel driving circuit provided in the embodiment of the present disclosure is applied to a display device, it can control the display device to display the entire 255 grayscales. The second gate T3-g2 in the pixel driving circuit provided in the embodiment of the present disclosure can provide a second control signal with a wider range of potentials. The more potentials of the second control signal provided, the better the display quality of the display device. In the case of displaying the entire 255 grayscales, the potential of the second control signal to be provided to the second gate T3-g2 can be determined based on the specific grayscale image to be achieved, and then, at this potential, Vgs can be simultaneously controlled to achieve the corresponding grayscale image. The potential of the second control signal provided to the second gate T3-g2 can also be fixed within a certain display grayscale range. In this case, only Vgs is controlled to achieve the corresponding grayscale image.

[0068] According to the specific structure of the above-mentioned pixel driving circuit, in the pixel driving circuit provided in the embodiment of the present disclosure, the driving transistor T3 is provided to include a first gate T3-g1, a second gate T3-g2 and an oxide active layer T3-o, and the second gate T3-g2 is coupled to the control subcircuit 10 to receive the second control signal provided by the control subcircuit 10, so that the driving transistor T3 realizes the driving function under the joint control of the first gate T3-g1 and the second gate T3-g2.

[0069] In the pixel driving circuit provided by the embodiment of the present disclosure, the second control signal provided by the second gate T3-g2 can affect the degree of opening of the channel of the driving transistor T3. Under this influence, the first control signal provided by the first gate T3-g1 and the data signal received by the input electrode of the driving transistor T3 further control the gate-source voltage Vgs of the driving transistor T3, thereby driving the display device using the pixel driving circuit to display different grayscale images. Because the transfer curve shifts under the control of the second gate T3-g2, the driving transistor T3 forms a new transfer curve under the joint control of the first gate T3-g1 and the second gate T3-g2. This transfer curve has a larger Vgs control range, and accordingly, the data signal adjustment range (i.e., Data Range) provided by the driver chip is also larger, thereby overcoming the narrow driving range of the oxide driving transistor T3 and achieving a more detailed display image.

[0070] Therefore, the pixel driving circuit provided by the embodiment of the present disclosure, when including the oxide driving transistor T3 and the control sub-circuit 10, solves the problem that the data signal range that can be achieved by the driving circuit including the oxide transistor is very small, the precision requirements of the driving chip in the display product are very high, and it will lead to poor low grayscale display quality.

[0071] In some embodiments, the pixel driving circuit includes circuit structures such as 2T1C (i.e., 2 transistors and 1 capacitor), 3T1C (i.e., 3 transistors and 1 capacitor), and 4T1C (i.e., 4 transistors and 1 capacitor), but is not limited thereto. The structure of the driving transistor T3 in the pixel driving circuit can also be applied to other transistors included in the pixel driving circuit.

[0072] As shown in FIG8 and FIG9 , the pixel driving circuit adopts a 4T1C circuit structure as an example.

[0073] The pixel driving circuit includes: a first switching transistor SW1, a second switching transistor SW2, a third switching transistor SW3, a storage capacitor Cst and a driving transistor T3.

[0074] The driving transistor T3 includes: a first gate T3-g1, a second gate T3-g2 and an oxide active layer T3-o. The driving transistor T3 is used to realize a driving function under the control of a first control signal transmitted by the first gate T3-g1 and a second control signal transmitted by the second gate T3-g2; the second gate T3-g2 of the driving transistor T3 is coupled to the control subcircuit 10, and the control subcircuit 10 is used to provide at least two different second control signals to the second gate T3-g2 coupled thereto.

[0075] During the reset period (and the initialization period mentioned later), the control sub-circuit 10 in the pixel driving circuit provides a second control signal to the second gate T3-g2 of the driving transistor T3 coupled thereto;

[0076] During the light emitting period, the driving transistor T3 realizes a driving function under the control of a first control signal transmitted by the first gate T3-g1 and a second control signal transmitted by the second gate T3-g2.

[0077] In more detail, during the initialization period (initial), the scan signal SCAN(n) has an off-level that turns off the first switching transistor SW1, while the initialization signal INI(n) and the reference signal INI(n-1) become on-levels that turn on the second switching transistor SW2 and the third switching transistor SW3. Therefore, the initialization voltage Vini is applied to the first gate of the driving transistor T3, and the reference voltage Vref is applied to the source node of the driving transistor T3. The initialization period may be one horizontal period.

[0078] A voltage corresponding to the difference between the initialization voltage Vini and the reference voltage Vref is charged to the storage capacitor Cst, so that the voltage between the gate and source of the driving transistor T3 becomes (Vini-Vref). The initialization voltage Vini is higher than the reference voltage Vref by an amount sufficient to turn on the driving transistor T3. For example, the initialization voltage Vini may be 4V, and the reference voltage Vref may be 1V.

[0079] In the front part of the threshold voltage sensing period (vth sensing), the scan signal SCAN(n) maintains the off-level at which the first switching transistor SW1 is turned off, and the initialization signal INI(n) maintains the on-level at which the second switching transistor SW2 is turned on, which causes the initialization voltage Vini to be continuously applied to the first gate of the driving transistor T3, and the reference signal INI(n-1) becomes the off-level to float the source node of the driving transistor T3.

[0080] During the initialization period, the driving transistor T3 is turned on by the voltage charged in the storage capacitor Cst. During the threshold voltage sensing period, the voltage at the source node of the driving transistor T3 rises toward the voltage at the gate node due to the current flowing through the driving transistor T3 (source follower). Therefore, if the sensing period is long enough, the voltage at the source of the driving transistor T3 rises until the difference between the initialization voltage applied to the gate node of the driving transistor T3 and the voltage at the source node corresponds to the threshold voltage Vth of the driving transistor T3.

[0081] At the end of the threshold voltage sensing period (Vth sensing), the scan signal SCAN(n) maintains an off-level to turn off the first switching transistor SW1, the initialization signal INI(n) becomes an off-level to turn off the second switching transistor SW2, which causes the gate node of the driving transistor T3 to float, and the reference signal INI(n-1) maintains an off-level to float the source node of the driving transistor T3.

[0082] The driving transistor T3 is maintained in an on state by the voltage charged in the storage capacitor Cst. Therefore, the voltage at the source node of the driving transistor T3 increases due to the current flowing through the driving transistor T3. The voltage at the first gate of the driving transistor T3 also increases due to the storage capacitor Cst connected to the source node, but the increase is smaller than the increase in the voltage at the source node. Therefore, as time continues, a voltage corresponding to the threshold voltage of the driving transistor T3 can be charged to the storage capacitor Cst.

[0083] In the data writing and mobility sensing period, the scan signal SCAN(n) becomes the on-level to turn on the first switching transistor SW1, so the data voltage supplied to the data line is applied to the first gate of the driving transistor T3, and the initialization signal INI(n) and the reference signal INI(n-1) maintain the off-level.

[0084] The voltage of the first gate electrode of the driving transistor T3 quickly rises to the data voltage, a current corresponding to the voltage difference between the gate and the source electrodes flows through the driving transistor T3, and the voltage of the source node of the driving transistor T3 rises toward the data voltage applied to the first gate electrode of the driving transistor T3. Therefore, the voltage difference between the first gate electrode and the source electrode of the driving transistor T3 is programmed to a desired grayscale level.

[0085] That is, when the current flowing through the driving transistor T3 is expressed as I=K*(Vgs-Vth)2, where K is a constant related to the electron mobility and is proportional to the electron mobility, when the electron mobility of the driving transistor T3 is high (K has a large value), the voltage of the source node of the driving transistor T3 rises rapidly and Vgs decreases relatively quickly, while when the electron mobility of the driving transistor T3 is small (K has a small value), the voltage of the source node of the driving transistor T3 rises slowly and Vgs decreases relatively slowly, so that the current flowing through the driving transistor T3 becomes independent of the electron mobility and the electron mobility can be compensated.

[0086] In the light emission period (light emission), the scan signal SCAN(n) becomes an off level to turn off the first switching transistor SW1 , and the initialization signal INI(n) and the reference signal INI(n−1) maintain an off level.

[0087] A current corresponding to the potential difference programmed between the first gate and source of the driving transistor T3 during the data write period (i.e., the potential difference programmed in the storage capacitor Cst) flows. As a result, the voltage of the source node of the driving transistor T3 rises, the voltage of the first gate also rises while maintaining the programmed potential difference, and the voltage of the source node becomes higher than the voltage for driving the light emitting diode, which causes the light emitting diode to emit light.

[0088] As shown in FIG1 , in some embodiments, the control subcircuit 10 includes a first control unit, a second control unit, and a first holding unit;

[0089] The first control unit is respectively coupled to the corresponding control signal line Vk1, the corresponding first signal line Vk2 and the control end of the second control unit, and is used to control the electrical connection between the first signal line Vk2 and the control end of the second control unit under the control of the corresponding control signal line Vk1;

[0090] The second control unit is further coupled to the corresponding second data line DA2 and the second gate T3-g2, respectively, and is configured to switch on or off the electrical connection between the second data line DA2 and the second gate T3-g2 under the control of the signal received by the control terminal;

[0091] The first holding unit is coupled to the control terminal of the second control unit and the second data line DA2 respectively.

[0092] Exemplarily, the first control unit includes a first control transistor T8, the second control unit includes a second control transistor T9, and the first holding unit includes a first capacitor C1; the gate of the first control transistor T8 is coupled to the corresponding control signal line Vk1, the first electrode of the first control transistor T8 is coupled to the first signal line Vk2, and the second electrode of the first control transistor T8 is coupled to the gate of the second control transistor T9; the first electrode of the second control transistor T9 is coupled to the corresponding second data line DA2, and the first electrode of the second control transistor T9 is coupled to the second gate T3-g2; the first plate of the first capacitor C1 is coupled to the gate of the second control transistor T9, and the second plate of the first capacitor C1 is coupled to the second data line DA2.

[0093] Exemplarily, the control subcircuit 10 adopts a 2T1C circuit structure, that is, includes two transistors and one capacitor, but is not limited thereto.

[0094] Exemplarily, the first control transistor T8 is turned on or off under the control of the signal transmitted by the control signal line Vk1. The second control transistor T9 is turned on or off under the control of the first signal transmitted by the first signal line Vk2. When the first control transistor T8 is turned on, the first signal can be transmitted to the gate of the second control transistor T9. When the second control transistor T9 is turned on, the second data signal transmitted by the second data line DA2 can be transmitted to the second gate T3-g2. The second data signal transmitted by the second data line DA2 serves as the second control signal provided to the second gate T3-g2.

[0095] Exemplarily, the second data line DA2 is coupled to a driving chip, and the driving chip provides a corresponding second data signal thereto.

[0096] As shown in FIG2 , in some embodiments, the control subcircuit 10 includes a third control unit and a second holding unit;

[0097] The third control unit is coupled to the corresponding control signal line Vk1, the corresponding second data line DA2 and the second gate T3-g2 respectively, and is used to control the conduction or disconnection of the electrical connection between the second data line DA2 and the second gate T3-g2 under the control of the control signal line Vk1; the second holding unit is coupled to the control signal line Vk1 and the second data line DA2 respectively.

[0098] Exemplarily, the third control unit includes a third control transistor T10, the gate of the third control transistor T10 is coupled to the corresponding control signal line Vk1, the first electrode of the third control transistor T10 is coupled to the corresponding second data line DA2, and the second electrode of the third control transistor T10 is coupled to the second gate T3-g2; the second holding unit includes a second capacitor, the first plate of the second capacitor is coupled to the gate of the third control transistor T10, and the second plate of the second capacitor is coupled to the second data line DA2.

[0099] Exemplarily, the control subcircuit 10 adopts a 1T1C circuit structure, that is, includes a transistor and a capacitor, but is not limited thereto.

[0100] Exemplarily, the third control transistor T10 is turned on or off under the control of the signal transmitted by the control signal line Vk1. When the third control transistor T10 is turned on, it can transmit the second data signal transmitted by the second data line DA2 to the second gate T3-g2. The second data signal transmitted by the second data line DA2 is provided as the second control signal to the second gate T3-g2.

[0101] It should be noted that, in the pixel driving circuit, except for the control subcircuit 10, the remaining structure can be a 7T1C structure (i.e., including 7 transistors and 1 capacitor) structure, an 8T1C structure (i.e., including 8 transistors and 1 capacitor) structure, etc., but is not limited to this.

[0102] As shown in FIG1 and FIG2 , in some embodiments, the pixel driving circuit further includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst;

[0103] The gate of the first transistor T1 is coupled to the corresponding first reset signal line RST1, the first electrode of the first transistor T1 is coupled to the corresponding first initialization signal line Vinit1, and the second electrode of the first transistor T1 is coupled to the first gate T3-g1 of the driving transistor T3; the gate of the second transistor T2 is coupled to the corresponding scan line GA, the first electrode of the second transistor T2 is coupled to the second electrode (such as T3-d) of the driving transistor T3, and the second electrode of the second transistor T2 is coupled to the first gate T3-g1 of the driving transistor T3; the gate of the fourth transistor T4 is coupled to the corresponding scan line GA, the first electrode of the fourth transistor T4 is coupled to the corresponding first data line DA1, and the second electrode of the fourth transistor T4 is coupled to the first electrode (such as T3-s) of the driving transistor T3; the gate of the fifth transistor T5 is coupled to the corresponding The first electrode of the fifth transistor T5 is coupled to the corresponding power line VDD, and the second electrode of the fifth transistor T5 is coupled to the first electrode of the driving transistor T3. The gate of the sixth transistor T6 is coupled to the corresponding light-emitting control line EM, the first electrode of the sixth transistor T6 is coupled to the second electrode of the driving transistor T3, and the second electrode of the sixth transistor T6 is coupled to the anode of the corresponding light-emitting element. The gate of the seventh transistor T7 is coupled to the corresponding second reset signal line RST2, the first electrode of the seventh transistor T7 is coupled to the corresponding second initialization signal line Vinit2, and the second electrode of the seventh transistor T7 is coupled to the anode of the corresponding light-emitting element. The first plate of the storage capacitor Cst is coupled to the second gate T3-g2 of the driving transistor T3, and the second plate of the storage capacitor Cst is coupled to the corresponding power line VDD. The cathode of the light-emitting element receives the negative power signal VSS.

[0104] It should be noted that, in the pixel driving circuit, except for the driving transistor T3, the remaining transistors may be oxide transistors or low-temperature polysilicon transistors.

[0105] When the pixel driving circuit is in operation, each operation cycle includes a first reset period, a writing compensation period, a second reset period and a light emitting period.

[0106] During the first reset period, the first reset signal input by the first reset signal line RST1 is at a valid level, the first transistor T1 is turned on, and the first initialization signal transmitted by the first initialization signal line Vinit1 is input to the first gate of the driving transistor T3, so that the gate-source voltage Vgs maintained on the driving transistor T3 in the previous frame is cleared, thereby resetting the gate of the driving transistor T3.

[0107] During the write compensation period, the first reset signal is at an inactive level, the first transistor T1 is turned off, the scan signal input by the scan line GA is at an active level, the second transistor T2 and the fourth transistor T4 are controlled to be turned on, the first data line DA1 is written with the first data signal, and the first data signal is transmitted to the source of the driving transistor T3 through the fourth transistor T4. At the same time, the second transistor T2 and the fourth transistor T4 are turned on, so that the driving transistor T3 forms a diode structure. Therefore, the threshold voltage of the driving transistor T3 is compensated by the cooperation of the second transistor T2, the driving transistor T3 and the fourth transistor T4. When the compensation time is long enough, the gate potential of the driving transistor T3 can be controlled to eventually reach Vdata+Vth, where Vdata represents the voltage value of the first data signal and Vth represents the threshold voltage of the driving transistor T3.

[0108] During the second reset period, the scanning signal is at a non-valid level, the second transistor T2 and the fourth transistor T4 are both turned off, the second reset signal input by the second reset signal line RST2 is at a valid level, controlling the seventh transistor T7 to be turned on, and the second initialization signal transmitted by the second initialization signal line Vinit2 is input to the anode of the light-emitting element, controlling the light-emitting element not to emit light.

[0109] During the light-emitting period, the light-emitting control signal written into the light-emitting control line EM is at an effective level, which controls the fifth transistor T5 and the sixth transistor T6 to be turned on, so that the power signal transmitted by the power line VDD is input to the source of the driving transistor T3. At the same time, since the gate of the driving transistor T3 is maintained at Vdata+Vth, the driving transistor T3 is turned on. The gate-source voltage corresponding to the driving transistor T3 is Vdata+Vth-Vdd, where Vdd is the potential corresponding to the power signal. The driving current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element, driving the corresponding light-emitting element to emit light.

[0110] The embodiment of the present disclosure further provides a driving method of a pixel driving circuit, which is used to drive the display substrate provided by the above embodiment; the driving method includes:

[0111] During the reset period, the control sub-circuit 10 in the pixel driving circuit provides a second control signal to the second gate T3-g2 of the driving transistor T3 coupled thereto;

[0112] During the light emitting period, the driving transistor T3 realizes a driving function under the control of a first control signal transmitted by the first gate T3-g1 and a second control signal transmitted by the second gate T3-g2.

[0113] Exemplarily, the reset period includes the first reset period mentioned in the above embodiment, but is not limited thereto.

[0114] In more detail, taking the control sub-circuit 10 employing a 2T1C structure as an example, during the reset period, the signal transmitted by the control signal line Vk1 is at an active level, controlling the first control transistor T8 to conduct, thereby transmitting the first signal transmitted by the first signal line Vk2 to the gate of the second control transistor T9. The first signal then controls the second control transistor T9 to conduct, transmitting the second data signal transmitted by the second data line DA2 to the second gate T3-g2 of the drive transistor T3. This second data signal, i.e., the second control signal provided by the control sub-circuit 10 to the second gate T3-g2 of the coupled drive transistor T3.

[0115] The driving method provided in the embodiments of the present disclosure drives the display substrate, so that the second control signal provided to the second gate T3-g2 can affect the degree of channel opening of the driving transistor T3. Under this influence, the first control signal provided by the first gate T3-g1 and the data signal received by the input electrode of the driving transistor T3 further control the gate-source voltage Vgs of the driving transistor T3, thereby driving the display device using the pixel driving circuit to display different grayscale images. Because the transfer curve shifts under the control of the second gate T3-g2, the driving transistor T3 forms a new transfer curve under the joint control of the first gate T3-g1 and the second gate T3-g2. This transfer curve has a larger Vgs control range, and accordingly, the data signal adjustment range (i.e., data range) provided by the driver chip is also larger. This overcomes the narrow driving range of the oxide driving transistor T3 and can achieve a more detailed display image.

[0116] An embodiment of the present disclosure further provides a display substrate, comprising a base substrate and a plurality of pixel driving circuits provided in the above embodiment, wherein the plurality of pixel driving circuits are arrayed on the base substrate.

[0117] Exemplarily, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixels include the pixel driving circuit and a light-emitting element. The pixel driving circuit is coupled to the anode of the light-emitting element and is used to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0118] Exemplarily, the multiple pixel driving circuits included in the multiple sub-pixels are distributed in an array. The multiple pixel driving circuits are divided into multiple rows of pixel driving circuits and multiple columns of pixel driving circuits. The multiple rows of pixel driving circuits are arranged along the second direction, and each row of pixel driving circuits includes multiple pixel driving circuits arranged along the first direction. The multiple columns of pixel driving circuits are arranged along the first direction, and each column of pixel driving circuits includes multiple pixel driving circuits arranged along the second direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes the horizontal direction, and the second direction includes the vertical direction.

[0119] For example, the control subcircuits 10 in a row of pixel driving circuits are coupled to the same control signal line Vk1, and the control subcircuits 10 in a column of pixel driving circuits are coupled to the same second data line DA2. This configuration can reduce the complexity of the display substrate and reduce the difficulty of the layout of the display substrate.

[0120] In the pixel driving circuit provided in the above embodiment, the driving transistor T3 is configured to include a first gate T3-g1, a second gate T3-g2, and an oxide active layer T3-o. The second gate T3-g2 is coupled to a control subcircuit 10 and receives a second control signal provided by the control subcircuit 10, so that the driving transistor T3 performs a driving function under the joint control of the first gate T3-g1 and the second gate T3-g2. In the pixel driving circuit provided in the above embodiment, the second control signal provided by the second gate T3-g2 can affect the degree of opening of the channel of the driving transistor T3. Under this influence, the first control signal provided by the first gate T3-g1 and the data signal received by the input electrode of the driving transistor T3 further control the gate-source voltage Vgs of the driving transistor T3, thereby driving the display device using the pixel driving circuit to display different grayscale images. Because the transfer curve shifts under the control of the second gate T3-g2, the driver transistor T3 forms a new transfer curve under the joint control of the first gate T3-g1 and the second gate T3-g2. This transfer curve has a larger Vgs control range, and the corresponding data signal adjustment range (i.e., Data Range) provided by the driver chip is also larger. This overcomes the narrow driving range of the oxide driver transistor T3 and enables a more detailed display image. This solves the problem that the data signal range that can be achieved by the driver circuit including the oxide transistor is very small, which requires a high precision of the driver chip in the display product and can lead to poor low grayscale display quality.

[0121] The display substrate provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when including the above-mentioned pixel driving circuit, which will not be described in detail here.

[0122] As shown in FIG4 , in some embodiments, in the driving transistor T3 included in the pixel driving circuit, the orthographic projection of the oxide active layer T3-o on the substrate at least partially overlaps with the orthographic projection of the first gate T3-g1 on the substrate, and the orthographic projection of the oxide active layer T3-o on the substrate at least partially overlaps with the orthographic projection of the second gate T3-g2 on the substrate; and in a direction away from the substrate, the second gate T3-g2, the oxide active layer T3-o, and the first gate T3-g1 are stacked in sequence. It should be noted that FIG4 also illustrates the insulating layer 20 and the second electrode 30 of the second control transistor T9 (or the third control transistor T10).

[0123] For example, as shown in FIG7 , the display substrate includes a buffer layer BF, a first active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, a third gate insulating layer GI3, a second active layer ACT, a fourth gate insulating layer GI4, a third gate metal layer gate3, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a passivation layer PVX, a first planarizing layer PLN1, a second source / drain metal layer SD2, a second planarizing layer PLN2, a third source / drain metal layer SD3, a third planarizing layer PLN3, an anode layer ANO, a pixel defining layer PDL, a light emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, which are sequentially stacked in a direction away from the base substrate 70. The display substrate may further include a light shielding layer located between the first active layer poly and the base substrate 70.

[0124] Exemplarily, the first electrode (e.g., T3-s) and the second electrode (e.g., T3-d) of the driving transistor T3 are provided in the same layer and material as the electrode of the control transistor (e.g., reference numeral 30 in FIG4 ) coupled to the second gate T3-g2. The first and second electrodes of the driving transistor T3 and the first and second electrodes of the control transistor are both made of the first source / drain metal layer.

[0125] Exemplarily, the display substrate includes a light shielding layer, and the first gate T3-g1 is provided in the same layer and material as the light shielding layer. The light shielding layer is made of a metallic material, molybdenum (Mo). Specifically, a Mo material layer can be first deposited and then patterned to form the light shielding layer and the second gate T3-g2.

[0126] As shown in FIG3 , in some embodiments, the display substrate further includes a power line VDD, and the power line VDD is multiplexed as a first signal line Vk2 coupled to the control sub-circuit 10 in the pixel driving circuit.

[0127] Exemplarily, the power line VDD is coupled to a first electrode of the fifth transistor T5 in the pixel driving circuit and a second electrode of the storage capacitor Cst.

[0128] The power line VDD is reused as the first signal line Vk2 coupled to the control subcircuit 10 in the pixel driving circuit. This eliminates the need to additionally fabricate the first signal line Vk2 in the display substrate, thereby simplifying the manufacturing process of the display substrate and reducing the complexity of the display substrate.

[0129] As shown in FIG. 3 , in some embodiments, the display substrate further includes a reset signal line, which is multiplexed as a control signal line Vk1 coupled to the control sub-circuit 10 in the pixel driving circuit.

[0130] Exemplarily, the reset signal line is coupled to the first transistor T1 and the seventh transistor T7 in the driving circuit.

[0131] The reset signal line is multiplexed as the control signal line Vk1 coupled to the control subcircuit 10 in the pixel driving circuit. This eliminates the need to manufacture an additional control signal line Vk1 in the display substrate, simplifies the manufacturing process of the display substrate, and reduces the complexity of the display substrate.

[0132] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0133] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0134] The display substrate provided in the above-mentioned embodiments solves the problem that the data signal range achievable by a driver circuit including oxide transistors is very small, requiring high precision from the driver chip in the display product, and resulting in poor low-grayscale display quality. The display device provided in the embodiments of the present disclosure, when including the above-mentioned display substrate, also has the aforementioned beneficial effects, which will not be further elaborated here.

[0135] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0136] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0137] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0138] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0139] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0140] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0141] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A pixel driving circuit, comprising: driver transistors and control subcircuits; The driving transistor comprises: a first gate, a second gate and an oxide active layer, and the driving transistor is used to realize a driving function under the control of a first control signal transmitted by the first gate and a second control signal transmitted by the second gate; The second gate of the driving transistor is coupled to the control subcircuit, and the control subcircuit is used to provide at least two different second control signals to the second gate coupled thereto.

2. The pixel driving circuit according to claim 1, wherein: The control subcircuit comprises a first control unit, a second control unit and a first holding unit; The first control unit is respectively coupled to the corresponding control signal line, the corresponding first signal line and the control end of the second control unit, and is used to control the conduction or disconnection of the electrical connection between the first signal line and the control end of the second control unit under the control of the corresponding control signal line; The second control unit is also coupled to the corresponding second data line and the second gate, respectively, and is used to turn on or off the electrical connection between the second data line and the second gate under the control of the signal received by the control end; The first holding unit is coupled to the control terminal of the second control unit and the second data line respectively.

3. The pixel driving circuit according to claim 2, wherein: The first control unit includes a first control transistor, the second control unit includes a second control transistor, and the first holding unit includes a first capacitor; The gate of the first control transistor is coupled to the corresponding control signal line, the first electrode of the first control transistor is coupled to the first signal line, and the second electrode of the first control transistor is coupled to the gate of the second control transistor; The first electrode of the second control transistor is coupled to the corresponding second data line, and the first electrode of the second control transistor is coupled to the second gate; The first plate of the first capacitor is coupled to the gate of the second control transistor, and the second plate of the first capacitor is coupled to the second data line.

4. The pixel driving circuit according to claim 1, wherein: The control subcircuit includes a third control unit and a second holding unit; The third control unit is coupled to the corresponding control signal line, the corresponding second data line and the second gate respectively, and is used to control the conduction or disconnection of the electrical connection between the second data line and the second gate under the control of the control signal line; The second holding unit is coupled to the control signal line and the second data line, respectively.

5. The pixel driving circuit according to claim 4, wherein: The third control unit comprises a third control transistor, a gate of the third control transistor is coupled to a corresponding control signal line, a first electrode of the third control transistor is coupled to a corresponding second data line, and a second electrode of the third control transistor is coupled to the second gate; The second holding unit includes a second capacitor, a first plate of the second capacitor is coupled to the gate of the third control transistor, and a second plate of the second capacitor is coupled to the second data line.

6. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit further includes: a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a storage capacitor; The gate of the first transistor is coupled to the corresponding first reset signal line, the first electrode of the first transistor is coupled to the corresponding first initialization signal line, and the second electrode of the first transistor is coupled to the first gate of the driving transistor; The gate of the second transistor is coupled to the corresponding scan line, the first electrode of the second transistor is coupled to the second electrode of the driving transistor, and the second electrode of the second transistor is coupled to the first gate of the driving transistor; The gate of the fourth transistor is coupled to the corresponding scan line, the first electrode of the fourth transistor is coupled to the corresponding first data line, and the second electrode of the fourth transistor is coupled to the first electrode of the driving transistor; The gate of the fifth transistor is coupled to the corresponding light emitting control line, the first electrode of the fifth transistor is coupled to the corresponding power supply line, and the second electrode of the fifth transistor is coupled to the first electrode of the driving transistor; The gate of the sixth transistor is coupled to the corresponding light emitting control line, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the anode of the corresponding light emitting element; The gate of the seventh transistor is coupled to the corresponding second reset signal line, the first electrode of the seventh transistor is coupled to the corresponding second initialization signal line, and the second electrode of the seventh transistor is coupled to the anode of the corresponding light emitting element; The first plate of the storage capacitor is coupled to the second gate of the driving transistor, and the second plate of the storage capacitor is coupled to the corresponding power line.

7. A display substrate, comprising a base substrate and a plurality of pixel driving circuits according to any one of claims 1 to 6, wherein the plurality of pixel driving circuits are arrayed on the base substrate.

8. The display substrate according to claim 7, wherein: In the driving transistor included in the pixel driving circuit, the orthographic projection of the oxide active layer on the substrate at least partially overlaps with the orthographic projection of the first gate on the substrate, and the orthographic projection of the oxide active layer on the substrate at least partially overlaps with the orthographic projection of the second gate on the substrate; Along a direction away from the base substrate, the second gate, the oxide active layer and the first gate are stacked in sequence.

9. The display substrate according to claim 8, wherein: The first electrode of the driving transistor and the electrode of the control transistor coupled to the second gate are arranged in the same layer and the same material.

10. The display substrate according to claim 8, wherein: The display substrate comprises a light shielding layer, and the second gate electrode is provided in the same layer and with the same material as the light shielding layer.

11. The display substrate according to claim 7, wherein: The display substrate further includes a power line, and the power line is multiplexed as a first signal line coupled to a control subcircuit in the pixel driving circuit.

12. The display substrate according to claim 7, wherein: The display substrate further includes a reset signal line, and the reset signal line is multiplexed as a control signal line coupled to a control subcircuit in the pixel driving circuit.

13. The display substrate according to claim 7, wherein: The plurality of pixel driving circuits are divided into a plurality of row pixel driving circuits and a plurality of column pixel driving circuits; The control sub-circuits in a row of pixel driving circuits are coupled to the same control signal line, and the control sub-circuits in a column of pixel driving circuits are coupled to the same second data line.

14. A display device comprising the display substrate according to any one of claims 7 to 13.

15. A driving method of a pixel driving circuit, used for driving the display substrate according to any one of claims 7 to 13; The driving method comprises: During the reset period, the control subcircuit in the pixel driving circuit provides a second control signal to the second gate of the driving transistor coupled thereto; During the light emitting period, the driving transistor realizes a driving function under the control of a first control signal transmitted by the first gate and a second control signal transmitted by the second gate.

Images