Driver circuit and driving method thereof, and display apparatus

Abstract

The present application relates to the technical field of display. Provided are a driver circuit and a driving method thereof, and a display apparatus. The driver circuit comprises a plurality of shift registers which are arranged in a cascaded manner, each shift register comprising an input module, an output module, a pull-up module, a pull-down module, a reset module and an adjustment module, wherein the reset module can reset an output end of the shift register under the control of the voltage of a fourth node; and the adjustment module can pull down the voltage of the fourth node, so as to increase the reset speed of the reset module for the output end, thereby improving the driving capability of the shift register.

Description

A driving circuit, a driving method thereof, and a display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on July 26, 2023, with application number 202310929408.6 and titled “A driving circuit, a driving method thereof, and a display device,” the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of display technology, and in particular to a driving circuit and a driving method thereof, and a display device. Background Art

[0004] Gate Driver on Array (GOA) is a technology that integrates gate drive circuitry onto an array substrate. The gate drive circuitry includes multiple shift registers, each corresponding to a row of gate lines. These shift registers sequentially output scanning signals. With the rapid development of display technology, gate drive circuit technology has matured, and the industry is placing increasingly high demands on the driving performance of the shift registers within gate drive circuits.

[0005] Summary of the Invention

[0006] The embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a driving circuit, comprising: a plurality of shift registers arranged in cascade, wherein the shift registers include:

[0008] a pull-down module, electrically connected to the trigger signal input terminal, the first clock signal line, the second clock signal line, the first level signal line, the first node, and the second node, respectively, and configured to pull down the voltage of the first node under the control of the voltage of the second node;

[0009] an input module, electrically connected to the first clock signal line, the trigger signal input terminal, and the third node, respectively, and configured to transmit the signal input from the trigger signal input terminal to the third node under the control of the signal input from the first clock signal line;

[0010] a pull-up module electrically connected to the first node, the first level signal line and the control terminal respectively, and configured to pull up the voltage of the first node under the control of the control terminal;

[0011] an output module electrically connected to the first node, the first level signal line, and the output end of the shift register, respectively, and transmitting the signal input by the first level signal line to the output end under the control of the voltage of the first node;

[0012] a reset module electrically connected to the third node, the second-level signal line, and the fourth node, respectively, the reset module being configured to transmit the signal input by the second-level signal line to the output end under the control of the voltage of the fourth node, so as to reset the output end;

[0013] The regulating module is electrically connected to the first node, the fourth node, the fifth node, the first level signal line and the control clock signal line respectively, and the regulating module is configured to assist the reset module in resetting the output end under the control of the voltage of the fifth node.

[0014] In at least one embodiment of the present application, the first level signal line and the second level signal line both transmit signals with constant voltage, and the voltage of the signal transmitted by the first level signal line is greater than the voltage of the signal transmitted by the second level signal line.

[0015] In at least one embodiment of the present application, the control terminal includes the trigger signal input terminal;

[0016] Alternatively, the control end includes the third node, and the pull-up module is electrically connected to the input module via the third node.

[0017] In at least one embodiment of the present application, the pull-down module includes a first transistor, a second transistor, a third transistor, and a first capacitor;

[0018] The gate of the first transistor is electrically connected to the second node, the source of the first transistor is electrically connected to the first clock signal line, and the drain of the first transistor is electrically connected to the first node; the source of the second transistor and the source of the third transistor are electrically connected to the first level signal line respectively, the drain of the second transistor and the drain of the third transistor are electrically connected to the second node respectively, the gate of the second transistor is electrically connected to the trigger signal input terminal, and the gate of the third transistor is electrically connected to the second clock signal line; the first electrode of the first capacitor is electrically connected to the source of the first transistor, and the second electrode of the first capacitor is electrically connected to the second node.

[0019] In at least one embodiment of the present application, the input module includes a fourth transistor, the gate of the fourth transistor is electrically connected to the first clock signal line, the source of the fourth transistor is electrically connected to the trigger signal input end, and the drain of the fourth transistor is electrically connected to the third node.

[0020] In at least one embodiment of the present application, the pull-up module includes a fifth transistor, a source of the fifth transistor is electrically connected to the first node, and a drain of the fifth transistor is electrically connected to the first level signal line;

[0021] The gate of the fifth transistor is electrically connected to the third node; or the gate of the fifth transistor is electrically connected to the trigger signal input terminal.

[0022] In at least one embodiment of the present application, the reset module includes a sixth transistor, a seventh transistor and a second capacitor, the gate of the sixth transistor is electrically connected to the second-level signal line, the source of the sixth transistor is electrically connected to the third node, and the drain of the sixth transistor is electrically connected to the fourth node; the gate of the seventh transistor is electrically connected to the fourth node, the source of the seventh transistor is electrically connected to the output end, and the drain of the seventh transistor is electrically connected to the second-level signal line; the first electrode of the second capacitor is electrically connected to the fourth node, and the second electrode of the second capacitor is electrically connected to the output end.

[0023] In at least one embodiment of the present application, the output module includes an eighth transistor and a third capacitor, the gate of the eighth transistor is electrically connected to the first node, the source of the eighth transistor is electrically connected to the first level signal line, and the drain of the eighth transistor is electrically connected to the output end; the first electrode of the third capacitor is electrically connected to the first node, and the second electrode of the third capacitor is electrically connected to the first level signal line.

[0024] In at least one embodiment of the present application, the regulation module includes a ninth transistor, a tenth transistor and a fourth capacitor, the gate of the ninth transistor is electrically connected to the first node, the source of the ninth transistor is electrically connected to the first level signal line, and the drain of the ninth transistor is electrically connected to the fifth node; the gate of the tenth transistor is electrically connected to the fourth node, the source of the tenth transistor is electrically connected to the fifth node, and the drain of the tenth transistor is electrically connected to the control clock signal line.

[0025] In at least one embodiment of the present application, the control clock signal line includes a third clock signal line and a fourth clock signal line, the third clock signal line is electrically connected to the drain of the tenth transistor in the shift register of the odd-numbered stages, and the fourth clock signal line is electrically connected to the drain of the tenth transistor in the shift register of the even-numbered stages;

[0026] The first signal edge of the third clock signal transmitted by the third clock signal line is delayed by a first preset time period relative to the first signal edge of the first clock signal transmitted by the first clock signal line, and the first signal edge of the fourth clock signal transmitted by the fourth clock signal line is delayed by the first preset time period relative to the first signal edge of the second clock signal transmitted by the second clock signal line, and the first signal edge includes a rising edge or a falling edge.

[0027] In at least one embodiment of the present application, the control clock signal line includes a third clock signal line, and the third clock signal line is electrically connected to the drain of the tenth transistor in each stage of the shift register;

[0028] The period and pulse width of the first clock signal transmitted by the first clock signal line are 2N times the third clock signal transmitted by the third clock signal line, where N is a positive integer; the first signal edge of the third clock signal transmitted by the third clock signal line is delayed by a first preset time period relative to the first signal edge of the first clock signal transmitted by the first clock signal line, and the first signal edge includes a rising edge or a falling edge.

[0029] In at least one embodiment of the present application, the control clock signal line includes the first clock signal line.

[0030] In at least one embodiment of the present application, the first preset time period includes 0 to 2 μs.

[0031] In at least one embodiment of the present application, all of the transistors are P-type transistors.

[0032] In a second aspect, an embodiment of the present application provides a display device, comprising a driving circuit as described in any one of the first aspects, and further comprising a plurality of sub-pixels arranged in an array, wherein the sub-pixels include a pixel driving circuit, and one of the shift registers is electrically connected to each of the pixel driving circuits in the same row of the sub-pixels.

[0033] In a third aspect, the present application provides a driving method, which is applied to the driving circuit as described in any one of the first aspects; the method comprises:

[0034] In the input stage, a high-level trigger signal is input to the trigger signal input terminal electrically connected to the shift register, a high-level first clock signal is input to the first clock signal line, a low-level second clock signal is input to the second clock signal line, a first-level signal is input to the first-level signal line, a second-level signal is input to the second-level signal line, and a high-level control clock signal is input to the control clock signal line;

[0035] In the output stage, a high-level trigger signal is input to the trigger signal input terminal, a low-level first clock signal is input to the first clock signal line, a high-level second clock signal is input to the second clock signal line, a first-level signal is input to the first-level signal line, a second-level signal is input to the second-level signal line, and a low-level control clock signal is input to the control clock signal line;

[0036] In the reset phase, a low-level trigger signal is input to the trigger signal input terminal, a low-level first clock signal is input to the first clock signal line, a high-level second clock signal is input to the second clock signal line, a first-level signal is input to the first-level signal line, a second-level signal is input to the second-level signal line, and a low-level control clock signal is input to the control clock signal line.

[0037] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0039] FIG1 is a schematic structural diagram of a pixel driving circuit provided in an embodiment of the present application;

[0040] 2 to 4 are schematic diagrams of circuit structures of three shift registers provided in embodiments of the present application;

[0041] 5 to 7 are schematic diagrams showing electrical connection relationships of multiple shift registers in three driving circuits provided in embodiments of the present application;

[0042] FIG8 is a timing diagram corresponding to FIG2;

[0043] FIG9 is a comparison diagram of reset time curves of a shift register provided in an embodiment of the present application and a shift register in a related art;

[0044] FIG10 is a timing diagram corresponding to FIG3 ;

[0045] FIG11A is a comparison diagram of current change curves of the seventh transistor T7 in the circuit structure shown in FIG2 and the circuit structure shown in FIG3;

[0046] FIG11B is a comparison diagram of the current change curves of the eighth transistor T8 in the circuit structure shown in FIG2 and the circuit structure shown in FIG3;

[0047] 12 to 17 are diagrams illustrating the states of components during the driving process of the circuit structure shown in FIG. 2 when driven under the timing shown in FIG. 8 . Specific embodiments

[0048] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0049] In the embodiments of the present application, words such as "first", "second", "third", and "fourth" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0050] In the embodiments of the present application, the terms "upper" and "lower" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0051] Throughout the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present application. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0052] In the embodiments of the present application, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0053] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, that is, meaning "including, but not limited to."

[0054] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0055] In the embodiment of the present application, since the source and drain of the transistor are symmetrical, the source and drain can be interchanged.

[0056] In order to ensure high-frequency charging of each sub-pixel in the display product and compensate for the uneven brightness problem caused by insufficient threshold voltage (Vth) of the driving transistor, the relevant technology adopts a pixel driving circuit (9T2C) as shown in Figure 1 to improve it. In the pixel driving circuit shown in Figure 1, an AZn signal needs to be provided to drive the second transistor M2, the sixth transistor M6 and the seventh transistor M7. The main function of the second transistor M2 is to control the compensation time of the threshold voltage (Vth) of the driving transistor (M8); the AZn signal is provided by the shift register (GOA) circuit. At this time, the driving capability of the GOA that provides the AZn signal is particularly important.

[0057] However, the GOA used to provide the AZn signal in the related art has a slow reset speed during reset, thereby affecting the control of the compensation time of the threshold voltage (Vth) of the driving transistor (M8) by the second transistor M2 in the pixel driving circuit. This may cause differences in the compensation time of the threshold voltage (Vth) in each pixel. When applied to display products, there may be a problem of uneven display brightness, which reduces the display effect.

[0058] Based on this, the embodiments of the present application urgently need to provide a shift register (GOA) circuit capable of rapid reset, so as to improve the display problem caused by the slow reset speed of the GOA.

[0059] An embodiment of the present application provides a driving circuit, as shown in Figure 5, Figure 6 or Figure 7, comprising: a plurality of shift registers (GOA) arranged in cascade; wherein, for the first-stage shift register (GOA1), a first scanning signal G[1] can be output according to a trigger signal (such as an STV signal) and a clock signal (including at least CK and CB signals). The first scanning signal G[1] output by the first-stage shift register serves as an input signal (Input) of the second-stage shift register. Similarly, for the second-stage and subsequent shift registers, the scanning signal output by the previous-stage shift register serves as an input signal of the next-stage shift register (i.e., the signal serves as a trigger signal). The second-stage and subsequent shift registers (GOA2, GOA3...GOAN) output the scanning signal of the current-stage shift register according to the scanning signal output by the previous-stage shift register and the received clock signal, wherein the output end of a shift register is electrically connected to at least one gate line to input the corresponding scanning signal into the gate line.

[0060] In actual applications, only the trigger signal of the first-stage shift register (GOA1) is the STV signal. At this time, the first-stage shift register (GOA1) and the STV signal line are electrically connected; the trigger signals of the shift registers at each stage after the first stage are all the scan signals output by the previous-stage shift register.

[0061] In some embodiments of the present application, as shown in FIG2 , FIG3 and FIG4 , the shift register includes:

[0062] The pull-down module 1 is electrically connected to the trigger signal input terminal (e.g., the STV signal input terminal), the first clock signal line CK line, the second clock signal line CB line, the first level signal line VGH line, the first node PU, and the second node PU-c. The pull-down module 1 is configured to pull down the voltage of the first node PU under the control of the voltage of the second node PU-c.

[0063] an input module 2 electrically connected to the first clock signal line CK line, the trigger signal input terminal, and the third node PD-in, and configured to transmit a signal input from the trigger signal input terminal to the third node PD-in under the control of a signal input from the first clock signal line CK line;

[0064] The pull-up module 3 is electrically connected to the first node PU, the first level signal line VGH line and the control terminal respectively. The pull-up module 3 is configured to pull up the voltage of the first node PU under the control of the control terminal.

[0065] The output module 5 is electrically connected to the first node PU, the first level signal line VGH line, and the output terminal Gout of the shift register. Under the control of the voltage of the first node PU, the output module 5 transmits the signal input by the first level signal line VGH line to the output terminal Gout.

[0066] a reset module 4 electrically connected to the third node PD-in, the second level signal line VGL, and the fourth node PD-out, respectively. The reset module 4 is configured to transmit a signal inputted from the second level signal line VGL to the output terminal Gout under the control of the voltage of the fourth node PD-out, so as to reset the output terminal Gout;

[0067] The adjustment module 6 is electrically connected to the first node PU, the fourth node PD-out, the fifth node PD-c, the first level signal line VGH line and the control clock signal line, respectively. The adjustment module 6 is configured to assist the reset module 4 in resetting the output terminal Gout under the control of the voltage of the fifth node PD-c.

[0068] Here, there is no limitation on the specific circuit structure included in the above-mentioned pull-down module 1, input module 2, pull-up module 3, output module 5, reset module 4, and adjustment module 6. As long as the corresponding functions are met, they are within the scope of the driving circuit protection provided in the embodiments of the present application.

[0069] The above-mentioned first node PU, second node PU-c, third node PD-in, fourth node PD-out, and fifth node PD-c are only defined for the convenience of describing the circuit structure. The first node PU, second node PU-c, third node PD-in, fourth node PD-out, and fifth node PD-c are not actual circuit structures.

[0070] In at least one embodiment of the present application, the control terminal includes a trigger signal input terminal (eg, an STV terminal).

[0071] In an exemplary embodiment, as shown in Figures 3 and 4, the pull-up module 3 is electrically connected to the first node PU, the first level signal line VGH line and the trigger signal input terminal (for example, the STV terminal), respectively, and the pull-up module 3 is configured to pull up the voltage of the first node PU under the control of the voltage of the third node PD-in.

[0072] In some other embodiments, the control end includes a third node PD-in, and the pull-up module 3 is electrically connected to the input module 2 via the third node PD-in.

[0073] In an exemplary embodiment, as shown in Figure 2, the pull-up module 3 is electrically connected to the first node PU, the first level signal line VGH line and the third node PD-in, respectively, and the pull-up module 3 is configured to pull up the voltage of the first node PU under the control of the voltage of the third node PD-in.

[0074] In an exemplary embodiment, as shown in Figure 4, the adjustment module 6 is electrically connected to the first node PU, the fourth node PD-out, the fifth node PD-c, the first level signal line VGH line and the first clock signal line CK line, respectively. The adjustment module 6 is configured to lower the voltage of the fourth node PD-out under the control of the voltage of the fifth node PD-c.

[0075] In an exemplary embodiment, as shown in Figures 2 and 3 , the adjustment module 6 is electrically connected to the first node PU, the fourth node PD-out, the fifth node PD-c, the first level signal line VGH, and the third clock signal line CK2. The adjustment module 6 is configured to lower the voltage of the fourth node PD-out under the control of the voltage of the fifth node PD-c. In this case, the display device includes an additional third clock signal line CK2. The period and pulse width of the clock signal transmitted by the third clock signal line CK2 can be the same as those of the clock signal transmitted by the first clock signal line CK.

[0076] In the driving circuit provided in the embodiment of the present application, by setting a pull-down module 1, an input module 2, a pull-up module 3, an output module 5, a reset module 4 and an adjustment module 6 to cooperate with each other, on the one hand, it can output scanning signals in sequence to control the row-by-row scanning of pixels in the array substrate; on the other hand, during the driving process of the driving circuit, when the reset module 4 resets the output terminal Gout of the shift register, the adjustment module 6 can quickly pull down the voltage of the fourth node PD-out, so that the reset module 4 can quickly transmit the signal input by the second level signal line VGL line to the output terminal Gout under the control of the voltage of the fourth node PD-out to reset the output terminal Gout, thereby improving the reset speed of the output terminal Gout of the shift register, thereby improving the driving capability of the shift register. When the driving circuit is used in combination with the pixel driving circuit shown in Figure 1 on the array substrate, it can greatly reduce the difference in compensation time of the pixel driving circuit in each sub-pixel, so that the charging rate of each sub-pixel tends to be exactly the same, thereby improving the display brightness uniformity and improving the display effect.

[0077] In at least one embodiment of the present application, the first level signal line VGH line and the second level signal line VGL line both transmit signals with constant voltage, and the voltage of the signal transmitted by the first level signal line VGH line is greater than the voltage of the signal transmitted by the second level signal line VGL line.

[0078] The voltages of the signals transmitted by the first level signal line VGH and the second level signal line VGL are not limited here, and can be specifically designed according to the type of product.

[0079] In at least one embodiment of the present application, as shown in FIG2 , FIG3 and FIG4 , the pull-down module 1 includes a first transistor T1 , a second transistor T2 , a third transistor T3 and a first capacitor C1 ;

[0080] The gate of the first transistor T1 is electrically connected to the second node PU-c, the source of the first transistor T1 is electrically connected to the first clock signal line CK line, and the drain of the first transistor T1 is electrically connected to the first node PU; the source of the second transistor T2 and the source of the third transistor T3 are electrically connected to the first level signal line VGH line, respectively, the drain of the second transistor T2 and the drain of the third transistor T3 are electrically connected to the second node PU-c, respectively, the gate of the second transistor T2 is electrically connected to the trigger signal input terminal (for example, the STV terminal), and the gate of the third transistor T3 is electrically connected to the second clock signal line CB line; the first electrode of the first capacitor C1 is electrically connected to the source of the first transistor T1, and the second electrode of the first capacitor C1 is electrically connected to the second node PU-c.

[0081] It should be noted that, for the second transistor T2 in the first-stage shift register, its gate is electrically connected to the trigger signal input terminal (for example, the STV terminal); for the shift register after the first stage, its gate is electrically connected to the trigger signal input terminal (for example, the output terminal Gout of the previous-stage shift register).

[0082] In at least one embodiment of the present application, as shown in Figures 2, 3 and 4, the input module 2 includes a fourth transistor T4, the gate of the fourth transistor T4 is electrically connected to the first clock signal line CK line, the source of the fourth transistor T4 is electrically connected to the trigger signal input terminal (for example, the STV terminal), and the drain of the fourth transistor T4 is electrically connected to the third node PD-in.

[0083] It should be noted that, for the fourth transistor T4 in the first-stage shift register, its source is electrically connected to the trigger signal input terminal (for example, the STV terminal); for the shift register after the first stage, its source is electrically connected to the trigger signal input terminal (for example, the output terminal Gout of the previous-stage shift register).

[0084] In at least one embodiment of the present application, as shown in FIG2 , FIG3 and FIG4 , the pull-up module 3 includes a fifth transistor T5 , a source of the fifth transistor T5 is electrically connected to the first node PU, and a drain of the fifth transistor T5 is electrically connected to the first level signal line VGH line;

[0085] As shown in FIG2 , the gate of the fifth transistor T5 is electrically connected to the third node PD-in; or, the gate of the fifth transistor T5 is electrically connected to the trigger signal input terminal (eg, the STV terminal).

[0086] In an exemplary embodiment, when the gate of the fifth transistor T5 is electrically connected to the third node PD-in, the fifth transistor T5 is turned on or off by the control of the voltage of the third node PD-in; when the gate of the fifth transistor T5 is electrically connected to the trigger signal input terminal (e.g., the STV terminal), the fifth transistor T5 is turned on or off by the control of the signal transmitted from the trigger signal input terminal (e.g., the STV terminal).

[0087] Among them, when the gate of the fifth transistor T5 is electrically connected to the trigger signal input terminal, for the fifth transistor T5 in the first-stage shift register, the trigger signal input terminal is the STV terminal; for the shift register after the first stage, the trigger signal input terminal is the output terminal Gout of the previous-stage shift register.

[0088] In an embodiment of the present application, when the gate of the fifth transistor T5 is electrically connected to the trigger signal input terminal (for example, the STV terminal), the voltage of the first node PU can be raised in advance through the STV signal, and the eighth transistor T8 is first turned off, and then the seventh transistor T7 is turned on, thereby avoiding the possibility of the first level signal line VGH line and the second level signal line VGL line being turned on at the same time through the seventh transistor T7 and the eighth transistor T8, which can greatly reduce the power consumption of the shift register.

[0089] In at least one embodiment of the present application, as shown in Figures 2, 3 and 4, the reset module 4 includes a sixth transistor T6, a seventh transistor T7 and a second capacitor C2, the gate of the sixth transistor T6 is electrically connected to the second level signal line VGL line, the source of the sixth transistor T6 is electrically connected to the third node PD-in, and the drain of the sixth transistor T6 is electrically connected to the fourth node PD-out; the gate of the seventh transistor T7 is electrically connected to the fourth node PD-out, the source of the seventh transistor T7 is electrically connected to the output terminal Gout, and the drain of the seventh transistor T7 is electrically connected to the second level signal line VGL line; the first electrode of the second capacitor C2 is electrically connected to the fourth node PD-out, and the second electrode of the second capacitor C2 is electrically connected to the output terminal Gout.

[0090] In at least one embodiment of the present application, as shown in Figures 2, 3 and 4, the output module 5 includes an eighth transistor T8 and a third capacitor C3, the gate of the eighth transistor T8 is electrically connected to the first node PU, the source of the eighth transistor T8 is electrically connected to the first level signal line VGH line, and the drain of the eighth transistor T8 is electrically connected to the output end Gout; the first electrode of the third capacitor C3 is electrically connected to the first node PU, and the second electrode of the third capacitor C3 is electrically connected to the first level signal line VGH line.

[0091] In at least one embodiment of the present application, as shown in Figures 2, 3 and 4, the regulation module 6 includes a ninth transistor T9, a tenth transistor T10 and a fourth capacitor C4, the gate of the ninth transistor T9 is electrically connected to the first node PU, the source of the ninth transistor T9 is electrically connected to the first level signal line VGH line, and the drain of the ninth transistor T9 is electrically connected to the fifth node PD-c; the gate of the tenth transistor T10 is electrically connected to the fourth node PD-out, the source of the tenth transistor T10 is electrically connected to the fifth node PD-c, and the drain of the tenth transistor T10 is electrically connected to the control clock signal line.

[0092] In at least one embodiment of the present application, as shown in FIG5 , the control clock signal line includes a third clock signal line CK2 and a fourth clock signal line CB2. In combination with FIG2 or FIG3 , the third clock signal line CK2 is electrically connected to the drain of the tenth transistor T10 in the odd-numbered shift register, and the fourth clock signal line CB2 is electrically connected to the drain of the tenth transistor T10 in the even-numbered shift register.

[0093] The first signal edge of the third clock signal transmitted by the third clock signal line is delayed by a first preset time period relative to the first signal edge of the first clock signal transmitted by the first clock signal line, and the first signal edge of the fourth clock signal transmitted by the fourth clock signal line is delayed by a first preset time period relative to the first signal edge of the second clock signal transmitted by the second clock signal line, and the first signal edge includes a rising edge or a falling edge.

[0094] In some embodiments, the rising edge of the third clock signal CK2 signal transmitted by the third clock signal line CK2 is delayed by a first preset time period relative to the rising edge of the first clock signal CK signal transmitted by the first clock signal line CK, and the rising edge of the fourth clock signal CB2 signal transmitted by the fourth clock signal line CB2 is delayed by a first preset time period relative to the rising edge of the second clock signal CB signal transmitted by the second clock signal line CB.

[0095] In other embodiments, referring to the marks at the bold dotted positions in Figure 10, the falling edge of the third clock signal CK2 signal transmitted by the third clock signal line CK2 line is delayed by a first preset time period relative to the falling edge of the first clock signal CK signal transmitted by the first clock signal line CK line, and the falling edge of the fourth clock signal CB2 signal transmitted by the fourth clock signal line CB2 line is delayed by a first preset time period relative to the falling edge of the second clock signal CB signal transmitted by the second clock signal line CB line.

[0096] It should be noted that the falling edge determines the reset start time in the PMOS circuit, and the rising edge determines the reset start time in the NMOS circuit.

[0097] For example, in the timing sequences shown in FIG8 and FIG10 , the third clock signal CK2 transmitted by the third clock signal line CK2 and the first clock signal CK transmitted by the first clock signal line CK have the same period and pulse width, and the fourth clock signal CB2 transmitted by the fourth clock signal line CB2 and the second clock signal CB transmitted by the second clock signal line CB have the same period and pulse width. Alternatively, the third clock signal CK2 transmitted by the third clock signal line CK2 and the first clock signal CK transmitted by the first clock signal line CK have different periods and pulse widths, and the fourth clock signal CB2 transmitted by the fourth clock signal line CB2 and the second clock signal CB transmitted by the second clock signal line CB have different periods and pulse widths.

[0098] In an exemplary embodiment, taking an odd-numbered shift register as an example, the third clock signal line CK2 is electrically connected to the drain of the tenth transistor T10 in the odd-numbered shift register. As shown in FIG2 , during the reset process of the shift register, the fourth transistor T4 is turned on by the control of the first clock signal CK, the signal input from the second level signal line VGL controls the sixth transistor T6 to be turned on, and the trigger signal inputted from the trigger signal input terminal (e.g., the STV signal input terminal) can pull down the voltage of the fourth node PD-out, thereby controlling the seventh transistor T7 to be turned on, and the output terminal Gout is reset (pulled down) by the seventh transistor T7. ); however, usually in the process of pulling down, the threshold voltage Vth of the seventh transistor T7 may attenuate, and the voltage of the output terminal Gout cannot be quickly pulled down to the level of the VGL line; in the embodiment of the present application, by setting the third clock signal CK2 signal that is slightly delayed relative to the first clock signal CK signal, the voltage of the fourth node PD-out is further pulled down through the coupling effect of the tenth transistor T10 and the fourth capacitor C4, thereby extending the time for pulling down the voltage of the fourth node PD-out, so that the output terminal Gout can be quickly reset by turning on the seventh transistor T7, thereby improving the driving capability of the shift register.

[0099] In an exemplary embodiment, taking an even-numbered shift register as an example, the fourth clock signal line CB2 is electrically connected to the drain of the tenth transistor T10 in the even-numbered shift register. During a reset process of the shift register, the fourth transistor T4 is turned on by the control of the second clock signal CB, the signal input from the second level signal line VGL controls the sixth transistor T6 to be turned on, and the trigger signal input from the trigger signal input terminal (e.g., the STV signal input terminal) can pull down the voltage of the fourth node PD-out, thereby controlling the seventh transistor T7 to be turned on, and resetting (pulling down) the output terminal Gout via the seventh transistor T7. However, Typically, during the pull-down process, the threshold voltage Vth of the seventh transistor T7 may attenuate, and the voltage of the output terminal Gout may not be quickly pulled down to the level of the VGL line. In an embodiment of the present application, by setting a fourth clock signal CB2 signal that is slightly delayed relative to the second clock signal CB signal, the voltage of the fourth node PD-out is further pulled down through the coupling effect of the tenth transistor T10 and the fourth capacitor C4, thereby extending the time for pulling down the voltage of the fourth node PD-out. This allows the output terminal Gout to be quickly reset by turning on the seventh transistor T7, thereby improving the driving capability of the shift register.

[0100] As shown in Figure 9, a comparison of the reset curves of the shift register provided by the present application as shown in Figure 2 and the shift register in the related art when they are reset is provided, wherein the one marked Ref is the reset process curve of the shift register in the related art, and the one marked A is the reset time curve of the shift register shown in Figure 2 of the present application. It can be clearly seen that the reset time of the output terminal Gout of the shift register provided by the embodiment of the present application is significantly improved. Through simulation calculation, it can be obtained that the reset time of the output terminal Gout of the shift register can be improved from 1.13 microseconds to about 0.58 microseconds, and the reset time is shortened by nearly half.

[0101] It should be noted that, as shown in FIG5 , in the GOA of even-numbered stages, the corresponding connected CK signal line and CB signal line are swapped with respect to the GOA of odd-numbered stages, so that the driving process of each GOA is the same. For a detailed description of this, please refer to the introduction of the shift register cascade setting in the related art, which will not be repeated here.

[0102] In at least one embodiment of the present application, as shown in FIG6 , the control clock signal line includes a third clock signal line CK2 line, and the third clock signal line CK2 line is electrically connected to the drain of the tenth transistor T10 in each stage of the shift register (odd-stage GOA and even-stage GOA);

[0103] The period and pulse width of the first clock signal CK signal transmitted by the first clock signal line CK line are 2N times that of the third clock signal CK2 signal transmitted by the third clock signal line CK2 line, where N is a positive integer, generally 1;

[0104] The first signal edge of the third clock signal CK2 transmitted by the third clock signal line CK2 is delayed by a first preset time period relative to the first signal edge of the first clock signal CK transmitted by the first clock signal line CK.

[0105] For example, the first signal edge may be a rising edge or a falling edge.

[0106] In some embodiments, a rising edge of the third clock signal CK2 transmitted by the third clock signal line CK2 is delayed by a first preset time period relative to a rising edge of the first clock signal CK transmitted by the first clock signal line CK.

[0107] In some other embodiments, a falling edge of the third clock signal CK2 transmitted by the third clock signal line CK2 is delayed by a first preset time period relative to a falling edge of the first clock signal CK transmitted by the first clock signal line CK.

[0108] For the specific circuit structure of the shift register as shown in Figure 2 or Figure 3, the third clock signal line CK2 line and the drain of the tenth transistor T10 in each level of the shift register (odd-level GOA and even-level GOA) are electrically connected; and the rising edge of the third clock signal CK2 signal transmitted by the third clock signal line CK2 line is delayed by a first preset time period relative to the rising edge of the first clock signal CK signal transmitted by the first clock signal line CK line.

[0109] In this way, during the reset process of the shift register, the fourth transistor T4 is turned on by controlling the first clock signal CK signal, the signal input by the second level signal line VGL line controls the sixth transistor T6 to be turned on, and the trigger signal input by the trigger signal input terminal (for example, the STV signal input terminal) can pull down the voltage of the fourth node PD-out, thereby controlling the seventh transistor T7 to be turned on, and resetting (pulling down) the output terminal Gout through the seventh transistor T7; but usually in the pull-down process, the threshold voltage Vth of the seventh transistor T7 may be attenuated, and the voltage of the output terminal Gout cannot be quickly pulled down to the level of the VGL line; in an embodiment of the present application, by setting a third clock signal CK2 signal that is slightly delayed relative to the first clock signal CK signal, the voltage of the fourth node PD-out is further pulled down through the coupling effect of the tenth transistor T10 and the fourth capacitor C4, thereby extending the time for pulling down the voltage of the fourth node PD-out, so that the output terminal Gout can be quickly reset by turning on the seventh transistor T7, thereby improving the driving capability of the shift register. In addition, compared to setting up four clock signal lines, this embodiment only requires three clock signal lines, which can release the design space of the peripheral area of ​​the array substrate, thereby facilitating the preparation of narrow-frame display products.

[0110] In at least one embodiment of the present application, as shown in conjunction with FIG. 4 and FIG. 7 , the control clock signal line includes a first clock signal line CK line. Specifically, the drain of the tenth transistor T10 is electrically connected to the first clock signal line CK line. This ensures that the reset time of the shift register is shortened compared to shift registers in related art while significantly freeing up design space in the peripheral area of ​​the array substrate, thereby facilitating the production of narrow-frame display products.

[0111] In at least one embodiment of the present application, the first preset time period includes 0 to 2 μs.

[0112] Exemplarily, the first preset time period may be 0μs, 0.5μs, 0.8μs, 1μs, 1.3μs, 1.5μs, or 1.8μs. The specific time of the first preset time period is determined by the load of the gate line and the capacitance of the capacitor inside the shift register, and can be set according to actual conditions.

[0113] In at least one embodiment of the present application, all transistors are P-type transistors.

[0114] For example, all transistors may be MOS transistors, where MOS is the abbreviation of MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0115] An embodiment of the present application provides a display device, including the driving circuit as described above, and also including a plurality of sub-pixels arranged in an array, the sub-pixels including a pixel driving circuit, and a shift register electrically connected to each pixel driving circuit in the same row of sub-pixels through a gate line.

[0116] The display device provided by the embodiment of the present application, by setting a pull-down module 1, an input module 2, a pull-up module 3, an output module 5, a reset module 4 and an adjustment module 6 to cooperate with each other, on the one hand, can output scanning signals in sequence to control the row-by-row scanning of pixels in the array substrate; on the other hand, during the driving process of the driving circuit, when the reset module 4 resets the output terminal Gout of the shift register, the adjustment module 6 can quickly pull down the voltage of the fourth node PD-out, so that the reset module 4 can quickly transmit the signal input by the second level signal line VGL line to the output terminal Gout under the control of the voltage of the fourth node PD-out to reset the output terminal Gout, thereby improving the reset speed of the output terminal Gout of the shift register, thereby improving the driving ability of the shift register, and can greatly reduce the difference in compensation time of the pixel driving circuit in each sub-pixel, so that the charging rate of each sub-pixel tends to be exactly the same, thereby improving the display brightness uniformity of the display device and improving the display effect.

[0117] The present application provides a driving method, which is applied to the driving circuit as described above. The driving method includes:

[0118] S801. In the input stage, a high-level trigger signal is input to a trigger signal input terminal (e.g., an STV signal input terminal) electrically connected to the shift register, a high-level first clock signal is input to the first clock signal line CK line, a low-level second clock signal is input to the second clock signal line CB line, a first-level signal is input to the first-level signal line VGH line, a second-level signal is input to the second-level signal line VGL line, and a high-level control clock signal is input to the control clock signal line;

[0119] S802. In the output phase, a high-level trigger signal is input to the trigger signal input terminal (e.g., the STV signal input terminal), a low-level first clock signal is input to the first clock signal line CK line, a high-level second clock signal is input to the second clock signal line CB line, a first-level signal is input to the first-level signal line VGH line, a second-level signal is input to the second-level signal line VGL line, and a low-level control clock signal is input to the control clock signal line;

[0120] S803. In the reset phase, a low-level trigger signal is input to the trigger signal input terminal (for example, the STV signal input terminal), a low-level first clock signal is input to the first clock signal line CK line, a high-level second clock signal is input to the second clock signal line CB line, a first-level signal is input to the first-level signal line VGH line, a second-level signal is input to the second-level signal line VGL line, and a low-level control clock signal is input to the control clock signal line.

[0121] The driving method of the driving circuit provided by the embodiment of the present application, during the driving process of the driving circuit, when the reset module 4 resets the output terminal Gout of the shift register, the adjustment module 6 can quickly pull down the voltage of the fourth node PD-out, so that the reset module 4 can quickly transmit the signal input by the second level signal line VGL line to the output terminal Gout under the control of the voltage of the fourth node PD-out to reset the output terminal Gout, thereby improving the reset speed of the output terminal Gout of the shift register, thereby improving the driving ability of the shift register, and can greatly reduce the difference in compensation time of the pixel driving circuit in each sub-pixel, so that the charging rate of each sub-pixel tends to be exactly the same, thereby improving the display brightness uniformity of the display device and improving the display effect.

[0122] The following takes the circuit diagram shown in FIG2 as an example, assuming that all transistors are P-type transistors, to specifically explain the driving principle and driving process of the driving circuit;

[0123] Figure 8 provides the timing sequence corresponding to the circuit diagram in Figure 2, and Figures 12-17 provide the circuit states of the circuit diagram in Figure 2 at different stages of the timing sequence shown in Figure 8. It should be noted that in Figures 12-17, the mark "H" indicates a high-level input signal, the mark "L" indicates a low-level input signal, the "×" mark indicates a transistor is off, and the "√" mark indicates a transistor is on.

[0124] In the first phase t1 (input phase), as shown in conjunction with FIG2 and FIG8 , a high-level trigger signal is input to the trigger signal input terminal (e.g., the STV signal input terminal) electrically connected to the shift register, a high-level first clock signal is input to the first clock signal line CK line, a low-level second clock signal is input to the second clock signal line CB line, a first-level signal is input to the first-level signal line VGH line, a second-level signal is input to the second-level signal line VGL line, and a high-level control clock signal is input to the control clock signal line (the third clock signal line CK2 line);

[0125] At this time, as shown in Figure 12, the second node PU-c is pulled up under the action of the first capacitor C1, the first transistor T1 is turned off, the second transistor T2 is turned off, the third transistor T3 is turned on, the fourth transistor T4 is turned off, and the fifth transistor T5 is turned on. The voltage of the first node PU is pulled high, the eighth transistor T8 is turned off, the ninth transistor T9 is turned off, the seventh transistor T7 is turned on, and the tenth transistor T10 is turned on. The output of the output terminal Gout maintains a low-level signal. This process is an advance shift process.

[0126] In the second phase t2 (output phase), as shown in combination with FIG2 and FIG8 , a high-level trigger signal is input to the trigger signal input terminal (for example, the STV signal input terminal), a low-level first clock signal is input to the first clock signal line CK line, a high-level second clock signal is input to the second clock signal line CB line, a first-level signal is input to the first-level signal line VGH line, a second-level signal is input to the second-level signal line VGL line, and a low-level control clock signal is input to the control clock signal line (the third clock signal line CK2 line);

[0127] At this time, as shown in Figure 13, the first transistor T1 is turned on, the second transistor T2 is turned off, the third transistor T3 is turned off, the fourth transistor T4 is turned on, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the seventh transistor T7 is turned off. The voltage of the first node PU is pulled low, the eighth transistor T8 is turned on, and the ninth transistor T9 is turned on. The voltages of the third node PD-in and the fourth node PD-out are both pulled high. At this time, the first level signal line VGH line transmits a high level signal to the output terminal Gout through the eighth transistor T8.

[0128] In the third stage t3, as shown in combination with FIG2 and FIG8 , a high-level trigger signal is input to the trigger signal input terminal (e.g., the STV signal input terminal) electrically connected to the shift register, a high-level first clock signal is input to the first clock signal line CK line, a low-level second clock signal is input to the second clock signal line CB line, a first-level signal is input to the first-level signal line VGH line, a second-level signal is input to the second-level signal line VGL line, and a high-level control clock signal is input to the control clock signal line (the third clock signal line CK2 line);

[0129] At this time, as shown in Figure 14, the first transistor T1 is turned off, the second transistor T2 is turned off, the third transistor T3 is turned on, the fourth transistor T4 is turned off, the fifth transistor T5 is turned on, the sixth transistor T6 is turned on, and the seventh transistor T7 is turned off. The voltage of the first node PU remains at a low level, the eighth transistor T8 and the ninth transistor T9 are kept on, and the tenth transistor T10 is turned off; the output terminal Gout maintains outputting a high-level signal.

[0130] In the fourth stage t4, as shown in combination with FIG2 and FIG8 , a high-level trigger signal is input to the trigger signal input terminal (e.g., the STV signal input terminal) electrically connected to the shift register, a low-level first clock signal is input to the first clock signal line CK line, a high-level second clock signal is input to the second clock signal line CB line, a first-level signal is input to the first-level signal line VGH line, a second-level signal is input to the second-level signal line VGL line, and a low-level control clock signal is input to the control clock signal line (the third clock signal line CK2 line);

[0131] At this time, as shown in Figure 15, the first transistor T1 is turned on, the second transistor T2 is turned off, the third transistor T3 is turned off, the fourth transistor T4 is turned on, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the seventh transistor T7 is turned off. The voltage of the first node PU maintains a low level, the eighth transistor T8 is turned on, and the ninth transistor T9 is turned on. The voltages of the third node PD-in and the fourth node PD-out both maintain high levels; at this time, the output terminal Gout maintains outputting a high-level signal.

[0132] In the fifth stage t5, as shown in combination with FIG2 and FIG8 , a low-level trigger signal is input to the trigger signal input terminal (e.g., the STV signal input terminal) electrically connected to the shift register, a high-level first clock signal is input to the first clock signal line CK line, a low-level second clock signal is input to the second clock signal line CB line, a first-level signal is input to the first-level signal line VGH line, a second-level signal is input to the second-level signal line VGL line, and a high-level control clock signal is input to the control clock signal line (the third clock signal line CK2 line);

[0133] At this time, as shown in Figure 16, the first transistor T1 is turned off, the second transistor T2 is turned on, the third transistor T3 is turned on, the fourth transistor T4 is turned off, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the seventh transistor T7 is turned off. The voltage of the first node PU remains at a low level, the eighth transistor T8 and the ninth transistor T9 are kept on, and the tenth transistor T10 is turned off; the output terminal Gout maintains outputting a high-level signal.

[0134] In the sixth stage t6 (reset stage), a low-level trigger signal is input to the trigger signal input terminal (for example, the STV signal input terminal), a low-level first clock signal is input to the first clock signal line CK line, a high-level second clock signal is input to the second clock signal line CB line, a first-level signal is input to the first-level signal line VGH line, a second-level signal is input to the second-level signal line VGL line, and a low-level control clock signal is input to the control clock signal line (for example, the third clock signal line CK2 line).

[0135] At this time, as shown in Figure 17, the first transistor T1 is turned off, the second transistor T2 is turned on, the third transistor T3 is turned off, the fourth transistor T4 is turned on, and the fifth transistor T5 is turned on. The voltage of the first node PU is pulled up, the eighth transistor T8 and the ninth transistor T9 are turned off, the sixth transistor T6 is turned on, and the seventh transistor T7 is turned on. The voltages of the third node PD-in and the fourth node PD-out are both pulled down. The tenth transistor is turned on. Under the coupling effect of the fourth capacitor C4, the voltage of the fourth node PD-out is further pulled down. When the rising edge of the signal input by the control clock signal line (for example, the third clock signal line CK2 line) is delayed by the first preset time relative to the rising edge of the signal input by the first clock signal line CK line, the time for pulling down the voltage of the fourth node PD-out is extended, so that the voltage of the fourth node PD-out is quickly reduced, which helps to quickly reset the signal of the output terminal Gout through the seventh transistor T7, thereby quickly pulling down the voltage of the output terminal Gout.

[0136] The following takes the circuit diagram shown in FIG3 as an example, assuming that all transistors are P-type transistors, to specifically explain the driving principle and driving process of the driving circuit; FIG10 provides the timing corresponding to the circuit diagram in FIG3;

[0137] The driving process of the circuit structure shown in FIG3 from the first stage t1 to the fourth stage t4 is the same as the driving process of the circuit structure shown in FIG2 , and the details are described above.

[0138] In the fifth stage t5, a low-level trigger signal is input to the trigger signal input terminal (e.g., the STV signal input terminal) electrically connected to the shift register, a high-level first clock signal is input to the first clock signal line CK line, a low-level second clock signal is input to the second clock signal line CB line, a first-level signal is input to the first-level signal line VGH line, a second-level signal is input to the second-level signal line VGL line, and a high-level control clock signal is input to the control clock signal line (the third clock signal line CK2 line).

[0139] At this time, the first transistor T1 is turned off, the second transistor T2 is turned on, the third transistor T3 is turned on, the fourth transistor T4 is turned off, the fifth transistor T5 is turned on, the voltage of the first node PU is pulled high, the eighth transistor T8 and the ninth transistor T9 are turned off, the sixth transistor T6 is turned on, the voltages of the third node PD-in and the fourth node PD-out are both high, the seventh transistor T7 is turned off, and the tenth transistor T10 is turned off; the output terminal Gout maintains outputting a high-level signal.

[0140] In the sixth stage t6 (reset stage), a low-level trigger signal is input to the trigger signal input terminal (for example, the STV signal input terminal), a low-level first clock signal is input to the first clock signal line CK line, a high-level second clock signal is input to the second clock signal line CB line, a first-level signal is input to the first-level signal line VGH line, a second-level signal is input to the second-level signal line VGL line, and a low-level control clock signal is input to the control clock signal line (for example, the third clock signal line CK2 line).

[0141] At this time, the first transistor T1 is turned off, the second transistor T2 is turned on, the third transistor T3 is turned off, the fourth transistor T4 is turned on, and the fifth transistor T5 is turned on. The voltage of the first node PU is pulled up, the eighth transistor T8 and the ninth transistor T9 are turned off, the sixth transistor T6 is turned on, and the seventh transistor T7 is turned on (when the seventh transistor T7 starts to turn on, the eighth transistor T8 is completely turned off). The voltages of the third node PD-in and the fourth node PD-out are both pulled down. The tenth transistor T10 is turned on. Under the coupling effect of the fourth capacitor C4, the voltage of the fourth node PD-out is further pulled down. When the rising edge of the signal input by the control clock signal line (for example, the third clock signal line CK2 line) is delayed by a first preset time relative to the rising edge of the signal input by the first clock signal line CK line, the time for pulling down the voltage of the fourth node PD-out is extended, causing the voltage of the fourth node PD-out to drop rapidly, thereby helping to quickly reset the signal of the output terminal Gout through the seventh transistor T7, thereby quickly pulling down the voltage of the output terminal Gout. In addition, since the voltage of the first node PU has been pulled up before the reset starts, the eighth transistor T8 has been completely turned off when the seventh transistor T7 starts to turn on, thereby avoiding the situation where the first level signal line VGH line and the second level signal line VGL line may be turned on through the seventh transistor T7 and the eighth transistor T8, reducing the power consumption of the driving circuit and extending its service life.

[0142] The driving process of the circuit structure shown in Figure 4 is the same as the driving process of the circuit structure shown in Figure 3. The difference is that the control clock signal terminal described in Figure 4 is the first clock signal line. At this time, during the reset process, the time for pulling down the fourth node PD-out voltage is shorter than the time for pulling down the fourth node PD-out voltage of the circuit structure shown in Figure 3.

[0143] In addition, it should be noted that Figure 11A provides a curve comparison of the reduction of the current of the seventh transistor T7 near the moment of the falling edge of the signal output from the output terminal Gout during the reset process of the circuit structure shown in Figure 2 and the circuit structure shown in Figure 3. By comparison, it can be seen that compared with the current change process of the seventh transistor T7 in the circuit structure shown in Figure 2 (such as the curve marked A in Figure 11), when the gate of the fifth transistor T5 is electrically connected to the STV signal input terminal (circuit structure of Figure 3), since the voltage of the first node PU is pulled up in advance, the eighth transistor T8 is completely turned off in advance, and the current of the seventh transistor T7 is not affected by the first level signal line VGH. The current of the seventh transistor T7 decreases significantly and the decrease speed is faster (such as the curve marked B in Figure 11).

[0144] Figure 11B provides a comparison curve of the current change of the eighth transistor T8 near the falling edge of the signal output from the output terminal Gout during the reset process of the circuit structure shown in Figure 2 and the circuit structure shown in Figure 3. By comparison, it can be seen that compared with the current change process of the eighth transistor T8 in the circuit structure shown in Figure 2 (such as the curve marked A in Figure 11B), when the gate of the fifth transistor T5 is electrically connected to the STV signal input terminal (circuit structure of Figure 3), since the voltage of the first node PU is pulled up in advance, the eighth transistor T8 is completely turned off in advance, and the current of the eighth transistor T8 at this stage almost disappears.

[0145] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A driving circuit, wherein: include: A plurality of shift registers arranged in cascade connection, the shift registers comprising: A pull-down module is electrically connected to the trigger signal input terminal, the first clock signal line, the second clock signal line, the first level signal line, the first node and the second node respectively, and the pull-down module is configured to pull down the voltage of the first node under the control of the voltage of the second node; an input module, electrically connected to the first clock signal line, the trigger signal input terminal and the third node respectively, and configured to transmit the signal input by the trigger signal input terminal to the third node under the control of the signal input by the first clock signal line; A pull-up module, electrically connected to the first node, the first level signal line and the control end respectively, and the pull-up module is configured to pull up the voltage of the first node under the control of the control end; an output module, electrically connected to the first node, the first level signal line and the output end of the shift register respectively, and the output module transmits the signal input by the first level signal line to the output end under the control of the voltage of the first node; a reset module, electrically connected to the third node, the second level signal line and the fourth node respectively, and configured to transmit the signal input by the second level signal line to the output end under the control of the voltage of the fourth node, so as to reset the output end; The regulating module is electrically connected to the first node, the fourth node, the fifth node, the first level signal line and the control clock signal line respectively, and the regulating module is configured to assist the reset module in resetting the output end under the control of the voltage of the fifth node.

2. The driving circuit according to claim 1, wherein: The first level signal line and the second level signal line both transmit signals with constant voltages, and the voltage of the signal transmitted by the first level signal line is greater than the voltage of the signal transmitted by the second level signal line.

3. The driving circuit according to claim 2, wherein: The control end includes the trigger signal input end; Alternatively, the control end includes the third node, and the pull-up module is electrically connected to the input module via the third node.

4. The driving circuit according to claim 1, wherein: The pull-down module includes a first transistor, a second transistor, a third transistor and a first capacitor; The gate of the first transistor is electrically connected to the second node, the source of the first transistor is electrically connected to the first clock signal line, and the drain of the first transistor is electrically connected to the first node; the source of the second transistor and the source of the third transistor are electrically connected to the first level signal line respectively, the drain of the second transistor and the drain of the third transistor are electrically connected to the second node respectively, the gate of the second transistor is electrically connected to the trigger signal input terminal, and the gate of the third transistor is electrically connected to the second clock signal line; the first electrode of the first capacitor is electrically connected to the source of the first transistor, and the second electrode of the first capacitor is electrically connected to the second node.

5. The driving circuit according to claim 4, wherein: The input module includes a fourth transistor, a gate of the fourth transistor is electrically connected to the first clock signal line, a source of the fourth transistor is electrically connected to the trigger signal input terminal, and a drain of the fourth transistor is electrically connected to the third node.

6. The driving circuit according to claim 5, wherein: The pull-up module includes a fifth transistor, a source of the fifth transistor is electrically connected to the first node, and a drain of the fifth transistor is electrically connected to the first level signal line; Wherein, the gate of the fifth transistor is electrically connected to the third node; or, the gate of the fifth transistor is electrically connected to the trigger signal input terminal.

7. The driving circuit according to claim 6, wherein: The reset module includes a sixth transistor, a seventh transistor and a second capacitor, the gate of the sixth transistor is electrically connected to the second level signal line, the source of the sixth transistor is electrically connected to the third node, and the drain of the sixth transistor is electrically connected to the fourth node; the gate of the seventh transistor is electrically connected to the fourth node, the source of the seventh transistor is electrically connected to the output end, and the drain of the seventh transistor is electrically connected to the second level signal line; the first electrode of the second capacitor is electrically connected to the fourth node, and the second electrode of the second capacitor is electrically connected to the output end.

8. The driving circuit according to claim 7, wherein: The output module includes an eighth transistor and a third capacitor, the gate of the eighth transistor is electrically connected to the first node, the source of the eighth transistor is electrically connected to the first level signal line, and the drain of the eighth transistor is electrically connected to the output end; the first electrode of the third capacitor is electrically connected to the first node, and the second electrode of the third capacitor is electrically connected to the first level signal line.

9. The driving circuit according to claim 8, wherein: The regulating module includes a ninth transistor, a tenth transistor and a fourth capacitor, the gate of the ninth transistor is electrically connected to the first node, the source of the ninth transistor is electrically connected to the first level signal line, and the drain of the ninth transistor is electrically connected to the fifth node; the gate of the tenth transistor is electrically connected to the fourth node, the source of the tenth transistor is electrically connected to the fifth node, and the drain of the tenth transistor is electrically connected to the control clock signal line.

10. The driving circuit according to claim 9, wherein: The control clock signal line includes a third clock signal line and a fourth clock signal line, the third clock signal line is electrically connected to the drain of the tenth transistor in the odd-numbered stages of the shift register, and the fourth clock signal line is electrically connected to the drain of the tenth transistor in the even-numbered stages of the shift register; The first signal edge of the third clock signal transmitted by the third clock signal line is delayed by a first preset time period relative to the first signal edge of the first clock signal transmitted by the first clock signal line, and the first signal edge of the fourth clock signal transmitted by the fourth clock signal line is delayed by the first preset time period relative to the first signal edge of the second clock signal transmitted by the second clock signal line, and the first signal edge includes a rising edge or a falling edge.

11. The driving circuit according to claim 9, wherein: The control clock signal line includes a third clock signal line, and the third clock signal line is electrically connected to the drain of the tenth transistor in each stage of the shift register; The period and pulse width of the first clock signal transmitted by the first clock signal line are 2N times of the third clock signal transmitted by the third clock signal line, where N is a positive integer; A first signal edge of a third clock signal transmitted by the third clock signal line is delayed by a first preset time period relative to a first signal edge of a first clock signal transmitted by the first clock signal line, and the first signal edge includes a rising edge or a falling edge.

12. The driving circuit according to claim 9, wherein: The control clock signal line includes the first clock signal line.

13. The driving circuit according to claim 10 or 11, wherein: The first preset time period includes 0 to 2 μs.

14. The driving circuit according to claim 9, wherein: All of the transistors are P-type transistors.

15. A display device, wherein: It comprises a driving circuit as described in any one of claims 1 to 14, and also comprises a plurality of sub-pixels arranged in an array, wherein the sub-pixels comprise pixel driving circuits, and one of the shift registers is electrically connected to each of the pixel driving circuits in the same row of the sub-pixels.

16. A driving method, wherein: Applicable to a driving circuit as claimed in any one of claims 1 to 14; the method comprising: In the input stage, a high-level trigger signal is input to the trigger signal input terminal electrically connected to the shift register, a high-level first clock signal is input to the first clock signal line, a low-level second clock signal is input to the second clock signal line, a first-level signal is input to the first-level signal line, a second-level signal is input to the second-level signal line, and a high-level control clock signal is input to the control clock signal line; In the output stage, a high-level trigger signal is input to the trigger signal input terminal, a low-level first clock signal is input to the first clock signal line, a high-level second clock signal is input to the second clock signal line, a first-level signal is input to the first-level signal line, a second-level signal is input to the second-level signal line, and a low-level control clock signal is input to the control clock signal line; In the reset stage, a low-level trigger signal is input to the trigger signal input terminal, a low-level first clock signal is input to the first clock signal line, a high-level second clock signal is input to the second clock signal line, a first-level signal is input to the first-level signal line, a second-level signal is input to the second-level signal line, and a low-level control clock signal is input to the control clock signal line.

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