Chip system and communication device

Abstract

The present application relates to the technical field of communications. Provided are a chip system and communication device, which are used for improving the data communication efficiency between non-storage dies while ensuring the function of each non-storage die. The chip system comprises: a storage die; and at least two non-storage dies comprising a first non-storage die and a second non-storage die, wherein the first non-storage die comprises a first controller, the second non-storage die comprises a second controller, and the first controller and the second controller are used for controlling access to the storage die.

Description

A chip system and communication equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on July 21, 2023, with application number 202310910216.0 and application name “A Chip System and Communication Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a chip system and communication equipment. Background Art

[0003] As the scale of system on chip (SoC) increases, the area of ​​SoC also continues to grow, but the manufacturing yield of the chip will deteriorate with the increase of area. If the area of ​​a complete SoC is too large, it is necessary to spread the SoC over multiple dies for implementation. The multiple dies usually include two types of dies, namely storage dies and non-storage dies. For example, the storage die may include dynamic random access memory (DRAM), and the non-storage die may include a central processing unit (CPU) and a modem.

[0004] Currently, most of the non-storage dies in the multiple dies require the use of the storage dies to complete their respective functions. Therefore, how to arrange the multiple dies to ensure the functions of each non-storage dies while improving the data communication efficiency between the non-storage dies is an urgent problem to be solved.

[0005] Summary of the Invention

[0006] The present application provides a chip system and a communication device for improving the data communication efficiency between non-storage dies while ensuring the function of each non-storage dies when multiple dies are provided.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a chip system is provided, which includes: a storage die, which can be a die with a storage function, for example, the storage die can include DRAM; at least two non-storage dies, including a first non-storage die and a second non-storage die, the non-storage die can be a die with a data processing function or a computing function, and the non-storage die can access the storage die; the first non-storage die includes a first controller, and the second non-storage die includes a second controller, and the first controller and the second controller are used to control access to the storage die.

[0009] In the above technical solution, the first non-storage die and the second non-storage die can both access the storage die through their respective controllers, so that the first non-storage die and the second non-storage die can use the storage die to complete their respective functions; the first non-storage die and the second non-storage die can both access the storage die, that is, different non-storage die can access the same storage die, so that the first non-storage die and the second non-storage die can use the storage die to achieve data communication, thereby improving the data communication efficiency between different non-storage die, saving storage die and reducing costs.

[0010] In a possible implementation of the first aspect, at least two interfaces of the storage die are coupled to the first interface of the first non-storage die and the first interface of the second non-storage die, respectively, and are used by the first controller and the second controller to control access to the storage die, so that the first non-storage die can access the storage die through the first interface of the first non-storage die, and the second non-storage die can access the storage die through the first interface of the second non-storage die; the second interface of the first non-storage die is coupled to the second interface of the second non-storage die, and is used by the first controller and the second controller to communicate, so that the first non-storage die and the second non-storage die can directly communicate through the second interface. For example, the first non-storage die and the second non-storage die can negotiate control of the storage die through the second interface. In the above possible implementation, the first controller of the first non-storage die and the second controller of the second non-storage die can negotiate control of the storage die through the corresponding second interface, thereby eliminating the need for major improvements to the storage die and thus not reducing the storage density and flexibility of the storage die.

[0011] In one possible implementation of the first aspect, the at least two non-storage dies access the storage die through time-sharing multiplexing, meaning that the at least two non-storage dies can access the storage die at different times. Exemplarily, when the at least two non-storage dies include a first non-storage die and a second non-storage die, the first non-storage die and the second non-storage die can access the storage die through time-sharing multiplexing. In this possible implementation, each of the at least two non-storage dies can access the storage die at a different time, eliminating the need for significant improvements to the storage die and, consequently, maintaining the storage density and flexibility of the storage die.

[0012] In a possible implementation of the first aspect, the first controller is configured to: send first instruction information via a second interface of a first non-storage die, the first instruction information being used to instruct the first non-storage die to access the storage die; and / or the second controller is configured to: send second instruction information via a second interface of a second non-storage die, the second instruction information being used to instruct the second non-storage die to access the storage die. In these possible implementations, the first controller of the first non-storage die and the second controller of the second non-storage die can negotiate control of the storage die via the second interface, thereby eliminating the need for major improvements to the storage die and, in turn, preventing a reduction in the storage density and flexibility of the storage die.

[0013] In one possible implementation of the first aspect, the at least two non-storage die further include a third non-storage die, and the third non-storage die includes a third controller configured to control access to the storage die. In this possible implementation, the third non-storage die can access the storage die via the third controller, thereby enabling the third non-storage die to perform its own functions. Furthermore, different non-storage die can access the same storage die, allowing the third non-storage die and other non-storage die to communicate data using the storage die. This improves data communication efficiency between different non-storage die, saves storage die, and reduces costs.

[0014] In a possible implementation of the first aspect, at least two interfaces of the storage die are further coupled to the first interface of the third non-storage die, so that the third controller controls access to the storage die, so that the third non-storage die can use the storage die to complete the function of the third non-storage die, and any two non-storage die of the at least two non-storage die can use the storage die to implement data communication, thereby improving the efficiency of data communication between the non-storage die; the second interface of the third non-storage die is coupled to the second interface of the first non-storage die and the second interface of the second non-storage die, so that the third controller communicates with the first controller and the second controller, so that the third non-storage die can negotiate with other non-storage die through the second interface for control of the storage die, thereby implementing access to the storage die in a time-sharing multiplexing manner.

[0015] In one possible implementation of the first aspect, the third controller is configured to send third instruction information via the second interface of the third non-storage die, where the third instruction information is used to instruct the third non-storage die to access the storage die. In this possible implementation, the third non-storage die can negotiate control of the storage die via the second interface, thereby eliminating the need for significant improvements to the storage die and thereby maintaining the storage density and flexibility of the storage die.

[0016] In a possible implementation of the first aspect, the memory die and some of the at least two non-memory die are packaged together; or the memory die and the at least two non-memory die are packaged together. In these possible implementations, by packaging the memory die with the at least two non-memory die, or with some of the at least two non-memory die, the chip system's integration can be improved and its area can be reduced.

[0017] In one possible implementation of the first aspect, each of the at least two non-storage dies includes a controller configured to control access to the storage die. In this possible implementation, each of the at least two non-storage dies can access the storage die via its respective controller, without integrating the controller into the storage die, thereby maintaining the flexibility of the storage die.

[0018] In one possible implementation of the first aspect, the at least two non-storage dies include at least one of the following: a central processing unit (CPU), a modem, an image signal processor (ISP), a digital signal processor (DSP), a graphics processing unit (GPU), a neural network processor (NPU), a tensor processing unit (TPU), or a network interface card (NIC). This possible implementation can increase the diversity and selection flexibility of the non-storage dies.

[0019] In a second aspect, a communication device is provided, comprising: a printed circuit board; and a chip system provided on the printed circuit board, as provided in the first aspect or any possible implementation of the first aspect. Optionally, the communication device comprises a mobile terminal, such as a mobile phone, a tablet computer, a laptop computer, a video camera, a camera, a wearable device, or an in-vehicle device.

[0020] It can be understood that the beneficial effects that can be achieved by any of the communication devices provided above can correspond to the beneficial effects in the chip system provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG1 is a schematic diagram of the structure of a dual-port DRAM;

[0022] FIG2 is a schematic diagram of the structure of another dual-port DRAM;

[0023] FIG3 is a schematic structural diagram of a terminal device provided in an embodiment of the present application;

[0024] FIG4 is a schematic structural diagram of a chip system provided in an embodiment of the present application;

[0025] FIG5 is a schematic structural diagram of another chip system provided in an embodiment of the present application;

[0026] FIG6 is a schematic structural diagram of another chip system provided in an embodiment of the present application;

[0027] FIG7 is a schematic structural diagram of another chip system provided in an embodiment of the present application;

[0028] FIG8 is a schematic structural diagram of another chip system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The following sections discuss the making and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided herein can be implemented in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to implement and use this description and technology and do not limit the scope of this application.

[0030] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0031] Various circuits or other components may be described or referred to as being "configured to" perform one or more tasks. In this case, "configured to" is used to imply structure by indicating that the circuit / component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when a specified circuit / component is not currently operational (e.g., not turned on), the circuit / component may be referred to as being configured to perform the task. Circuits / components used with the phrase "configured to" include hardware, such as circuitry that performs an operation, etc.

[0032] The following describes the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings. In the description of the present application, unless otherwise specified, " / " indicates that the objects associated with each other are in an "or" relationship. For example, A / B can represent A or B. "And / or" in the present application is only a description of the association relationship between the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural.

[0033] In the description of this application, unless otherwise specified, "plurality" means two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or plural.

[0034] To facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or execution order, and the words "first" and "second" do not necessarily mean different.

[0035] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner to facilitate understanding.

[0036] Before introducing the embodiments of the present application, the relevant background involved in the present application is first introduced and explained.

[0037] As the scale of system on chip (SoC) increases, the area of ​​SoC also continues to grow, but the manufacturing yield of the chip will deteriorate as the area grows. If the area of ​​a complete SoC is too large, the SoC needs to be distributed to multiple dies for implementation. The multiple dies usually include two types of dies, namely storage dies and non-storage dies. Most of the non-storage dies in the multiple dies need to use storage dies to complete their respective functions. Therefore, how to arrange the multiple dies so as to improve the data communication efficiency between non-storage dies while ensuring the functions of each non-storage dies is a problem that needs to be solved urgently.

[0038] In the related art, the storage die is usually improved, that is, the storage die is implemented using a dual-port DRAM, which has two access ports, allowing two non-storage dies to access it simultaneously, thereby ensuring the function of the non-storage die while improving the data communication efficiency between the non-storage dies.

[0039] Figure 1 is a schematic diagram of the structure of a dual-port DRAM, which allows simultaneous access from both ports. This allows two non-memory die to access the DRAM simultaneously through the dual ports. In this dual-port DRAM, a memory cell (i.e., a capacitor C) is coupled to two transistors (represented as T1 and T2), each coupled to a bit line (BL) and a word line (WL). For example, transistor T1 is coupled to bit line BL1 and word line WL1, and transistor T2 is coupled to bit line BL2 and word line WL2. In Figure 1, / BL1 represents the inversion of bit line BL1, and / BL2 represents the inversion of bit line BL2.

[0040] Figure 2 is a schematic diagram of the structure of another dual-port DRAM, which also allows two ports to be accessed simultaneously, so that two non-storage bare chips can access the DRAM simultaneously through the dual ports. The dual-port DRAM is integrated with a DRAM controller and has an additional dual-port controller. The dual-port controller is used to sort the access requests received by the two ports and send the access requests to the DRAM controller for processing in the sorted order to prevent timing conflicts that occur when the two ports are accessed simultaneously. In addition, the dual-port DRAM can also include I / O buffers, sense amplifiers and I / O circuits, storage arrays, and serial shift registers, etc., which are related devices for data input, output, and caching. CLK in Figure 2 represents the clock signal of the serial shift register, and SD represents the output data of the serial shift register.

[0041] While the aforementioned two dual-port DRAMs can improve data communication efficiency between non-storage die when used as memory dies in a SoC, they still present certain limitations, limiting their use. For example, the dual-port DRAM shown in Figure 1 introduces additional bit lines BL and word lines WL, which reduces its storage density. The dual-port DRAM shown in Figure 2 also incorporates an additional dual-port controller, which must be integrated with the DRAM controller, resulting in reduced flexibility.

[0042] Based on this, an embodiment of the present application provides a chip system that can ensure the functions of non-storage dies without reducing the storage density and flexibility of storage dies, while improving the data communication efficiency between non-storage dies.

[0043] The technical solution of the present application can be applied to various communication devices, for example, the communication device can be a terminal device. The terminal device can include, but is not limited to, mobile phones, tablet computers, computers, laptop computers, video cameras, cameras, wearable devices, vehicle-mounted devices (e.g., cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed trains, etc.), virtual reality (VR) devices, augmented reality (AR) devices, or intelligent robots.

[0044] Figure 3 is a schematic diagram of the structure of a terminal device provided in an embodiment of the present application. Taking a mobile phone as an example, the mobile phone includes components such as a radio frequency (RF) circuit 110, a memory 120, an input unit 130, a display unit 140, a sensor assembly 150, an audio circuit 160, a processor 170, and a power supply 180. The following describes the various components of the mobile phone in detail with reference to Figure 3:

[0045] The RF circuit 110 can be used to send and receive information or receive and transmit signals during a call. Typically, the RF circuit 110 includes, but is not limited to, an antenna, an amplifier, a transceiver, a coupler, a low-noise amplifier (LNA), a duplexer, and the like. Optionally, the antenna may include multiple receiving antennas and multiple transmitting antennas. Furthermore, the RF circuit 110 can communicate with networks and other devices via wireless communications, such as communicating with access devices via a WiFi network.

[0046] The memory 120 can be used to store software programs and modules. The processor 170 executes the various functional applications and data processing of the mobile phone by running the software programs and modules stored in the memory 120. The memory 120 may mainly include a program storage area and a data storage area. The program storage area may store the operating system, at least one application required for a function, etc.; the data storage area may store data generated based on the use of the mobile phone (e.g., audio data, image data, phone book, etc.). In addition, the memory 120 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0047] The input unit 130 can be used to receive input digital or character information, and to generate key signal input related to the user settings and function control of the mobile phone. Specifically, the input unit 130 may include a touch screen 131 and other input devices 132. The touch screen 131, also known as a touch panel, can collect user touch operations on or near it (such as operations performed by the user using a finger, stylus, or any other suitable object or accessory on or near the touch screen 131) and drive the corresponding connection device according to a pre-set program. Other input devices 132 may include, but are not limited to, one or more of a physical keyboard, function keys (such as volume control keys, power switch keys, etc.), a trackball, a mouse, a joystick, and the like.

[0048] The display unit 140 can be used to display information input by the user or information provided to the user, as well as various menus of the mobile phone. The display unit 140 may include a display panel 141. Optionally, the display panel 141 may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), or the like. Furthermore, the touch screen 131 may cover the display panel 141. When the touch screen 131 detects a touch operation on or near it, it transmits the information to the processor 170 to determine the type of touch event. The processor 170 then provides a corresponding visual output on the display panel 141 based on the type of touch event. Although in Figure 3, the touch screen 131 and the display panel 141 are two independent components to implement the input and output functions of the mobile phone, in some embodiments, the touch screen 131 and the display panel 141 can be integrated to implement the input and output functions of the mobile phone.

[0049] Sensor assembly 150 includes one or more sensors for assessing various aspects of the phone's status. These sensors may include temperature sensors, accelerometers, gyroscopes, magnetic sensors, or pressure sensors. Sensor assembly 150 can detect changes in the phone's temperature, acceleration / deceleration, orientation, open / closed status, or the relative positioning of components. Furthermore, sensor assembly 150 may include optical sensors, such as CMOS or CCD image sensors, for use in imaging applications.

[0050] The audio circuit 160, speaker 161, and microphone 162 provide an audio interface between the user and the mobile phone. The audio circuit 160 converts received audio data into electrical signals and transmits them to the speaker 161, which then converts the signals into sound signals for output. Meanwhile, the microphone 162 converts collected sound signals into electrical signals, which are then received by the audio circuit 160 and converted into audio data. The audio data is then output to the RF circuit 110 for transmission to, for example, another mobile phone, or to the memory 120 for further processing.

[0051] Processor 170 is the control center of the mobile phone, connecting all parts of the mobile phone using various interfaces and circuits. By running or executing software programs and / or modules stored in memory 120 and accessing data stored in memory 120, it performs various functions of the mobile phone and processes data, thereby providing overall monitoring of the mobile phone. Optionally, processor 170 may include one or more processing units. For example, processor 170 may integrate an application processor and a modem processor, wherein the application processor primarily processes the operating system, user interface, and application programs, while the modem processor primarily handles wireless communications. It is understood that the modem processor may not be integrated into processor 170.

[0052] The mobile phone also includes a power supply 180 (such as a battery) for supplying power to various components. Optionally, the power supply can be logically connected to the processor 170 through a power management system, thereby managing charging, discharging, and power consumption through the power management system.

[0053] Furthermore, the mobile phone may also include a connectivity chip 190, which may integrate a wireless fidelity (WiFi) chip. In the embodiment of the present application, the antenna for receiving or transmitting multiple data streams or a single data stream may be the antenna of the WiFi chip. In addition, the chip 190 may also integrate one or more of a Bluetooth module, a near field communication (NFC) module, a global navigation satellite system (GNSS) module, or a frequency modulation (FM) module, which will not be described in detail in this application.

[0054] Those skilled in the art will appreciate that the mobile phone structure shown in FIG3 does not limit the mobile phone and may include more or fewer components than shown, or a combination of certain components, or a different arrangement of components.

[0055] FIG4 is a schematic diagram of the structure of a chip system provided in an embodiment of the present application, which can be used in the communication device provided above. The chip system may include: a storage die 210 and at least two non-storage dies 220. The at least two non-storage dies 220 may include a first non-storage die 221 and a second non-storage die 222. The first non-storage die 221 includes a first controller, and the second non-storage die includes a second controller. The first controller and the second controller are used to control access to the storage die 210.

[0056] In one possible embodiment, at least two interfaces of the storage die 210 are coupled to the first interface of the first non-storage die 221 and the first interface of the second non-storage die 222, respectively, for the first controller and the second controller to control access to the storage die 210, respectively; the second interface of the first non-storage die 221 is coupled to the second interface of the second non-storage die 222, for the first controller and the second controller to communicate.

[0057] A die may also be referred to as a crystal, a bare crystal, a particle, or a core, and specifically refers to a crystal obtained by cutting from a wafer. The storage die 210 may be a die having a storage function. The non-storage die may be a die having a data processing function or a computing function, and the non-storage die may be able to access the storage die 210.

[0058] Optionally, the memory die 210 may include but is not limited to: DRAM, static random access memory (SRAM), synchronous dynamic random-access memory (SDRAM), double data rate SDRAM (DDR), etc.

[0059] Optionally, the at least two non-storage dies 220 may include but are not limited to: a central processing unit (CPU), a modem, an image signal processor (ISP), a digital signal processor (DSP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU), a network card, and various accelerators, etc.

[0060] In addition, the at least two interfaces of the storage die 210 may include two or more interfaces. The first interface and the second interface of the first non-storage die 221 may each include one or more interfaces. The first interface and the second interface of the second non-storage die 222 may each include one or more interfaces. The first interface of the first non-storage die 221 and the first interface of the second non-storage die 222 may be coupled to different interfaces of the at least two interfaces of the storage die 210.

[0061] Exemplarily, the memory die 210 includes four interfaces, designated I1 to I4. The first interface of the first non-memory die 221 and the first interface of the second non-memory die 222 each include two interfaces, designated J1 to J2 and K1 to K2, respectively. The second interface of the first non-memory die 221 and the second interface of the second non-memory die 222 each include one interface, designated J3 and K3, respectively. Interfaces I1 to I2 of the memory die 210 can be coupled to interfaces J1 to J2 of the first non-memory die 221, interfaces I3 to I4 of the memory die 210 can be coupled to interfaces K1 to K2 of the second non-memory die 222, and interface J3 of the first non-memory die 221 can be coupled to interface K3 of the second non-memory die 222.

[0062] In this chip system, some interfaces of the memory die are coupled to the first interface of the first non-memory die 221, so that the first non-memory die 221 can access the memory die 210 through the first interface of the first non-memory die 221. Similarly, some interfaces of the memory die are coupled to the first interface of the second non-memory die 222, so that the second non-memory die 222 can access the memory die 210 through the first interface of the second non-memory die 222. The second interface of the first non-memory die 221 is coupled to the second interface of the second non-memory die 222, so that the first non-memory die 221 and the second non-memory die 222 can communicate directly through the second interface. For example, the first non-memory die 221 and the second non-memory die 222 can negotiate control rights (or access rights) of the memory die 210 through the second interface.

[0063] In the embodiment of the present application, both the first non-storage die 221 and the second non-storage die 222 can access the storage die 210, so that the first non-storage die 221 and the second non-storage die 222 can use the storage die 210 to complete their respective functions. In addition, both the first non-storage die 221 and the second non-storage die 222 can access the storage die 210, that is, different non-storage die can access the same storage die. In this way, the first non-storage die 221 and the second non-storage die 222 can use the storage die 210 to achieve data communication, thereby improving the data communication efficiency between the first non-storage die 221 and the second non-storage die 222, and can also save the storage die 210, thereby reducing costs. For example, the first non-storage die 221 writes data to the storage die 210 and the second non-storage die 222 reads the data from the storage die 210 ; or the second non-storage die 222 writes data to the storage die 210 and the first non-storage die 221 reads the data from the storage die 210 .

[0064] Optionally, the at least two non-storage dies 220 access the storage die 210 through time-sharing multiplexing, that is, the at least two non-storage dies 220 can access the storage die 210 at different times. When the at least two non-storage dies 220 include a first non-storage die 221 and a second non-storage die 222, the first non-storage die 221 and the second non-storage die 222 can access the storage die 210 through time-sharing multiplexing. In this case, the storage die 210 can also be called a dual-port storage die. For example, the storage die 210 can be a dual-port DRAM.

[0065] In one possible embodiment, when the first non-storage die 221 needs to access the storage die 210, the first controller of the first non-storage die 221 may be configured to send first indication information via the second interface of the first non-storage die 221, where the first indication information is used to instruct the first non-storage die 221 to access the storage die 210. Thus, when the second non-storage die 222 receives the first indication information via the second interface of the second non-storage die 222, the second non-storage die 222 may not access the storage die 210, thereby transferring control of the storage die 210 to the first non-storage die 221. Optionally, the second non-storage die 222 may also send first response information via the second interface of the second non-storage die 222, where the first response information may be used to confirm that the first non-storage die 221 has accessed the storage die 210.

[0066] Similarly, when the second non-storage die 222 needs to access the storage die 210, the second controller of the second non-storage die 222 may be configured to send second indication information via the second interface of the second non-storage die 222, where the second indication information is used to instruct the second non-storage die 222 to access the storage die 210. Thus, when the first non-storage die 221 receives the second indication information via the second interface of the first non-storage die 221, the first non-storage die 221 may not access the storage die 210, thereby transferring control of the storage die 210 to the second non-storage die 222. Optionally, the first non-storage die 221 may also send second response information via the second interface of the first non-storage die 221, where the second response information may be used to confirm that the second non-storage die 222 has accessed the storage die 210.

[0067] In an embodiment of the present application, the at least two non-storage dies 220 access the storage die 210 through time-sharing multiplexing, so that each of the at least two non-storage dies 220 can access the storage die 210 at a different time, that is, only one non-storage die accesses the storage die 210 at the same time, thereby eliminating the need for major improvements to the storage die 210 and thus not reducing the storage density and flexibility of the storage die 210.

[0068] Furthermore, as shown in FIG. 5 , the at least two non-storage die 220 further include a third non-storage die 223 . The third non-storage die 223 includes a third controller. The third controller is used to control access to the storage die 210 .

[0069] In one possible embodiment, at least two interfaces of the storage die 210 are also coupled to the first interface of the third non-storage die 223, so that the third controller controls access to the storage die 210; the second interface of the third non-storage die 223 is coupled to the second interface of the first non-storage die 221 and the second interface of the second non-storage die 222, so that the third controller communicates with the first controller and the second controller.

[0070] Among them, at least two interfaces of the storage die 210 are also coupled to the first interface of the third non-storage die 223, so that the third non-storage die 223 can access the storage die 210 through the first interface of the third non-storage die 223, so that the third non-storage die 223 can use the storage die 210 to complete the function of the third non-storage die 223.

[0071] In addition, the first non-storage die 221, the second non-storage die 222, and the third non-storage die 223 can all access the storage die 210, that is, different non-storage die can access the same storage die. In this way, any two of the above three non-storage die can use the storage die 210 to achieve data communication, thereby improving the data communication efficiency between the non-storage die.

[0072] Furthermore, the second interface of the third non-storage die 223 is coupled to the second interface of the first non-storage die 221 and the second interface of the second non-storage die 222, so that the three non-storage die can communicate directly with each other through the second interface. For example, the first non-storage die 221, the second non-storage die 222, and the third non-storage die 223 can negotiate control of the storage die 210 through the second interface to achieve time-division multiplexing access to the storage die 210.

[0073] In one possible embodiment, when the third non-storage die 223 needs to access the storage die 210, the third memory of the third non-storage die 223 may be configured to send third indication information via the second interface of the third non-storage die 223. The third indication information is used to instruct the third non-storage die 223 to access the storage die 210. In this way, when both the first non-storage die 221 and the second non-storage die 222 receive the third indication information via their respective second interfaces, the first non-storage die 221 and the second non-storage die 222 may not access the storage die 210, thereby transferring control of the storage die 210 to the third non-storage die 223. Optionally, the first non-storage die 221 and the second non-storage die 222 may also send third response information via their respective second interfaces. The third response information may be used to confirm that the third non-storage die 223 has accessed the storage die 210.

[0074] It will be appreciated that the above description is based on the example of the at least two non-storage dies 220 including three non-storage dies. In actual applications, the at least two non-storage dies 220 may also include a larger number of non-storage dies. These larger number of non-storage dies may be coupled to the storage die 210 and other non-storage dies in a manner similar to the third non-storage die 223 described above, and time-sharing multiplexing of the storage die 210 may be achieved through the aforementioned negotiation of control rights over the storage die 210. This embodiment of the present application does not specifically limit the number of non-storage dies included in the at least two non-storage dies 220.

[0075] Furthermore, each of the at least two non-storage dies 220 may include a controller, which may be used to control access to the storage die 210. For example, the storage die 210 may include a storage array, and the controller may be used to write data to the storage array or read data stored in the storage array.

[0076] For ease of understanding, the following description uses as an example a case where the at least two non-storage dies 220 include a first non-storage die 221 and a second non-storage die 222, the storage die 210 is a DRAM, and the controller is a DRAM controller. For example, as shown in FIG6 , the first non-storage die 221 includes a DRAM controller 1, and the second non-storage die 222 includes a DRAM controller 2. The DRAM controller 1 can access the storage die 210 via a first interface of the first non-storage die 221, and the DRAM controller 2 can access the storage die 210 via a first interface of the second non-storage die 222. The DRAM controller 1 and the DRAM controller 2 can also communicate via the second interfaces of their respective non-storage dies.

[0077] It will be appreciated that FIG6 illustrates an example in which each of the at least two non-storage dies 220 includes a controller. In practical applications, each of the at least two non-storage dies 220 may not have an integrated controller. For example, a controller may be integrated into the memory die 210, or an independent controller may be provided between the memory die 210 and the at least two non-storage dies 220. The example in FIG6 does not limit the embodiments of the present application.

[0078] Furthermore, in the chip system, the memory die 210 and the at least two non-memory die 220 may be packaged together, or the memory die 210 and some of the at least two non-memory die 220 may be packaged together. For ease of understanding, the following description uses an example in which the at least two non-memory die 220 include a first non-memory die 221 and a second non-memory die 222.

[0079] In one possible embodiment, as shown in FIG7 , the chip system includes the memory die 210, a first non-memory die 221, and a second non-memory die 222. The memory die 210, the first non-memory die 221, and the second non-memory die 222 are packaged together. FIG7 does not show the first controller of the first non-memory die 221 and the second controller of the second non-memory die 222.

[0080] In another possible embodiment, as shown in FIG8 , the chip system includes the memory die 210, a first non-memory die 221, and a second non-memory die 222. The memory die 210 and the first non-memory die 221 are packaged together. FIG8 does not show the first controller of the first non-memory die 221 and the second controller of the second non-memory die 222.

[0081] In an embodiment of the present application, by packaging the storage die 210 and the at least two non-storage die 220 together, or packaging the storage die 210 and some of the at least two non-storage die 220 together, the integration of the chip system can be improved and the area of ​​the chip system can be reduced.

[0082] Based on this, an embodiment of the present application also provides a communication device, which may include a printed circuit board (PCB) and a chip system arranged on the printed circuit board PCB. The chip system may be any chip system provided above.

[0083] Optionally, the communication device may be a mobile terminal. For example, the mobile terminal may include but is not limited to: a mobile phone, a tablet computer, a laptop computer, a video camera, a camera, a wearable device, a vehicle-mounted device, etc., and the present embodiment does not impose any specific restrictions on this.

[0084] It should be noted that the above detailed descriptions of the chip system can be referred to in the corresponding embodiments of the communication device, and the embodiments of the present application will not be repeated here.

[0085] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A chip system, characterized in that: include: Storage die; at least two non-storage die, including a first non-storage die and a second non-storage die; The first non-storage die includes a first controller, the second non-storage die includes a second controller, and the first controller and the second controller are used to control access to the storage die.

2. The chip system according to claim 1, characterized in that: At least two interfaces of the storage die are respectively coupled to the first interface of the first non-storage die and the first interface of the second non-storage die, and are used for the first controller and the second controller to control access to the storage die; The second interface of the first non-storage die is coupled to the second interface of the second non-storage die for communication between the first controller and the second controller.

3. The chip system according to claim 1 or 2, characterized in that: The at least two non-storage dies access the storage die through time-division multiplexing.

4. The chip system according to claim 2 or 3, characterized in that: The first controller is used to send first indication information through the second interface of the first non-storage die, where the first indication information is used to instruct the first non-storage die to access the storage die; and / or, The second controller is used to send second indication information through the second interface of the second non-storage die, where the second indication information is used to instruct the second non-storage die to access the storage die.

5. The chip system according to any one of claims 1 to 4, characterized in that: The at least two non-storage die further include a third non-storage die including a third controller for controlling access to the storage die.

6. The chip system according to claim 5, characterized in that: The at least two interfaces of the storage die are also coupled to the first interface of the third non-storage die for the third controller to control access to the storage die; The second interface of the third non-storage die is coupled to both the second interface of the first non-storage die and the second interface of the second non-storage die for the third controller to communicate with the first controller and the second controller.

7. The chip system according to claim 6, characterized in that: The third controller is used to send third indication information through the second interface of the third non-storage die, where the third indication information is used to instruct the third non-storage die to access the storage die.

8. The chip system according to any one of claims 1 to 7, characterized in that: The memory die and some of the at least two non-memory die are packaged together.

9. The chip system according to any one of claims 1 to 7, characterized in that: The memory die and the at least two non-memory die are packaged together.

10. The chip system according to any one of claims 1 to 9, characterized in that: The memory die includes a dynamic random access memory DRAM.

11. The chip system according to any one of claims 1 to 10, characterized in that: The at least two non-storage bare chips include at least one of the following: a central processing unit CPU, a modem modem, an image signal processor ISP, a digital signal processor DSP, a graphics processor GPU, a neural network processor NPU, a tensor processing unit TPU, and a network card.

12. A communication device, characterized in that: The communication device comprises: a printed circuit board, and a chip system according to any one of claims 1 to 11 arranged on the printed circuit board.

13. The communication device according to claim 12, characterized in that The communication device includes a mobile terminal.

Images