Matrix operation system, matrix operation method, satellite navigation method and storage medium

Abstract

The present application relates to the technical field of positioning navigation, and provides a matrix operation system, a matrix operation method, a satellite navigation method and a storage medium. The system comprises: a matrix operation accelerator, a bus, a processor, and an internal memory arranged in the matrix operation accelerator; the bus is connected to the matrix operation accelerator and the processor; a floating-point operation unit array is arranged in the matrix operation accelerator; the processor is used for issuing a target task needing to be executed, to allow the matrix operation accelerator to process; and the matrix operation accelerator is used for carrying out pipeline calculation on a target matrix of the target task on the basis of the floating-point operation unit array to obtain calculation data. Pipeline calculation is carried out on a matrix operation task by means of the floating-point operation unit array arranged in a matrix operation accelerator, and data of stages are respectively stored in corresponding internal memories, so that the cost of matrix operation can be reduced, the efficiency of matrix operation is improved, and the working efficiency of positioning navigation systems can be improved.

Description

Matrix operation system, matrix operation method, satellite navigation method and storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application number 2023109255522, filed with the China Patent Office on July 25, 2023, entitled “Matrix operation system, matrix operation method, satellite navigation method and storage medium”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of positioning and navigation technology, and in particular to a matrix operation system, a matrix operation method, a satellite navigation method and a storage medium. Background Art

[0004] Due to the diversity of application scenarios, different positioning and navigation systems are used in different scenarios. For example, various types of positioning and navigation systems can be used to provide users with positioning and navigation services, including satellite positioning and navigation systems, inertial positioning and navigation systems, visual positioning and navigation systems, radio positioning and navigation systems, integrated positioning and navigation systems, and specialized positioning and navigation systems. Each type of positioning and navigation system requires matrix operations to provide the corresponding positioning and navigation services. For example, a satellite positioning and navigation system is a system consisting of radio frequency (RF), baseband, various sensors, and positioning algorithms. Each device can input collected data into the positioning algorithm, which integrates satellite positioning information from the baseband with input from the aforementioned sensors to obtain highly reliable positioning and navigation information and transmit it to downstream devices. Positioning calculations are typically designed using an embedded processor architecture using a system-on-chip (SOC) approach. This system integrates a complete microelectronic circuit system on a single chip, including a general-purpose processor core, auxiliary cores, a data bus, storage devices, execution devices, general interfaces, power management, sensors, and other components. In addition, around the embedded processor chip, we develop the underlying driver software, upper-level business application software, and supporting hardware PCB circuit boards to achieve the positioning function.

[0005] Existing processor chips typically use a general-purpose processor to access a dedicated storage system through its bus. The storage system stores the operand matrices to be processed and the result matrices after matrix operations, and the general-purpose processor completes each step of the matrix operation. However, this approach is only suitable for business scenarios with simple calculations. For large-dimensional matrices, it requires more CPU computing power and bus bandwidth, resulting in low matrix operation performance, large power consumption, and large chip area. As a result, current positioning and navigation systems perform positioning calculations inefficiently and at high costs, making them unable to meet diverse positioning and navigation needs.

[0006] Summary of the Invention

[0007] In view of this, the purpose of the embodiments of the present application is to provide a matrix operation system, a matrix operation method, a satellite navigation method and a storage medium to improve the problems of low positioning calculation efficiency and high cost in the prior art.

[0008] In order to solve the above problems, in a first aspect, an embodiment of the present application provides a matrix operation system, the system comprising: a matrix operation accelerator, a bus, a processor, and an internal memory arranged inside the matrix operation accelerator;

[0009] The bus connects the matrix operation accelerator and the processor;

[0010] The matrix operation accelerator is provided with a floating point operation unit array;

[0011] The processor is used to send target tasks to be executed for processing by the matrix operation accelerator;

[0012] The matrix operation accelerator is used to perform pipeline calculation on the target matrix of the target task based on the floating-point operation unit array to obtain calculation data;

[0013] The internal memory is used to store the target matrix and the calculation data respectively.

[0014] In the above implementation process, a floating-point operation unit array supporting multiple operations is set in the matrix operation accelerator, so as to perform pipeline calculations on the target matrix of the received target matrix operation task based on the floating-point operation unit array, and the matrix data of each stage and the calculated data are respectively stored in the corresponding internal memory. There is no need to set up a complex or large processing chip for matrix operation, and the cost of matrix operation can be reduced and the efficiency of matrix operation can be improved through floating-point calculation. It is suitable for processing matrix operation tasks of multiple dimensions, and the storage entity is scheduled in a shared resource pool mode, which effectively saves the number of memory blocks and capacity requirements, improves the performance of the matrix operation accelerator, improves the efficiency of positioning calculation, reduces the calculation cost of positioning calculation, and thus improves the working efficiency of the positioning and navigation system.

[0015] Optionally, the setting parameters of the floating-point operation unit array are determined according to the computational requirements of the matrix operation; wherein the setting parameters include: operator type and at least one of the number of parallelism, number of pipeline stages and dimensional information.

[0016] In the above implementation process, in order to achieve a variety of different computing functions and be applicable to matrix calculations of various dimensions, one or more parameters of the floating-point arithmetic unit array, such as the operator type, number of parallelism, number of pipeline stages, and dimensional information, can be determined based on the matrix calculation requirements in the actual application scenario, thereby configuring the corresponding floating-point arithmetic unit array. The ability to configure a high-performance floating-point arithmetic unit array for calculations at a low cost effectively improves the efficiency of matrix operations and is suitable for processing a variety of different types of matrix calculation tasks.

[0017] Optionally, the calculation data includes: intermediate data and result data;

[0018] The matrix operation accelerator specifically obtains the target matrix of the target task currently being executed; splits the target matrix based on the floating-point operation unit array to obtain one or more split matrices and / or one or more operation row-column vectors; performs pipeline calculations on one or more split matrices and / or one or more operation row-column vectors based on the floating-point operation unit array to obtain the intermediate data; based on the floating-point operation unit array and the corresponding operator type, calls all the intermediate data to perform combined operations to obtain the result data.

[0019] In the above implementation process, when performing matrix operations, the target matrix of large dimensions can be split to obtain one or more small split matrices and / or one or more operation row and column vectors, so that the one or more split matrices and / or one or more operation row and column vectors are pipelined based on the floating-point operation unit array to obtain a plurality of intermediate data to be used, and then the intermediate data are combined and operated according to the floating-point operation unit array and the corresponding operator type to obtain the result data after the target matrix is ​​calculated. The target matrix of large dimensions can be split into one or more small-dimensional matrices and / or one or more operation row and column vectors for calculation, and pipeline calculation is used to improve the efficiency of calculation, which is suitable for matrix operations of multiple dimensions.

[0020] Optionally, the internal memory includes: a first type of memory, a second type of memory and a third type of memory;

[0021] The first type of memory is used to store the target matrix;

[0022] The second type of memory is used to store the intermediate data;

[0023] The third type of memory is used to store the result data.

[0024] In the above implementation process, since the original target matrix needs to be called for calculation during the matrix operation accelerator's matrix operation, and the corresponding intermediate data and result data can be calculated, in order to improve the reading efficiency of each type of data during the operation, the data of each stage can be stored separately, and multiple types of data can be stored in the corresponding type of internal memory respectively. Therefore, when the data needs to be read, there is no need to pre-process it before reading, and the required data can be directly read from the corresponding internal memory, which effectively improves the efficiency of internal storage arbitration and access of the matrix operation accelerator, thereby improving the efficiency of matrix operations.

[0025] Optionally, the system further includes: an external memory, and the internal memory further includes: a fourth type of memory; the external memory is connected to the matrix operation accelerator and the processor via a bus;

[0026] The external memory is used to store the operand matrix of the unstarted task;

[0027] In a case where the matrix operation accelerator calculates the target matrix, the fourth type of memory is used to store the operand matrices of the next one or more subsequent tasks to be executed, which are pre-read by the matrix operation accelerator from the external memory;

[0028] The matrix operation accelerator is used to move the result data stored in the third type of memory to the external memory.

[0029] In the above implementation process, since there are multiple matrix operation tasks, an external memory connected to the matrix operation accelerator and the processor can be provided to store the operand matrices of the multiple tasks. Furthermore, since each matrix operation task requires reading corresponding data for calculation, in order to reduce the waiting time and data reading time of subsequent tasks, the internal memory can also include a fourth type of memory. When the matrix operation accelerator calculates the current target task, the matrix operation accelerator can pre-read the operand matrices of the next one or more subsequent tasks from the external memory and store the operand matrices in the fourth type of memory. The matrix operation accelerator can also move the result data stored in the third type of memory to the external memory for processing, thereby ensuring efficient pipeline processing between matrix operation tasks and improving the execution efficiency of matrix operation tasks.

[0030] Optionally, the matrix operation accelerator is further provided with a state machine and a management module; the state machine is connected to the management module, and the management module is connected to each of the internal memories;

[0031] The state machine is used to apply for storage requirements from the management module according to the target task;

[0032] The management module is used to determine the type of each internal memory according to the storage requirement, and the current storage status and remaining storage space of each internal memory.

[0033] In the above implementation process, in order to realize the classified storage of various data, a state machine and a management module can also be set in the matrix operation accelerator. The state machine can make storage requests based on the actual situation of the target task, and the management module can determine the storage type of each internal memory based on the storage requirements, the current storage status of the internal memory, and the remaining storage space. That is, the type of the internal memory is variable to meet the actual computing requirements of different matrix operation tasks and is suitable for a variety of computing scenarios.

[0034] Optionally, the number of the internal memories is greater than or equal to 4, and the capacity of each internal memory is greater than or equal to the matrix capacity of the maximum matrix of the matrix operation.

[0035] In the above implementation process, in order to store the data completely and effectively, the number of internal memories can be greater than or equal to 4 to ensure that there is at least one internal memory of each type, and the capacity of the internal memory is set so that the internal memory can store the matrix data completely.

[0036] In a second aspect, an embodiment of the present application further provides a matrix operation method, which is applied to a matrix operation system, the system comprising: a matrix operation accelerator, a bus, a processor, and an internal memory disposed within the matrix operation accelerator; the bus connecting the matrix operation accelerator and the processor; the matrix operation accelerator being provided with a floating-point operation unit array;

[0037] Sending target tasks to be executed by the processor to the matrix operation accelerator for processing;

[0038] Performing pipeline calculations on the target matrix of the target task based on the floating-point operation unit array by a matrix operation accelerator to obtain calculation data;

[0039] The target matrix and the calculated data are stored separately in an internal memory.

[0040] In the above implementation process, the processor sends the target task to the matrix operation accelerator for execution, and the floating-point operation unit array supporting multiple operations set in the matrix operation accelerator is used to perform pipeline calculations on the target matrix of the received matrix operation target task, and the matrix data of each stage and the calculated data are stored in the corresponding internal memory respectively.

[0041] Optionally, the target task is obtained in the following manner:

[0042] Acquiring collected information through the processor; wherein the collected information includes: at least one of satellite positioning information, inertial motion information, image information, and wireless information;

[0043] The target task for performing positioning calculation is determined by the processor based on the collected information.

[0044] In the above implementation process, the target task for positioning calculation can be determined by the processor. The target task can be the target task for positioning calculation in various types of positioning and navigation systems such as satellite positioning and navigation systems, inertial positioning and navigation systems, visual positioning and navigation systems, radio positioning and navigation systems, integrated positioning and navigation systems, and positioning and navigation systems in other specific fields. Therefore, the processor can respectively obtain the collection information collected by the corresponding sensors or collection devices in various types of positioning and navigation systems, and determine one or more task queues for positioning calculation based on the collection information. Each task queue can include target tasks for multiple matrix operations. It can be applied to various different types of positioning and navigation systems to effectively optimize various types of navigation and positioning algorithms based on matrix operations.

[0045] Optionally, the method further includes:

[0046] Moving result data of the calculation data stored in the internal memory to the external memory for processing through the matrix operation accelerator;

[0047] The processor calls the result data stored in the external memory for processing to obtain positioning and navigation information.

[0048] In the above implementation process, the matrix operation accelerator moves the result data of the calculation data stored in the internal processor to the external memory, so that the processor calls the result data stored in the external memory for analysis to obtain the corresponding positioning and navigation information in various types of positioning and navigation systems. There is no need to set up a complex or large processing chip for matrix operations. The cost of matrix operations can be reduced and the efficiency of matrix operations can be improved through floating-point calculations. It is suitable for processing matrix operation tasks of various dimensions, and the storage entity is scheduled in a shared resource pool mode, which effectively saves the number of memory blocks and capacity requirements, improves the performance of the matrix operation accelerator, improves the efficiency of positioning calculations, and reduces the computational cost of positioning calculations, thereby improving the work efficiency of various types of positioning and navigation systems.

[0049] In a third aspect, an embodiment of the present application further provides a satellite navigation method, the method comprising:

[0050] Determining a target task for positioning calculation based on the collected and generated satellite positioning information and / or sensor information by a processor;

[0051] The processor sends the target task to be executed to the matrix operation accelerator for processing; wherein the matrix operation accelerator is provided with a floating point operation unit array;

[0052] Performing pipeline calculations on the target matrix of the target task based on the floating-point operation unit array by the matrix operation accelerator to obtain calculation data;

[0053] Storing the target matrix and the calculation data respectively in an internal memory within the matrix operation accelerator;

[0054] Moving result data of the calculation data stored in the internal memory to the external memory for processing through the matrix operation accelerator;

[0055] The processor calls the result data stored in the external memory for processing to determine satellite positioning and navigation information.

[0056] In the above implementation process, the target task for positioning calculation is determined by the processor, and a matrix operation accelerator equipped with a floating-point operation unit array is scheduled to execute the current target task. During execution, the target matrix of the target task can be pipelined based on the floating-point operation unit array to obtain corresponding calculation data, and the calculation data and the target matrix are stored in different internal memories respectively. The matrix operation accelerator moves the result data of the calculation data stored in the internal processor to the external memory, so that the processor calls the result data stored in the external memory for analysis to obtain corresponding satellite positioning and navigation information. There is no need to set up a complex or large processing chip for matrix operation. The cost of matrix operation can be reduced and the efficiency of matrix operation can be improved through floating-point calculation. It is suitable for processing matrix operation tasks of multiple dimensions, and the storage entity is scheduled using a shared resource pool mode, which effectively saves the number of memory blocks and capacity requirements, improves the performance of the matrix operation accelerator, improves the efficiency of positioning calculation, reduces the calculation cost of positioning calculation, and thus improves the working efficiency of the satellite positioning and navigation system.

[0057] In a fourth aspect, an embodiment of the present application also provides a computer-readable storage medium, in which computer program instructions are stored. When the computer program instructions are read and executed by a processor, the steps in any implementation method of the above-mentioned matrix operation method or satellite navigation method are executed.

[0058] In summary, the embodiments of the present application provide a matrix operation system, a matrix operation method, a satellite navigation method and a storage medium. By setting a floating-point operation unit array that supports multiple operations in a matrix operation accelerator, the matrix operation tasks are pipelined based on the floating-point operation unit array, and the data of each stage are stored in the corresponding internal memory respectively. This can reduce the cost of matrix operation and improve the efficiency of matrix operation, thereby improving the performance of positioning calculation and improving the working efficiency of the positioning and navigation system. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0060] FIG1 is a schematic structural diagram of a matrix operation system provided in an embodiment of the present application;

[0061] FIG2 is a schematic diagram of the architecture of a floating-point arithmetic unit array provided in an embodiment of the present application;

[0062] FIG3 is a schematic diagram of the structure of another matrix operation system provided in an embodiment of the present application;

[0063] FIG4 is a flow chart of a matrix operation method provided in an embodiment of the present application;

[0064] FIG5 is a flow chart of another matrix operation method provided in an embodiment of the present application;

[0065] FIG6 is a flow chart of another matrix operation method provided in an embodiment of the present application;

[0066] FIG7 is a flow chart of a satellite navigation method provided in an embodiment of the present application.

[0067] Icons: 110 - matrix operation accelerator; 120 - bus; 130 - internal memory; 140 - processor; 111 - floating-point operation unit array; 131 - first type of memory; 132 - second type of memory; 133 - third type of memory; 134 - fourth type of memory; 150 - external memory; 112 - state machine; 113 - management module. DETAILED DESCRIPTION

[0068] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of them. Based on the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the embodiments of the present application.

[0069] Due to the diversity of application scenarios, when performing positioning and navigation, the positioning and navigation systems used in different application scenarios are also different. For example, various types of positioning and navigation systems such as satellite positioning and navigation systems, inertial positioning and navigation systems, visual positioning and navigation systems, radio positioning and navigation systems, integrated positioning and navigation systems, and positioning and navigation systems in specific fields can be used to provide users with positioning and navigation services.

[0070] For example, satellite positioning and navigation systems can include the Global Positioning System, the BeiDou Navigation System, and other global navigation satellite systems. By transmitting signals containing satellite position and time information to the surface of the earth, receiving devices on the ground (such as GPS receivers) receive these signals and calculate the signal transmission time based on the signal transmission time and the local reception time. Since the speed of signal propagation in a vacuum is constant (i.e., the speed of light), the distance between the satellite and the receiving device can be calculated by the transmission time. Satellite positioning and navigation systems have the characteristics of global coverage, high precision, high real-time performance, and all-day operation. They are suitable for application scenarios in various fields such as transportation, surveying and mapping, military, and disaster detection.

[0071] The inertial positioning and navigation system is an autonomous positioning and navigation system that does not rely on external information or radiate energy. It utilizes the principle of inertia to measure the acceleration of the carrier in an inertial reference frame, integrate it over time, and transform it into a navigation coordinate system. This information provides information such as velocity, yaw angle, and position in the navigation coordinate system. The inertial positioning and navigation system offers advantages such as autonomy, concealment, and continuity, making it suitable for a variety of high-precision applications, such as military and aviation.

[0072] Visual positioning and navigation systems use image information captured by cameras to determine the relative position and orientation of a robot or vehicle within an environment through image recognition, feature extraction, and matching. This process may involve identifying and analyzing landmarks, road signs, obstacles, and other elements in the image, and using these elements to make path planning and obstacle avoidance decisions. Visual positioning and navigation systems offer strong real-time performance and high accuracy, making them suitable for short-range navigation and obstacle avoidance applications such as autonomous driving, robot navigation, and drones.

[0073] Radio positioning and navigation systems utilize the propagation characteristics of radio waves for navigation and positioning. They include a variety of specific systems, such as the radio compass, the Decca positioning and navigation system, the Omega positioning and navigation system, the Loran-C positioning and navigation system, the Doppler positioning and navigation system, and the radar positioning and navigation system. Radio positioning and navigation systems feature simple equipment, ease of use, and high navigation accuracy. They are suitable for applications requiring wide coverage and high precision, such as aviation, maritime navigation, and land transportation.

[0074] An integrated positioning and navigation system combines two or more positioning and navigation systems based on different principles, using data processing and fusion technologies to improve their accuracy and reliability. This system leverages the strengths of various positioning and navigation systems to enhance overall navigation performance. It is suitable for aviation, military, and other applications requiring high precision or in complex environments with high interference. For example, an inertial / satellite positioning and navigation system combines an inertial and satellite positioning and navigation system, using data fusion technology to achieve high-precision navigation and positioning.

[0075] Positioning and navigation systems in other specific fields may include positioning and navigation systems in the aviation field that ensure the safe flight and orderly management of aircraft in the air, systems that integrate multiple navigation and flight control functions for aircraft route planning, flight monitoring and navigation, systems that use radio waves to measure the height between the aircraft and the ground, mainly used for navigation during low-altitude flight and landing phases, and systems that provide atmospheric environment parameters around the aircraft (such as air pressure, temperature, wind speed, etc.), etc., which are suitable for environments such as urban canyons and tunnels where GPS signals cannot be covered or are interfered with, as well as application scenarios in special industries such as oil exploration, geological exploration, and agricultural automation.

[0076] Many types of positioning and navigation systems require matrix operations to provide corresponding positioning and navigation services. For example, in satellite positioning and navigation systems, current processing chips typically use a general-purpose processor to access a dedicated storage system through its bus. The storage system stores the operand matrix to be processed and the result matrix after the matrix operation. The general-purpose processor then performs the matrix operation to complete each step of the matrix operation. However, this approach is only suitable for business scenarios with simple calculations. For large-dimensional matrix operations, it requires more CPU computing power and bus bandwidth, resulting in lower matrix operation performance, larger computing power consumption, and larger chip area. As a result, current positioning and navigation systems are inefficient and costly when performing positioning calculations, and are unable to meet various positioning and navigation needs.

[0077] In order to solve the above problems, the present application provides a matrix operation system, which can be set in various types of positioning and navigation systems such as satellite positioning and navigation systems, inertial positioning and navigation systems, visual positioning and navigation systems, radio positioning and navigation systems, integrated positioning and navigation systems, and positioning and navigation systems in specific fields.

[0078] Please refer to Figure 1, which is a structural diagram of a matrix operation system provided in an embodiment of the present application. The system may include: a matrix operation accelerator 110, a bus 120, a processor 140 and an internal memory 130 set inside the matrix operation accelerator.

[0079] Among them, bus 120 connects matrix operation accelerator 110 and processor 140. An independent bus interface can be set in matrix operation accelerator 110 to exchange data with processor 140 through bus 120. Different system bus architectures can also be used, and after being split and combined into multiple ports, system-level connections with the same functions can be achieved. Therefore, the processor 140 in this application can perform task scheduling but does not perform matrix operations. Compared with the method of using a general-purpose processor to perform matrix operations, it effectively improves the processing performance of the system, saves general computing power costs, reduces the energy consumption required for calculation, and reduces the hardware area and volume.

[0080] It should be noted that the matrix operation accelerator 110 is provided with a floating-point operation unit array 111 corresponding to a variety of algorithms. The matrix operation accelerator 110 can perform pipeline calculations on the target matrix of the received target task based on the floating-point operation unit array 111 to obtain calculation data, and the internal memory 130 can store the target matrix and the calculation data separately. There is no need to set up a complex or large processing chip for matrix operation. The cost of matrix operation can be reduced and the efficiency of matrix operation can be improved through floating-point calculation. It is suitable for processing matrix operation tasks of multiple dimensions, and the storage entity is scheduled in a shared resource pool mode, which effectively saves the number of memory blocks and capacity requirements, improves the performance of the matrix operation accelerator 110, improves the efficiency of positioning calculation, reduces the calculation cost of positioning calculation, and thus improves the working efficiency of the positioning navigation system.

[0081] Optionally, the matrix operation accelerator 110 may include one or more floating-point operation unit arrays 111, which are connected to the internal memory 130. The floating-point operation unit arrays 111 may employ a parallel computing architecture, capable of completing n floating-point operations within one cycle. Each floating-point operation unit array 111 may support single-precision or double-precision floating-point operations. Multiple floating-point operation unit arrays 111 support parallel and pipeline operations, enabling uninterrupted operations for multiple cycles.

[0082] It should be noted that in order to realize a variety of different computing functions and be applicable to matrix calculations of various dimensions, one or more parameter information such as the operator type, number of parallelism, number of pipeline stages, and dimension information of the floating-point operation unit array 111 can be determined according to the computational requirements of the matrix operations in the actual application scenario, so as to set the corresponding floating-point operation unit array 111.

[0083] Optionally, parameters such as operator type, number of parallelism, number of pipeline stages, and dimension information can be set and modified according to the actual operation scenario and requirements. For example, the operator type can include the following five types of operators: (1) Y = A*B; (2) Y = C + A*B; (3) Y = CA*B; (4) Y = A*B*AT; (5) Y = 1 / A, where A, B, and C can be multiple target matrices corresponding to the target task, and Y is the calculated result data. The upper-level software in the positioning and navigation system can schedule these five types of operators to complete the accelerated operation of complex matrices. The degree of parallelism can be the number of floating-point operations processed when executing a certain operator type. The number of pipeline levels can include the number of intra-task pipelines and inter-task pipelines. The intra-task pipeline includes the process of calling each cycle to perform floating-point operations, so that the matrix within the task is split according to the dimension into multiple vector operations that flow continuously. The inter-task pipeline includes the process of calculating between multiple matrix operation tasks, so that multiple matrix operations flow continuously, thereby improving the computational efficiency of the task. The dimension information can be the number of dimensions of the matrix during a single calculation by the floating-point operation unit array 111.

[0084] Therefore, the configuration parameters of the floating-point operation unit array 111 can be determined based on the computational requirements of the matrix operation. The configuration parameters include: operator type and at least one of the number of parallelism, number of pipeline stages, and dimensionality information. This allows for the configuration of the floating-point operation unit array 111 with high computational performance to perform computations at a low cost, effectively improving the efficiency of matrix operations and making it suitable for processing a variety of different types of matrix operation tasks.

[0085] Due to the different dimensions of the target matrix of the calculation, the calculation data may include intermediate data and result data; the specific calculation process of the matrix operation accelerator 110 may include: obtaining the target matrix of the target task currently being executed; splitting the target matrix based on the floating-point operation unit array 111 to obtain one or more split matrices and / or one or more operation row-column vectors; performing pipeline calculations on the one or more split matrices and / or one or more operation row-column vectors based on the floating-point operation unit array 111 to obtain intermediate data; based on the floating-point operation unit array 111 and the corresponding operator type, calling all the intermediate data to perform combined operations to obtain result data. When performing matrix operations, the target matrix of large dimensions may be split to obtain one or more small split matrices and / or one or more operation row-column vectors, thereby performing pipeline calculations on the one or more split matrices and / or one or more operation row-column vectors based on the floating-point operation unit array 111 to obtain multiple intermediate data to be used, and then performing combined operations on the intermediate data based on the floating-point operation unit array 111 and the corresponding operator type to obtain result data after the target matrix is ​​calculated. It can split a large-dimensional target matrix into one or more small-dimensional matrices and / or one or more operation row and column vectors for calculation, and use pipeline calculation to improve calculation efficiency. It is suitable for matrix operations of various dimensions.

[0086] It should be noted that the multiplication and accumulation structure of the floating-point operation unit array 111 can perform vector operations, and the combination of vector operations can support matrix operation types such as matrix multiplication, matrix addition, matrix inversion, and matrix multiplication and addition.

[0087] For example, please refer to Figure 2, which is a schematic diagram of the architecture of a floating-point operation unit array 111 provided in an embodiment of the present application. Taking the multiplication of a 1*4 row vector and a 4*1 column vector as an example, the operator type is Y=A*B, and the first row of A*the first column of B is processed with a parallelism of 4 in a pipeline operation. The resulting calculation data includes multiple intermediate data: a11*b11, a12*b21, a13*b31, a14*b41, and result data: a11*b11+a12*b21+a13*b31+a14*b41. For vectors or matrices of other dimensions, hardware logic control can be used to repeatedly call the floating-point operation unit array 111 with a parallelism of 4 to perform pipeline calculations to complete the final complete matrix operation.

[0088] Please refer to Figure 3, which is a structural diagram of another matrix operation system provided in an embodiment of the present application, wherein the internal memory 130 may include: a first type of memory 131, a second type of memory 132 and a third type of memory 133.

[0089] Optionally, the matrix operation accelerator 110 can perform data flow control for different matrix operation types, parsing matrix operations of different dimensions and types into floating-point row and column vector operations, performing parallel pipeline floating-point operations on multiple floating-point row and column vectors in the floating-point operation unit array 111, and reading and outputting parallel data from the operation array based on the requirements of floating-point vector operations (row / column). A cache management module can be provided in the matrix operation accelerator 110 to control access to the multiple internal memories 130.

[0090] Since the matrix operation accelerator 110 needs to call the original target matrix for calculation during the matrix operation process and obtain the corresponding intermediate data and result data, in order to improve the reading efficiency of each type of data during the operation, the data at each stage can be stored separately to ensure timely access and improve the pipeline efficiency of matrix task operation processing. For example, the first type of memory 131 is used to store the target matrix; the second type of memory 132 is used to store intermediate data; and the third type of memory 133 is used to store result data. By storing multiple types of data in corresponding types of internal memory 130, when the data needs to be read, there is no need for preprocessing before reading. The required data can be read directly from the corresponding internal memory 130, effectively improving the efficiency of internal storage arbitration and access in the matrix operation accelerator 110, thereby improving the efficiency of matrix operations.

[0091] Optionally, since there are multiple matrix operation tasks, an external memory 150 connected to the matrix operation accelerator and the processor can be set to store the operand matrices of multiple unstarted tasks or the result data of completed matrix operation tasks. After the task is started, the matrix operation accelerator 110 can move the operand matrix from the external memory 150 to the internal memory 130 and start the operation. After the operation is completed, the matrix operation accelerator 110 can also write the result data from the internal memory 130 to the external memory 150 for processing. Furthermore, since each matrix operation task needs to read corresponding data for calculation, in order to reduce the waiting time and data reading time of subsequent tasks, the internal memory 130 may also include: a fourth type of memory 134. When the matrix operation accelerator 110 calculates the target matrix, the matrix operation accelerator 110 can pre-read the operand matrix of one or more subsequent tasks to be executed from the external memory 150 in advance, and store the operand matrix in the fourth type of memory 134. The operand matrix can be related data such as matrix data of the subsequent task, and the matrix operation accelerator 110 can also move the result data stored in the third type of memory 133 to the external memory 150 for processing, so as to ensure efficient pipeline processing between matrix operation tasks and improve the execution efficiency of matrix operation tasks.

[0092] For example, the first type of memory 131, the second type of memory 132, the third type of memory 133 and the fourth type of memory 134 can all be SRAM (Static Random-Access Memory), and the external memory 150 can be a storage medium with a larger capacity such as SRAM, DDR (Double Data Rate, double data rate synchronous dynamic random access memory), Flash (flash memory), etc.

[0093] It should be noted that the internal memory 130 can be in resource pool mode, so the stored data type can be switched. The type of each internal memory 130 is not fixed but variable. Compared with other modes with relatively fixed storage data types, the resource pool mode can effectively save storage resources and achieve higher storage and reading efficiency. To achieve classified storage of multiple data, the matrix operation accelerator 110 can also be provided with a state machine 112 and a management module 113. The state machine 112 can apply for storage requirements from the management module 113 based on the actual situation of the target task to make a storage request. The management module 113 can determine the storage type of each internal memory 130 based on the storage requirements, as well as the current storage status and remaining storage space of each internal memory 130. That is, the type of the internal memory 130 is variable. Therefore, in actual usage scenarios, an internal memory 130 that does not store data can be selected to store the target matrix, intermediate data, result data, operand matrix, etc. It is also possible to select an internal memory 130 with remaining storage space greater than the data size based on the data size of the target matrix, intermediate data, result data, and operand matrix for storage. This meets the actual computing requirements of different matrix operation tasks and is suitable for a variety of computing scenarios.

[0094] Optionally, the state machine 112 can also control the target matrix corresponding to the target task to perform splitting processing to obtain one or more split matrices and / or one or more operation row and column vectors. The state machine 112 can also control the master port (the port on the shortest path among all paths connecting the multiple spanning tree domains and the total root) of the AXI (Advanced eXtensible Interface) of the matrix operation accelerator 110 to realize data interaction between the matrix operation accelerator 110 and the external memory 150.

[0095] It should be noted that in order to store data completely and effectively, each type of internal memory 130 can include one or more, and the number of internal memories 130 is greater than or equal to 4, that is, there is at least one internal memory of each type, and the capacity of the internal memory 130 is also set, and the capacity of each internal memory 130 is greater than or equal to the matrix capacity of the maximum matrix of the matrix operation, so that the internal memory 130 can completely store the matrix data.

[0096] In summary, the matrix operation system provided in the embodiment of the present application has strong applicability, can adapt to product application forms, is not restricted by a fixed architecture, uses a dedicated matrix operation accelerator to implement matrix operations, supports any matrix operation type of vector multiplication and addition operation combination, supports a wide range of matrix operation types, and can support a variety of matrix operations that can be equivalently decomposed into vector multiplication and addition operations. Matrix operations are implemented using a floating-point operation unit array 111, support parallel pipeline processing, and effectively improve the computing performance of the matrix operation system.

[0097] Please refer to FIG. 4 , which is a flow chart of a matrix operation method provided in an embodiment of the present application. The matrix operation method is applied to a matrix operation system, and the method may include steps S210 - S230 .

[0098] Step S210: The processor sends the target task to be executed to the matrix operation accelerator for processing.

[0099] Step S220 , performing pipeline calculations on the target matrix of the target task based on the floating-point operation unit array by the matrix operation accelerator to obtain calculation data.

[0100] Step S230: Store the target matrix and the calculated data separately in the internal memory.

[0101] Among them, the target task is sent to the matrix operation accelerator for execution through the processor, and the target matrix of the received target task of matrix operation is pipelined through the floating-point operation unit array supporting multiple operations set in the matrix operation accelerator, and the matrix data of each stage and the calculated data are stored in the corresponding internal memory respectively.

[0102] Since the principle of solving the problem by the matrix operation method in the embodiment of the present application is similar to that of the embodiment of the aforementioned matrix operation system, the implementation of the matrix operation method in this embodiment can refer to the description in the embodiment of the aforementioned matrix operation system, and the repeated parts will not be repeated.

[0103] Please refer to FIG. 5 , which is a flowchart of another matrix operation method provided in an embodiment of the present application. The method may further include steps S211 - S212 .

[0104] Step S211: Acquire collection information through the processor.

[0105] Among them, the matrix operation system can be set in a variety of different types of positioning and navigation systems. Therefore, the matrix operation method can be applied to a variety of different types of positioning and navigation systems, such as satellite positioning and navigation systems, inertial positioning and navigation systems, visual positioning and navigation systems, radio positioning and navigation systems, integrated positioning and navigation systems, and positioning and navigation systems in other specific fields. A variety of different types of sensors or acquisition devices can be set in different types of positioning and navigation systems. For example, corresponding positioning satellites can be set in satellite positioning and navigation systems, and a variety of types of inertial sensors can be set in inertial positioning and navigation systems, such as accelerometers (or acceleration sensors) and angular velocity sensors (gyroscopes) and their single, dual, and three-axis combinations IMU (Inertial Measurement Unit), AHRS (Attitude and heading reference system, including attitude reference system of magnetic sensors), MEMS (Micro-Electro-Mechanical System, micro-electromechanical system), etc.; various types of visual sensors can be provided in the visual positioning and navigation system, for example, monocular, binocular, multi-eye and RGB-D cameras based on cameras, etc. The visual sensor may include one or two graphic sensors (such as CMOS or CCD semiconductor chips), light sources, lenses, analog / digital converters, graphic processors, graphic memories and other parts, and may also include light projectors and other auxiliary equipment; in the radio positioning and navigation system, taking the radar positioning and navigation system as an example, various types of lidar sensors can be provided, for example, mechanical lidar, solid-state lidar and hybrid solid-state lidar, etc. The lidar sensor may include a laser emitting unit, a receiving unit, a scanning module and related control and signal processing circuits, etc.; the integrated positioning and navigation system may include one or more of inertial sensors, visual sensors and lidar sensors to perform integrated positioning and navigation processing based on multiple different types of sensors. Therefore, the collection information collected by various types of sensors or collection devices may include: satellite positioning information collected by positioning satellites, inertial motion information collected by inertial sensors, image information collected by visual sensors, three-dimensional information collected by lidar sensors, time, phase, amplitude, frequency of radio signal propagation collected by other sensors, as well as various information such as the direction, distance, speed, etc. of the target. The processor can be communicatively connected or electrically connected to various types of sensors or collection devices to obtain the collection information collected by the sensors or collection devices.

[0106] Optionally, in positioning and navigation systems in other specific fields, the collected information may also include flight control information, route information, altitude information, air pressure information, temperature information, wind speed information and other information.

[0107] Step S212: The processor determines a target task for positioning calculation based on the collected information.

[0108] The processor may determine one or more task queues for performing positioning calculations based on the acquired collection information, and each task queue may include target tasks for multiple matrix operations.

[0109] In the embodiment shown in FIG5 , the matrix operation method can be applied to various types of positioning and navigation systems to effectively optimize various types of navigation and positioning algorithms based on matrix operations.

[0110] Please refer to FIG. 6 , which is a flow chart of another matrix operation method provided in an embodiment of the present application. The method may further include steps S231 - S232 .

[0111] Step S231 : Moving the result data of the calculation data stored in the internal memory to the external memory for processing through the matrix operation accelerator.

[0112] Among them, the matrix operation accelerator moves the result data of the calculation data stored in the internal processor to the external memory. The matrix operation accelerator can notify the processor of the change of the execution status of the task based on the interrupt reporting method, and the change of the task execution status can be obtained through the processor's periodic query method. After the matrix operation accelerator completes the processing of the matrix operation task, the internal memory can write the calculated processing data to the external memory, so that the processor can read the processing data stored in the external memory for processing, or send new tasks to be scheduled for processing.

[0113] Step S232: The processor calls the result data stored in the external memory for processing to obtain positioning and navigation information.

[0114] The result data may be a result matrix or other type of data, and the processor may call the result data stored in the external memory for analysis to obtain corresponding positioning and navigation information for various types of positioning and navigation systems. The processor may send the positioning and navigation information to downstream electronic devices with logic computing capabilities, such as servers, personal computers (PCs), tablet computers, smartphones, and personal digital assistants (PDAs), so that the electronic devices can implement corresponding navigation functions.

[0115] In the embodiment shown in FIG6 , the positioning and navigation information required for positioning can be provided to various types of positioning and navigation systems, thereby effectively improving the working efficiency of the various types of positioning and navigation systems.

[0116] It should be noted that since the matrix operation system can be set up in many different types of positioning and navigation systems, the embodiments shown in Figures 1 to 4 can all be implemented in the embodiments shown in Figures 5 and 6 based on the implementation methods of similar embodiments, and the repeated implementation methods will not be repeated.

[0117] Please refer to Figure 7, which is a flow chart of a satellite navigation method provided in an embodiment of the present application. The satellite navigation method is applied to a satellite positioning navigation system including a matrix operation system. The method may include steps S310-S360.

[0118] Step S310: The processor determines a target task for performing positioning calculation based on the collected and generated satellite positioning information and / or sensor information.

[0119] Among them, the processor can obtain corresponding satellite positioning information and / or sensor information, and determine one or more task queues for positioning calculation based on the satellite positioning information and / or sensor information. Each task queue can include multiple target tasks for matrix operations.

[0120] Optionally, satellite positioning information can be collected and acquired by radio frequency devices and baseband devices in the satellite positioning and navigation system. For example, the radio frequency device receives satellite signals, converts them into intermediate frequency signals, and transmits them to the baseband device. The baseband device then processes the intermediate frequency signals to obtain corresponding satellite positioning information, and transmits the satellite positioning information to the processor. Sensor information can include information collected by various sensors in the satellite positioning and navigation system. For example, the sensors can include inertial sensors, visual sensors, and lidar sensors. Accordingly, the sensor information can include various types of information, such as inertial motion information, image information, and three-dimensional information.

[0121] Step S320: The processor sends the target task to be executed to the matrix operation accelerator for processing.

[0122] Among them, the matrix operation accelerator is equipped with a floating-point operation unit array corresponding to multiple algorithms. The processor can schedule multiple target tasks according to demand to control the matrix operation accelerator to perform calculations on the current corresponding target task.

[0123] Step S330 , performing pipeline calculations on the target matrix of the target task based on the floating-point operation unit array through the matrix operation accelerator to obtain calculation data.

[0124] The matrix operation accelerator can perform pipeline calculations on the target matrix of the target task based on the floating-point operation unit array provided therein to obtain corresponding calculation data.

[0125] Step S340 , storing the target matrix and the calculation data separately in the internal memory of the matrix operation accelerator.

[0126] Among them, the execution order of step S330 and step S340 is not limited. In order to realize the separate storage of different types of data, the internal memory can store the target matrix before the matrix operation accelerator calculates, and store the obtained calculation data during the calculation process of the matrix operation accelerator to realize the separate storage of different types of data.

[0127] Step S350: Move the result data of the calculation data stored in the internal memory to the external memory for processing through the matrix operation accelerator.

[0128] Among them, the matrix operation accelerator can notify the processor of the change in the execution status of the task based on interrupt reporting, or the processor can obtain the change in the task execution status through periodic query. After the matrix operation accelerator completes the processing of the matrix operation task, the internal memory can write the calculated processing data to the external memory, so that the processor can read the processing data stored in the external memory for processing, or send new tasks to be scheduled for processing.

[0129] Step S360: The processor calls the result data stored in the external memory for processing to determine the satellite positioning and navigation information.

[0130] Among them, the result data can be data of types such as result matrix. The processor can analyze the result data obtained through processing to obtain corresponding satellite positioning and navigation information, thereby sending the satellite positioning and navigation information to downstream servers, personal computers (PC), tablet computers, smart phones, personal digital assistants (PDA) and other electronic devices with logical computing functions, so that the electronic devices can realize corresponding navigation functions.

[0131] It should be noted that since the matrix operation system is set in the satellite positioning navigation system, the embodiments shown in Figures 1 to 4 can all be implemented in the embodiment shown in Figure 7 based on the implementation method of similar embodiments, and the repeated implementation methods will not be repeated.

[0132] An embodiment of the present application further provides a computer-readable storage medium, in which computer program instructions are stored. When the computer program instructions are read and executed by a processor, the steps of any one of the matrix operation method or satellite navigation method provided in this embodiment are executed.

[0133] In the several embodiments provided in this application, it should be understood that the disclosed devices can also be implemented in other ways. The system embodiments described above are merely schematic. For example, the block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices according to the multiple embodiments of the present application. In this regard, each box in the block diagram can represent a module, a program segment or a part of a code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram, and the combination of the block diagrams, can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0134] In addition, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0135] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0136] The foregoing is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included within the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined or explained in subsequent figures.

[0137] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

[0138] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

Claims

1. A matrix operation system, characterized in that: The system comprises: a matrix operation accelerator, a bus, a processor and an internal memory arranged inside the matrix operation accelerator; The bus connects the matrix operation accelerator and the processor; The matrix operation accelerator is provided with a floating point operation unit array; The processor is used to send the target task to be executed for the matrix operation accelerator to process; The matrix operation accelerator is used to perform pipeline calculation on the target matrix of the target task based on the floating-point operation unit array to obtain calculation data; The internal memory is used to store the target matrix and the calculation data respectively.

2. The system according to claim 1, characterized in that The setting parameters of the floating point operation unit array are determined according to the operation requirements of the matrix operation; wherein the setting parameters include: operator type and at least one of the number of parallelism, number of pipeline stages and dimension information.

3. The system according to claim 1, characterized in that in, The calculation data includes: intermediate data and result data; The matrix operation accelerator specifically obtains the target matrix of the target task currently being executed; splits the target matrix based on the floating-point operation unit array to obtain one or more split matrices and / or one or more operation row-column vectors; performs pipeline calculations on one or more split matrices and / or one or more operation row-column vectors based on the floating-point operation unit array to obtain the intermediate data; based on the floating-point operation unit array and the corresponding operator type, calls all the intermediate data to perform combined operations to obtain the result data.

4. The system according to claim 3, characterized in that in, The internal memory includes: a first type of memory, a second type of memory and a third type of memory; The first type of memory is used to store the target matrix; The second type of memory is used to store the intermediate data; The third type of memory is used to store the result data.

5. The system according to claim 4, characterized in that in, The system further includes: an external memory, and the internal memory further includes: a fourth type of memory; the external memory is connected to the matrix operation accelerator and the processor via a bus; The external memory is used to store the operand matrix of the unstarted tasks; In the case where the matrix operation accelerator calculates the target matrix, the fourth type of memory is used to store the operand matrix of the next one or more subsequent tasks to be executed pre-read by the matrix operation accelerator from the external memory; The matrix operation accelerator is used to move the result data stored in the third type of memory to the external memory.

6. The system according to claim 4 or 5, characterized in that: in, The matrix operation accelerator is also provided with a state machine and a management module; the state machine is connected to the management module, and the management module is connected to each of the internal memories; The state machine is used to apply for storage requirements from the management module according to the target task; The management module is used to determine the type of each of the internal memories according to the storage requirements, and the current storage status and remaining storage space of each of the internal memories.

7. The system according to claim 6, characterized in that in, The number of the internal memories is greater than or equal to 4, and the capacity of each of the internal memories is greater than or equal to the matrix capacity of the maximum matrix of the matrix operation.

8. A matrix operation method, characterized in that: The method is applied to a matrix operation system, the system comprising: a matrix operation accelerator, a bus, a processor and an internal memory arranged inside the matrix operation accelerator; the bus connects the matrix operation accelerator and the processor; a floating point operation unit array is arranged in the matrix operation accelerator; Sending the target task to be executed by the processor for processing by the matrix operation accelerator; Perform pipeline calculation on the target matrix of the target task based on the floating-point operation unit array by a matrix operation accelerator to obtain calculation data; The target matrix and the calculated data are stored separately in an internal memory.

9. The method according to claim 8, characterized in that in, The target task is obtained in the following way: Acquire acquisition information through the processor; wherein the acquisition information includes: at least one of satellite positioning information, inertial motion information, image information, and wireless information; The target task for performing positioning calculation is determined by the processor based on the collected information.

10. The method according to claim 8, characterized in that The method further comprises: The matrix operation accelerator moves the result data of the calculation data stored in the internal memory to the external memory for processing; The processor calls the result data stored in the external memory for processing to obtain positioning and navigation information.

11. A satellite navigation method, characterized in that: The method comprises: Determine, by a processor, a target task for performing positioning calculation based on the collected and generated satellite positioning information and / or sensor information; The target task to be executed is sent by the processor to the matrix operation accelerator for processing; wherein the matrix operation accelerator is provided with a floating point operation unit array; Perform pipeline calculation on the target matrix of the target task based on the floating-point operation unit array by the matrix operation accelerator to obtain calculation data; The target matrix and the calculation data are stored respectively in an internal memory inside the matrix operation accelerator; The matrix operation accelerator moves the result data of the calculation data stored in the internal memory to the external memory for processing; The processor calls the result data stored in the external memory for processing to determine the satellite positioning navigation information.

12. A computer-readable storage medium, characterized in that: The readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the steps of the method according to any one of claims 8 to 11 are executed.

Images