Dynamic element matching with frequency dependent sequence rate

Abstract

A digital-to-analog-converter (DAC) includes binary-to-thermometer encoder circuitry configured to produce one or more sets of thermometer-coded bits from a stream of input data words. The DAC includes a control signal generation circuit configured to generate a scrambling rate control signal based at least in part on a time-varying frequency parameter associated with the stream of input data words and / or with an analog output signal to be generated by the DAC. A dynamic element matching (DEM) circuit includes a first DEM segment configured to scramble a first one of the sets of thermometer-coded bits, based on the scrambling rate control signal. The DAC may further include DAC circuitry that includes a first thermometer-coded DAC segment configured to convert the scrambled thermometer-coded bits of the first one of the sets of thermometer-coded bits to form at least a first component of an analog output signal.

Description

[0001] Dynamic Element Matching with Frequency Dependent Sequence Rate

[0002] TECHNICAL FIELD

[0003] The present disclosure generally relates to improved implementations of digital-to-analog converters (DACs) that support high bandwidth wireless communications. More particularly, the present disclosure improves dynamic element matching (DEM) techniques used in DACs.

[0004] BACKGROUND

[0005] As wireless communication standards constantly evolve to demand higher bandwidth and carrier frequencies, DACs used in transmitters face stringent requirements such as high linearity, high SNR, and low levels of spurs and other emission contributions in the output signal spectrum. Sample rates reaching tens of GHz may be needed to generate high bandwidth baseband transmitter signals or even the radio frequency (RF) signal directly, bypassing the up- conversion in the analog domain altogether. Such high capability DACs are difficult to design, with extremely tight requirements on every subblock.

[0006] Existing DAC solutions have various inherent problems. First, a unit-weight DAC having unit cells of nominally the same weights has a relative mismatch among the unit cells due to random and systematic errors. For example, random errors originate from the finite accuracy of the manufacturing, while systematic errors originate from design decisions on architecture and layout causing a systematic difference in supply voltage or clock skew between the unit cells.

[0007] Second, a binary-coded DAC with binary-weighted cells has difficulties in maintaining a desired relation between weights of different DAC cells across process-voltage-temperature (PVT). When the weights deviate from the nominal ones, the output of the DAC may not accurately represent the input data, leading to distortion manifested in lower spurious-free dynamic range (SFDR) and increased integral nonlinearity (INL). Further, DAC cells of different weights may exhibit slightly different behavior in their response to a change of input data, often seen as a time skew between the DAC cells. As the frequency of the DAC signal being generated increases, time skew rapidly increases the level of distortion.

[0008] Third, a thermometer-coded DAC with multiple segments, e.g., a most-significant-bits (MSB) segment, an intermediate-significant-bits (ISB) segment, and a least-significant-bits (LSB) segment, face an exacerbated mismatch problem that requires calibration of the segments. Some existing thermometer-coded DACs employ DEM techniques to decorrelate distortion caused by the DAC cell mismatch, but at the expense of increased noise level. The existing DEM technique increases switching activity in the DAC, even when a DC signal is generated, increases power consumption, and changes the spectral content of the supply current which in turn changes the spectral content of the supply voltage due to the non-zero supply resistance. The existing DEM technique leads to an increase in nonlinear distortion, due to the multiplicative effect when the supply voltage variation modulates the DAC (e.g., R-DAC or C-DAC) output amplitude and sampling time.

[0009] SUMMARY

[0010] The present disclosure provides an improved DAC design that enables fulfillment of tight requirements for scenarios where RF or bandpass signals are generated directly by the DAC.

[0011] In one aspect, the disclosure describes a highly linear RF-sampling DAC that suppresses or eliminates harmonic components and tone separation components in the power supply network, to achieve high linear radio performance.

[0012] According to one aspect of the disclosure, a DAC may comprise binary-to-thermometer encoder circuitry, a control signal generation circuit, a DEM circuit, and DAC circuitry. The binary-to-thermometer encoder may be configured to produce one or more sets of thermometer- coded bits from a stream of input data words. The control signal generation circuit may be configured to generate a scrambling rate control signal based at least in part on a time-varying frequency parameter associated with the stream of input data words and / or with an analog output signal to be generated by the DAC. The DEM circuit may include a first DEM segment. The first DEM segment may be configured to scramble a first one of the sets of thermometer-coded bits, based on the scrambling rate control signal. The DAC circuitry may be configured to generate an analog signal. The DAC circuitry may include a first thermometer-coded DAC segment configured to convert the scrambled thermometer-coded bits of the first one of the sets of thermometer-coded bits to form at least a first component of the analog output signal.

[0013] In some embodiments, the DEM segment may further include at least a second DEM segment configured to scramble a second one of the sets of thermometer-coded bits. The DAC circuitry may include at least a second thermometer-coded DAC segment configured to convert the scrambled thermometer-coded bits of the second one of the sets of thermometer-coded bits to form a second component of the analog output signal. The DAC circuitry may be configured to combine the first and second components to form the analog output signal.

[0014] In some embodiments, the second DEM segment may be configured to scramble the second set of thermometer-coded bits based on a second scrambling rate control signal. The second scrambling rate control signal may differ from the scrambling rate control signal used by the first DEM segment.

[0015] In some embodiments, the first and second sets of thermometer-coded bits may correspond to first and second weights, respectively. The first and second weights may differ from one another. The DAC circuitry may be configured so that the bits of the first and second sets may be represented in the analog output signal according to the respective weights.

[0016] In some embodiments, the first DEM segment may be configured to scramble the first one of the sets of thermometer-coded bits by updating a mapping between the bits of the first one of the sets of thermometer-coded bits as output by the binary-to-thermometer encoder circuitry to input bits to the at least one thermometer-coded DAC segment, at varying intervals. The varying intervals may be based on the scrambling rate control signal. In some embodiments, the DAC circuitry may further include a binary-coded DAC segment configured to convert two or more least-significant bits of the input data words into a least-significant component of the analog output signal. The binary-to-thermometer encoder circuitry may be configured to operate on bits of the input data words other than the two or more least-significant bits.

[0017] In some embodiments, the control signal generation circuit may comprise a random number generator configured to output a random number at a sample clock rate. The control signal generation circuit may be configured to determine a threshold based on the time-varying frequency parameter. The control signal generation circuit may be configured to generate the scrambling rate control signal at the sample clock rate based on a comparison between the random number and the threshold.

[0018] In some embodiments, the time-varying frequency parameter may be indicative of a spectral allocation of the analog output signal to be generated.

[0019] In some embodiments, the time-varying frequency parameter may include one or more of the following: a center frequency of the analog output signal to be generated, and a frequency range of the analog output signal to be generated.

[0020] According to another aspect of the disclosure, a method may convert a stream of input data words to an analog output signal. In the method, binary-to-thermometer encoder circuitry may produce one or more sets of thermometer-coded bits from the stream of input data words. A control signal generation circuit may generate a scrambling rate control signal based at least in part on a time-varying frequency parameter associated with the stream of input data words and / or with the analog output signal to be generated. A first DEM segment of a dynamic element matching (DEM) circuit may scramble a first one of the sets of thermometer-coded bits, based on the scrambling rate control signal. DAC circuitry may generate the analog output signal. For example, a first thermometer-coded DAC segment of the DAC circuity may convert the scrambled thermometer-coded bits of the first one of the sets of thermometer-coded bits to form at least a first component of the analog output signal.

[0021] In some embodiments, at least a second DEM segment of the DEM segment may scramble a second one of the sets of thermometer-coded bits. At least a second thermometer-coded DAC segment of the DAC circuitry may convert the scrambled thermometer-coded bits of the second one of the sets of thermometer-coded bits to form a second component of the analog output signal. The DAC circuitry may combine the first and second components to form the analog output signal.

[0022] In some embodiments, at least the second DEM segment may scramble the second set of thermometer-coded bits based on a second scrambling rate control signal. The second scrambling rate control signal may differ from the scrambling rate control signal used by the first DEM segment.

[0023] In some embodiments, the first and second sets of thermometer-coded bits may correspond to first and second weights, respectively. The first and second weights may differ from one another. When generating the analog output signal, the DAC circuitry may represent the bits of the first and second sets in the analog output signal according to the respective weights.

[0024] In some embodiments, the first DEM segment may scramble the first one of the sets of thermometer-coded bits by updating a mapping between the bits of the first one of the sets of thermometer-coded bits as output by the binary -to-thermometer encoder circuitry to input bits to the at least one thermometer-coded DAC segment, at varying intervals. The varying intervals may be based on the scrambling rate control signal.

[0025] In some embodiments, a binary-coded DAC segment of the DAC circuitry may convert two or more least-significant bits of the input data words into a least-significant component of the analog output signal. When producing the thermometer-coded bits, the binary -to-thermometer encoder circuitry may operate on bits of the input data words other than the two or more leastsignificant bits. In some embodiments, a random number generator of the control signal generation circuit may output a random number at a sample clock rate. The control signal generation circuit may determine a threshold based on the time-varying frequency parameter. The control signal generation circuit may generate the scrambling rate control signal at the sample clock rate based on a comparison between the random number and the threshold.

[0026] In some embodiments, the time-varying frequency parameter may be indicative of a spectral allocation of the analog output signal to be generated.

[0027] In some embodiments, the time-varying frequency parameter may include one or more of the following: a center frequency of the analog output signal to be generated, and a frequency range of the analog output signal to be generated.

[0028] According to yet another aspect of the disclosure, a transmitter may be configured to perform the method described herein.

[0029] Of course, the present invention is not limited to the above features and advantages. Indeed, those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

[0030] BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other objects, features and advantages will be more apparent from the following description of embodiments with reference to the accompanied drawings.

[0032] FIG. 1 is a schematic diagram illustrating a DAC according to one aspect of the technology.

[0033] FIG. 2 is a schematic diagram illustrating the DAC of FIG. 1 interacting with a waveform generator according to one aspect of the technology.

[0034] FIGS. 3A-3F are schematic diagrams of different embodiments of the DAC according to aspects of the technology.

[0035] FIG. 4 is a schematic diagram illustrating use cases of the DAC according to aspects of the technology. FIG. 5 is a flow diagram illustrating a method implemented by the DAC according to one aspect of the technology.

[0036] FIG. 6 A illustrates a spectrum of a supply current and / or voltage of a DAC according to an existing design, when a single tone is generated by the DAC.

[0037] FIG. 6B illustrates a spectrum of a supply current and / or voltage of a DAC according to an existing design, when a two-tone is generated by the DAC.

[0038] FIGS. 7A-C illustrate three examples of spectrums of a supply current and / or voltage of a DAC according to an existing design, with 2 tones being generated at three different center frequencies.

[0039] FIGS. 8A-C illustrate 2ndorder intermodulation distortion (IM2) and DC levels of a supply current and / or voltage of a DAC according to an existing design.

[0040] FIGS. 9A-C illustrate IM2 and DC levels of a supply current and / or voltage of a DAC when a threshold for controlling a DEM scrambling rate is set to zero, according to one aspect of the technology.

[0041] FIGS. 10A-C illustrate IM2 and DC levels of a supply current and / or voltage of a DAC when the threshold for controlling the DEM scrambling rate is set to 0.15, according to one aspect of the technology.

[0042] FIGS. 11A-C illustrate IM2 and DC levels of a supply current and / or voltage of a DAC when the threshold for controlling the DEM scrambling rate is set to 0.3, according to one aspect of the technology.

[0043] FIGS. 12A-C illustrate IM2 and DC levels of a supply current and / or voltage of a DAC when the threshold for controlling the DEM scrambling rate is set to 0.5, according to one aspect of the technology.

[0044] FIGS. 13A-C illustrate IM2 and DC levels of a supply current and / or voltage of a DAC when the threshold for controlling the DEM scrambling rate is set to 0.15, according to one aspect of the technology. DETAILED DESCRIPTION

[0045] Notably, modifications and other embodiments of the disclosed invention(s) will come to mind to one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the invention(s) is / are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of this disclosure. Although specific terms may be employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

[0046] FIG. 1 shows a high-level block diagram of an example DAC 100 for converting a stream of input data words 102 to an analog output signal 104. The DAC 100 may be a voltage mode RF DAC. The DAC 100 may be a resistor-based DAC (R-DAC) or a capacitor-based DAC (C- DAC), among other possibilities. The analog output signal 104 may be a bandpass signal.

[0047] The DAC 100 may include a binary -to-thermometer encoder circuitry 106, a control signal generation circuit 108, a DEM circuit 110 and DAC circuitry 112. The DEM circuit 110 may have a frequency dependent scrambling rate, which may also be referred to as an update rate. The scrambling rate of the DEM 110 may be set based at least in part on a frequency parameter associated with one or more of the following: the stream of input data words 102, and the analog output signal 104 to be generated by the DAC 100. The DAC circuitry 112 may have at least one thermometer-coded DAC segment that operates based on the DEM circuit 110.

[0048] The DEM circuit 110 with the frequency dependent scrambling rate may provide many technical advantages, such as lowering overall nonlinear distortion and / or lowering order of the nonlinear distortion of the analog output signal 104, and decreasing power consumption associated with switching activity in the DAC circuitry. In the event that digital predistortion (DPD) is required for linearization of the DAC, the latter effect may substantially decrease the required complexity of the DPD. Each component of the DAC 100 is discussed in detail below.

[0049] With continued reference to FIG. 1, the binary -to-thermometer encoder circuitry 106 may be configured to produce one or more sets of thermometer-coded bits 114 from the stream of input data words 102. The circuitry 106 may convert each As-bit word of the stream of input data words 102 to an y-bit thermometer-coded data word, wherein Nd= 2Nb— 1.

[0050] The control signal generation circuit 108 may be configured to generate a scrambling rate control signal 116 based at least in part on a time-varying frequency parameter 118.

[0051] The frequency parameter 118 may be associated with at least one of the following: the stream of input data words 102, and the analog output signal 104 to be generated by the DAC 100. In one example, the frequency parameter may include an inherent characteristic of the stream of input data words 102, such as a center frequency or a bandwidth reflected in the stream of input data words 102. In another example, the frequency parameter may be indicative of a spectral allocation of the analog output signal 104 to be generated. For instance, the frequency parameter may include one or more of the following: a center frequency of the analog output signal 104 to be generated, and a frequency range of the analog output signal 104 to be generated.

[0052] The circuit 108 may be configured to determine a threshold A based on the frequency parameter 118. In one example, the circuit 108 may determine a value for the threshold T according to a predetermined mapping between various values of the frequency parameter 118 and various values of the threshold T.

[0053] The circuit 108 may include a random number generator (RNG) 120 configured to output a random number A at a sample clock rate. For example, the random number generator may be triggered by a falling edge or a rising edge of a sample-rate clock 122. The RNG 12 may generate the random number A with uniform distribution over [0 1). The RNG 120 may be beneficial in comparison to a static pattern such as a repeated finite length static pattern or a periodic pattern having a desired average rate, as such patterns may yield undesired tones, spurs or frequency components into the DAC 100. Further, the RNG 120 may serve to dither the DEM scrambling / updating.

[0054] The circuit 108 may be configured to generate the scrambling rate control signal 116 at the sample clock rate based on a comparison 124 between the random number R and the threshold T. For example, the circuit 108 may include an AND operation 126, where the circuit 108 may output the scrambling rate control signal 116 at the sample clock rate when the random number R is greater than the threshold T.

[0055] In some embodiments, the circuit 108 may include one or more segments each configured to generate a respective scrambling rate control signal, for application to respective segments of the DEM circuit 110. Each segment may operate independently of other segments. The RNG 120 may generate a different random sequence for each segment, by using, for example, a different initial seed or a different configuration. In one example, a first segment may generate a first scrambling rate control signal. A second segment may generate a second scrambling rate control signal. The first scrambling rate control signal may be different from the second scrambling rate control signal.

[0056] The DEM circuit 110 may scramble the thermometer-coded bits 114 output by the binary - to-thermometer encoder circuitry 106 based on the scrambling rate control signal 116, and output the scrambled thermometer-coded bits 128 to the DAC circuitry 112.

[0057] The DEM circuit 110 may include one or more DEM segments. Each DEM segment may be configured to scramble a set of thermometer-coded bits 114, and output the scrambled set of thermometer-coded bits 128 to one or more corresponding thermometer-coded DAC segments in the DAC circuitry 112. When performing scrambling, each DEM segment may update a mapping between the set of thermometer-coded bits 114 and input bits to at least one DAC segment. Updating the mapping may also be referred to as performing a remapping. The remapping may be memoryless in the sense that the remapping does not depend on previous inputs to nor on previous outputs from the DEM circuit 110. The DEM segment may be driven by the scrambling rate control signal 116 to generate a new mapping between the set of thermometer-coded bits 114 and the input bits to at least one DAC segment.

[0058] In one example, a first DEM segment may be configured to scramble a first set of thermometer-coded bits 114, and output the scrambled first set of thermometer-coded bits to one or more corresponding thermometer-coded DAC segments of the DAC circuitry 112. When performing the scrambling, the first DEM segment may update a mapping between the bits of the first set of thermometer-coded bits 114 as output by the binary -to-thermometer encoder circuitry 106 and input bits to one or more thermometer-coded DAC segments. The first DEM segment may perform the update at varying intervals. The varying intervals may be based on the scrambling rate control signal 116.

[0059] In another example, a second DEM segment may be configured to scramble a second set of thermometer-coded bits, based on a second scrambling rate control signal. The second scrambling rate control signal may be identical to the scrambling rate control signal used by the first DEM segment. Alternatively, the second scrambling rate control signal may differ from the scrambling rate control signal used by the first DEM segment.

[0060] The scrambling rate control signal 116 controls the average scrambling rate of the DEM circuit 110. Due to the scrambling rate control signal 116, the average scrambling rate of the DEM circuit 110 over any given interval depends on the frequency parameter 118. Because the frequency parameter 118 changes over time, e.g., as the frequency content of the input signal changes, the average scrambling rate of the DEM circuit 110 will also vary.

[0061] In general, the DEM circuit 110 will have an average scrambling rate different from the sample rate fsof the input data words 102. The average scrambling rate fdemof the DEM circuit 110 may be determined based on the following formula, fdem= fs( ~ T), where T as discussed earlier is the threshold computed by the control signal generation circuit 108. Higher average scrambling rates may be more effective at spreading spurious signals created by circuit nonlinearities. Note that it is possible for the average scrambling rate at which the DEM performs scrambling to be higher than the sample rate of the input data words 102. In this case, the DEM circuit of the DAC 100 may operate, for example, at a multiple of the sample rate fsof the input data words 102, so that the DEM scrambling can be updated multiple times for each input sample, subject to the scrambling rate control signal 116. In these embodiments, the control signal generation circuit 108 and the DAC circuitry 112 must operate at this multiple of the sample rate fsas well.

[0062] The DAC circuitry 112 may have one or more DAC segments, outputs of which are combined to form a composite DAC output signal, namely, the analog output signal 104.

[0063] In some embodiments, the DAC circuitry 112 may include only one DAC segment. The analog signal generated by that DAC segment may be regarded as the analog output signal 104 output by the DAC 100.

[0064] In another embodiment, the DAC circuitry 112 may include a plurality of DAC segments. The DAC segments may include one or more of the following, a MSB segment, an ISB segment, and an LSB segment, among other possibilities. Each DAC segment may include one or more subsets of cells within the DAC circuitry 112. The DAC segments may be physically distinct from each other, such that cells associated with different DAC segments may be separate from each other. Alternatively, the DAC segments may have at least partially overlapping subsets of cells.

[0065] Each DAC segment may be configured to generate a component of the analog output signal 104. The circuitry 112 may generate the analog output signal 104 by combining components of the analog output signals 104 generated by all DAC segments, by using one or more summers.

[0066] In some embodiments, each segment may be associated with a weight. For instance, n DAC segments may have weights wo, wi, W2, . . . wn-i, respectively. The weights for the DAC segments may be different or identical. To generate the analog output signal 104, the DAC circuitry 112 may combine outputs of all DAC segments, in which case differences in the weights for different DAC segments are automatically reflected in the combined output. In some embodiments, at least one DAC segment may be a thermometer-coded DAC segment. At least one thermometer-coded DAC segment may receive the scrambled thermometer- coded bits 122 from the DEM circuit 110.

[0067] In some embodiments, the DAC circuitry 112 may include one or more binary-coded DAC segments. At least one binary-coded DAC segment may be configured to convert two or more least-significant bits of the input data words into a least-significant component of the analog output signal. In this case, the binary-to-thermometer encoder circuitry 106 may be configured to operate on bits of the input data words other than the two or more least-significant bits.

[0068] In one example, the DAC circuitry 112 may include a first thermometer-coded DAC segment configured to convert the scrambled thermometer-coded bits of the first set of thermometer-coded bits to at least a first component of the analog output signal. In another example, the DAC circuitry 112 may further include at least a second thermometer-coded DAC segment configured to convert the scrambled thermometer-coded bits of the second set of thermometer-coded bits to form a second component of the analog output signal 104. The DAC circuitry 112 may be configured to combine the first and second components to form the analog output signal 104. The first and second sets of thermometer-coded bits may correspond to first and second weights, respectively. The first and second weights may differ from one another. The bits of the first and second sets may be represented in the analog output signal 104 according to the respective weights.

[0069] Referring to FIG. 2, in some embodiments the stream of input data words 102 may represent a modulated RF signal generated by a waveform generator 202. The waveform generator 202 may receive the frequency parameter 118 as an input. In one example, the frequency parameter 118 may be a center frequency of the RF signal to be generated, or another parameter indicative of the RF signal spectral allocation. The waveform generator 202 may generate the modulated RF signal at a sample rate fs. The DAC 100 may convert the modulated RF signal to the analog output signal 104. For instance, the binary -to-thermometer encoder circuitry 106 may encode the modulated RF signal to a thermometer code. The DEM circuit 110 may subsequently scramble the thermometer code and feed the scrambled thermometer code to the DAC circuitry 112. The DAC circuitry 112 may then produce the analog output signal 104.

[0070] In some embodiments of the DAC as illustrated in FIG. 3 A, all DAC segments 112a-c, including the MSB segment 112a, the ISB segment 112b and the LSB segment 112c, may be individually thermometer-coded. Each thermometer-coded DAC segment may correspond to a DEM segment in the DEM circuit 110. The binary -to-thermometer encoder circuitry 106 may output a plurality sets of thermometer-coded bits 114 to a plurality of DEM segments 110a, 110b and 110c of the DEM circuit 110, e.g., a first set of thermometer-coded bits to a first DEM segment 110a, a second set of thermometer-coded bits to a second DEM segment 110b, and a third set of thermometer-coded bits to a third DEM segment 110c. The control signal generation circuit 108 may output the same scrambling rate control signal 116 to all DEM segments 1 lOa-c. Each DEM segment may scramble its respective set of thermometer-coded bits, and output the scrambled thermometer-coded bits to a corresponding DAC segment. For instance, the first DEM segment 110a may output scrambled thermometer-coded bits 128a to a MSB segment 112a. Similarly, the second DEM segment 110b may output scrambled thermometer-coded bits 128b to an ISB segment 112b. The third DEM segment 110c may output scrambled thermometer-coded bits 128c to an LSB segment 112c. One or more summers 302 may combine outputs from the MSB segment 112a, the ISB segment 112b and the LSB segment 112c to produce the analog output signal 104.

[0071] FIG. 3B illustrates another embodiment of the DAC, which is similar to the embodiment illustrated in FIG. 3 A except that the control signal generation circuit 108 may include one or more control signal generation segments. For example, the control signal generation circuit 108 may include control signal generation segments 108a, 108b and 108c configured to output scrambling rate control signals 116a, 116b and 116c to different DEM segments 110a, 110b and 110c, respectively. For example, a first control signal generation circuit 108a may output a first scrambling rate control signal 116a to a first DEM segment 110a. A second control signal generation circuit 108b may output a second scrambling rate control signal 116b to a second DEM segment 110b. A third control signal generation circuit 108c may output a third scrambling rate control signal 116c to a third DEM segment 110c. Each DEM segment HOa-c may perform scrambling based on its respective scrambling rate control signal, and output respective scrambled thermometer-coded bits 128a-c to respective DAC segments 112a-c.

[0072] FIG. 3C illustrates a further embodiment of the DAC, where one DAC segment may be thermometer-coded while remaining DAC segments may not be thermometer-coded. For example, the MSB segment 112a may be a thermometer-coded DAC segment, while the ISB segment 112b and the LSB segment 112c may be binary-coded. The binary-to-thermometer encoder circuitry 106 may operate on bits of the input data words 102 other than the four or more least-significant bits. The four or more least-significant bits of the input data words 102 may be provided to the ISB segment 112b and the LSB segment 112c. The DEM circuit 110 may include a DEM segment 110a that scrambles the thermometer-coded bits 114 provided by the binary-to-thermometer encoder circuit 106, and output scrambled thermometer-coded bits 128 to the MSB segment 112a. Outputs of the MSB segment 112a, the ISB segment 112b and the LSB segment 112c may be summed by one or more summers 302 to produce the analog output signal 104.

[0073] FIG. 3D illustrates another embodiment of the DAC, where multiple DAC segments may be thermometer-coded, while at least one remaining DAC segment may not be thermometer coded. For example, the MSB segment 112a and the ISB segment 112b may be thermometer-coded, and the LSB segment 112c may be binary-coded. In particular, the MSB segment 112a may be 5-bit thermometer-coded, the ISB segment 112b may be 3 -bit thermometer-coded, and the LSB segment 112c may be 4-bit binary-coded. In this example, the binary-to-thermometer encoder circuitry 106 may operate on bits of the input data words 102 other than the four least-significant bits. The four least-significant bits of the input data words 102 may be provided to the LSB segment 112c. The DEM circuit 110 may include DEM segments 110a and 110b that scramble the thermometer- coded bits 114 provided by the binary -to-thermometer encoder circuit 106, and output scrambled thermometer-coded bits 128a and 128b to the MSB segment 112a and the ISB segment 112b, respectively. Outputs of the MSB segment, the ISB segment 112 and the LSB segment 112 may be summed by one or more summers 302 to produce the analog output signal 104.

[0074] FIG. 3E illustrates yet another embodiment of the DAC, in which the binary-to- thermometer encoder circuitry 106 may include a plurality of binary -to-thermometer encoder segments 106a-c. Each encoder segment may output a set of thermometer-coded data bits to one or more corresponding DEM segments. For example, the first encoder segment 106a may output a first set of thermometer-coded data bits 114a to a first DEM segment 110a. The second encoder segment 106b may output a second set of thermometer-coded data bits 114b to a second DEM segment 110b. The third encoder segment 106c may output a third set of thermometer-coded data bits 114c to a third DEM segment 110c. The control signal generation circuit 108 may output the same scrambling rate control signal 116 to all DEM segments 110a, 110b and 110c. The DEM segments 110a, 110b and 110c may output scrambled thermometer-code bits 128a, 128b and 128c to the MSB segment 112a, the ISB segment 112b, and the LSB segment 112, respectively. One or more summers 302 may combine outputs of the MSB segment 112a, the ISB segment 112 and the LSB segment 112c to generate the analog output signal 104.

[0075] FIG. 3F illustrates another embodiment of the DAC, where one DAC segment may not be thermometer-coded, while remaining DAC segments are thermometer-coded. For example, the LSB segment 112 may be binary-coded, whereas the MSB and ISB segments 112a-b may be thermometer-coded. The binary -to-thermometer encoder circuitry 106 may include binary -to- thermometer encoder segments 106a and 106b operate on bits of the input data words 102 other than the two or more least-significant bits. The two or more least-significant bits of the input data words 102 may be provided to the LSB segment 112c. The binary -to-thermometer encoder segments 106a and 106b may output thermometer-coded data bits 114a and 114b to DEM segments 110a and 110b, respectively. The DEM segments 110a and 110b may output scrambled thermometer-coded bits 128a and 128b to the MSB segment 112a and the ISB segment 112b, respectively. One or more summers 302 may combine outputs of the MSB segment 112a, the ISB segment 112b and the LSB segment 112c to generate the analog output signal 104.

[0076] Referring to FIG. 4, the DAC 100 described herein may be part of a transmitter, which forms part of a base station or a wireless device to facilitate communications over a network 400. The network 400 may implement any suitable communication standard, such as new radio (NR), Long Term Evolution (LTE), LTE-Advanced (LTE-A), Wideband Code Division Multiple Access (WCDMA), and High-Speed Packet Access (HSPA). Furthermore, communications within the network may be performed according to any suitable generation communication protocols, including, but not limited to, Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), Long Term Evolution (LTE), and / or other suitable 1G (the First Generation), 2G (the Second Generation), 2.5G, 2.75G, 3G (the Third Generation), 4G (the Fourth Generation), 4.5G, 5G (the Fifth Generation) communication protocols, wireless local area network (WLAN) standards, such as the IEEE 802.11 standards; and / or any other appropriate wireless communication standard, such as the Worldwide Interoperability for Microwave Access (WiMax), Bluetooth, and / or ZigBee standards, and / or any other protocols either currently known or to be developed in the future.

[0077] In some embodiments, the DAC may be part of a transmitter 402 within a base station 404. The base station 404 may be a wireless network node, such as a Node B (NodeB or NB), an evolved NodeB (eNodeB or eNB), or gNodeB (gNB), a Remote Radio Unit (RRU), a Radio Header (RH), a Remote Radio Head (RRH), a relay and a low power node such as a femto, and a pico.

[0078] In another embodiment, the DAC may be part of a transmitter 406 within a wireless device 408. The wireless device 408 may be a terminal device, such as a mobile terminal, user equipment (UE), or other suitable devices. The UE may refer to any end device that can access a wireless communication network and receive services therefrom. By way of example and not limitation, the UE may refer to a mobile terminal or other suitable user devices. The UE may be, for example, a Subscriber Station (SS), a Portable Subscriber Station, a Mobile Station (MS), or an Access Terminal (AT). The UE may include, but not limited to, portable computers, image capture terminal devices such as digital cameras, gaming terminal devices, music storage and playback appliances, a mobile phone, a cellular phone, a smart phone, voice over IP (VoIP) phones, wireless local loop phones, a tablet, a wearable device, a personal digital assistant (PDA), portable computers, desktop computer, image capture terminal devices such as digital cameras, gaming terminal devices, music storage and playback appliances, wearable terminal devices, vehiclemounted wireless terminal devices, wireless endpoints, mobile stations, laptop-embedded equipment (LEE), laptop-mounted equipment (LME), USB dongles, smart devices, wireless customer-premises equipment (CPE) and the like.

[0079] FIG. 5 illustrates a process for converting a stream of input data words to an analog output signal. At 502, the binary -to-thermometer encoder circuitry may produce one or more sets of thermometer-coded bits from the stream of input data words. At 504, the control signal generation circuit may generate a scrambling rate control signal based at least in part on a time-varying frequency parameter associated with the stream of input data words and / or with an analog output signal to be generated. At 506, a first DEM segment of the dynamic element matching (DEM) circuit may scramble a first one of the sets of thermometer-coded bits, based on the scrambling rate control signal. At 508, the DAC circuitry may generate the analog output signal. A first thermometer-coded DAC segment of the DAC circuity may convert the scrambled thermometer- coded bits of the first one of the sets of thermometer-coded bits to form at least a first component of the analog output signal.

[0080] In some embodiments, the DEM segment may include at least a second DEM segment. The DAC circuitry may include at least a second thermometer-coded DAC segment. The second DEM segment may scramble a second one of the sets of thermometer-coded bits. The second thermometer-coded DAC segment may convert the scrambled thermometer-coded bits of the second one of the sets of thermometer-coded bits to form a second component of the analog output signal. The DAC circuitry may combine the first and second components to form the analog output signal.

[0081] In some embodiments, the control signal generation circuit may generate a second scrambling rate control signal that is different from the scrambling rate control signal used by the first DEM segment. The second DEM segment may scramble the second set of thermometer-coded bits based on the second scrambling rate control signal.

[0082] In some embodiments, the first and second sets of thermometer-coded bits may correspond to first and second weights, respectively. The first and second weights may differ from one another. When generating the analog signal, the DAC circuity may represent the bits of the first and second sets in the analog output signal according to the respective weights.

[0083] In some embodiments, the first DEM segment may scramble the first one of the sets of thermometer-coded bits by updating a mapping between the bits of the first one of the sets of thermometer-coded bits as output by the binary -to-thermometer encoder circuitry to input bits to the at least one thermometer-coded DAC segment, at varying intervals. The varying intervals may be based on the scrambling rate control signal.

[0084] In some embodiments, the DAC circuitry may include a binary-coded DAC segment. The binary-coded DAC segment may convert two or more least-significant bits of the input data words into a least-significant component of the analog output signal. When producing the sets of thermometer-coded bits from the stream of input data words, the binary -to-thermometer encoder circuitry may operate on bits of the input data words other than the two or more least-significant bits.

[0085] In some embodiments, the control signal generation circuit may include a random number generator. The random number generator may output a random number at a sample clock rate. The control signal generation circuit may determine a threshold based on the time-varying frequency parameter. The control signal generation circuit may generate the scrambling rate control signal at the sample clock rate based on a comparison between the random number and the threshold.

[0086] In some embodiments, the time-varying frequency parameter may be indicative of a spectral allocation of the analog output signal to be generated.

[0087] In some embodiments, the time-varying frequency parameter may include one or more of the following: a center frequency of the analog output signal to be generated, and a frequency range of the analog output signal to be generated.

[0088] In some embodiments, a transmitter may be configured to perform any of the methods described herein.

[0089] FIG. 6 A shows a spectrum of a power supply current and / or voltage to a DAC of an example design, when a single tone is generated by the DAC at 4.517 GHz and with a level of 0 dBFS. It is clearly seen that without DEM, the spectrum of the supply current and / or voltage is very rich with even order harmonics as well non-harmonic components. With DEM on the other hand, all even harmonics but 2ndorder harmonic distortion (H2) are gone. H2 is, however, lower than without DEM. The DC level may indicate a mean power consumption or an average current consumption of the DAC related to switching. As shown in FIG. 6A, the DC level is higher with DEM, indicating a higher average current consumption. Except for a small residue of the fundamental frequency (Hl), there is only flat noise. The DACs featured in FIG. 6A and subsequent figures FIGS. 6B-13C have a sampling rate of 10GHz.

[0090] FIG. 6B shows the spectrum of the supply current and / or voltage when a two-tone output is generated by a DAC of an existing design, at 1.281 GHz and 1.481 GHz, respectively, with 9dB backoff from full scale per tone. Similar to the single-tone case, there is plenty of even order distortion without DEM, while even-order intermodulation products are much suppressed when DEM is introduced, leaving essentially only the second order products (e.g., H2, IM2) and some residue of the fundamental frequencies. The DC component is substantially higher for DEM. The inventors have found that the spectrum of the supply current and / or voltage, and more importantly, the level of second order distortion IM2 when using DEM is strongly dependent on the frequencies being generated by the DAC, regardless whether it is a 1-tone, 2-tone, or multitone at different levels. FIGS. 7A-7C illustrate three examples with 2 tones 200MHz apart for three different center frequencies. FIG. 7A illustrates a first example when the two tones are generated at 1.281 GHz and 1.481 GHz, respectively, and -9 dBFS each. FIG. 7B illustrates a second example when the two tones are generated at 2.281 GHz and 2.481 GHz, respectively, and -9 dBFS each. FIG. 7C illustrates a third example when the two tones are generated at 3.281 GHz and 3.481 GHz, respectively, and -9 dBFS each. As shown in FIGS. 7A-C, the levels of IM2 near DC (f2-f 1) vary when compared with the other IM2 (and H2) at higher frequencies. While IM2 at higher frequencies (f2+f 1 ) are easier to filter out, the same cannot be said about the lower IM2 and this component will mix with the desired signal due to the supply modulation. Accordingly, IM2 at lower frequencies (f2-fl) is more important than IM2 at higher frequencies (f2+fl), because when it modulates the DAC supply current and / or voltage, the net effect will be a multiplication of IM2 and the DAC input signal which then translates to third order intermodulation distortion (IM3) distortion around the carrier of interest.

[0091] FIGS. 8A-C illustrates IM2 (f2-f 1), IM2 (f2+f 1) and DC levels of a supply and / or voltage to an existing DAC, with and without DEM, as a function of center frequency for a two-tone signal, each tone at -6 dBFS. As shown in FIG. 8B, the dependency on center frequency becomes very clear with a deep dip for the lower IM2 when the center frequency is around 2.5 GHz.

[0092] The present disclosure improves the DEM with a frequency dependent scrambling rate, z.e., a scrambling control signal that depends in some way on the frequency content of the input or output signals, so that the scrambling rate / control signal varies according to that frequency content, rather than according to a statically defined scrambling pattern, the DAC of the present disclosure achieves a reduced overall nonlinear distortion.

[0093] FIGS. 9A-13C illustrate IM2 and DC levels of a supply current (and hence the supply voltage) of the DAC of the present disclosure for different settings of the threshold T. As discussed earlier, the threshold T may affect the scrambling rate control signal. Each figure illustrates two plots, a plot without DEM, and a plot with DEM. Since DEM changes the activity pattern, the supply current and / or voltage may have different spectral contents depending on the scrambling rate control signal. For illustration purposes only, the threshold T used for generating these figures is a function of a center frequency fcfor a two-tone signal, each tone at -6 dBFS.

[0094] FIGS. 9A-9C are a first set of figures that illustrates IM2 and DC levels when the threshold T is set to zero, such that the DEM scrambling rate equals to the sample rate fs. FIGS. 10A-10C are a second set of figures that illustrates IM2 and DC levels when the threshold T is set to 0.15, yielding an average DEM scrambling rate of 0.85^. FIGS. 11 A-l 1C are a third set of figures that illustrates IM2 and DC levels when the threshold T is set to 0.3, yielding an average DEM scrambling rate of 0.7^. FIGS. 12A-12C are a fourth set of figures that illustrates IM2 and DC levels when the threshold Zis set to 0.5, yielding an average DEM scrambling rate of 0.5fs. FIGS. 13A-13C are a fifth set of figures that illustrate IM2 and DC levels when the threshold T is set to 0.15, yielding an average DEM scrambling rate of 0.85 ■ 2fs, with the core of the DAC operating at 2fswhile input data sample rate is fs. In FIGS. 13A-13C, the DEM scrambling rate is higher than the input data sample rate fs, while the core of the DAC operates at a speed corresponds to a maximum targeted DEM scrambling rate.

[0095] In each set of figures, the first figure, e.g., FIGS. 9A, 10A, 11 A, 12A or 13A, illustrates a comparison of DC levels with and without DEM. The second figure in each set, e.g., FIGS. 9B, 10B, 1 IB, 12B or 13B, illustrates a comparison of levels of IM2 at lower frequencies (f2-f 1) with and without DEM. The third figure in each set, e.g., FIGS. 9C, 10C, 11C, 12C or 13C, illustrates a comparison of levels of IM2 at higher frequencies (f2+fl) with and without DEM.

[0096] As shown in these figures, IM2 levels at lower frequencies (f2-f 1) become very low with a correct setting of the threshold T in relation to the frequency of the signal being generated. The IM2 at higher frequencies (f2+f 1 ) stays at roughly the same level as with DEM at full scrambling rate, while the IM2 at lower frequencies (f2-f 1 ) is suppressed. Accordingly, by using a DEM with a frequency dependent scrambling rate, IM2 at lower frequencies (f2-fl) is minimized, without a detrimental effect on IM2 at higher frequencies (f2+fl ).

[0097] In general, the various exemplary embodiments may be implemented in hardware or special purpose chips, circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the disclosure is not limited thereto. While various aspects of the exemplary embodiments of this disclosure may be illustrated and described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that these blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

[0098] Various modifications and adaptations to the foregoing exemplary embodiments of this disclosure may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings. However, any and all modifications will still fall within the scope of the non-limiting and exemplary embodiments of this disclosure.

Claims

CLAIMSWhat is claimed is:

1. A digital-to-analog converter (DAC), comprising: binary-to-thermometer encoder circuitry configured to produce one or more sets of thermometer-coded bits from a stream of input data words; a control signal generation circuit configured to generate a scrambling rate control signal based at least in part on a time-varying frequency parameter associated with the stream of input data words and / or with an analog output signal to be generated by the DAC; a dynamic element matching (DEM) circuit including a first DEM segment, the first DEM segment being configured to scramble a first one of the sets of thermometer-coded bits, based on the scrambling rate control signal; andDAC circuitry configured to generate an analog signal, the DAC circuitry including a first thermometer-coded DAC segment configured to convert the scrambled thermometer-coded bits of the first one of the sets of thermometer-coded bits to form at least a first component of the analog output signal.

2. The DAC of claim 1, wherein: the DEM segment further includes at least a second DEM segment configured to scramble a second one of the sets of thermometer-coded bits; the DAC circuitry further includes at least a second thermometer-coded DAC segment configured to convert the scrambled thermometer-coded bits of the second one of the sets of thermometer-coded bits to form a second component of the analog output signal; and the DAC circuitry is configured to combine the first and second components to form the analog output signal.

3. The DAC of claim 2, wherein the second DEM segment is configured to scramble the second set of thermometer-coded bits based on a second scrambling rate control signal, the second scrambling rate control signal differing from the scrambling rate control signal used by the first DEM segment.

4. The DAC of any one of the preceding claims, wherein the first and second sets of thermometer- coded bits correspond to first and second weights, respectively, the first and second weights differing from one another and the DAC circuitry being configured so that the bits of the first and second sets are represented in the analog output signal according to the respective weights.

5. The DAC of any one of the preceding claims, wherein the first DEM segment is configured to scramble the first one of the sets of thermometer-coded bits by updating a mapping between the bits of the first one of the sets of thermometer-coded bits as output by the binary -to-thermometer encoder circuitry to input bits to the at least one thermometer-coded DAC segment, at varying intervals, wherein the varying intervals are based on the scrambling rate control signal.

6. The DAC of any one of the preceding claims, wherein the DAC circuitry further incudes a binary-coded DAC segment configured to convert two or more least-significant bits of the input data words into a least-significant component of the analog output signal, and wherein the binary -to-thermometer encoder circuitry is configured to operate on bits of the input data words other than the two or more least-significant bits.

7. The DAC of any of the preceding claims, wherein the control signal generation circuit comprises a random number generator configured to output a random number at a sample clock rate, wherein the control signal generation circuit is configured to determine a threshold based on the time-varying frequency parameter; andwherein the control signal generation circuit is configured to generate the scrambling rate control signal at the sample clock rate based on a comparison between the random number and the threshold.

8. The DAC of any of the preceding claims, wherein the time-varying frequency parameter is indicative of a spectral allocation of the analog output signal to be generated.

9. The DAC of any of the preceding claims, wherein the time-varying frequency parameter includes one or more of the following: a center frequency of the analog output signal to be generated, and a frequency range of the analog output signal to be generated.

10. A method for converting a stream of input data words to an analog output signal, comprising: producing, by binary -to-thermometer encoder circuitry, one or more sets of thermometer- coded bits from the stream of input data words; generating, by a control signal generation circuit, a scrambling rate control signal based at least in part on a time-varying frequency parameter associated with the stream of input data words and / or with the analog output signal to be generated; scrambling, by a first DEM segment of a dynamic element matching (DEM) circuit, a first one of the sets of thermometer-coded bits, based on the scrambling rate control signal; and generating, by DAC circuitry, the analog output signal, including: converting, by a first thermometer-coded DAC segment of the DAC circuity, the scrambled thermometer-coded bits of the first one of the sets of thermometer-coded bits to form at least a first component of the analog output signal.

11. The method of claim 10, wherein the scrambling includes scrambling, by at least a secondDEM segment of the DEM segment, a second one of the sets of thermometer-coded bits; andwherein the generating the analog output signal includes: converting, by at least a second thermometer-coded DAC segment of the DAC circuitry, the scrambled thermometer-coded bits of the second one of the sets of thermometer-coded bits to form a second component of the analog output signal; and combining, by the DAC circuitry, the first and second components to form the analog output signal.

12. The method of claim 11, wherein the scrambling by at least the second DEM segment includes: scrambling the second set of thermometer-coded bits based on a second scrambling rate control signal, the second scrambling rate control signal differing from the scrambling rate control signal used by the first DEM segment.

13. The method of any one of claims 10-12, wherein the first and second sets of thermometer- coded bits correspond to first and second weights, respectively, the first and second weights differing from one another; and wherein the generating the analog output signal includes representing the bits of the first and second sets in the analog output signal according to the respective weights.

14. The method of any one of claims 10-13, wherein the scrambling includes: scrambling, by the first DEM segment, the first one of the sets of thermometer-coded bits by updating a mapping between the bits of the first one of the sets of thermometer-coded bits as output by the binary -to-thermometer encoder circuitry to input bits to the at least one thermometer- coded DAC segment, at varying intervals, wherein the varying intervals are based on the scrambling rate control signal.

15. The method of any one of claims 10-14, wherein the generating the analog output signal includes: converting, by a binary-coded DAC segment of the DAC circuitry, two or more leastsignificant bits of the input data words into a least-significant component of the analog output signal, and wherein the producing includes operating, by the binary-to-thermometer encoder circuitry, on bits of the input data words other than the two or more least-significant bits.

16. The method of any one of claims 10-15, wherein the generating the scrambling rate control signal includes: outputting, by a random number generator of the control signal generation circuit, a random number at a sample clock rate. determining, by the control signal generation circuit, a threshold based on the time-varying frequency parameter; and generating, by the control signal generation circuit, the scrambling rate control signal at the sample clock rate based on a comparison between the random number and the threshold.

17. The method of any one of claims 10-16, wherein the time-varying frequency parameter is indicative of a spectral allocation of the analog output signal to be generated.

18. The method of any one of claims 10-17, wherein the time-varying frequency parameter includes one or more of the following: a center frequency of the analog output signal to be generated, and a frequency range of the analog output signal to be generated.

19. A transmitter configured to perform the method of any one of claims 10-18.

Images