Semiconductor device having memory element, and method for manufacturing same

Abstract

According to the present invention, a first mask material layer formed by self-alignment and a second mask material layer formed on both sides of the first mask material layer are used to form all elements constituting a memory cell, i.e., a P-layer semiconductor pillar 15, a first gate insulating layer 21, a first gate conductor layer 22, a second gate insulating layer 34, a second gate conductor layer 35, N layers 18a, 27a, 27b, and N+ layers 30a, 30b, by self-alignment.

Description

Semiconductor device having memory element and manufacturing method thereof

[0001] The present invention relates to a semiconductor device having a memory element and a manufacturing method thereof.

[0002] 2. Description of the Related Art In recent years, with the development of LSI (Large Scale Integration) technology, there has been a demand for higher integration, higher performance, lower power consumption, and higher functionality in semiconductor devices including memory elements.

[0003] Compared to planar MOS transistors, SGTs enable higher density semiconductor devices. Using SGTs as select transistors, high integration is possible for DRAMs (Dynamic Random Access Memory, see, for example, Non-Patent Document 1) connected to a capacitor, PCMs (Phase Change Memory, see, for example, Non-Patent Document 2) connected to a resistance change element, RRAMs (Resistive Random Access Memory, see, for example, Non-Patent Document 3), and MRAMs (Magneto-Resistive Random Access Memory, see, for example, Non-Patent Document 4) that change resistance by changing the direction of magnetic spins using current. Other examples include DRAM memory cells that do not have a capacitor but are composed of a single MOS transistor (see, for example, Non-Patent Document 5), and DRAM memory cells that have a carrier-accumulating groove and two gate electrodes (see, for example, Non-Patent Document 6). However, DRAMs without capacitors have a problem of insufficient voltage margin due to significant influence of gate electrode coupling from the floating body word line. In contrast to this, there is a memory element that has a second channel connected to the first channel of a MOS transistor, this second channel is surrounded by a gate insulating layer and a gate conductor layer, and has an impurity region on the opposite side of the second channel from the first channel side (see Patent Document 1).

[0004] The operation of the memory cell shown in Patent Document 1 will be explained using Figures 4A to 4C. Figure 4A shows the vertical cross-sectional structure of the memory cell. An N layer 102 containing donor impurities is on a P layer 101 (hereinafter, the semiconductor region containing donor impurities will be referred to as the "N layer"). A columnar P layer 103a containing acceptor impurities is on top of the N layer 102. A P layer 103b is on top of the P layer 103a. A first gate insulating layer 105 is in contact with the columnar side surface of the P layer 103a. A first gate conductor layer 106 is in contact with the outer side surface of the first gate insulating layer 105. A first insulating layer 104 is between the N layer 102 and the gate conductor layer 106. A second insulating layer 108 is on the first gate insulating layer 105 and the first gate conductor layer 106. An N layer 103a containing high concentration donor impurities is on both sides of the P layer 103b in the X-X' direction. + Layer 111a and N + There is a layer 111b. + Layer 111a and N + A second gate insulating layer 109 is disposed on top of the P layer 103b between the first and second gate insulating layers 109 and 111b. A second gate conductor layer 110 is disposed on top of the second gate insulating layer 109.

[0005] N + The layer 111a is connected to the source line SL, and + The layer 111b is connected to the bit line BL, the gate conductor layer 110 is connected to the word line WL, the gate conductor layer 106 is connected to the plate line PL, and the N layer 102 is connected to the control line CDC. The memory operates by manipulating the potentials of the source line SL, bit line BL, plate line PL, and word line WL. In an actual memory device, a large number of the above-mentioned memory cells are arranged two-dimensionally on the P layer 101.

[0006] 4B(a), (b), and (c) will be used to explain the write operation of the memory cell. In FIG. 4B(a), 0 V is applied to the P layer 101, and N + 0V is input to layer 111a, and N +A voltage of 3 V is input to the layer 111b, 0 V to the first gate conductor layer 6, and 1.5 V to the second gate conductor layer 10 connected to the word line WL. A partial inversion layer 112 is formed in the P layer 103b directly below the gate insulating layer 109 below the gate conductor layer 110, and a pinch-off point 113 exists. In this case, the MOS transistor having the second gate conductor layer 110 operates in the saturation region.

[0007] As a result, the pinch-off point 113 and N + The electric field is maximized between the layers 111b and 111c, and impact ionization occurs in this region. + Layers 111a to N + The electrons accelerated toward the layer 111b collide with the Si lattice, and the kinetic energy generates electron-hole pairs. The generated holes 114a diffuse toward the lower hole concentration due to the concentration gradient. The electrons are N + Instead of causing the impact ionization phenomenon, the hole group 114a may be generated by passing a gate-induced drain leakage (GIDL) current (see, for example, Non-Patent Document 7).

[0008] As shown in FIG. 4B(b), immediately after writing, the word line WL, bit line BL, plate line PL, and source line SL are set to, for example, 0 V, causing holes 114b to accumulate in the P layer 103a. As a result, the hole concentration in the P layer 103a becomes higher than that in the P layer 103b. Because the P layer 103a and the P layer 103b are electrically connected, the P layer 103a, which is essentially the substrate of the MOS transistor having the gate conductor layer 110, is charged with a positive bias. The threshold voltage of the MOS transistor having the second gate conductor layer 110 is lowered by the positive substrate bias effect caused by the holes 114b accumulated in the P layer 103a. As a result, the threshold voltage of the MOS transistor having the second gate conductor layer 110 connected to the word line WL is lowered, as shown in FIG. 4B(c).

[0009] Next, the erase operation mechanism will be explained using Figures 4C(a), (b), and (c). As shown in Figure 4C(a), before the erase operation, the hole group 114b generated and accumulated by impact ionization is stored mainly in the P layer 103a. Then, during the erase operation, for example, the voltage of the source line SL is set to -0.5V and the plate line PL is set to 2V. As a result, regardless of the value of the initial potential of the P layer 103a, the N + As a result, as shown in FIG. 4C(b), a group of holes 114b, which were generated by impact ionization in the previous cycle and stored mainly in the P layer 103a, are transferred to the N + The electrons move to the layer 111a. Furthermore, when a voltage of 2V is applied to the plate line PL, an inversion layer 116 is formed at the interface between the first gate insulating layer 105 and the P layer 103a, which contacts the N layer 102. As a result, the holes 114b accumulated in the P layer 103a flow from the P layer 103a to the N layer 102 and the inversion layer 116, where they recombine with electrons. As a result, the hole concentration in the P layer 103a decreases over time, and the threshold voltage of the MOSFET becomes higher than when "1" was written, returning to its initial state. As a result, as shown in FIG. 4C(c), the MOSFET having the gate conductor layer 110 connected to this word line WL returns to its initial threshold. The erased state of this memory corresponds to logically stored data "0."

[0010] In the memory cell shown in FIGS. 4A to 4C, the components of the N layer 102, the P layers 103a and 103b, the first gate insulating layer 105, the first gate conductor layer 106, the second gate insulating layer 109, the first gate conductor layer 110, the N + There is a demand for higher precision and density in the formation of the layers 111a and 111b, as well as lower costs through simplified processes.

[0011] US2023 / 0077140 / A1

[0012] H. Chung, H. Kim, H. Kim, K. Kim, S. Kim, K.W. Song, J. Kim, Y.C. Oh, Y. Hwang, H. Hong, G. Jin, and C. Chung: “4F2 DRAM Cell with Vertical Pillar Transistor(VPT),” 2011 Proceeding of the European Solid-State Device Research Conference, (2011)H. S. Philip Wong, S. Raoux, S. Kim, Jiale Liang, J. R. Reifenberg, B. Rajendran, M. Asheghi and K. E. Goodson: “Phase Change Memory,” Proceeding of IEEE, Vol.98, No 12, December, pp2b012b27 (2010)K. Tsunoda, K .Kinoshita, H. Noshiro, Y. Yamazaki, T. Iizuka, Y. Ito, A. Takahashi, A. Okano, Y. Sato, T. Fukano, M. Aoki, and Y. Sugiyama : “Low Power and high Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3V,” IEDM (2007)W. Kang, L. Zhang, J. Klein, Y. Zhang, D. Ravelosona, and W. Zhao: “Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology,” IEEE Transaction on Electron Devices, pp.1-9 (2015)M. G. Ertosun, K. Lim, C. Park, J. Oh, P. Kirsch,and K. C. Saraswat: “Novel Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM) Utilizing Electron,” IEEE Electron Device Letter, Vol. 31, No. 5, pp. 405-407 (2010) Md. Hasan Raza Ansari, Nupur Navlakha, Jae Yoon Lee, Seongjae Cho, “Double-Gate Junctionless 1T DRAM With Physical "Barriers for Retention Improvement", IEEE Trans, on Electron Devices vol. 67, pp. 1471-1479 (2020)E. Yoshida, T, Tanaka, “A Capacitorless 1T-DARM Technology Using Gate-Induced Drain-Leakage (GIDL) Current for Low-Power and High-Speed ​​Embedded Memory”, IEEE Trans, on Electron Devices vol. 53, pp. 692-697 (2006),

[0013] In memory devices, memory cells must be manufactured at high density and low cost.

[0014] In order to achieve the above object, a method for manufacturing a semiconductor device having a memory element according to a first aspect of the present invention includes the steps of: forming a first strip-shaped material layer on a semiconductor layer, the first strip-shaped material layer extending in a first direction in a plan view; forming second strip-shaped material layers of equal width on both sides of the first strip-shaped material layer; forming a third strip-shaped material layer on the semiconductor layer, the third strip-shaped material layer covering the first and second strip-shaped material layers and extending in a second direction perpendicular to the first direction; etching the first and second strip-shaped material layers using the third strip-shaped material layer as a mask to form a first mask material layer that is a part of the first strip-shaped material layer and second mask material layers that are a part of the second strip-shaped material layer on both sides of the first mask material layer; etching the semiconductor layer using the first and second mask material layers as a mask to form a semiconductor pillar; forming a first impurity region of an opposite conductivity type to that of the semiconductor pillar at the bottom of the semiconductor pillar; and forming a first gate insulating layer in contact with a side surface of the semiconductor pillar. The method includes the steps of: forming one or two first gate conductor layers in contact with the side surfaces of the first gate insulating layer; removing the second mask material layer; forming a second impurity region and a third impurity region of the same conductivity type as the first impurity region at the top of the semiconductor pillar on both sides of an area where the first mask material layer is located in a plan view; removing the first mask material layer to form a first hole; and forming a second gate insulating layer in contact with the inner side surface of the first hole and a second gate conductor layer in contact with the second gate insulating layer.

[0015] A second invention is characterized in that, in the above-mentioned first invention, it further includes the steps of connecting a control line to the first impurity region, connecting a plate line to the first gate conductor layer, connecting a source line to the second impurity region, connecting a word line to the second gate conductor layer, and connecting a bit line to the third impurity region.

[0016] A third invention, in the above-mentioned first invention, comprises the steps of: removing the second mask material layer while leaving the first mask material layer; forming first low-concentration impurity regions on the tops of the semiconductor pillars on both sides of the first mask material layer in a planar view; forming a third mask material layer on the semiconductor pillars, having an equal width on the side surfaces of the first mask material layer in the second direction; and forming first high-concentration impurity regions, which contain more impurities than the first low-concentration impurity regions, on the tops of the semiconductor pillars on both sides of the third mask material layer, wherein the low-concentration impurity regions and the high-concentration impurity regions form the second impurity regions and the third impurity regions.

[0017] A fourth invention is characterized in that, in the first invention, the second impurity region and the third impurity region are formed using the first mask material layer as a mask, and then the first mask material layer is removed, and then the second gate insulating layer and the second gate conductor layer are formed.

[0018] A fifth invention is characterized in that, in the first invention, the first mask material layer is removed, the second gate insulating layer and the second gate conductor layer are formed on the inner side surface of the first hole, and then the second mask material layer is removed, and then the second impurity region and the third impurity region are formed.

[0019] A sixth invention is characterized in that, in the first invention, it further comprises the steps of: forming the second mask material layer with fourth mask material layers of equal width formed on both sides of the first mask material layer and fifth mask material layers of equal width formed on both sides of the fourth mask material layer; removing the fifth mask material layers; forming a second high-concentration impurity region at the top of the semiconductor pillar in a portion where the fifth mask material layer was located in a planar view; removing the fourth mask material layer; and forming a second low-concentration impurity region at the top of the semiconductor pillar in a portion where the fourth mask material layer was located in a planar view.

[0020] A seventh invention is characterized in that, in the above-mentioned first invention, the method further comprises the steps of: removing the first mask material layer; etching the top of the semiconductor pillar in the portion of the first mask material layer removed using the second mask material layer as an etching mask so that the bottom surface position in the vertical direction is higher than the top surface position of the first gate conductor layer to form a second hole; forming the second gate insulating layer and the second gate conductor layer in contact with the inner side surface of the first hole; removing the second mask material layer; and forming the second impurity region and the third impurity region at the top of the pillar-shaped semiconductor pillar above the bottom of the first hole.

[0021] An eighth invention is characterized in that, in the seventh invention, after the second gate insulating layer and the second gate conductor layer are formed, the second mask material layer is removed, and then the second impurity region and the third impurity region are formed.

[0022] A ninth invention is characterized in that, in the seventh invention, the second impurity region and the third impurity region are formed using the first mask material layer as a mask, and then the second gate insulating layer and the second gate conductor layer are formed in contact with an inner side surface of the second hole formed by removing the first mask material layer.

[0023] A tenth aspect of the present invention is characterized in that, in the seventh aspect of the present invention, the upper surface of the second gate conductor layer is located near the bottoms of the second impurity region and the third impurity region in the vertical direction.

[0024] An eleventh invention is characterized in that, in the first invention described above, it further comprises the steps of: after forming the semiconductor pillar, forming an impurity layer of an opposite conductivity type to that of the semiconductor pillar in an upper layer of the semiconductor layer at the outer periphery of the semiconductor pillar; and thermally oxidizing the upper layer of the semiconductor layer at the outer periphery of the semiconductor pillar to form thermally oxidized layers at the outer and inner peripheries of the semiconductor pillar; and further comprising the steps of spreading the impurity layer of the opposite conductivity type over the entire bottom surface of the semiconductor pillar by heat treatment to form the first impurity region.

[0025] A twelfth invention is characterized in that, in the first invention, it further comprises a step of forming a fourth gate conductor layer and a fifth gate conductor layer by separating the first gate conductor layer at a center portion between the second impurity region and the third impurity region in a direction in which the second impurity region and the third impurity region are connected in a plan view.

[0026] A thirteenth invention is characterized in that there is a semiconductor pillar extending vertically on a substrate, a first impurity region connected to the bottom of the semiconductor pillar, a first gate insulating layer in contact with the side surface of the lower part of the semiconductor pillar, one or two first gate conductor layers in contact with the side surface of the first gate insulating layer, a second impurity region located above an upper surface of the first gate conductor layer in the vertical direction and at both ends of the top of the semiconductor pillar in a first direction in a planar view, a third impurity region, a second gate insulating layer on the top of the semiconductor pillar between the second impurity region and the third impurity region, and a second gate conductor layer in contact with the second gate insulating layer, wherein in a planar view, the semiconductor pillar in a portion in contact with the first gate insulating layer and the semiconductor pillar in a portion where the second impurity region and the third impurity region are present are overlapping and have substantially the same shape.

[0027] A fourteenth aspect of the present invention is the thirteenth aspect of the present invention, characterized in that the first gate conductor layer is divided into two parts, and a fixed voltage or zero volts is applied to one of the two parts.

[0028] A fifteenth invention is the fourteenth invention, characterized in that, in a plan view, one of the two divided first gate conductor layers to which a fixed voltage or a zero volt voltage is applied is adjacent to the second impurity region or the third impurity region connected to a bit line.

[0029] A sixteenth invention is characterized in that, in the thirteenth invention, the top surface position of the semiconductor pillar between the second impurity region and the third impurity region is located lower than the bottom positions of the second impurity region and the third impurity region.

[0030] A seventeenth aspect of the present invention is the sixteenth aspect of the present invention, characterized in that a wiring metal layer is in contact with an upper portion of the second gate conductor layer, and the upper end position of the wiring metal layer is below or near the lower ends of the second and third impurity regions in the vertical direction.

[0031] An eighteenth invention is characterized in that, in the thirteenth invention, the second and third impurity regions comprise low impurity concentration regions adjacent to both sides of the second gate insulating layer, with the second gate conductor layer sandwiched therebetween, and high impurity concentration regions in contact with both outer sides of the low impurity concentration regions.

[0032] A nineteenth aspect of the present invention is characterized in that in the eighteenth aspect, the low impurity concentration region surrounds the entire side surface of the high impurity concentration region and is located within the semiconductor pillar.

[0033] A twentieth invention is characterized in that, in the thirteenth invention, there is a thermal oxide layer between the substrate and the first conductor layer, on the outer and inner peripheries of the bottom of the semiconductor pillar.

[0034] 1 is a diagram for explaining a method for manufacturing a memory device according to a first embodiment. FIG. 2 is a diagram for explaining a method for manufacturing a memory device according to a first embodiment. FIG. 3 is a diagram for explaining a method for manufacturing a memory device according to a first embodiment. FIG. 4 is a diagram for explaining a method for manufacturing a memory device according to a first embodiment. FIG. 5 is a diagram for explaining a method for manufacturing a memory device according to a first embodiment. FIG. 6 is a diagram for explaining a method for manufacturing a memory device according to a first embodiment. FIG. 7 is a diagram for explaining a method for manufacturing a memory device according to a first embodiment. FIG. 8 is a diagram for explaining a method for manufacturing a memory device according to a first embodiment. FIG. 9 is a diagram for explaining a method for manufacturing a memory device according to a first embodiment. FIG. 10 is a diagram for explaining a method for manufacturing a memory device according to a second embodiment. FIG. 11 is a diagram for explaining a method for manufacturing a memory device according to a second embodiment. FIG. 12 is a diagram for explaining a method for manufacturing a memory device according to a second embodiment. FIG. 13 is a diagram for explaining a method for manufacturing a memory device according to a third embodiment. FIG. 14 is a diagram for explaining a method for manufacturing a memory device according to a third embodiment. FIG. 15 is a diagram for explaining a method for manufacturing a memory device according to a third embodiment. FIG. 16 is a diagram for explaining a method for manufacturing a memory device according to a third embodiment. FIG. 17 is a diagram for explaining a method for manufacturing a memory device according to a third embodiment. FIG. 18 is a diagram for explaining a method for manufacturing a memory device according to a third embodiment. FIG. 19 is a diagram for explaining a method for manufacturing a memory device according to a third embodiment. FIG. 19 is a diagram for explaining a method for manufacturing a memory device according to a third embodiment. FIG. 19 is a diagram for explaining a method for manufacturing a memory device according to a third embodiment. FIG. 19 is a diagram for explaining a method for manufacturing a memory device according to a third embodiment. FIG. 19 is a diagram for explaining a method for manufacturing a memory 10A to 10C are diagrams for explaining a method for manufacturing a memory device according to a third embodiment; FIG. 11A is a diagram showing a vertical cross-sectional structure of a conventional memory cell; FIG. 12A is a diagram showing a write operation of a conventional memory cell; and FIG. 13A is a diagram showing an erase operation mechanism of a conventional memory cell.

[0035] Hereinafter, a method for manufacturing a semiconductor device having a memory element according to an embodiment of the present invention will be described with reference to the drawings.

[0036] 1A to 1M show the manufacturing process of a memory device using a semiconductor element of this embodiment. In each figure, (a) is a plan view of one memory cell, (b) is a cross-sectional view taken along line XX' in (a) (an example of the "second direction" in the claims), and (c) is a cross-sectional view taken along line YY' in (a). In an actual memory device, these memory cells are arranged two-dimensionally.

[0037] 1A , a strip-shaped first material layer 11 (an example of a "first strip-shaped material layer" in the claims) extending in the Y-Y′ direction (an example of a "first direction" in the claims) is formed on a P layer 10 (an example of a "semiconductor layer" in the claims), and then strip-shaped second material layers 12 a, 12 b (an example of a "second strip-shaped material layer" in the claims) having equal widths in a planar view are formed on both sides of the strip-shaped first material layer 11. The strip-shaped second material layers 12 a, 12 b are formed, for example, by coating the entire surface with a material film using a CVD (Chemical Vapor Deposition) method, and then etching the material film using an RIE (Reactive Ion Etching) method to form the strip-shaped second material layers 12 a, 12 b on both sides of the strip-shaped first material layer 11. As a result, the strip-shaped second material layers 12a and 12b are formed in a self-aligned manner with respect to the strip-shaped first material layer 11. "Formed in a self-aligned manner" refers to forming the strip-shaped second material layers 12a and 12b at desired positions on the strip-shaped first material layer 11 without using additional lithography techniques. Forming the strip-shaped first material layer 11 and the strip-shaped second material layers 12a and 12b using separate lithography processes inevitably results in mask misalignment during the two lithography processes, leading to a decrease in the integration density of memory cells. Furthermore, the additional lithography processes result in increased costs. The strip-shaped first material layer 11 and the strip-shaped second material layers 12a and 12b may be formed from multiple material layers in a direction perpendicular to the P layer 10. Each of the strip-shaped second material layers 12a and 12b may also be formed from multiple material layers in the X-X' direction.

[0038] Next, as shown in FIG. 1B , a strip-shaped third material layer 13 (an example of the “third strip-shaped material layer” in the claims) is formed on the P layer 10 so as to cover the strip-shaped first material layer 11 and the strip-shaped second material layers 12 a and 12 b in a plan view and extend in the X-X′ direction (an example of the “second direction” in the claims) perpendicular to these.

[0039] Next, as shown in FIG. 1C , the first material layer 11 and the second material layers 12a and 12b are etched using the third material layer 15 as a mask to form a first mask material layer 11a (an example of the “first mask material layer” in the claims) and second mask material layers 12aa and 12ba (an example of the “second mask material layer” in the claims).

[0040] 1D, the third material layer 15 is removed, thereby forming, on the P layer 10, a first mask material layer 11a and second mask material layers 12aa and 12ba of equal width on both sides of the first mask material layer 11a in a plan view.

[0041] 1E, the first mask material layer 11a and the second mask material layers 12aa and 12ba are used as etching masks to form P-layer semiconductor pillars 15 (an example of a "semiconductor pillar" in the claims) on the P-layer 10. As a result, the P-layer semiconductor pillars 15 are formed in self-alignment with the first mask material layer 11a and the second mask material layers 12aa and 12ba.

[0042] Next, as shown in FIG. 1F, a silicon nitride (SiN) layer 17, for example, is formed on the side surface of the P-layer semiconductor pillar 15. Next, arsenic (As) ions, for example, are implanted into the P-layer 10 at the periphery of the P-layer semiconductor pillar 15 by ion implantation to form an N-layer 18. This allows the N-layer 18 to be formed in a self-aligned manner with the first mask material layer 11a and the second mask material layers 12aa and 12ba. The N-layer 18 may also be formed by ion implantation of other ion atoms than As that can form the N-layer 18. The N-layer 18 may also be formed by other methods, such as solid-phase diffusion.

[0043] Next, as shown in FIG. 1G , the N layer 18 is expanded into the P layer 10 and the bottom of the P-layer semiconductor pillar 15 by thermal diffusion, followed by the formation of a thermally oxidized layer 20 by thermal oxidation, and an N layer 18a (an example of the “first impurity region” in the claims) connected to the entire bottom of the P-layer semiconductor pillar 15. The N layer 18a is formed by thermal diffusion, extending from the outer periphery of the bottom of the P-layer semiconductor pillar 15 to the interior of the bottom of the P-layer semiconductor pillar 15, so that the N layer 18a is formed in a self-aligned manner with the P-layer semiconductor pillar 15. Since the P-layer semiconductor pillar 15 is formed in a self-aligned manner with the first mask material layer 11a and the second mask material layers 12aa and 12ba, the N layer 18 is also formed in a self-aligned manner with the first mask material layer 11a and the second mask material layers 12aa and 12ba. The N layer 18a may be connected to the entire bottom of the P-layer semiconductor pillar 15 by the final process of the memory device. Furthermore, instead of P layer 10, an epitaxial crystal growth method may be used to form a substrate consisting of a P layer, an N layer, and a P layer from the bottom up, with the N layer being N layer 18a. In this case, at the stage where P-layer semiconductor pillar 15 is formed, N layer 18a is formed on the entire bottom surface of P-layer semiconductor pillar 15 in a plan view, so that N layer 18a is self-aligned with P-layer semiconductor pillar 15.

[0044] Next, as shown in FIG. 1H , after removing the SiN layer 17, a first gate insulating layer 21 (an example of the “first gate insulating layer” in the claims) is formed on the side of the P-layer semiconductor pillar 15 and on the thermal oxide layer 20 on the periphery of the P-layer semiconductor pillar 15. A first gate conductor layer 22 (an example of the “first gate conductor layer” in the claims) is formed around the lower side of the first gate insulating layer 21 covering the P-layer semiconductor pillar 15, and an insulating layer 23 is formed on the first gate conductor layer 22. Since the first gate insulating layer 21 is formed around the periphery of the P-layer semiconductor pillar 15 without using lithography, the first gate insulating layer 21 is formed in a self-aligned manner with the P-layer semiconductor pillar 15. Note that the first gate insulating layer 21 may be, for example, an oxide insulating layer formed by oxidizing the surface of the P-layer semiconductor pillar 15. In this case, the first gate insulating layer 21 is not formed on the thermal oxide layer 20. The first gate insulating layer 21 may be formed of a single layer or multiple layers. The insulating layer 23 may be omitted. The first gate conductor layer 22 may be formed by first forming a dummy material layer, and then removing the dummy material layer in a later step.

[0045] Next, an insulating layer (not shown) is deposited over the entire surface by CVD. This insulating layer is polished using CMP (Chemical Mechanical Polish) so that its upper surface coincides with the upper surfaces of the first mask material layer 11a and the second mask material layers 12aa and 12ba. Then, as shown in FIG. 1I, this insulating layer is etched using RIE to form an insulating layer 25 whose upper surface is substantially flush with the upper surface of the P-layer semiconductor pillar 15.

[0046] 1J, the second material layers 12a and 12b are removed. Using As ion implantation, N layers 27a and 27b containing donor impurities are formed on the top surface of the P-layer semiconductor pillar 15 on both sides of the first material layer 11aa. As a result, the N layers 27a and 27b are formed in self-alignment with the first material layer 11aa and the P-layer semiconductor pillar 15.

[0047] 1K, a third material layer 29 is formed on the side surface of the first material layer 11a. For example, by CVD deposition of an insulating layer, polishing the insulating layer by CMP, and etching the insulating layer by RIE, a material layer 29 of equal width is formed surrounding the side surface of the first mask insulating layer 11aa in a plan view. Then, N dopant ... + The material layer 29 is formed in a self-aligned manner with the first mask material layer 11a. + The layers 30a and 30b are formed in self-alignment with the first mask material layer 11a, the material layer 29, and the P-layer semiconductor pillar 15. As a result, the N-layer 27a and the N-layer 27b are formed on the top of the P-layer semiconductor pillar 15 on both sides of the first mask material layer 11a. + a second impurity region (which is an example of the "second impurity region" in the claims) consisting of an N layer 27b and an N + A third impurity region (one example of the "third impurity region" in the claims) made of the layer 30b is formed.

[0048] Next, as shown in FIG. 1L , an insulating layer 32 is formed around the outer periphery of the material layer 29. The first mask material layer 11a is removed. A second gate insulating layer 34 (the "second gate insulating layer" in the claims) is formed on the inside of the hole (the "first hole" in the claims) using, for example, ALD (Atomic Layer Deposition) to form a second gate conductor layer 35 (the "second gate conductor layer" in the claims) in contact with the second gate insulating layer 34. The second gate insulating layer 34 and the second gate conductor layer 35 are formed so that their upper surfaces substantially coincide with the upper surface of the insulating layer 32. Because the second gate insulating layer 34 and the second gate conductor layer 35 are formed by deposition using, for example, ALD in the hole where the first mask material layer 11a has been removed, the second gate insulating layer 34 and the second gate conductor layer 35 are formed in a self-aligned manner with the first mask material layer 11a. The second gate insulating layer 34 and the second gate conductor layer 35 may be formed from a single layer or multiple material layers.

[0049] Next, as shown in FIG. 1M, a metal wiring 39 is formed in contact with the second gate conductor layer 35 and extending in the direction of line YY′ in plan view. + A metal wiring layer 37 connected to the layer 30a is formed on the insulating layer 32, extending in the YY' direction. An insulating layer 40 is formed on the insulating layer 32. + A metal wiring layer 41 connected to layer 30b is formed on insulating layer 40, extending in the X-X' direction. Metal wiring 37 is connected to source line SL, metal wiring 39 is connected to word line WL, metal wiring 41 is connected to bit line BL, first gate conductor layer 22 is connected to plate line PL, and N layer 18a is connected to control line (CL). This forms a memory cell on P layer 10 that performs the basic operations described with reference to Figures 4A to 4C. Note that metal wiring 39 and metal wiring layer 37 are formed parallel to each other in the Y-Y' direction on insulating layer 32, but the wiring height in the vertical direction may be changed to reduce capacitive coupling between source line SL and word line WL.

[0050] 1A, a material layer that serves as a stopper for etching the first material layer 11 and the second material layers 12a and 12b in FIG. 1C may be provided on the P layer 10 below the first material layer 11 and the second material layers 12a and 12b. Also, a mask material layer may be provided to cover the first mask material layer 11a and the second mask material layers 12aa and 12ba to reduce undesirable film thickness reduction in an etching step after formation.

[0051] In the manufacturing method of this embodiment, the second mask material layers 12aa and 12ba are first removed, leaving the first mask material layer 11a, and the N layers 27a, 27b, and N + After the layers 30a and 30b are formed, the second gate insulating layer 34 and the second gate conductor layer 35 are formed. On the other hand, the first mask material layer 11a is removed, leaving the second mask material layers 12aa and 12ba, and the second gate insulating layer 34 and the second gate conductor layer 35 are formed. After the second mask material layers 12aa and 12ba are removed, the N layers 27a, 27b, and N + Layers 30a and 30b may be formed.

[0052] In addition, in FIGS. 1K to 1M, the N layers 27a and 27b are N +In this example, the P-layer semiconductor pillar 15 is formed between the layers 30a and 30b and the second gate insulating layer 34. + Alternatively, the insulating layer 32 may be formed to cover the entire side surfaces of the layers 30a and 30b. The N layers 27a and 27b may also be omitted. In this case, it is not necessary to form the third material layer 29 on the side surfaces of the first material layer 11a. The insulating layer 32 serves as an etching mask for forming holes (the "first holes" in the claims). This also applies to the embodiments described below.

[0053] In the description of this embodiment, N + Although the layers 30a and 30b are formed by ion implantation in the above example, they may be formed by selective epitaxial crystal growth followed by a heat treatment. + The connections to layers 30a and 30b are N + The layers 30a and 30b may be provided on the side surfaces as well as on the top surfaces thereof. This also applies to the embodiments described later.

[0054] Furthermore, the metal wiring 39 may be entirely or partially buried in the second gate conductor layer 35. This also applies to the embodiments described later.

[0055] In this embodiment, the method for manufacturing a memory cell has been described using an example in which a planar MOS transistor is formed on the top of the P-layer semiconductor pillar 15. However, as will be described with reference to FIGS. 3A to 3D, + A memory element having a U-channel MOS transistor with a U-shaped channel cross section formed on the top of the P-layer semiconductor pillar between the layers 30a and 30b is also formed using substantially the same process.

[0056] In addition, in this embodiment, the first gate conductor layer 22 is formed to surround the entire side surface of the first gate insulating layer 21 in plan view. However, the first gate conductor layer 22 may be divided into two in plan view. A synchronous or asynchronous drive voltage may be applied to the two divided first gate conductor layers. This also ensures normal memory operation. Furthermore, the first gate conductor layer 35 may be divided into two near the center of the second gate conductor layer 35 on the line XX' in plan view. The N connected to the bit line BL may be formed in the N + A fixed voltage that does not change with time or a zero voltage may be applied to one of the divided gate conductor layers closer to layer 30b. This allows, for example, the one side of the first gate conductor layer to which this zero voltage is applied to have an electrostatic shielding effect, thereby stabilizing the floating body voltage of P-layer semiconductor pillar 15, which stores holes that are signal charges. This also applies to the embodiments described below.

[0057] 1E, the cross section of the P-layer semiconductor pillar 15 formed by etching is rectangular, but it may be trapezoidal. This also applies to the embodiments described later.

[0058] In this embodiment, the first gate insulating layer 21 is formed above the first gate conductor layer 22 in the vertical direction, but since only the portion of the gate insulating layer covered by the first gate conductor layer 22 is required, it is not necessary for the gate insulating layer to extend above the upper surface of the first gate conductor layer 22. This is the same in the examples described below.

[0059] According to the method for manufacturing the memory cell of this embodiment, all elements constituting the memory cell, namely, the P-layer semiconductor pillar 15, the first gate insulating layer 21, the first gate conductor layer 22, the second gate insulating layer 34, the second gate conductor layer 35, the N layers 18a, 27a, 27b, the N layers 18b, 27c, 27d, and 27e, are formed by using the first mask material layer 11a and the second mask material layers 12ab, 12ba formed by self-alignment. +The features of the self-aligned formation of layers 30a and 30b are obtained. (a) The first mask material layer 11a and the second mask material layers 12aa and 12ba are formed without using separate patterned lithography processes, and both are formed by self-alignment (FIGS. 1A and 1B). (b) The P-layer semiconductor pillar 15 is formed using the first mask material layer 11a and the second mask material layers 12aa and 12ba as etching masks, so the first mask material layer 11a, the second mask material layers 12aa and 12ba, and the P-layer semiconductor pillar 15 are formed by self-alignment (FIG. 1E). (c) The N-layer 18 formed by ion implantation using the first mask material layer 11a and the second mask material layers 12aa and 12ba as masks is thermally diffused to form an N-layer 18a extending to the bottom of the P-layer semiconductor pillar 15. As a result, the N layer 18a is formed in self-alignment with the first mask material layer 11a, the second mask material layers 12aa and 12ba, and the P-layer semiconductor pillar 15 (FIGS. 1F and 1G). (d) The first gate insulating layer 21 and the first gate conductor layer 22 are formed in self-alignment around the P-layer semiconductor pillar 15 without using a lithography process (FIG. 1H). (e) The N layers 27a and 27b, which are LDD regions, and the N layers outside them are formed in self-alignment with the N layers 27a and 27b. + The layers 30a and 30b are formed in a self-aligned manner with the first mask material layer 11a (FIGS. 1J and 1K). (f) The second gate insulating layer 34 and the second gate conductor layer 35 are embedded in the holes formed by removing the first mask material layer 11a, so that the second gate insulating layer 34 and the second gate conductor layer 35 are formed in a self-aligned manner with the first mask material layer 11a (FIG. 1L). This reduces the number of lithography steps, thereby reducing costs and enabling higher integration of memory cells.

[0060] In the memory cell of this embodiment, in plan view, the top cross section of the P-layer semiconductor pillar 15 in the portion surrounded by the first gate conductor layer 22 and the N-layer semiconductor pillar 15 in contact therewith are + The layers 30a and 30b are characterized in that they overlap with the bottom cross section of the P-layer semiconductor pillar 15 in a portion thereof with substantially the same shape.

[0061] 2A to 2D show a method for manufacturing a memory device using a semiconductor element according to this embodiment. In each figure, (a) shows a plan view of one memory cell, (b) shows a cross-sectional view taken along line XX' in (a), and (c) shows a cross-sectional view taken along line YY' in (a). In an actual memory device, these memory cells are arranged two-dimensionally.

[0062] As shown in FIG. 2A , strip-shaped material layers 51 a and 51 b with equal widths and strip-shaped material layers 52 a and 52 b with equal widths are formed on both sides of the strip-shaped first material layer 11. Similar to the formation of the second material layers 12 a and 12 b shown in FIG. 2A , the material layers 51 a and 51 b are formed by, for example, coating the entire surface with a material film by CVD and then etching this material film by RIE to form the material layers 51 a and 51 b on both sides of the first material layer 11. Then, using the same method as for forming the material layers 51 a and 51 b, material layers 52 a and 52 b are formed on both sides of the material layers 51 a and 51 b. The material layers 51 a and 52 a correspond to the second material layer 12 a in FIG. 1A , and the material layers 51 b and 52 b correspond to the second material layer 12 b in FIG. 1A . As a result, the material layers 51 a , 51 b , 52 a , and 52 b are formed in self-alignment with the first material layer 11 .

[0063] Next, the same processes as those shown in Figures 1B to 1I are performed. As a result, as shown in Figure 2B, a first mask material layer 11a and material layers 51aa, 51ba, 52aa, and 52ba, each rectangular in plan view, are formed on the P-layer semiconductor pillar 15. Material layers 51aa and 51ba of equal width are formed outside the material layers 51aa and 51ba. Material layers 52aa and 52ba are formed outside the material layers 51aa and 51ba. The material layers 51aa and 52aa correspond to the second mask material layer 12aa in Figure 1I, and the material layers 51ab and 52ab correspond to the second mask material layer 12ba.

[0064] Next, as shown in FIG. 2C, after removing the material layers 52aa and 52ba, N is implanted into the top of the P-layer semiconductor pillar 15 outside the material layers 51aa and 51ba by, for example, ion implantation. + Layers 54a and 54b are formed.

[0065] Next, as shown in FIG. 2D, the material layers 51aa and 51ba are removed, and then N is implanted by ion implantation into the top of the P-layer semiconductor pillar 15 outside the first mask material layer 11a. + The donor impurity ion atoms are implanted at a higher concentration than in the formation of the layers 54a and 54b. As a result, the first mask material layer 11a and the N + N layers 55a and 55b are formed between the layers 54a and 54b. + The layers 54a and 54b and the N layers 55a and 55b are formed in a self-aligned manner with the first mask material layer 11a in a plan view. Thereafter, the same memory cell as shown in FIG. 1M is formed on the P layer 10 by performing the same steps as shown in FIG. 1L to FIG. 1M.

[0066] In this embodiment, compared to the first embodiment, N layers 55a and 55b (corresponding to N layers 27a and 27b in FIG. 1M) and N + Layers 54a, 54b (N in FIG. 1M) + However, the order of forming the N layers 55a, 55b, and N layers 30a, 30b is reversed. + The material layers 51aa, 51ba, 52aa, and 52ba for forming the layers 54a and 54b are still formed in a self-aligned manner with the first mask material layer 11a. The first and second embodiments are essentially the same if the material layers 51aa and 52aa are used as the second mask material layer 12aa and the material layers 51ba and 52ba are used as the second mask material layer 12ab. This allows the second embodiment to achieve low costs and high integration of memory cells, similar to the first embodiment.

[0067] 3A to 3H show a method for manufacturing a memory device using a semiconductor element according to this embodiment. In each figure, (a) shows a plan view of one memory cell, (b) shows a cross-sectional view taken along line XX' in (a), and (c) shows a cross-sectional view taken along line YY' in (a). In an actual memory device, these memory cells are arranged two-dimensionally.

[0068] As shown in FIG. 3A, similarly to FIG. 1E, the P layer 10 is etched by RIE using the first mask material layer 11a and the second mask material layers 12aa and 12ba as etching masks to form P layer semiconductor pillars 15.

[0069] 1B to 1H are then performed to form an N layer 18a, a first gate insulating layer 21, a first gate conductor layer 22, and an insulating layer 23 on the P layer 10, as shown in Fig. 3B. Then, an insulating layer 25a is formed surrounding the first mask material layer 11a, the second mask material layers 12aa and 12ba, and the P-layer semiconductor pillar 15, with its upper surface positioned at the same level as the upper surfaces of the first mask material layer 11a and the second mask material layers 12aa and 12ba.

[0070] 3C, the first mask material layer 11a is removed. Then, using the second mask material layers 12aa and 12ba and the insulating layer 25a as an etching mask, the top of the P-layer semiconductor pillar 15 is etched to form a hole 57. The bottom of the hole 57 is located higher than the upper surface of the first gate conductor layer 22.

[0071] Next, a gate insulating layer (not shown) and a gate conductor layer (not shown) are formed on the inner side surface of the hole 57 and on the upper surface of the insulating layer 25a by, for example, ALD. The gate insulating layer and the gate conductor layer are polished by CMP so that their upper surfaces are aligned with the upper surface of the insulating layer 25a. The gate insulating layer and the gate conductor layer are etched from their upper surfaces by RIE, forming a second gate insulating layer 59 and a second gate conductor layer 60 inside the hole 57 as shown in FIG. 3D .

[0072] Next, as shown in FIG. 3E , an insulating layer 63 is formed in the hole 57. A hole (not shown) is formed by lithography and RIE, with its bottom located above the second gate conductor layer 60 and extending in the Y-Y′ direction. A metal layer (not shown) is formed in this hole so that its top surface is located at the same level as or close to the top surface of the insulating layer 25a. This metal layer is etched from above by RIE to form a metal wiring layer 62 extending in the Y-Y′ direction. An insulating layer 64 is formed on the metal wiring layer 62. Note that the metal wiring layer 62 may be made of the same conductive material as the second gate conductor layer 60.

[0073] 3F, after the second mask material layers 12aa and 12ba are removed by etching, N layers 65a and 65b are formed by ion implantation on the tops of the two exposed P-layer semiconductor pillars 15. The bottoms of the N layers 65a and 65b are located near the top of the second gate conductor layer 60. In practice, the N layers 65a and 65b have an impurity concentration distribution in the vertical direction, so the vertical positional relationship between the N layers 65a and 65b and the second gate conductor layer 60 is adjusted according to the design requirements of the MOS transistor.

[0074] Next, as shown in FIG. 3G, N is implanted into the tops of the two exposed P-layer semiconductor pillars 15 by ion implantation. + Layers 66a and 66b are formed. + The layers 66a and 66b are formed so that the bottom positions thereof are higher than the bottom positions of the N layers 65a and 65b. + N layers 65 aa and 65 ba are formed between the layers 66 a and 66 b and the P layer semiconductor pillar 15 .

[0075] Next, as shown in FIG. 3H, an insulating layer 68 is formed over the entire surface, and then N + A wiring metal layer 69 is formed so as to be connected to the layer 66a and extend in the YY' direction. An insulating layer 70 is formed on the entire surface, and then an N + The N layer 18a is connected to the control line CL, the first gate conductor layer 22 is connected to the plate line PL, the metal wiring layer 62 is connected to the word line WL, and the N + The layer 66a is connected to the source line SL, and the N + The layer 66b is connected to the bit line BL. As a result, a memory cell having the same basic operation as that shown in the first embodiment is formed on the P layer 10. In this memory cell, + A MOS transistor is formed in which the channel between the layers 66a and 66b has a U-shaped cross section.

[0076] In the manufacturing method of this embodiment, the first mask material layer 11a is first removed, leaving the second mask material layers 12aa and 12ba, and then the second gate insulating layer 59 and the second gate conductor layer 60 are formed in the formed hole 57. Thereafter, the N layers 65aa, 65ba, and N +On the other hand, first, the second mask material layers 12aa and 12ba are removed, leaving the first mask material layer 11a, and then N layers 65aa, 65ba, and N layers 65b are formed. + Then, after removing the first mask material layer 11a, a step of forming a second gate insulating layer 59 and a second gate conductor layer 60 in the formed hole 57 may be used.

[0077] In the present embodiment, the cross-sectional shape of the channel of the MOS transistor is U-shaped, but it may be rectangular, trapezoidal, or V-shaped, which increases the effective channel length.

[0078] According to the method for manufacturing the memory cell of this embodiment, as in the first embodiment, the first mask material layer 11a and the second mask material layers 12aa and 12ba are formed by self-alignment, and in plan view, the second gate insulating layer 59 and the second gate conductor layer 60 are formed at the location of the first mask material layer 11a, and N + The layers 66a and 66b and the N layers 65aa and 65ba are formed in a self-aligned manner. As a result, all elements constituting the memory cell, namely, the P layer semiconductor pillar 15, the first gate insulating layer 21, the first gate conductor layer 22, the second gate insulating layer 59, the second gate conductor layer 60, the N layers 18a, 65aa, 65ba, and the N layers 18a, 65aa, 65ba, and the N layers 18a, 65b, and the N layers 18b ... + The layers 66a and 66b are formed in a self-aligned manner.

[0079] Although the vertical cross section of the P-layer semiconductor pillar 15 has been described as rectangular in the above embodiments, it may also be trapezoidal or barrel-shaped. Furthermore, the horizontal cross section of the P-layer semiconductor pillar 15 may also be square, rectangular, or have rounded corners.

[0080] In addition, in the description of the embodiment, the N layer 18 is depicted as being connected to the adjacent memory cell, but it may be located only at the bottom of the P layer semiconductor pillar 15. In this case, the N layer is not connected to the control line CL. In this case, normal memory operation can also be performed.

[0081] In addition, when the N layer 18a shown in the embodiment is connected to the adjacent memory cell and connected to the control line CL, in a plan view, a part or the entire surface of the N layer 18a in the outer periphery of the P layer semiconductor pillar 15 is filled with N containing a large amount of donor impurities. + A layer or a conductive layer may be provided.

[0082] Also, the N connected to the source line SL of the memory cell shown in FIG. + The layer 30a may be shared by adjacent cells. + The layer 30b may be shared between adjacent cells, which allows for higher integration of the memory area. This also applies to other embodiments.

[0083] In addition, in the embodiment, the first gate conductor layer 22 may be divided into two parts in the horizontal or vertical direction and driven synchronously or asynchronously. This also ensures normal memory operation. For example, the first gate conductor layer 22 may be divided in the horizontal direction, and each part may be connected to one of the divided first gate conductor layers of the memory cells on both sides.

[0084] In addition, the P layer 10 in the embodiment may be an SOI (Silicon On Insulator) substrate or a substrate with a well structure, etc. Also, a MOS transistor circuit may be provided below the N layer 2.

[0085] In the first embodiment, the N layers 18a, 27a, 27b, and N + The memory element has been described in which holes are used as write carriers by using the layers 30a, 30b, and the P-layer semiconductor pillar 15. In contrast, the N-layers 18a, 27a, 27b, and N + The layers 30a and 30b may be replaced with P-type impurity layers to form a memory element in which the write carriers are electrons. Both may be formed on the same substrate. This also applies to the other embodiments.

[0086] In addition, in FIG. 1M, the metal wiring layers 37 and 41 are N + On the other hand, the metal wiring layers 37 and 41 are formed in contact with the upper surfaces of the layers 30a and 30b. +The insulating layer 30 may be formed in contact with the upper and side surfaces of the layers 30a and 30b. This also applies to other embodiments.

[0087] Furthermore, the present invention allows for various embodiments and modifications without departing from the broad spirit and scope of the present invention. Furthermore, the above-described embodiments are intended to illustrate examples of the present invention and do not limit the scope of the present invention. The above-described embodiments and modifications can be combined arbitrarily. Furthermore, even if some of the constituent elements of the above-described embodiments are omitted as necessary, they will still fall within the scope of the technical concept of the present invention.

[0088] By using the semiconductor device having a memory element and the manufacturing method thereof according to the present invention, a high-performance and low-cost semiconductor device can be provided.

[0089] 10: P layer 11: Strip-shaped first material layer 12a, 12b: Strip-shaped second material layer 13: Strip-shaped third material layer 11a: First mask material layer 12aa, 12ba: Second mask material layer 15: P layer semiconductor pillar 17: Silicon nitride (SiN) layer 18, 18a, 27a, 27b, 55a, 55b, 65a, 65b: N layer 20: Thermal oxidation layer 21: First gate insulating layer 22: First gate conductor layer 23, 25, 25a, 32, 40, 63, 64, 68, 70: Insulating layer 29: Third material layer 30a, 30b, 54a, 54b, 66a, 66b: N + Layers 34, 59: second gate insulating layer 35, 60: second gate conductor layer 37, 39, 41, 69, 71: metal wiring layer 51a, 51b, 51aa, 51ba, 52a, 52b, 52aa, 52ba: material layer 57: hole SL: source line WL: word line BL: bit line PL: plate line CL: control line

Claims

1. forming a first strip-shaped material layer on a semiconductor layer, the first strip-shaped material layer extending in a first direction in a plan view; forming second strip-shaped material layers of equal width on both sides of the first strip-shaped material layer; forming a third strip-shaped material layer on the semiconductor layer, the third strip-shaped material layer covering the first and second strip-shaped material layers and extending in a second direction perpendicular to the first direction; etching the first and second strip-shaped material layers using the third strip-shaped material layer as a mask to form a first mask material layer which is a part of the first strip-shaped material layer, and second mask material layers which are a part of the second strip-shaped material layer on both sides of the first mask material layer; etching the semiconductor layer using the first and second mask material layers as a mask to form a semiconductor pillar; forming a first impurity region of an opposite conductivity type to that of the semiconductor pillar at the bottom of the semiconductor pillar; forming a first gate insulating layer in contact with a side surface of the semiconductor pillar. a step of forming a first gate conductor layer consisting of one or two layers in contact with a side surface of the first gate insulating layer; a step of removing the second mask material layer; a step of forming a second impurity region and a third impurity region of the same conductivity type as the first impurity region at a top of the semiconductor pillar on both sides of a region where the first mask material layer is located in a plan view; a step of removing the first mask material layer to form a first hole; and a step of forming a second gate insulating layer in contact with an internal side surface of the first hole and a second gate conductor layer in contact with the second gate insulating layer.

2. A method for manufacturing a semiconductor device having the memory element described in claim 1, characterized in that it includes a step of connecting a control line to the first impurity region, connecting a plate line to the first gate conductor layer, connecting a source line to the second impurity region, connecting a word line to the second gate conductor layer, and connecting a bit line to the third impurity region.

3. A method for manufacturing a semiconductor device having a memory element as described in claim 1, comprising the steps of: removing the second mask material layer while leaving the first mask material layer; forming a first low concentration impurity region on the top of the semiconductor pillar on both sides of the first mask material layer in a planar view; forming a third mask material layer on the semiconductor pillar, the third mask material layer having an equal width on a side of the first mask material layer in the second direction; and forming a first high concentration impurity region containing more impurity than the first low concentration impurity region on the top of the semiconductor pillar on both sides of the third mask material layer, the low concentration impurity region and the high concentration impurity region forming the second impurity region and the third impurity region.

4. A method for manufacturing a semiconductor device having a memory element as described in claim 1, characterized in that after forming the second impurity region and the third impurity region using the first mask material layer as a mask, the first mask material layer is removed and then the second gate insulating layer and the second gate conductor layer are formed.

5. A method for manufacturing a semiconductor device having a memory element as described in claim 1, characterized in that after removing the first mask material layer and forming the second gate insulating layer and the second gate conductor layer on the inner side surface of the first hole, the second mask material layer is removed and then the second impurity region and the third impurity region are formed.

6. A method for manufacturing a semiconductor device having a memory element as described in claim 1, further comprising the steps of: forming the second mask material layer by a fourth mask material layer of equal width formed on both sides of the first mask material layer and a fifth mask material layer of equal width formed on both sides of the fourth mask material layer; removing the fifth mask material layer; forming a second high concentration impurity region at the top of the semiconductor pillar in a portion where the fifth mask material layer was located in a planar view; removing the fourth mask material layer; and forming a second low concentration impurity region at the top of the semiconductor pillar in a portion where the fourth mask material layer was located in a planar view.

7. A method for manufacturing a semiconductor device having a memory element as described in claim 1, further comprising the steps of: removing the first mask material layer; etching the top of the semiconductor pillar in the first mask material layer portion removed using the second mask material layer as an etching mask so that the bottom surface position in the vertical direction is higher than the top surface position of the first gate conductor layer to form a second hole; forming the second gate insulating layer and the second gate conductor layer in contact with the inner side surface of the first hole; removing the second mask material layer; and forming the second impurity region and the third impurity region at the top of the pillar-shaped semiconductor pillar above the bottom of the first hole.

8. The method for manufacturing a semiconductor device having a memory element according to claim 7, characterized in that after forming the second gate insulating layer and the second gate conductor layer, the second mask material layer is removed and then the second impurity region and the third impurity region are formed.

9. A method for manufacturing a semiconductor device having a memory element as described in claim 7, characterized in that after forming the second impurity region and the third impurity region using the first mask material layer as a mask, the second gate insulating layer and the second gate conductor layer are formed in contact with the inner side surface of the second hole formed by removing the first mask material layer.

10. A method for manufacturing a semiconductor device having a memory element as described in claim 7, characterized in that, in the vertical direction, the top surface position of the second gate conductor layer is near the bottom positions of the second impurity region and the third impurity region.

11. A method for manufacturing a semiconductor device having a memory element as described in claim 1, further comprising the steps of: after forming the semiconductor pillar, forming an impurity layer of an opposite conductivity type to that of the semiconductor pillar in an upper layer of the semiconductor layer on the outer periphery of the semiconductor pillar; and thermally oxidizing the upper layer of the semiconductor layer on the outer periphery of the semiconductor pillar to form a thermally oxidized layer on the outer periphery and inner periphery of the semiconductor pillar, wherein the impurity layer of the opposite conductivity type is spread over the entire bottom surface of the semiconductor pillar by heat treatment to form the first impurity region.

12. A method for manufacturing a semiconductor device having a memory element as described in claim 1, characterized in that it comprises a step of forming a fourth gate conductor layer and a fifth gate conductor layer by separating the first gate conductor layer at a center portion between the second impurity region and the third impurity region in a direction in which the second impurity region and the third impurity region are connected in a plan view.

13. A semiconductor device having a memory element comprising: a semiconductor pillar extending vertically on a substrate; a first impurity region connected to a bottom of the semiconductor pillar; a first gate insulating layer in contact with a lower side surface of the semiconductor pillar; one or two first gate conductor layers in contact with side surfaces of the first gate insulating layer; a second impurity region located above an upper surface of the first gate conductor layer in the vertical direction and at both ends of the top of the semiconductor pillar in a first direction in a planar view, a third impurity region, a second gate insulating layer on the top of the semiconductor pillar between the second impurity region and the third impurity region, and a second gate conductor layer in contact with the second gate insulating layer, wherein in a planar view, a top cross section of the semiconductor pillar in contact with the first gate insulating layer and a bottom cross section of the semiconductor pillar in contact with the top cross section of the semiconductor pillar in a portion where the second impurity region and the third impurity region are located overlap with each other and have substantially the same shape.

14. A semiconductor device having a memory element according to claim 13, characterized in that the first gate conductor layer is divided into two and configured so that a fixed voltage or zero volts is applied to one of the two.

15. A semiconductor device having a memory element as described in claim 14, characterized in that, in a plan view, one of the two split first gate conductor layers to which a fixed voltage or zero volts is applied is adjacent to the second impurity region connected to a bit line or the third impurity region.

16. A semiconductor device having a memory element as described in claim 13, characterized in that the top surface position of the semiconductor pillar between the second impurity region and the third impurity region is located lower than the bottom positions of the second impurity region and the third impurity region.

17. A semiconductor device having a memory element as described in claim 16, characterized in that a wiring metal layer is in contact with an upper portion of the second gate conductor layer, and the upper end position of the wiring metal layer is lower than or in the vicinity of the lower ends of the second and third impurity regions in the vertical direction.

18. A semiconductor device having a memory element as described in claim 13, characterized in that the second and third impurity regions are composed of low impurity concentration regions adjacent to both sides of the second gate insulating layer, with the second gate conductor layer in between, and high impurity concentration regions in contact with both outsides of the low impurity concentration regions.

19. A semiconductor device having a memory element according to claim 18, wherein the low impurity concentration region surrounds the entire side surface of the high impurity concentration region and is located within the semiconductor pillar.

20. A semiconductor device having a memory element according to claim 13, characterized in that a thermal oxide layer is present between the substrate and the first conductor layer and on the outer and inner peripheries of the bottom of the semiconductor pillar.

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