Electric current detection circuit, feedback control circuit, electric power supply control device, and switching electric power supply

Abstract

This electric current detection circuit detects an inductor electric current that flows through an inductor of a switch output stage used for a switching power supply of a stack system for generating an output voltage from an input voltage, and generates an electric current detection signal for electric current mode control by a predetermined current gain Gc. The current gain Gc is set to a different value (GcH, GcL) according to the frequency band.

Description

Current detection circuits, feedback control circuits, power supply control devices, switching power supplies

[0001] The present disclosure relates to a current detection circuit, a feedback control circuit, a power supply control device, and a switching power supply.

[0002] One known method for increasing the current supply capacity of a switching power supply is the stack (or multi-phase) method, in which multiple switch output stages connected in parallel are driven with a predetermined phase difference. In this driving method, it is ideal for the magnitude of the inductor currents flowing through the inductors of each switch output stage to be the same.

[0003] An example of the related prior art is disclosed in Japanese Patent Application Laid-Open No. 2003-222299.

[0004] Japanese Patent Application Laid-Open No. 2018-161008

[0005] [Summary] However, for example, due to variations in the characteristics of each switch output stage, the drivers that drive them, or the control circuit that controls the drivers, the magnitude of the inductor currents in each switch output stage may not match, resulting in a current imbalance. In this state, the output current of the switching power supply may be biased, potentially leading to a decrease in efficiency. Furthermore, if the current imbalance is relatively large, a protection circuit may be activated, causing the switching power supply to malfunction (e.g., the output operation may be forcibly stopped).

[0006] For example, a current detection circuit according to the present disclosure is a current detection circuit configured to detect an inductor current flowing in an inductor of a switch output stage used in a switching power supply that generates an output voltage from an input voltage, and includes a first current detection circuit configured to generate a first current detection signal from a switch voltage generated in the switch output stage, the first current detection circuit including: a level shifter configured to generate a pulse-width modulated voltage that is pulse-driven between the input voltage and a ground voltage by level-shifting the switch voltage; a first filter configured to generate an average pulse-width modulated voltage by passing frequency components of the pulse-width modulated voltage that are lower than a first cutoff frequency; a second filter configured to generate an average switch voltage by passing frequency components of the switch voltage that are lower than a second cutoff frequency; and a subtractor configured to generate a first current detection signal by subtracting the average switch voltage from the average pulse-width modulated voltage.

[0007] Furthermore, for example, a current detection circuit according to the present disclosure is a current detection circuit configured to detect an inductor current flowing in an inductor of a switch output stage used in a switching power supply that generates an output voltage from an input voltage, the current detection circuit including: a first current detection circuit configured to generate a first current detection signal; a second current detection circuit configured to generate a second current detection signal that has higher tracking ability to fluctuations in the inductor current than the first current detection signal; and an adder configured to generate the current detection signal by adding the first current detection signal and the second current detection signal, wherein the first current detection circuit includes a first current sensor configured to generate a first detection voltage from a voltage across a switch element forming the switch output stage; and a first filter configured to pass, among frequency components of the first detection voltage, a frequency component that is lower than a first cutoff frequency, thereby generating the first current detection signal, and the second current detection circuit includes a second current sensor configured to generate a second detection voltage from the voltage across the inductor; and a second filter configured to pass, among frequency components of the second detection voltage, a frequency component that is higher than a second cutoff frequency, thereby generating the second current detection signal.

[0008] Also, for example, a current detection circuit according to the present disclosure is a current detection circuit configured to detect an inductor current flowing in an inductor of a switch output stage used in a switching power supply that generates an output voltage from an input voltage, and includes: a first current detection circuit configured to generate a first current detection signal; a second current detection circuit configured to generate a second current detection signal that has higher tracking ability to fluctuations in the inductor current than the first current detection signal; and an adder configured to generate the current detection signal by adding the first current detection signal and the second current detection signal, wherein the first current detection circuit includes an external terminal configured to receive an external input of a first detection voltage corresponding to the inductor current from the external switch output stage and outputs the first detection voltage as the first current detection signal, and the second current detection circuit includes: a current sensor configured to generate a second detection voltage from a voltage across the inductor; and a filter configured to generate the second current detection signal by passing frequency components of the second detection voltage that are higher than a predetermined cutoff frequency.

[0009] Furthermore, for example, a current detection circuit according to the present disclosure is a current detection circuit configured to detect an inductor current flowing through an inductor of a switch output stage used in a stack-type switching power supply that generates an output voltage from an input voltage, and to generate a current detection signal for current mode control with a predetermined current gain, where the current gain is set to a different value depending on the frequency band.

[0010] FIG. 1 is a diagram illustrating a comparative example of a switching power supply. FIG. 2 is a diagram illustrating how current balance is disrupted in the comparative example. FIG. 3 is a diagram illustrating a first embodiment of the switching power supply. FIG. 4 is a diagram illustrating how current balance is improved in the first embodiment. FIG. 5 is a diagram illustrating an example of a configuration of a semiconductor device. FIG. 6 is a diagram illustrating an example of current mode control. FIG. 7 is a diagram illustrating current balance characteristics (ideal state) of the first embodiment. FIG. 8 is a diagram illustrating current balance characteristics (first NG example) of the first embodiment. FIG. 9 is a diagram illustrating current balance characteristics (second NG example) of the first embodiment. FIG. 10 is a diagram illustrating transient response characteristics and current balance characteristics when the current gain is uniformly set to a first set value across all frequency bands. FIG. 11 is a diagram illustrating frequency characteristics when the current gain is uniformly set to the first set value across all frequency bands. FIG. 12 is a diagram illustrating transient response characteristics and current balance characteristics when the current gain is uniformly increased from the first set value to the second set value across all frequency bands. FIG. 13 is a diagram showing frequency characteristics when the current gain is raised from a first set value to a second set value across the entire frequency band. FIG. 14 is a diagram showing a second embodiment of a switching power supply. FIG. 15 is a diagram showing frequency characteristics when the current gain is raised from a first set value to a second set value only in the low frequency band. FIG. 16 is a diagram showing transient response characteristics and current balance characteristics when the current gain is raised from the first set value to a second set value only in the low frequency band. FIG. 17 is a diagram showing transient response characteristics when the current gain is set to the first set value across the entire frequency band. FIG. 18 is a diagram showing transient response characteristics when the current gain is raised from the first set value to the second set value only in the low frequency band. FIG. 19 is a diagram showing a third embodiment of a switching power supply (a first example of a current detection circuit). FIG. 20 is a diagram showing the difficulty of current detection in the third embodiment. FIG. 21 is a diagram showing a fourth embodiment of a switching power supply (a second example of a current detection circuit). Fig. 22 is a diagram showing an example of an SW average detection method. Fig. 23 is a diagram showing a fifth embodiment of a switching power supply (=a third example of a current detection circuit). Fig. 24 is a diagram showing the frequency characteristics of current gain in each current detection method.Fig. 25 is a diagram showing the frequency characteristics of the current gain of a current detection signal. Fig. 26 is a diagram showing the transient response characteristics and current balance characteristics when a continuous load change occurs while the current gain is uniformly set to a first setting value across the entire frequency band. Fig. 27 is a diagram showing the transient response characteristics and current balance characteristics when a continuous load change occurs while the current gain is increased from the first setting value to the second setting value only in the low frequency band. Fig. 28 is a diagram showing a sixth embodiment of a switching power supply (= a fourth example of a current detection circuit). Fig. 29 is a diagram showing a seventh embodiment of a switching power supply (= a fifth example of a current detection circuit). Fig. 30 is a diagram showing an eighth embodiment of a switching power supply (= a sixth example of a current detection circuit).

[0011] 1 is a diagram showing a comparative example of a switching power supply (i.e., a general configuration example to be compared with the embodiments described later). A switching power supply Y of this comparative example has semiconductor devices Y1 and Y2, inductors L1 and L2, and capacitors C1 and C2.

[0012] The semiconductor device Y1 is connected to an application terminal of the input voltage Vi and a ground terminal. The output terminal of the semiconductor device Y1 is connected to a first terminal of the inductor L1. The second terminal of the inductor L1 is commonly connected to a first terminal of the capacitor C1 and an application terminal of the output voltage Vo. The second terminal of the capacitor C1 is connected to the ground terminal.

[0013] The semiconductor device Y1, inductor L1, and capacitor C1 form a step-down switch output stage that generates a switch voltage Vst1 from an input voltage Vi and rectifies and smoothes the switch voltage Vst1. The semiconductor device Y1 controls the switching of an inductor current IL1 flowing through the inductor L1 based on a clock signal (not shown) generated internally. The inductor current IL1 is smoothed by the capacitor C1. The smoothed inductor current IL1 is output to the load Z as a first-phase output current Io1.

[0014] The semiconductor device Y2 is connected to the application terminal of the input voltage Vi and the ground terminal. The output terminal of the semiconductor device Y2 is connected to the first terminal of the inductor L2. The second terminal of the inductor L2 is commonly connected to the first terminal of the capacitor C2 and the application terminal of the output voltage Vo. The second terminal of the capacitor C2 is connected to the ground terminal.

[0015] The semiconductor device Y2, inductor L1, and capacitor C2 form a step-down switch output stage that generates a switch voltage Vst2 from an input voltage Vi and rectifies and smoothes the switch voltage Vst2. The semiconductor device Y2 controls the switching of an inductor current IL2 flowing through the inductor L2 based on a clock signal (not shown) generated internally. The inductor current IL2 is smoothed by the capacitor C2. The smoothed inductor current IL2 is output to the load Z as a second-phase output current Io2.

[0016] A load Z is connected to the output terminal of the output voltage Vo. An output current Io flows through the load Z according to the output voltage Vo and the resistance value of the load Z. The output current Io flowing through the load Z is the sum of the first-phase output current Io1 and the second-phase output current Io2 (=Io1+Io2).

[0017] In this way, the switching power supply Y includes the semiconductor devices Y1 and Y2 as means for driving and controlling each of the plurality of switch output stages whose outputs are common to each other.

[0018] 2 is a diagram showing how current balance is lost in the switching power supply Y of this comparative example. In particular, the diagram depicts, from top to bottom, inductor currents IL1 (dashed line) and IL2 (solid line), switch voltage Vst1, and switch voltage Vst2.

[0019] In the switching power supply Y, it is preferable that the average value A1 of the inductor current IL1 (corresponding to the output current Io1) and the average value A2 of the inductor current IL2 (corresponding to the output current Io2) are approximately equal.

[0020] However, for example, due to manufacturing variations in the semiconductor devices Y1 and Y2, the inductors L1 and L2, or the capacitors C1 and C2, the average value A1 of the inductor current IL1 and the average value A2 of the inductor current IL2 may not match, i.e., the current balance may be disrupted.

[0021] When the current balance is lost in this way, the output current Io of the switching power supply Y becomes biased, which may lead to a decrease in the efficiency of the switching power supply Y. Furthermore, when the current balance is lost to a relatively large extent, the protection circuit may be activated and the switching power supply Y may enter a malfunctioning state (for example, a state in which the output operation is forcibly stopped).

[0022] <Switching Power Supply (First Embodiment)> Fig. 3 is a diagram showing a first embodiment of a switching power supply. The switching power supply X of this embodiment is a stack-type switching power supply that generates an output voltage Vo from an input voltage Vi, similar to the comparative example (Fig. 1) described above. Referring to this figure, the switching power supply X of this embodiment is based on the comparative example (Fig. 1) described above, but includes semiconductor devices X1 and X2 instead of semiconductor devices Y1 and Y2.

[0023] Each of the semiconductor devices X1 and X2 is a power supply control device (a so-called power supply control IC [integrated circuit]) configured to drive and control a plurality of switch output stages that generate an output voltage Vo from an input voltage Vi.

[0024] Referring to this figure, the semiconductor devices X1 and X2, like the semiconductor devices Y1 and Y2 described above, each form a plurality of switch output stages together with external discrete components (inductors L1 and L2, and capacitors C1 and C2).

[0025] Furthermore, in order to improve the current balance, the semiconductor devices X1 and X2 use common internal signals (e.g., a common error signal Vc and a common clock signal CLK) in their output feedback control. The common error signal Vc may be a voltage signal or a current signal corresponding to the difference between the output voltage Vo and a desired target value. The common clock signal CLK may be a square-wave signal pulse-driven at a predetermined switching frequency fsw. The output feedback control may employ a so-called current-mode control method (described in detail below).

[0026] The semiconductor devices X1 and X2 are of the same model and have a common circuit configuration, and can be switched between master and slave by register settings or the like.

[0027] For example, consider a case where semiconductor device X1 is the master and semiconductor device X2 is the slave. In this case, semiconductor device X1 internally generates an error signal Vc1 and a clock signal CLK1, and performs output feedback control using the error signal Vc1 and the clock signal CLK1. That is, semiconductor device X1 determines the duty ratio of switch voltage Vst1 in accordance with the error signal Vc1 and the clock signal CLK1. Furthermore, semiconductor device X1 outputs the error signal Vc1 and the clock signal CLK1 to semiconductor device X2 as the aforementioned common error signal Vc and common clock signal CLK.

[0028] On the other hand, the semiconductor device X2 does not internally generate the error signal Vc2 and the clock signal CLK2, but instead receives the common error signal Vc and the common clock signal CLK output from the semiconductor device X1 and performs output feedback control using the common error signal Vc and the common clock signal CLK (corresponding to the error signal Vc1 and the clock signal CLK1). In other words, the semiconductor device X2 determines the duty ratio of the switch voltage Vst2 in accordance with the common error signal Vc and the common clock signal CLK.

[0029] In addition to the semiconductor devices X1 and X2, a third or more power supply control devices may be provided. In this case, one of the multiple power supply control devices is set as a master, and the rest are set as slaves.

[0030] 4 is a diagram showing how the current balance is improved in the switching power supply X of the first embodiment. In particular, in this diagram, as in the above-mentioned FIG. 3, inductor currents IL1 (dashed line) and IL2 (solid line), switch voltage Vst1, and switch voltage Vst2 are depicted in this order from top to bottom.

[0031] As described above, the semiconductor devices X1 and X2 share a common error signal Vc and a common clock signal CLK (for example, the error signal Vc1 and clock signal CLK1 internally generated in the semiconductor device X1).

[0032] Therefore, in the semiconductor devices X1 and X2, output feedback control is performed so that the duty ratios of the switch voltages Vst1 and Vst2 match in accordance with the common error signal Vc and the common clock signal CLK. As a result, the current balance of the inductor currents IL1 and IL2 is adjusted, improving the efficiency of the switching power supply X. In addition, heat generated by the semiconductor devices X1 and X2 is dispersed.

[0033] 5 is a diagram showing an example of the configuration of a semiconductor device X1. Referring to this diagram, the semiconductor device X1 includes an output transistor M1, a synchronous rectification transistor M2, and a feedback control circuit 100.

[0034] The output transistor M1 corresponds to the upper switch of the half bridge. The output transistor M1 may be an NMOSFET (N-channel type metal oxide semiconductor field effect transistor). The drain of the output transistor M1 is connected to a terminal to which the input voltage Vi is applied. The source of the output transistor M1 is connected to a terminal to which the switch voltage Vst1 is applied. The gate of the output transistor M1 is connected to a terminal to which the upper gate signal HG is applied. The output transistor M1 is turned on when the upper gate signal HG is at a high level, and turned off when the upper gate signal HG is at a low level.

[0035] The synchronous rectifier transistor M2 corresponds to the lower switch of the half bridge. The synchronous rectifier transistor M2 may be an NMOSFET. The source of the synchronous rectifier transistor M2 is connected to the application terminal (=ground terminal) of the ground voltage GND. The drain of the synchronous rectifier transistor M2 is connected to the application terminal of the switch voltage Vst1. The gate of the synchronous rectifier transistor M2 is connected to the application terminal of the lower gate signal LG. The synchronous rectifier transistor M2 is turned on when the lower gate signal LG is at a high level, and turned off when the lower gate signal LG is at a low level.

[0036] The output transistor M1 and the synchronous rectifier transistor M2 are complementarily turned on / off in response to the upper gate signal HG and the lower gate signal LG. This on / off operation generates a square-wave switch voltage Vst1 at the first end of the inductor L1 that is pulse-driven between the input voltage Vi and the ground voltage GND. The term "complementary" above includes cases where the on / off states of the output transistor M1 and the synchronous rectifier transistor M2 are completely reversed, as well as cases where a period (dead time) during which both transistors are simultaneously off is provided.

[0037] The output transistor M1 and synchronous rectification transistor M2 connected in this manner, together with the inductor L1 and capacitor C1, form a switch output stage SW1 that generates an output voltage Vo from an input voltage Vi.

[0038] The rectification method of the switch output stage SW1 is not limited to the synchronous rectification method described above, and may be a diode rectification method using a rectifier diode as a lower switch. The output transistor M1 may be replaced with a PMOSFET. The output transistor M1 and the synchronous rectification transistor M2 may be externally attached to the semiconductor device X1.

[0039] In particular, when a high voltage is applied as the input voltage Vi, it is preferable to use high-voltage elements such as power MOSFETs, insulated gate bipolar transistors (IGBTs), and SiC transistors as the output transistor M1 and the synchronous rectifier transistor M2, respectively. Also, GaN devices may be used as the output transistor M1 and the synchronous rectifier transistor M2, respectively.

[0040] The feedback control circuit 100 determines the duty ratio Don1 of the switch output stage SW1 in response to an error signal Vc1 between a feedback voltage Vfb corresponding to the output voltage Vo and a predetermined reference voltage Vref. The duty ratio Don1 is defined as the ratio of the on-period Ton1 of the output transistor M1 to the switching period Tsw1 (=Ton1 / Tsw1).

[0041] Referring to this figure, the feedback control circuit 100 includes an error amplifier 101, an oscillator 102, a ramp signal generating circuit 103, a current detecting circuit 104, a signal adding circuit 105, a comparator 106, a controller 107, and a driver 108.

[0042] The error amplifier 101 generates an error signal Vc1 (=voltage feedback information) according to the difference between a feedback voltage Vfb applied to the inverting input terminal (-) and a reference voltage Vref applied to the non-inverting input terminal (+). The error signal Vc1 increases when the feedback voltage Vfb is lower than the reference voltage Vref, and decreases when the feedback voltage Vfb is higher than the reference voltage Vref.

[0043] The feedback voltage Vfb may be, for example, a divided voltage of the output voltage Vo. If the output voltage Vo is within the input dynamic range of the error amplifier 101, the output voltage Vo may be directly input to the error amplifier 101 as the feedback voltage Vfb. The reference voltage Vref may be, for example, a bandgap voltage with a relatively flat temperature characteristic.

[0044] The oscillator 102 generates a clock signal CLK1 (corresponding to an ON signal) that is pulse-driven at a predetermined switching frequency fsw1 (=1 / Tsw1).

[0045] The ramp signal generating circuit 103 generates a ramp signal Vr1 having a triangular waveform, a sawtooth waveform, or an n-th order slope waveform (e.g., n=2) that rises during the on-period Ton1 of the output transistor M1. For example, the ramp signal Vr1 starts rising from zero when the output transistor M1 is turned on, and is reset to zero when the output transistor M1 is turned off.

[0046] For example, the current detection circuit 104 detects the inductor current IL1 (hereinafter referred to as the upper inductor current IL1H) flowing through the switch output stage SW1 during the on period Ton1 of the output transistor M1, and generates a current detection signal Vcs1 (corresponding to current feedback information) for current mode control with a predetermined current gain Gc.

[0047] The upper inductor current IL1H may be detected by any method. For example, the drain-source voltage of the output transistor M1 may be detected, or the voltage across a sense resistor connected in series to the output transistor M1 may be detected. Alternatively, the drain-source voltage of a current detection transistor connected in parallel to the output transistor M1 may be detected.

[0048] The signal adding circuit 105 adds the ramp signal Vr1 and the current detection signal Vcs1 together to generate a slope signal SLP1.

[0049] The comparator 106 generates a comparison signal CMP1 (corresponding to an OFF signal) by comparing the error signal Vc1 input to its inverting input terminal (-) with the slope signal SLP1 input to its non-inverting input terminal (+). This comparison process determines the OFF timing of the output transistor M1.

[0050] The comparison signal CMP1 is at a high level when SLP1<Vc1, and at a low level when SLP1>Vc1. That is, the pulse generation timing of the comparison signal CMP1 is delayed as the error signal Vc1 is higher, and is accelerated as the error signal Vc1 is lower.

[0051] The controller 107 generates a pulse-width modulation signal PWM in response to the clock signal CLK1 and the comparison signal CMP1. For example, the controller 107 raises the pulse-width modulation signal PWM to a high level (=the logical level when the switch voltage Vst1 is at a high level) when a pulse is generated in the clock signal CLK1. On the other hand, the controller 107 lowers the pulse-width modulation signal PWM to a low level (=the logical level when the switch voltage Vst1 is at a low level) when a pulse is generated in the comparison signal CMP1.

[0052] Therefore, the on-period Ton1 of the output transistor M1 (=the high-level period of the switch voltage Vst1) becomes longer as the pulse generation timing of the comparison signal CMP1 becomes later, and conversely, becomes shorter as the pulse generation timing of the comparison signal CMP1 becomes earlier. In other words, the duty ratio Don1 (=Ton1 / Tsw1) of the switch output stage SW1 becomes larger as the error signal Vc1 becomes higher, and becomes smaller as the error signal Vc1 becomes lower. In this way, the controller 107 determines the duty ratio Don1 in accordance with the clock signal CLK1 and the comparison signal CMP1.

[0053] The driver 108 generates an upper gate signal HG and a lower gate signal LG in response to the pulse-width modulation signal PWM. For example, when the pulse-width modulation signal PWM is at a high level, the driver 108 sets the upper gate signal HG to a high level and the lower gate signal LG to a low level. On the other hand, when the pulse-width modulation signal PWM is at a low level, the driver 108 sets the upper gate signal HG to a low level and the lower gate signal LG to a high level.

[0054] On the other hand, the semiconductor device X2, which controls the drive of the switch output stage SW2, is the same model as the semiconductor device X1, and the internal configurations of the two are the same. Therefore, redundant explanations will be omitted. Note that this figure illustrates an example in which the semiconductor device X1 is the master and the semiconductor device X2 is the slave. In this case, the semiconductor device X1 outputs the error signal Vc1 and clock signal CLK1 to the semiconductor device X2 as the aforementioned common error signal Vc and common clock signal CLK. At this time, the error amplifier and oscillator (neither shown) of the semiconductor device X2 are both disabled (inoperative).

[0055] <Considerations Regarding Current Balance> Fig. 6 is a diagram showing an example of current-mode control. The upper part of the diagram depicts the output current Io1 (small dashed line) and the inductor current IL1 (solid line). The middle part of the diagram depicts the error signal Vc1 (large dashed line) and the slope signal SLP1 (solid line). The lower part of the diagram depicts the switch voltage Vst1.

[0056] The slope signal SLP1 includes current information of the inductor current IL1. For example, if the ratio of the inductor current IL1 to the slope signal SLP1 is defined as the current gain Gc (corresponding to a current / voltage conversion coefficient), the slope signal SLP1 is expressed as the product of the inductor current IL1 and the current gain Gc (=IL1×Gc). Therefore, the waveform of the slope signal SLP1 is similar to the waveform of the inductor current IL1.

[0057] The slope signal SLP1 is compared with the error signal Vc1. This figure illustrates how the peak value of the slope signal SLP1 is determined by the error signal Vc1. That is, the error signal Vc1 determines the peak value IL1_peak of the inductor current IL1 (Vc1=IL1_peak×Gc).

[0058] Therefore, in the feedback control circuit 100, the duty ratio Don1 of the switch output stage SW1 is determined by current mode control according to the current detection signal Vcs1. For example, the earlier the timing at which the error signal Vc1 and the slope signal SLP1 intersect, the smaller the duty ratio Don1. Conversely, the later the timing at which the error signal Vc1 and the slope signal SLP1 intersect, the larger the duty ratio Don1.

[0059] In current-mode control, a series of control paths from the comparator 106 to the inductor L1 operates as a voltage / current converter. Therefore, in the switching power supply X of the first embodiment, the common error signal Vc is shared between the semiconductor device X1 (master) and the semiconductor device X2 (slave), thereby adjusting the current balance of the inductor currents IL1 and IL2.

[0060] For example, when the first-phase output current Io1 is greater than the second-phase output current Io2, the intersection of the common error signal Vc and the slope signal SLP2 occurs earlier than the intersection of the common error signal Vc and the slope signal SLP1. Therefore, an offset is applied so that the second-phase duty ratio Don2 is smaller than the first-phase duty ratio Don1. As a result, the switch output stages SW1 and SW2 are controlled so that the inductor currents IL1 and IL2 are balanced.

[0061] Conversely, when the first-phase output current Io1 is smaller than the second-phase output current Io2, the intersection timing between the common error signal Vc and the slope signal SLP2 is later than the intersection timing between the common error signal Vc and the slope signal SLP1. Therefore, an offset is applied so that the second-phase duty ratio Don2 is greater than the first-phase duty ratio Don1. As a result, the switch output stages SW1 and SW2 are controlled so that the inductor currents IL1 and IL2 are balanced.

[0062] However, even if such a configuration is adopted, there is a risk that the current balance between the inductor currents IL1 and IL2 may not be sufficiently achieved.

[0063] 7 is a diagram showing the current balance characteristics (ideal state) of the first embodiment. The upper part of the diagram depicts the inductor current IL1 (solid line) and the inductor current IL2 (small dashed line). The middle part of the diagram depicts the error signal Vc1 (large dashed line), the slope signal SLP1 (solid line), and the slope signal SLP2 (small dashed line). The lower part of the diagram depicts the switch voltage Vst1 (solid line) and the switch voltage Vst2 (small dashed line).

[0064] If the semiconductor devices X1 and X2 were exactly the same and in a completely ideal state with absolutely no manufacturing variations in the external discrete components, then naturally the inductor currents IL1 and IL2 would be balanced as shown in this diagram.

[0065] 8 is a diagram showing the current balance characteristics (first NG example) of the first embodiment. As with FIG. 7, the upper part of this diagram depicts the inductor current IL1 (solid line) and the inductor current IL2 (small dashed line). The middle part of this diagram depicts the error signal Vc1 (large dashed line), the slope signal SLP1 (solid line), and the slope signal SLP2 (small dashed line). The lower part of this diagram depicts the switch voltage Vst1 (solid line) and the switch voltage Vst2 (small dashed line).

[0066] Note that this diagram depicts behavior when there is variation in the input offset of the comparator 106 between the semiconductor device X1 and the semiconductor device X2 (master: 0 mV, slave: +10 mV). Such variation in input offset can occur when the ground voltages of the analog circuitry are different between the semiconductor device X1 and the semiconductor device X2.

[0067] For example, when the input offset of the comparator 106 is 0, the error signal Vc1 (=common error signal Vc) increases by a voltage change ΔVc in accordance with the current change ΔIo of the output current Io. Here, when the aforementioned current gain Gc is 2 mΩ, even if the current change ΔIo is 25 A / 1 μs, the voltage change ΔVc is only 50 mV. Therefore, even a 10 mV variation in the input offset of the comparator 106 can cause the inductor currents IL1 and IL2 to deviate by 5 A, resulting in a major current imbalance. In other words, setting the current gain Gc to an excessively small value is considered to be one of the causes of the NG.

[0068] 9 is a diagram showing the current balance characteristics (second NG example) of the first embodiment. As in FIG. 7, the upper part of this diagram depicts the inductor current IL1 (solid line) and the inductor current IL2 (small dashed line). The middle part of this diagram depicts the error signal Vc1 (large dashed line), the slope signal SLP1 (solid line), and the slope signal SLP2 (small dashed line). The lower part of this diagram depicts the switch voltage Vst1 (solid line) and the switch voltage Vst2 (small dashed line).

[0069] Note that this diagram illustrates the behavior when there is variation in the DC resistance component DCR between inductors L1 and L2 (master: 5 mΩ, slave: 1 mΩ). The DC resistance component DCR can be understood as the resistance value of an inductor receiving a DC signal (= a signal with a frequency near 0 Hz).

[0070] When the current detection circuit 104 is of the DCR detection type, the DC resistance component DCR of each of the inductors L1 and L2 becomes the current gain Gc in the low frequency band. That is, the current change amount ΔIo of each of the inductor currents IL1 and IL2 becomes the magnitude (=ΔVc / DCR) obtained by dividing the voltage change amount ΔVc of the error signal Vc1 (=common error signal Vc) by the DC resistance component DCR of each of the inductors L1 and L2.

[0071] Therefore, even if there is no difference in the voltage change amount ΔVc of the error signal Vc1 (=common error signal Vc) between the semiconductor device X1 and the semiconductor device X2 and the waveforms of the slope signals SLP1 and SLP2 are the same, if the DC resistance components DCR of the inductors L1 and L2 are different, the current balance of the inductor currents IL1 and IL2 will be lost. In other words, it is thought that one of the causes of this is that the current gain Gc depends on the DC resistance components DCR of the inductors L1 and L2.

[0072] As described above, the switching power supply X of the first embodiment has two major problems with respect to the current balance of the inductor currents IL1 and IL2. The first problem is that the current gain Gc is too small, so that current information is significantly impaired by error factors such as offset and noise. The second problem is that the current gain Gc fluctuates depending on external factors (e.g., the DC resistance components DCR of the inductors L1 and L2) that cannot be controlled within the semiconductor devices X1 and X2.

[0073] <Considerations Regarding Increasing the Current Gain Gc> Fig. 10 is a diagram showing the transient response characteristics and current balance characteristics when the current gain Gc is uniformly set to a first set value GcL (e.g., 1 to 2 mΩ) across the entire frequency band. The upper part of the diagram depicts the output voltage Vo. The middle part of the diagram depicts the inductor current IL1 (solid line) and the inductor current IL2 (small dashed line). The lower part of the diagram depicts the error signal Vc1 (large dashed line) and the slope signal SLP1 (solid line).

[0074] Note that this diagram depicts the behavior when there is variation in the input offset of the comparator 106 between the semiconductor device X1 and the semiconductor device X2 (master: 0 mV, slave: +10 mV). Therefore, as in the case of FIG. 8 , the current balance between the inductor currents IL1 and IL2 is significantly disrupted. However, the transient response characteristics are good, and the voltage drop ΔVo of the output voltage Vo associated with an increase in the output current Io is kept small (for example, ΔVo = approximately 40 mV for ΔIo = 0 → 25 A / 1 μs).

[0075] 11 is a diagram showing frequency characteristics when the current gain Gc is set to a first set value GcL (e.g., 1 to 2 mΩ) across the entire frequency band. The solid line shows the gain diagram of the feedback control circuit 100. The small dashed line shows the phase diagram of the feedback control circuit 100.

[0076] As shown in this figure, the feedback control circuit 100 is designed to ensure a sufficient phase margin within its bandwidth BW (e.g., Fc = 100 to 500 kHz). Also, in this figure, the frequency Fc at which the gain is 1 (0 dB) is 400 kHz.

[0077] 12 is a diagram showing the transient response characteristics and current balance characteristics when the current gain Gc is raised uniformly across the entire frequency band from a first set value GcL (e.g., 1 to 2 mΩ) to a second set value GcH (e.g., 10 times the first set value GcL, i.e., 10 to 20 mΩ). The upper part of the diagram shows the output voltage Vo. The middle part of the diagram shows the inductor current IL1 (solid line) and the inductor current IL2 (small dashed line). The lower part of the diagram shows the error signal Vc1 (large dashed line) and the slope signal SLP1 (solid line).

[0078] 10, the diagram also depicts the behavior when there is a variation in the input offset of the comparator 106 between the semiconductor device X1 and the semiconductor device X2 (master: 0 mV, slave: +10 mV). In the diagram, the current balance between the inductor currents IL1 and IL2 is well maintained by increasing the current gain Gc.

[0079] However, as the output current Io increases, the slope signal SLP1 also increases significantly. Therefore, if the error signal Vc1 does not also increase quickly in response to the slope signal SLP1, the duty ratio Don1 cannot be maintained. As such, the amount of fluctuation in the error signal Vc1 required to maintain the duty ratio Don1 increases, resulting in a deterioration in the transient response characteristics (for example, ΔVo = approximately 130 mV when ΔIo = 0 → 25 A / 1 μs).

[0080] 13 is a diagram showing frequency characteristics when the current gain Gc is raised uniformly across the entire frequency band from a first set value GcL (e.g., 1 to 2 mΩ) to a second set value GcH (e.g., 10 to 20 mΩ). The solid line indicates the gain diagram of the feedback control circuit 100. The small dashed line indicates the phase diagram of the feedback control circuit 100.

[0081] 11, it is clear that the current gain Gc is raised uniformly from the first set value GcL to the second set value GcH across the entire frequency band, which causes a breakdown in the loop design of the feedback control circuit 100. For example, the frequency Fc at which the gain becomes 1 (0 dB) is 150 kHz in this figure.

[0082] To summarize the above, in order to balance the inductor currents IL1 and IL2 using current-mode control, it is desirable to increase the current gain Gc. However, in order to hide the 180° phase rotation caused by LC resonance, it is better to reduce the current gain Gc. Furthermore, an excessively large current gain Gc leads to a deterioration in transient response characteristics.

[0083] Therefore, the inventors of the present application focused on the following two points. The first point is that it may take some time for the current balance to converge. The second point is that the cancellation of LC resonance targets a band of approximately several tens of kHz, although this depends on the LC value. In view of these points, it should be sufficient to increase the current gain Gc only in the low frequency band. An embodiment that reflects this idea will be proposed below.

[0084] <Switching Power Supply (Second Embodiment)> Fig. 14 is a diagram showing a second embodiment of the switching power supply X. The solid line indicates the current gain Gc_var of the second embodiment. The small dashed line indicates the current gain Gc_fix of the first embodiment for comparison. Note that the current gain Gc_fix of the first embodiment is set to a first set value GcL (e.g., 1 to 2 mΩ) uniformly across the entire frequency band.

[0085] In contrast to this, the current gain Gc_var of the current detection circuit 104 in the second embodiment is set to a different value depending on the frequency band.

[0086] Referring to this figure, the current gain Gc_var is set to a first set value GcL (e.g., 1 to 2 mΩ) in the first frequency band FB1. The first frequency band FB1 is preferably set to include the bandwidth BW (e.g., Fc = 100 to 500 kHz) of the feedback control circuit 100. In other words, the current gain Gc_var is preferably maintained at the first set value GcL from the lower limit frequency to the upper limit frequency of the bandwidth BW. For example, the first frequency band FB1 may be a frequency band higher than 50 kHz.

[0087] Furthermore, in a second frequency band FB2 that is lower than the first frequency band FB1, the current gain Gc_var is set to a second set value GcH (e.g., 50 mΩ) that is higher than the first set value GcL (e.g., 1 to 2 mΩ). For example, the second frequency band FB2 may be a low frequency band of 50 kHz or less. That is, the current gain Gc_var is increased from the first set value GcL to the second set value GcH only in the low frequency band.

[0088] 15 is a diagram showing frequency characteristics when the current gain Gc is increased from a first set value GcL to a second set value GcH only in the low frequency band. The solid line shows the gain diagram of the feedback control circuit 100. The small dashed line shows the phase diagram of the feedback control circuit 100.

[0089] 11, the frequency characteristics of the gain and phase in the bandwidth BW of the feedback control circuit 100 are almost the same as when the current gain Gc is set to the first set value GcL uniformly across the entire frequency band. Therefore, the loop design of the conventional feedback control circuit 100 can be used as is.

[0090] 16 is a diagram showing the transient response characteristics and current balance characteristics when the current gain Gc is increased from the first set value GcL to the second set value GcH only in the low frequency band, depicting, from top to bottom, the output voltage Vo, the output current Io, and the inductor currents IL1 and IL2.

[0091] The inductor currents IL1 and IL2 have identifiers for the first embodiment (@Gc_fix) and the second embodiment (@Gc_var) added to the end of their respective reference symbols.

[0092] As shown in the figure, by increasing the current gain Gc in the low frequency band, the inductor currents IL1 and IL2 become equal, although it takes some time. In addition, the transient response characteristics are good, and the voltage drop ΔVo of the output voltage Vo that accompanies an increase in the output current Io is kept small (for example, ΔVo = approximately 40 mV when ΔIo = 0 → 50 A / 1 μs).

[0093] In this way, by increasing the current gain Gc in the low frequency band, it is possible to achieve a current balance between the inductor currents IL1 and IL2 without affecting the transient response characteristics.

[0094] Fig. 17 shows transient response characteristics when the current gain Gc is set to a first set value GcL across the entire frequency band. Fig. 18 shows transient response characteristics when the current gain Gc is increased from the first set value GcL to a second set value GcH only in the low frequency band. From top to bottom, the figures depict the output voltage Vo, the inductor current IL1, the error signal Vc1 (small dashed line), and the slope signal SLP1 (solid line).

[0095] During transient response, a response in a short time, such as a few microseconds, is important. Therefore, the current gain Gc in the low frequency band does not affect the transient response characteristics. In fact, the voltage change ΔVc of the error signal Vc1 during transient response is almost the same in both figures. Furthermore, the current gain Gc is only increased in the low frequency band. Therefore, the slope signal SLP1 rises gradually, as shown in FIG.

[0096] <Considerations on a Current Detection Method Independent of External Factors> Next, a second problem of the switching power supply X of the first embodiment (FIG. 3), for example, the fact that the current gain Gc varies depending on the DC resistance components DCR of the inductors L1 and L2, will be considered.

[0097] When the so-called DCR detection method is adopted as a method for detecting the inductor currents IL1 and IL2, the current balance of the inductor currents IL1 and IL2 may be disrupted due to variations in the DC resistance components DCR of the inductors L1 and L2. Therefore, a current detection circuit 104 that adopts a current detection method other than the DCR detection method is proposed below.

[0098] <Switching Power Supply (Third Embodiment)> Fig. 19 is a diagram showing a third embodiment of the switching power supply X (=first example of the current detection circuit 104). The current detection circuit 104 of this embodiment detects the drain-source voltage Vds of the output transistor M1 as a current detection signal Vcs1 (=IL1 x Ron, where Ron is the on-resistance of the output transistor M1). That is, the current detection signal Vcs1 increases as the inductor current IL1 increases, and decreases as the inductor current IL1 decreases. This current detection method is referred to in this specification as a "Ron direct detection method."

[0099] 20 is a diagram illustrating the difficulty of current detection in the third embodiment. The upper part of the diagram depicts the inductor current IL1. The lower part of the diagram depicts the pulse-width modulation signal PWM (solid line) and the switch voltage Vst1 (small dashed line). The balloons in the diagram also depict enlarged rising waveforms of the pulse-width modulation signal PWM and the switch voltage Vst1.

[0100] In order to accurately detect the drain-source voltage Vds of the output transistor M1 using the Ron direct detection method, it is necessary to overcome the noise problem. In particular, when the output transistor M1 has a low on-resistance (e.g., Ron = 2 to 4 mΩ), the drain-source voltage Vds to be detected becomes a very small value, making accurate detection difficult. While providing a noise filter is an option, as the switching frequency fsw increases, there is a risk that the signal component (current information) to be detected will also be filtered out.

[0101] Furthermore, as indicated by the dashed oval in the balloon, immediately after the output transistor M1 turns on, a large inrush current may flow toward the parasitic capacitance associated with the drain-source of the synchronous rectifier transistor M2. Therefore, controlling the sampling timing of the drain-source voltage Vds is also important for accurately detecting the inductor current IL1. Furthermore, the higher the switching frequency fsw, the more quickly the drain-source voltage Vds must be sampled. This increases the difficulty of signal processing and may lead to an increase in circuit size.

[0102] Although the description here focuses on the first-phase inductor current IL1, the same can be said about the second-phase inductor current IL2.

[0103] In view of the above considerations, the following embodiment proposes a novel current detection method that is neither a DCR detection method nor a Ron direct detection method.

[0104] 21 is a diagram showing a fourth embodiment of the switching power supply X (= a second example of the current detection circuit 104). For ease of explanation, only the current detection circuit 104 connected to the first-phase switch output stage SW1 will be illustrated below. However, a similar configuration can also be adopted for the current detection circuit 104 connected to the second-phase switch output stage SW2.

[0105] The current detection circuit 104 of this embodiment includes a first current detection circuit 10. The first current detection circuit 10 generates a first current detection signal S10 from a switch voltage SW (corresponding to the aforementioned switch voltage Vst1) generated in a switch output stage SW1.

[0106] Referring to the figure, the first current detection circuit 10 includes a level shifter 11, a low-pass filter 12, a low-pass filter 13, and a subtractor 14.

[0107] The level shifter 11 generates a pulse-width modulated voltage SWLVS that is pulse-driven between the input voltage Vi and the ground voltage GND by level-shifting the switch voltage SW. The pulse-width modulated voltage SWLVS can be understood as a rectangular wave voltage signal having the same duty ratio Don as the aforementioned pulse-width modulated signal PWM.

[0108] The low-pass filter 12 generates an average pulse-width modulated voltage PWMave by passing frequency components of the pulse-width modulated voltage SWLVS that are lower than the first cutoff frequency fc1.

[0109] The low-pass filter 13 generates an average switch voltage SWave by passing frequency components of the switch voltage SW that are lower than the second cutoff frequency fc2.

[0110] The subtractor 14 generates a first current detection signal S10 (=PWMave-SWave) by subtracting the average switch voltage SWave from the average pulse width modulation voltage PWMave. This current detection method is referred to as the "SW average detection method" in this specification.

[0111] 22 is a diagram showing an example of the SW average detection method. The solid line represents the pulse width modulation voltage SWLVS. The small dashed line represents the switch voltage SW. The large dashed line represents the output voltage Vo. The dashed-dotted line represents the average pulse width modulation voltage PWMave. The dashed-two-dot line represents the average switch voltage SWave.

[0112] The high-level voltage of the switch voltage SW is lower than the input voltage Vi by the voltage drop (=Ron×IL1) across the output transistor M1, and the low-level voltage of the switch voltage SW is lower than the ground voltage GND by the voltage drop (=Ron×IL1) across the synchronous rectifier transistor M2.

[0113] In other words, the differential voltage information (=SWLVS-SW) obtained by subtracting the switch voltage SW from the pulse-width modulated voltage SWLVS that is pulse-driven between the input voltage Vi and the ground voltage GND indicates the voltage drop amount (=Ron×IL) of each of the output transistor M1 and the synchronous rectification transistor M2.

[0114] However, signal processing to directly subtract the switch voltage SW from the pulse-width modulation voltage SWLVS is difficult in terms of both the amplifier's input range and operating speed. On the other hand, signal processing to subtract the average switch voltage SWave after low-pass filtering from the average pulse-width modulation voltage PWMave after low-pass filtering is relatively easy. In other words, the subtractor 14 does not require a high-speed amplifier with a wide input range or a sample / hold circuit. Therefore, the first current detection signal S10 (=PWMave-SWave) can be easily obtained.

[0115] The average pulse width modulation voltage PWMave is expressed as (Ron+DCR)×Io. The average switch voltage SWave is expressed as DCR×Io. Therefore, the first current detection signal S10, which is the difference voltage between the two, is expressed as Ron×Io.

[0116] That is, the first current detection signal S10 includes information about the power loss of the IC, specifically, information about the conduction loss and switching loss of the switch output stage SW1. Meanwhile, the first current detection signal S10 does not depend on the DC resistance component DCR of the inductor L1. Therefore, by adjusting the first cutoff frequency fc1 of the low-pass filter 12 and the second cutoff frequency fc2 of the low-pass filter 13, it is possible to arbitrarily design the current gain Gc without depending on the DC resistance component DCR of the inductor L1.

[0117] <Considerations Regarding Application to Current-Mode Control> If the first current detection signal S10 is applied to current-mode control, current balance control independent of the external inductor L1 can be realized. However, the first current detection signal S10 is generated through low-pass filters 12 and 13. Therefore, if the first current detection signal S10 is simply applied to current-mode control as the current detection signal Vcs1, it becomes difficult to perform high-speed current feedback control.

[0118] This makes it difficult to realize the advantage of current mode control, that is, to configure loop compensation with 1 pole - 1 zero phase compensation by regarding the switch output stage SW1 as a current source. In other words, the current gain Gc in the bandwidth BW (Fc = 100 to 500 kHz) of the feedback control circuit 100 becomes 0 dB (1x).

[0119] In view of the above considerations, the following embodiment proposes a current detection circuit 104 suitable for current mode control.

[0120] <Switching Power Supply (Fifth Embodiment)> Fig. 23 is a diagram showing a fifth embodiment (= a third example of the current detection circuit 104) of the switching power supply X. The current detection circuit 104 of this embodiment is based on the fourth embodiment (Fig. 21) described above, and further includes a second current detection circuit 20 and an adder 30 in addition to the first current detection circuit 10.

[0121] As described above, the first current detection circuit 10 generates the first current detection signal S10 using the SW average detection method. Although the first current detection signal S10 has poor response to fluctuations in the inductor current IL1, it has the advantage of being independent of the DC resistance component DCR of the inductor L1. The first current detection signal S10 can contribute to determining the current gain Gc in the low frequency band (details will be described later).

[0122] The second current detection circuit 20 generates a second current detection signal S20 that has higher tracking ability to fluctuations in the inductor current IL1 than the first current detection signal S10. Referring to the figure, the second current detection circuit 20 includes a current sensor 21 and a high-pass filter 22.

[0123] The current sensor 21 generates a detection voltage S21 from the voltage across the inductor L1 using a DCR detection method.

[0124] The high-pass filter 22 generates the second current detection signal S20 by passing frequency components of the detection voltage S21 that are higher than the third cutoff frequency fc3. For example, the high-pass filter 22 cuts off the DC component of the detection voltage S21.

[0125] The second current detection signal S20 thus generated depends on the DC resistance component DCR of the inductor L1, but has the advantage of being highly responsive to fluctuations in the inductor current IL1. The second current detection signal S20 can contribute to determining the current gain Gc in the high frequency band (details will be described later).

[0126] The adder 30 generates a current detection signal Vcs1 (=S10+S20) by adding the first current detection signal S10 and the second current detection signal S20 together.

[0127] 24 is a diagram showing the frequency characteristics of the current gain Gc in each current detection method. The small dashed line indicates the current gain Gc10 of the first current detection signal S10 generated by the SW average detection method. The dashed-dotted line indicates the current gain Gc21 of the detection voltage S21 generated by the DCR detection method. The dashed-two-dotted line indicates the current gain Gc20 of the second current detection signal S20 generated by high-pass filtering the detection voltage S21.

[0128] As described above, the current gain Gc of the detection voltage S21 generated by the DCR detection method in the low frequency band depends on the DC resistance component DCR of the inductor L1. This can adversely affect the current balance of the inductor currents IL1 and IL2. Therefore, in the current-mode control of this embodiment, the first current detection signal S10 (SW detection method) and the second current detection signal S20 (DCR detection method + HPF processing) are used together. That is, in the current-mode control of this embodiment, a current detection signal Vcs1 is used, which is the sum of the first current detection signal S10 and the second current detection signal S20.

[0129] FIG. 25 is a diagram showing the frequency characteristics of the current gain Gc of the current detection signal Vcs1 (= S10 + S20). The solid line indicates the current gain Gc_total (corresponding to the aforementioned current gain Gc_var) of the current detection signal Vcs1. The small dashed line indicates the current gain Gc10 of the first current detection signal S10 generated using the SW average detection method. The dashed-dotted line indicates the current gain Gc21 of the detection voltage S21 generated using the DCR detection method. The two-dot chain line indicates the current gain Gc20 of the second current detection signal S20 generated by high-pass filtering of the detection voltage S21. The balloon frames also show enlarged depictions of the frequency characteristics of the current gains Gc_total, Gc10, Gc20, and Gc21.

[0130] As shown in the figure, the current gain Gc_total of the current detection signal Vcs1 is a first set value GcL (e.g., 1 to 2 mΩ) in the first frequency band FB1. The first frequency band FB1 is preferably set to include the bandwidth BW (e.g., Fc = 100 to 500 kHz) of the feedback control circuit 100. For example, the first frequency band FB1 may be a frequency band higher than 50 kHz.

[0131] The first set value GcL is derived from the current gain Gc20 of the second current detection signal S20 obtained by the DCR detection method. Therefore, although current information of the inductor current IL1 is superimposed on the slope signal SLP1, its sensitivity to abrupt current changes, i.e., the current gain Gc_total (=GcL) in the high-frequency band, is kept low. Of course, the first set value GcL has a magnitude sufficient to establish current-mode control. Furthermore, as described above, the second current detection signal S20 has high tracking ability to fluctuations in the inductor current IL1. Therefore, for example, during load fluctuations, the amount of fluctuation in the error signal Vc1 required to maintain the duty ratio Don1 is kept small.

[0132] In particular, within the bandwidth BW of the feedback control circuit 100, if the current gain Gc_total of the current detection signal Vcs1 is too large, the transient response characteristics deteriorate, and if the current gain Gc_total is too small, stability deteriorates. In this regard, the first set value GcL is set using the DCR detection method, which has a proven track record. Therefore, the balance between transient response characteristics and stability can be maintained at a level comparable to that of existing products.

[0133] Furthermore, in a second frequency band FB2 that is lower than the first frequency band FB1, the current gain Gc_total is set to a second set value GcH (e.g., 50 mΩ) that is higher than the first set value GcL (e.g., 1 to 2 mΩ). For example, the second frequency band FB2 may be a low frequency band of 50 kHz or less. That is, the current gain Gc_total is increased from the first set value GcL to the second set value GcH only in the low frequency band.

[0134] The second set value GcH is derived from the current gain Gc10 of the first current detection signal S10 obtained by the SW average detection method. As described above, the first current detection signal S10 does not depend on the DC resistance component DCR of the inductor L1.

[0135] In this way, by increasing the current gain Gc_total in the second frequency band FB2, the inductor currents IL1 and IL2 become equal, although it takes some time. Therefore, it is possible to balance the inductor currents IL1 and IL2 without affecting the transient response characteristics.

[0136] Fig. 26 is a diagram showing transient response characteristics and current balance characteristics when a continuous load change occurs in a state where the current gain Gc is uniformly set to the first set value GcL across the entire frequency band, while Fig. 27 is a diagram showing transient response characteristics and current balance characteristics when a continuous load change occurs in a state where the current gain Gc is increased from the first set value GcL to the second set value GcH only in the low frequency band.

[0137] In both figures, from top to bottom, the output current Io, the output voltage Vo, the common error signal Vc, the slope signals SLP1 and SLP2, and the inductor currents IL1 and IL2 are depicted.

[0138] In both figures, variations are imparted to the input offset of the comparator 106 between the semiconductor device X1 and the semiconductor device X2 so as to produce differences in the current balance effect. Variations are also imparted to the inductance component L and the DC resistance component DCR of each of the inductors L1 and L2.

[0139] As is clear from comparing the two figures, by increasing the current gain Gc in the low frequency band, current balance is achieved so that the inductor currents IL1 and IL2 match, even when continuous load fluctuations occur.

[0140] <Switching Power Supply (Sixth Embodiment)> Fig. 28 is a diagram showing a sixth embodiment (=fourth example of the current detection circuit 104) of the switching power supply X. The current detection circuit 104 of this embodiment is based on the fifth embodiment (Fig. 23) described above, and the components of each part are clearly shown.

[0141] Referring to the figure, the level shifter 11 includes a resistor 11a and a buffer 11b. A first terminal of the resistor 11a is connected to a terminal to which a switch voltage SW is applied. A second terminal of the resistor 11a is connected to an input terminal of the buffer 11b. An output terminal of the buffer 11b is connected to a terminal to which a pulse width modulation voltage SWLVS is applied. The buffer 11b can be replaced with an inverter.

[0142] The low-pass filter 12 includes capacitors 12a to 12c and resistors 12d to 12g. A first end of each of the capacitors 12a to 12c and a first end of the resistor 12d are connected to a ground end (i.e., an application end of the ground voltage GND). A second end of the capacitor 12a and a first end of the resistor 12e are connected to an application end of the average pulse-width modulation voltage PWMave. A second end of the capacitor 12b and a first end of the resistor 12f are connected to a second end of the resistor 12e. A second end of each of the capacitor 12c and the resistor 12d and a first end of the resistor 12g are connected to a second end of the resistor 12f. A second end of the resistor 12g is connected to an application end of the pulse-width modulation voltage SWLVS.

[0143] The capacitance of the capacitor 12a may be, for example, 40 pF. The capacitance of each of the capacitors 12b and 12c may be, for example, 2 pF. The resistance of each of the resistors 12d and 12g may be, for example, 200 kΩ. The resistance of the resistor 12e may be, for example, 2 MΩ. The resistance of the resistor 12f may be, for example, 100 kΩ.

[0144] The low-pass filter 13 includes capacitors 13a to 13c and resistors 13d to 13g. A first end of each of the capacitors 13a to 13c and a first end of the resistor 13d are connected to the ground terminal. A second end of the capacitor 13a and a first end of the resistor 13e are connected to an application terminal for the average switch voltage SWave. A second end of the capacitor 13b and a first end of the resistor 13f are connected to the second end of the resistor 13e. A second end of each of the capacitor 13c and the resistor 13d and a first end of the resistor 13g are connected to the second end of the resistor 13f. A second end of the resistor 13g is connected to an application terminal for the switch voltage SW.

[0145] The capacitance of the capacitor 13a may be, for example, 40 pF. The capacitance of each of the capacitors 13b and 13c may be, for example, 2 pF. The resistance of each of the resistors 13d and 13g may be, for example, 200 kΩ. The resistance of the resistor 13e may be, for example, 2 MΩ. The resistance of the resistor 13f may be, for example, 100 kΩ.

[0146] Note that as the first cutoff frequency fc1 and the second cutoff frequency fc2 of the low-pass filters 12 and 13 are set to lower frequencies, the frequency characteristics of the gain and phase become more similar to the previous state, i.e., the state in which the current gain Gc is uniformly set to the first set value GcL across the entire frequency band. However, the tradeoff is that the capacitance values ​​of the capacitors 12a to 12c and 13a to 13c become larger. Furthermore, the time required for current balancing becomes longer. Therefore, the first cutoff frequency fc1 and the second cutoff frequency fc2 may be increased to a level that does not adversely affect the transient response characteristics (e.g., fc1 = fc2 = 2 kHz).

[0147] The subtractor 14 generates a first current detection signal S10 (=α×(PWMave−SWave)) by multiplying the difference voltage obtained by subtracting the average switch voltage SWave from the average pulse width modulation voltage PWMave by α (for example, 10 times).

[0148] The current sensor 21 includes capacitors 21a and 21b and resistors 21c to 21f. A first end of resistor 21c is connected to the application terminal of switch voltage SW. A second end of resistor 21c and a first end of resistor 21d are connected to the first end of capacitor 21a (corresponding to the application terminal of detection voltage S21). A second end of resistor 21d is connected to the ground terminal. A first end of resistor 21e is connected to the application terminal of output voltage Vo. A second end of resistor 21e and first ends of resistor 21f and capacitor 21b are connected to the second end of capacitor 21a. A second end of resistor 21f and capacitor 21b are connected to the ground terminal. Note that in this figure, an inductor L1 (including a DC resistance component DCR) connected between the application terminal of switch voltage SW and the application terminal of output voltage Vo is depicted by a dashed line.

[0149] Furthermore, the application terminal of the switch voltage SW may be replaced with an application terminal of the pulse width modulation signal PWM. In this case, the switching loss in the switch output stage SW1 is included in the detection voltage S21. Therefore, the signal level of the detection voltage S21 becomes larger.

[0150] The high-pass filter 22 includes a capacitor 22a and a resistor 22b. A first end of the capacitor 22a is connected to a first end of the capacitor 21a. A second end of the capacitor 22a is connected to a first end of the resistor 22b. A second end of the resistor 22b is connected to a second end of the capacitor 21a. The capacitance of the capacitor 22a may be, for example, 10 pF.

[0151] The second current detection circuit 20 includes a calculator 23 in addition to the current sensor 21 and high-pass filter 22. The calculator 23 generates a second current detection signal S20 (= β × S22) by multiplying a voltage S22 across the resistor 22b (= equivalent to the high-pass filtered detection voltage S21) by β.

[0152] <Switching Power Supply (Seventh Embodiment)> Figure 29 is a diagram showing a seventh embodiment of the switching power supply X (= a fifth example of a current detection circuit 104). The current detection circuit 104 of this embodiment is based on the fifth embodiment (Figure 23) described above, but instead of the first current detection circuit 10 of the SW average detection type, it includes a first current detection circuit 10' of a different type. Referring to this figure, the first current detection circuit 10' includes a current sensor 15 of the Ron direct detection type and a low-pass filter 16.

[0153] The current sensor 15 generates a detection voltage S15 (=IL1×Ron) corresponding to the inductor current IL1 from the voltage across the switch element forming the switch output stage SW1 (for example, the drain-source voltage Vds of the output transistor M1). The current sensor 15 may have a configuration similar to that of the current detection circuit 104 in the third embodiment ( FIG. 19 ).

[0154] The low-pass filter 16 generates a first current detection signal S10' by passing frequency components of the detection voltage S15 that are lower than the fourth cutoff frequency fc4. The first current detection signal S10' has a low response to fluctuations in the inductor current IL1, but has the advantage of being independent of the DC resistance component DCR of the inductor L1. The first current detection signal S10' can contribute to determining the current gain Gc in the low-frequency band.

[0155] In this way, the first current detection signal S10 described above may be replaced with a first current detection signal S10' obtained by averaging the detection voltage S15 obtained by the Ron direct detection method.

[0156] <Switching Power Supply (Eighth Embodiment)> Fig. 30 is a diagram showing an eighth embodiment of the switching power supply X (=sixth example of the current detection circuit 104). The current detection circuit 104 of this embodiment is based on the fifth embodiment (Fig. 23) described above, but instead of the first current detection circuit 10 of the SW average detection type, it includes a first current detection circuit 10" of a different type. Note that this configuration is based on the premise that the switch output stage SW1 is not built into the semiconductor device X1, but is attached externally as an independent package (a so-called driver IC [integrated circuit]).

[0157] Referring to this figure, the first current detection circuit 10″ includes an external terminal 17. The external terminal 17 receives an external input of a detection voltage S17 corresponding to the inductor current IL1 from a driver IC in a separate package. The detection voltage S17 may be, for example, a current monitor signal Imon (= an external output signal for constantly monitoring the magnitude of the output current Io1 by the host controller) generated by the driver IC.

[0158] The first current detection circuit 10" outputs the detection voltage S17 as a first current detection signal S10" to the adder 30 without modification. The first current detection signal S10" has a low ability to follow fluctuations in the inductor current IL1, but has the advantage of not depending on the DC resistance component DCR of the inductor L1. The first current detection signal S10" can contribute to determining the current gain Gc in the low frequency band.

[0159] In this way, the first current detection signal S10 mentioned above may be replaced with a first current detection signal S10'' that is externally input from a driver IC in a separate package.

[0160] <Additional Notes> The following additional notes are provided regarding the above disclosure.

[0161] For example, a current detection circuit according to the present disclosure is a current detection circuit configured to detect an inductor current flowing in an inductor of a switch output stage used in a switching power supply that generates an output voltage from an input voltage, and includes a first current detection circuit configured to generate a first current detection signal from a switch voltage generated in the switch output stage, the first current detection circuit including: a level shifter configured to generate a pulse-width modulated voltage that is pulse-driven between the input voltage and a ground voltage by level-shifting the switch voltage; a first filter configured to generate an average pulse-width modulated voltage by passing frequency components of the pulse-width modulated voltage that are lower than a first cutoff frequency; a second filter configured to generate an average switch voltage by passing frequency components of the switch voltage that are lower than a second cutoff frequency; and a subtractor configured to generate a first current detection signal by subtracting the average switch voltage from the average pulse-width modulated voltage (first configuration).

[0162] In addition, the current detection circuit according to the first configuration may be configured (second configuration) further including a second current detection circuit configured to generate a second current detection signal that has higher tracking ability to fluctuations in the inductor current than the first current detection signal, and an adder configured to generate a current detection signal by adding together the first current detection signal and the second current detection signal.

[0163] Furthermore, in the current detection circuit of the second configuration described above, the second current detection circuit may be configured (third configuration) to include a current sensor configured to generate a detection voltage from the voltage across the inductor, and a third filter configured to generate the second current detection signal by passing frequency components of the detection voltage that are higher than a third cutoff frequency.

[0164] Furthermore, for example, a current detection circuit according to the present disclosure is a current detection circuit configured to detect an inductor current flowing in an inductor of a switch output stage used in a switching power supply that generates an output voltage from an input voltage, the current detection circuit including: a first current detection circuit configured to generate a first current detection signal; a second current detection circuit configured to generate a second current detection signal that has higher tracking ability to fluctuations in the inductor current than the first current detection signal; and an adder configured to generate the current detection signal by adding the first current detection signal and the second current detection signal; the first current detection circuit including a first current sensor configured to generate a first detection voltage from a voltage across a switch element forming the switch output stage; and a first filter configured to pass a frequency component of the first detection voltage that is lower than a first cutoff frequency to generate the first current detection signal; and the second current detection circuit including a second current sensor configured to generate a second detection voltage from a voltage across the inductor; and a second filter configured to pass a frequency component of the second detection voltage that is higher than a second cutoff frequency to generate the second current detection signal (fourth configuration).

[0165] Furthermore, for example, a current detection circuit according to the present disclosure is a current detection circuit configured to detect an inductor current flowing in an inductor of a switch output stage used in a switching power supply that generates an output voltage from an input voltage, and includes: a first current detection circuit configured to generate a first current detection signal; a second current detection circuit configured to generate a second current detection signal that has higher tracking ability to fluctuations in the inductor current than the first current detection signal; and an adder configured to generate the current detection signal by adding the first current detection signal and the second current detection signal, wherein the first current detection circuit includes an external terminal configured to receive an external input of a first detection voltage corresponding to the inductor current from the external switch output stage and outputs the first detection voltage as the first current detection signal, and the second current detection circuit includes a current sensor configured to generate a second detection voltage from a voltage across the inductor, and a filter configured to generate the second current detection signal by passing frequency components of the second detection voltage that are higher than a predetermined cutoff frequency (fifth configuration).

[0166] Furthermore, for example, a feedback control circuit according to the present disclosure includes a current detection circuit having any one of the second to fifth configurations, and is configured (sixth configuration) to determine the duty ratio of the switch output stage by current mode control according to the current detection signal.

[0167] The feedback control circuit according to the sixth configuration may be configured (seventh configuration) further including: an error amplifier configured to generate an error signal corresponding to a difference between a feedback voltage corresponding to the output voltage and a predetermined reference voltage; a ramp signal generating circuit configured to generate a ramp signal; a signal adding circuit configured to generate a slope signal by adding the ramp signal and the current detection signal; a comparator configured to compare the error signal with the slope signal to generate a comparison signal; and a controller configured to determine a duty ratio of the switch output stage according to the comparison signal.

[0168] Furthermore, for example, the power supply control device according to the present disclosure has a configuration (eighth configuration) including a feedback control circuit according to the seventh configuration.

[0169] Furthermore, for example, a switching power supply according to the present disclosure includes a plurality of switch output stages having a common output, and a plurality of power supply control devices configured to control the drive of each of the plurality of switch output stages, and each of the plurality of power supply control devices is configured to be a power supply control device having the above-mentioned eighth configuration (ninth configuration).

[0170] In addition, in the switching power supply according to the ninth configuration, one of the plurality of power supply control devices may be a master and the rest may be slaves, the master may internally generate the error signal, determine the duty ratio in accordance with the error signal, and output the error signal as a common error signal to the slaves, and the slaves may determine the duty ratio in accordance with the common error signal output from the master (tenth configuration).

[0171] According to the first to tenth configurations, for example, the inductor current can be detected without depending on the DCR of the inductor.

[0172] Furthermore, for example, the current detection circuit according to the present disclosure is a current detection circuit configured to detect an inductor current flowing through an inductor of a switch output stage used in a stack-type switching power supply that generates an output voltage from an input voltage, and to generate a current detection signal for current mode control with a predetermined current gain, and the current gain is configured to be set to different values ​​depending on the frequency band (eleventh configuration).

[0173] In addition, in the current detection circuit of the above-mentioned 11th configuration, the current gain may be configured to have a first set value in a first frequency band, and a second set value higher than the first set value in a second frequency band lower than the first frequency band (12th configuration).

[0174] Furthermore, the current detection circuit according to the twelfth configuration may be configured (a thirteenth configuration) to include a first current detection circuit configured to generate a first current detection signal in response to the inductor current, a second current detection circuit configured to generate a second current detection signal in response to the inductor current that has better tracking capability with respect to fluctuations in the inductor current than the first current detection signal, and a subtractor configured to generate the current detection signal by adding together the first current detection signal and the second current detection signal.

[0175] Furthermore, in the current detection circuit according to the thirteenth configuration, the first current detection circuit may be configured (fourteenth configuration) to include: a level shifter configured to generate a pulse-width modulated voltage that is pulse-driven between the input voltage and a ground voltage by level-shifting the switch voltage generated in the switch output stage; a first filter configured to generate an average pulse-width modulated voltage by passing frequency components of the pulse-width modulated voltage that are lower than a first cutoff frequency; a second filter configured to generate an average switch voltage by passing frequency components of the switch voltage that are lower than a second cutoff frequency; and an adder configured to generate the first current detection signal by subtracting the average switch voltage from the average pulse-width modulated voltage.

[0176] Furthermore, for example, a feedback control circuit according to the present disclosure includes a current detection circuit having any one of the twelfth to fourteenth configurations, and is configured (fifteenth configuration) to determine the duty ratio of the switch output stage by current mode control according to the current detection signal.

[0177] In the feedback control circuit according to the fifteenth configuration, the first frequency band may be configured to include the bandwidth of the feedback control circuit (sixteenth configuration).

[0178] Furthermore, the feedback control circuit according to the fifteenth or sixteenth configuration may be configured (seventeenth configuration) to further include an error amplifier configured to generate an error signal corresponding to a difference between a feedback voltage corresponding to the output voltage and a predetermined reference voltage, a ramp signal generating circuit configured to generate a ramp signal, a signal adding circuit configured to generate a slope signal by adding the ramp signal and the current detection signal, a comparator configured to compare the error signal with the slope signal to generate a comparison signal, and a controller configured to determine a duty ratio of the switch output stage according to the comparison signal.

[0179] Furthermore, for example, the power supply control device according to the present disclosure has a configuration (18th configuration) including a feedback control circuit according to the 17th configuration.

[0180] Furthermore, for example, a switching power supply according to the present disclosure includes a plurality of switch output stages having a common output, and a plurality of power supply control devices configured to control the drive of each of the plurality of switch output stages, and each of the plurality of power supply control devices is configured to be a power supply control device having the above-mentioned 18th configuration (19th configuration).

[0181] In addition, in the switching power supply according to the nineteenth configuration, one of the plurality of power supply control devices may be a master and the rest may be slaves, the master may internally generate the error signal, determine the duty ratio in accordance with the error signal, and output the error signal as a common error signal to the slaves, and the slaves may determine the duty ratio in accordance with the common error signal output from the master (twentieth configuration).

[0182] According to the eleventh to twentieth configurations, for example, a stack type switching power supply that is less likely to lose current balance can be provided.

[0183] <Others> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0184] 10, 10', 10" First current detection circuit 11 Level shifter 11a Resistor 11b Buffer 12 Low-pass filter 12a to 12c Capacitors 12d to 12g Resistors 13 Low-pass filter 13a to 13c Capacitors 13d to 13g Resistors 14 Subtractor 15 Current sensor (Ron direct detection method) 16 Low-pass filter 17 External terminal 20 Second current detection circuit 21 Current sensor (DCR detection method) 21a, 21b Capacitors 21c to 21f Resistors 22 High-pass filter 22a Capacitor 22b Resistor 23 Arithmetic unit 30 Adder 100 Feedback control circuit 101 Error amplifier 102 Oscillator 103 Ramp signal generation circuit 104 Current detection circuit 105 Signal addition circuit 106 Comparator 107 Controller 108 Driver C1, C2 Capacitor L1, L2 Inductor M1 Output transistor M2 Synchronous rectification transistor SW1, SW2 Switch output stage X, Y Switching power supply X1, X2, Y1, Y2 Semiconductor device (power supply control device) Z Load

Claims

1. A current detection circuit configured to detect an inductor current flowing through an inductor of a switch output stage used in a stack-type switching power supply that generates an output voltage from an input voltage, and to generate a current detection signal for current mode control with a predetermined current gain, wherein the current gain is set to a different value depending on the frequency band.

2. A current detection circuit as described in claim 1, wherein the current gain is a first set value in a first frequency band, and a second set value higher than the first set value in a second frequency band lower than the first frequency band.

3. The current detection circuit of claim 2, comprising: a first current detection circuit configured to generate a first current detection signal in response to the inductor current; a second current detection circuit configured to generate a second current detection signal in response to the inductor current, the second current detection signal having higher tracking ability to fluctuations in the inductor current than the first current detection signal; and a subtractor configured to generate the current detection signal by adding together the first current detection signal and the second current detection signal.

4. The current detection circuit according to claim 3, wherein the first current detection circuit includes: a level shifter configured to generate a pulse-width modulated voltage pulse-driven between the input voltage and a ground voltage by level-shifting a switch voltage generated in the switch output stage; a first filter configured to generate an average pulse-width modulated voltage by passing frequency components of the pulse-width modulated voltage that are lower than a first cutoff frequency; a second filter configured to generate an average switch voltage by passing frequency components of the switch voltage that are lower than a second cutoff frequency; and an adder configured to generate the first current detection signal by subtracting the average switch voltage from the average pulse-width modulated voltage.

5. A feedback control circuit comprising the current detection circuit according to any one of claims 2 to 4, and determining the duty ratio of the switch output stage by current mode control in response to the current detection signal.

6. The feedback control circuit of claim 5, wherein said first frequency band encompasses a bandwidth of said feedback control circuit.

7. The feedback control circuit according to claim 5 or 6, further comprising: an error amplifier configured to generate an error signal corresponding to a difference between a feedback voltage corresponding to the output voltage and a predetermined reference voltage; a ramp signal generating circuit configured to generate a ramp signal; a signal summing circuit configured to generate a slope signal by adding together the ramp signal and the current detection signal; a comparator configured to compare the error signal with the slope signal to generate a comparison signal; and a controller configured to determine a duty ratio of the switch output stage in response to the comparison signal.

8. A power supply control device comprising the feedback control circuit according to claim 7.

9. A switching power supply comprising: a plurality of switch output stages having a common output; and a plurality of power supply control devices configured to control the drive of each of the plurality of switch output stages, wherein each of the plurality of power supply control devices is the power supply control device defined in claim 8.

10. The switching power supply according to claim 9, wherein one of the plurality of power supply control devices is a master and the rest are slaves, the master internally generates the error signal, determines the duty ratio in response to the error signal, and outputs the error signal to the slave as a common error signal, and the slave determines the duty ratio in response to the common error signal output from the master.

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