Display substrate and display device

Abstract

The present disclosure provides a display substrate and a display device. The display substrate comprises a base substrate, a plurality of sub-pixels, and first scan lines; the sub-pixels each comprise a sub-pixel driving circuit; the sub-pixel driving circuit comprises a driving transistor and a compensation transistor; a gate of the compensation transistor is coupled to a corresponding first scan line, a first electrode of the compensation transistor is coupled to a second electrode of the driving transistor, and a second electrode of the compensation transistor is coupled to a gate of the driving transistor; the compensation transistor comprises a compensation active layer; the compensation active layer comprises a first channel part, a second channel part, and a first conductor part; the first conductor part is separately coupled to the first channel part and the second channel part; and at least part of the orthographic projection of the first conductor part on the base substrate is located between the orthographic projection of the first scan line on the base substrate and the orthographic projection of the gate of the driving transistor on the base substrate.

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] With the continuous development of display technology, the market demand and expectations for smart terminal display devices are increasing, and the average daily usage time and frequency of these devices are also rising. Currently, the main display technologies used in smart terminal display devices include liquid crystal display (LCD) technology and organic light-emitting diode (OLED) display technology. OLED display technology offers advantages such as fast response time, wide viewing angles, and thinness, and therefore, it is increasingly being used in smart terminal display devices.

[0003] Summary of the Invention

[0004] The purpose of this disclosure is to provide a display substrate and a display device.

[0005] To achieve the above objectives, this disclosure provides the following technical solution:

[0006] A first aspect of this disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels and a first scan line disposed on the substrate, the first scan line including at least a portion extending along a first direction, each sub-pixel including a sub-pixel driving circuit, the sub-pixel driving circuit including a driving transistor and a compensation transistor, the gate of the compensation transistor being coupled to a corresponding first scan line, the first electrode of the compensation transistor being coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor being coupled to the gate of the driving transistor;

[0007] The compensation transistor includes a compensation active layer, which includes a first channel portion, a second channel portion, and a first conductor portion. The first conductor portion is coupled to the first channel portion and the second channel portion, respectively. At least a portion of the orthographic projection of the first conductor portion on the substrate is located between the orthographic projection of the first scan line on the substrate and the orthographic projection of the gate of the driving transistor on the substrate.

[0008] Optionally, the compensation transistor includes a first compensation gate and a second compensation gate, wherein the orthographic projection of the first compensation gate on the substrate covers the orthographic projection of the first channel portion on the substrate, and the orthographic projection of the second compensation gate on the substrate covers the orthographic projection of the second channel portion on the substrate.

[0009] The first compensation gate is coupled to the corresponding first scan line, and at least a portion of the first compensation gate is located between the coupled first scan line and the gate of the driving transistor, wherein the first scan line is multiplexed as the second compensation gate.

[0010] Optionally, the display substrate further includes a data line and a second scan line, the second scan line including at least a portion extending along the first direction, the sub-pixel driving circuit further includes a data writing transistor, the gate of the data writing transistor being coupled to the corresponding second scan line, the first electrode of the data writing transistor being coupled to the corresponding data line, and the second electrode of the data writing transistor being coupled to the first electrode of the driving transistor.

[0011] Within the same sub-pixel, the gate of the data writing transistor is located on the side of the first scan line facing the gate of the driving transistor.

[0012] Optionally, the data writing transistor includes a data active layer, and the gate of the data writing transistor includes a gate body portion and a gate extension portion coupled to each other. The orthographic projection of the gate body portion on the substrate overlaps at least partially with the orthographic projection of the data active layer on the substrate, and the gate extension portion is coupled to the corresponding second scan line.

[0013] The gate body portion and the gate of the driving transistor are arranged along a first direction, and at least a portion of the gate extension portion is arranged along a second direction with the gate of the driving transistor, wherein the first direction and the second direction intersect; the gate body portion and the gate extension portion are disposed in the same layer or in different layers.

[0014] Optionally, the sub-pixel driving circuit further includes a first conductive connection portion and a first reset transistor, wherein a first end of the first conductive connection portion is coupled to the gate of the driving transistor, and a second end of the first conductive connection portion is coupled to the second terminal of the first reset transistor; the second scan line is at least partially disposed around the second end of the first conductive connection portion.

[0015] Optionally, the gate of the data writing transistor is disposed in the same layer and with the same material as the first scan line, the second scan line is disposed in a different layer from the first scan line, and the second scan line is disposed in the same layer and with the same material as the first conductive connection portion.

[0016] Optionally, the second scan line includes a plurality of straight edges and a plurality of curved edges, the straight edges and the curved edges being alternately arranged along a first direction, the curved edges being arranged around the second end of the first conductive connection portion, the straight edges including a protruding end, at least a portion of the orthographic projection of the protruding end on the substrate being arranged along a second direction with the orthographic projection of the gate of the driving transistor on the substrate, and the protruding end being coupled to the gate of the data writing transistor.

[0017] Optionally, the display substrate further includes a first initialization signal line, the first initialization signal line including at least a portion extending along a second direction; the first electrode of the first reset transistor is coupled to the first initialization signal line;

[0018] The orthographic projection of the first initialization signal line on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the data line on the substrate.

[0019] Optionally, the display substrate further includes a power line and a first initialization signal line, wherein the power line and the data line are disposed on the same layer and made of the same material, and the first initialization signal line is located between the power line and the data line.

[0020] Optionally, the display substrate further includes a second initialization signal line, a third initialization signal line, and a third scan line, the third scan line including at least a portion extending along the first direction; the sub-pixel further includes a light-emitting element; the sub-pixel driving circuit further includes a second reset transistor and a third reset transistor, the gate of the second reset transistor and the gate of the third reset transistor are both coupled to the same corresponding third scan line; the first electrode of the second reset transistor is coupled to the second initialization signal line, and the second electrode of the second reset transistor is coupled to the anode of the light-emitting element; the first electrode of the third reset transistor is coupled to the third initialization signal line, and the second electrode of the third reset transistor is coupled to the first electrode of the driving transistor.

[0021] Optionally, the second scan line is disposed in a different layer from the first scan line, and the orthographic projection of the second scan line on the substrate overlaps at least partially with the orthographic projection of the first scan line on the substrate.

[0022] The display substrate includes a second gate metal layer and a first source / drain metal layer. The second initialization signal line is disposed in the same layer and with the same material as the first source / drain metal layer. The third initialization signal line is disposed in the same layer and with the same material as the second gate metal layer.

[0023] Optionally, the display substrate further includes a power line; the first reset transistor includes a first reset active layer, the first reset active layer includes a third channel portion, a fourth channel portion and a second conductor portion, the second conductor portion being coupled to the third channel portion and the fourth channel portion respectively;

[0024] The orthographic projection of the second conductor portion on the substrate at least partially overlaps with the orthographic projection of the second initialization signal line on the substrate; and / or, the orthographic projection of the second conductor portion on the substrate at least partially overlaps with the orthographic projection of the third initialization signal line on the substrate; and / or, the orthographic projection of the second conductor portion on the substrate at least partially overlaps with the orthographic projection of the power line on the substrate.

[0025] Optionally, the display substrate further includes a power line and a first conductive connection portion, a first end of the first conductive connection portion being coupled to the gate of the driving transistor, and a second end of the first conductive connection portion being coupled to the second electrode of the compensation transistor; the sub-pixel driving circuit further includes a storage capacitor, a first electrode of the storage capacitor being coupled to the gate of the driving transistor, and a second electrode of the storage capacitor being coupled to the corresponding power line.

[0026] The compensation active layer further includes a conductor extension coupled to the first conductor portion, wherein the orthographic projection of the conductor extension on the substrate at least partially overlaps with the orthographic projection of the second electrode on the substrate; and / or

[0027] The orthographic projection of the first conductor portion onto the substrate does not overlap with the orthographic projection of the first conductive connection portion onto the substrate; and / or,

[0028] The orthographic projection of the second electrode plate on the substrate overlaps at least partially with the orthographic projection of the first conductor portion on the substrate.

[0029] Optionally, the display substrate further includes a light-shielding layer, the orthographic projection of the light-shielding layer on the substrate at least partially overlapping the orthographic projection of the active layer of the driving transistor on the substrate, and at least partially overlapping the orthographic projection of the compensation active layer on the substrate.

[0030] Optionally, the sub-pixel further includes a light-emitting element, the light-emitting element including an anode; the sub-pixel driving circuit further includes a light-emitting control transistor and a second conductive connection portion, the first terminal of the light-emitting control transistor is coupled to the second terminal of the driving transistor, the first end of the second conductive connection portion is coupled to the second terminal of the light-emitting control transistor, and the second end of the second conductive connection portion is coupled to the anode through a first via.

[0031] The sub-pixel also includes a pixel opening region, the orthographic projection of which on the substrate does not overlap with the orthographic projection of the first via on the substrate.

[0032] Optionally, the sub-pixel further includes a light-emitting element, the light-emitting element including an anode; at least some of the anodes in the sub-pixels include an anode main portion and an anode virtual portion; the orthographic projection of the anode main portion on the substrate overlaps at least partially with the orthographic projection of the compensation active layer included in the sub-pixel to which it belongs on the substrate; the orthographic projection of the anode virtual portion on the substrate overlaps at least partially with the orthographic projection of the compensation active layer included in the sub-pixel adjacent to it along the first direction on the substrate.

[0033] Optionally, the display substrate includes red sub-pixels, green sub-pixels, and blue sub-pixels; at least some of the sub-pixels include red sub-pixels and blue sub-pixels, and the adjacent sub-pixels include green sub-pixels.

[0034] A second aspect of this disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels, a second scan line, and a data line all disposed on the substrate, wherein the second scan line includes at least a portion extending along a first direction, and each sub-pixel includes a sub-pixel driving circuit, the sub-pixel driving circuit including a first conductive connection portion, a driving transistor, a compensation transistor, and a data writing transistor.

[0035] The first terminal of the compensation transistor is coupled to the second terminal of the driving transistor, and the second terminal of the compensation transistor is coupled to the gate of the driving transistor through the first conductive connection portion; the compensation transistor includes a compensation active layer, the compensation active layer includes a first channel portion, a second channel portion and a first conductor portion, the first conductor portion being coupled to the first channel portion and the second channel portion respectively; at least a portion of the orthographic projection of the first conductor portion on the substrate is located between the orthographic projection of the second scan line on the substrate and the orthographic projection of the gate of the driving transistor on the substrate;

[0036] The gate of the data writing transistor is coupled to the corresponding second scan line, the first terminal of the data writing transistor is coupled to the corresponding data line, and the second terminal of the data writing transistor is coupled to the first terminal of the driving transistor.

[0037] At least a portion of the second scan line is disposed around one end of the first conductive connection portion.

[0038] Optionally, the display substrate further includes a power line; the sub-pixel driving circuit further includes a storage capacitor, the first plate of the storage capacitor being coupled to the gate of the driving transistor, and the second plate of the storage capacitor being coupled to the corresponding power line; the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the first conductor portion on the substrate; and / or,

[0039] The orthographic projection of the first conductor portion on the substrate overlaps at least partially with the orthographic projection of the first conductive connection portion on the substrate.

[0040] Optionally, the display substrate further includes a power line; the sub-pixel driving circuit further includes a storage capacitor, the first plate of the storage capacitor being coupled to the gate of the driving transistor, and the second plate of the storage capacitor being coupled to the corresponding power line; the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the first conductor portion on the substrate; and / or,

[0041] The orthographic projection of the first conductor portion onto the substrate does not overlap with the orthographic projection of the first conductive connection portion onto the substrate; and / or,

[0042] The orthographic projection of the first conductor portion on the substrate overlaps at least partially with the orthographic projection of the power line on the substrate.

[0043] Based on the above-described display substrate technical solution, a third aspect of this disclosure provides a display device including the above-described display substrate. Attached Figure Description

[0044] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0045] Figure 1 is a schematic diagram of the light-shielding layer layout of the display substrate provided in an embodiment of this disclosure;

[0046] Figure 2 is a schematic diagram of the active layer layout of the display substrate provided in an embodiment of this disclosure;

[0047] Figure 3 is a schematic diagram of the layout of the first gate metal layer of the display substrate provided in an embodiment of this disclosure;

[0048] Figure 4 is a schematic diagram of the layout of the active layer and the first gate metal layer of the display substrate provided in the embodiment of this disclosure;

[0049] Figure 5 is a schematic diagram of the layout of the second gate metal layer of the display substrate provided in an embodiment of this disclosure;

[0050] Figure 6 is a schematic diagram of the layout with a second gate metal layer added based on Figure 4;

[0051] Figure 7 is a schematic diagram of the first layout of the first source / drain metal layer of the display substrate provided in an embodiment of the present disclosure;

[0052] Figure 8 is a schematic diagram of the layout with the first source / drain metal layer added based on Figure 6;

[0053] Figure 9 is a schematic diagram of the layout with the first source / drain metal layer added based on Figure 4;

[0054] Figure 10 is a schematic diagram of the layout of the second source / drain metal layer of the display substrate provided in an embodiment of this disclosure;

[0055] Figure 11 is a schematic diagram of the layout with a second source / drain metal layer added based on Figure 8;

[0056] Figure 12 is a schematic diagram of the layout of the first source / drain metal layer and the second source / drain metal layer provided in an embodiment of this disclosure;

[0057] Figure 13 is a schematic diagram of the vias with an added light-shielding layer and a second planarization layer based on Figure 11;

[0058] Figure 14 is a schematic diagram of a via formed on an interlayer insulating layer according to an embodiment of this disclosure;

[0059] Figure 15 is a schematic diagram of a via formed on the first planarization layer according to an embodiment of this disclosure;

[0060] Figure 16 is a schematic diagram of a via formed on the second planarization layer according to an embodiment of this disclosure;

[0061] Figure 17 is a schematic diagram of the layout of the anode layer provided in an embodiment of this disclosure;

[0062] Figure 18 is a schematic diagram of the layout with an added anode layer based on Figure 13;

[0063] Figure 19 is a circuit schematic diagram of the sub-pixel driving circuit provided in an embodiment of this disclosure;

[0064] Figure 20 is a timing diagram of the sub-pixel driving circuit provided in an embodiment of this disclosure;

[0065] Figure 21 is a schematic cross-sectional view of each film layer of the display substrate provided in the embodiments of this disclosure;

[0066] Figure 22 is a schematic diagram of the second layout of the first source / drain metal layer in the display substrate provided in an embodiment of this disclosure. Detailed Implementation

[0067] To further illustrate the display substrate and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0068] This disclosure provides a display substrate, which includes a plurality of sub-pixels. Each sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit adopts an 8T1C (i.e., 8 transistors and 1 storage capacitor) circuit structure, and all transistors in the sub-pixel driving circuit are low-temperature polysilicon transistors.

[0069] As shown in Figure 19, the display substrate further includes a power supply line VDD, a light emission control signal line EM, a data line DA, a first scan line GA1, a second scan line GA2, a third scan line GA3, a first initialization signal line Vinit1, a second initialization signal line Vinit2, a third initialization signal line Vinit3, and a reset signal line RST. The sub-pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a storage capacitor Cst.

[0070] The gate of the first transistor T1 is coupled to the corresponding reset signal line RST, the first terminal of the first transistor T1 is coupled to the first initialization signal line Vinit1, and the second terminal of the first transistor T1 is coupled to the gate (i.e., node N1) of the third transistor T3.

[0071] The gate of the second transistor T2 is coupled to the corresponding first scan line GA1, the first terminal of the second transistor T2 is coupled to the second terminal of the third transistor T3, and the second terminal of the second transistor T2 is coupled to the gate of the third transistor T3.

[0072] The gate of the fourth transistor T4 is coupled to the corresponding second scan line GA2, the first terminal of the fourth transistor T4 is coupled to the corresponding data line DA, and the second terminal of the fourth transistor T4 is coupled to the first terminal (i.e., node N2) of the third transistor T3.

[0073] The gate of the fifth transistor T5 is coupled to the corresponding light-emitting control signal line EM, the first terminal of the fifth transistor T5 is coupled to the power supply line VDD, and the second terminal of the fifth transistor T5 is coupled to the first terminal of the third transistor T3.

[0074] The gate of the sixth transistor T6 is coupled to the corresponding light-emitting control signal line EM. The first terminal of the sixth transistor T6 is coupled to the second terminal (i.e., node N3) of the third transistor T3. The second terminal of the sixth transistor T6 is coupled to the anode Ano (i.e., node N4) of the light-emitting element. The cathode of the light-emitting element is connected to the negative power supply signal VSS.

[0075] The gate of the seventh transistor T7 is coupled to the corresponding third scan line GA3, the first electrode of the seventh transistor T7 is coupled to the second initialization signal line Vinit2, and the second electrode of the seventh transistor T7 is coupled to the anode Ano of the light-emitting element.

[0076] The gate of the eighth transistor T8 is coupled to the corresponding third scan line GA3, the first terminal of the eighth transistor T8 is coupled to the third initialization signal line Vinit3, and the second terminal of the eighth transistor T8 is coupled to the first terminal of the third transistor T3.

[0077] The first plate Cst1 of the storage capacitor Cst is coupled to the gate of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power line VDD. For example, the gate of the third transistor T3 is multiplexed to the first plate Cst1.

[0078] As shown in Figures 19 and 20, the display substrate includes multiple driving cycles, each driving cycle including a write frame and a hold frame. The operation of the sub-pixel driving circuit in each driving cycle is as follows:

[0079] During frame writing, at time P1 (circle 1 in Figure 2), the light emission control signal transmitted by the EM light emission control signal line is set to a high level, and both the fifth transistor T5 and the sixth transistor T6 are turned off. Nodes N1, N2, and N3 are all in a floating state. At time P2 (circle 2 in Figure 2), the third scan signal transmitted by the third scan line GA3 is set to a low level, and both the seventh transistor T7 and the eighth transistor T8 are turned on. The third initialization signal transmitted by the third initialization signal line Vinit3 refreshes the initial bias of node N2 for the new frame, while the second initialization signal transmitted by the second initialization signal line Vinit2 resets node N4 in a timely manner. At time P3 (circle 3 in Figure 2), the reset signal transmitted by the reset signal line RST is set to a low level, the first transistor T1 is turned on, and the first initialization signal transmitted by the first initialization signal line Vinit1 initializes node N1. At time P4 (circle 4 in Figure 2), the first scan signal transmitted by the first scan line GA1 is set to low level, the first transistor T1 and the second transistor T2 are turned on simultaneously, and the first initialization signal transmitted by the first initialization signal line Vinit1 initializes node N1, completing the initialization of all three nodes in the Floating state. At time P5 (circle 5 in Figure 2), the second scan signal transmitted by the second scan line GA2 is set to low level, the fourth transistor T4 is turned on, and a new frame of data signal is written. From time P5 to P6 (circles 5 and 6 in Figure 2), the data signal information stored by node N2 and parasitic capacitance continues to compensate for the threshold voltage Vth of the third transistor T3. At time P6, the first scan signal transmitted by the first scan line GA1 is set to high level, the second transistor T2 is turned off, and the writing is completed. At time P7 (circle 7 in Figure 2), the third scan signal transmitted by the third scan line GA3 is set to low level again, and nodes N2 and N4 are reset and refreshed again before light emission, keeping the source and drain of the third transistor T3 in the same state before the new frame is written. At time P8 (circle 8 in Figure 2), the light emission control signal transmitted by the light emission control signal line EM is set to a low level, and the fifth transistor T5 and the sixth transistor T6 are turned on, charging and illuminating the light emission element during the write frame. During the low-frequency display hold frame, at times P9 and P10 (circles 9 and 10 in Figure 2), the third scan signal transmitted by the third scan line GA3 is set to a low level, and both the seventh transistor T7 and the eighth transistor T8 are turned on, allowing for the refreshing of the N2 node bias and the reset of the N4 node.

[0080] For example, the reset signal line RST coupled to the sub-pixel driving circuit is signaled by a set of light emission control shift register units (EM GOA). For instance, the signal transmitted by the reset signal line RST coupled to the nth row sub-pixel driving circuit is provided by the (n-7)th row EM GOA. The signals transmitted by the second scan line GA2 and the third scan line GA3 can be provided by independent gate shift register units (Gate GOA), but are not limited to this.

[0081] In the sub-pixel driving circuit of the above structure, an eighth transistor T8 and a third initialization signal line Vinit3 are added. By controlling the timing to refresh the N2 node voltage, low-frequency and low-power display can be achieved, and the low-frequency flicker problem can be improved.

[0082] While consumers seek low-frequency, low-power, and low-frequency flicker reduction, they also desire higher-resolution display products. However, due to the size limitations of display products, the layout space for sub-pixels is greatly restricted. Therefore, it is necessary to consider the working principles and states of each signal line, as well as potential defects, and to rationally arrange the design to avoid these defects.

[0083] Please refer to Figures 2 to 4. This disclosure provides a display substrate, including: a substrate and a plurality of sub-pixels and a first scan line GA1, all disposed on the substrate. The first scan line GA1 includes at least a portion extending along a first direction. Each sub-pixel includes a sub-pixel driving circuit. The sub-pixel driving circuit includes a driving transistor (i.e., the third transistor T3) and a compensation transistor (i.e., the second transistor T2). The gate T2-g of the compensation transistor is coupled to the corresponding first scan line GA1. The first electrode of the compensation transistor is coupled to the second electrode of the driving transistor. The second electrode of the compensation transistor is coupled to the gate T3-g of the driving transistor.

[0084] The compensation transistor includes a compensation active layer 22, which includes a first channel portion 221, a second channel portion 222, and a first conductor portion 223. The first conductor portion 223 is coupled to the first channel portion 221 and the second channel portion 222, respectively. At least a portion of the orthographic projection of the first conductor portion 223 on the substrate is located between the orthographic projection of the first scan line GA1 on the substrate and the orthographic projection of the gate T3-g of the driving transistor on the substrate.

[0085] For example, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixel pixels are arranged in an array. The plurality of sub-pixel driving circuits are divided into multiple rows of sub-pixel driving circuits and multiple columns of sub-pixel driving circuits. The multiple rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The multiple columns of sub-pixel driving circuits are arranged along the first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. For example, the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0086] For example, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to the anode of the light-emitting element and is used to provide a driving signal to the light-emitting element to drive it to emit light.

[0087] For example, the display substrate includes a plurality of first scan lines GA1 arranged along the second direction, and each first scan line GA1 includes at least a portion extending along the first direction. For instance, each of the plurality of first scan lines GA1 corresponds one-to-one with a multi-row sub-pixel driving circuit, and each first scan line GA1 is coupled to the gate T2-g of each compensation transistor in the corresponding row of sub-pixel driving circuit.

[0088] For example, the compensation transistor includes a dual-gate transistor, and the first scan line GA1 is coupled to the two gates of the compensation transistor. For instance, the first scan line GA1 is multiplexed as at least one gate of the compensation transistor.

[0089] For example, the compensation transistor includes a compensation active layer 22, which includes a first channel portion 221, a second channel portion 222, and a first conductor portion 223, wherein the first conductor portion 223 is coupled to both the first channel portion 221 and the second channel portion 222. For instance, the first conductor portion 223 is formed as an integral structure with both the first channel portion 221 and the second channel portion 222.

[0090] For example, at least a portion of the orthographic projection of the first channel portion 221 onto the substrate is located between the orthographic projection of the first scan line GA1 onto the substrate and the orthographic projection of the gate T3-g of the driving transistor onto the substrate.

[0091] For example, the first channel portion 221 and the first conductor portion 223 are arranged along the first direction, and the second channel portion 222 and the first conductor portion 223 are arranged along the second direction.

[0092] As can be seen from the specific structure of the display substrate described above, in the display substrate provided in this embodiment, the compensation transistor includes a compensation active layer 22. At least a portion of the orthogonal projection of the first conductor portion 223 in the compensation active layer 22 onto the substrate is located between the orthogonal projection of the first scan line GA1 onto the substrate and the orthogonal projection of the gate T3-g of the driving transistor onto the substrate. Compared with conventional layout methods, the above arrangement allows the compensation transistor to be formed as a dual-gate inverted structure. That is, within the same sub-pixel driving circuit layout area, the first conductor portion 223 and the first compensation gate T2-g1 can both be disposed in the area between the first scan line GA1 and the gate T3-g of the driving transistor, effectively compressing the vertical design space occupied by the sub-pixel driving circuit, which is beneficial to the development of high resolution of the display substrate.

[0093] Furthermore, since the gate T2-g of the compensation transistor is coupled to the first scan line GA1, the first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate T3-g of the driving transistor, that is, the compensation transistor itself is coupled to the first scan line GA1 and the driving transistor, therefore, disposing at least part of the compensation active layer 22 in the region between the first scan line GA1 and the gate T3-g of the driving transistor will not cause defects due to the difference in their potentials.

[0094] Therefore, the display substrate provided in this embodiment comprehensively considers the working principle, working state, and possible defects of the sub-pixel driving circuit and signal lines, and makes reasonable arrangements for the design, thereby improving the resolution and avoiding defects.

[0095] As shown in Figures 2 to 4, in some embodiments, the compensation transistor includes a first compensation gate T2-g1 and a second compensation gate T2-g2. The orthographic projection of the first compensation gate T2-g1 on the substrate covers the orthographic projection of the first channel portion 221 on the substrate, and the orthographic projection of the second compensation gate T2-g2 on the substrate covers the orthographic projection of the second channel portion 222 on the substrate.

[0096] The first compensation gate T2-g1 is coupled to the corresponding first scan line GA1. At least a portion of the first compensation gate T2-g1 is located between the coupled first scan line GA1 and the gate T3-g of the driving transistor. The first scan line GA1 is multiplexed as the second compensation gate T2-g2.

[0097] For example, the first compensation gate T2-g1 and the second compensation gate T2-g2 are both formed as an integral structure with the first scan line GA1 coupled to them.

[0098] The above configuration allows the compensation transistor to be formed as a dual-gate inverted structure. That is, within the same sub-pixel driving circuit layout area, both the first conductor portion 223 and the first compensation gate T2-g1 can be located in the area between the first scan line GA1 and the gate T3-g of the driving transistor, effectively compressing the vertical design space occupied by the sub-pixel driving circuit. Furthermore, since the gate T2-g of the compensation transistor is coupled to the first scan line GA1, the first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate T3-g of the driving transistor, meaning the compensation transistor itself is coupled to both the first scan line GA1 and the driving transistor, placing at least a portion of the compensation active layer 22 in the area between the first scan line GA1 and the gate T3-g of the driving transistor will not cause defects due to potential differences between them.

[0099] As shown in Figures 3, 4, 7 to 13, in some embodiments, the display substrate further includes a data line DA and a second scan line GA2, the second scan line GA2 including at least a portion extending along the first direction, the sub-pixel driving circuit further includes a data writing transistor (i.e., the fourth transistor T4), the gate T4-g of the data writing transistor is coupled to the corresponding second scan line GA2, the first terminal of the data writing transistor is coupled to the corresponding data line DA, and the second terminal of the data writing transistor is coupled to the first terminal of the driving transistor;

[0100] As shown in Figure 3, in the same sub-pixel, the gate T4-g of the data writing transistor is located on the side of the first scan line GA1 facing the gate T3-g of the driving transistor.

[0101] For example, the display substrate further includes a plurality of data lines DA and a plurality of second scan lines GA2. The plurality of data lines DA are arranged along the first direction, and each data line DA includes at least a portion extending along the second direction. The plurality of second scan lines GA2 are arranged along the second direction, and each second scan line GA2 includes at least a portion arranged along the first direction.

[0102] For example, the multiple data lines DA correspond one-to-one with the multiple columns of sub-pixel driving circuits, and the data lines DA are respectively coupled to each sub-pixel driving circuit in the corresponding column of sub-pixel driving circuits. The second scan line GA2 is respectively coupled to each sub-pixel driving circuit in the corresponding row of sub-pixel driving circuits.

[0103] For example, the first scan line GA1 and the second scan line GA2 are independent of each other and can independently control the transmission of the scan signal. The first scan line GA1 controls the on or off state of the compensation transistor, and the second scan line GA2 controls the on or off state of the data writing transistor. Therefore, the compensation transistor and the data writing transistor can be driven independently.

[0104] For example, the compensation transistor and the data writing transistor are driven independently, and the refresh rate and data signal writing are controlled by the data writing transistor. The compensation transistor is driven by a set of light-emitting control shift register units (EM GOA). Since the priority level time of the scan signal output by the EMGOA is relatively long, the Vth sampling time can be increased, thereby improving the compensation rate and the low grayscale uniformity of the display substrate.

[0105] In the display substrate provided by the above embodiments, the compensation transistor and the data writing transistor can be controlled independently, achieving a high compensation rate and low grayscale display uniformity. By setting them in the same sub-pixel, the gate T4-g of the data writing transistor is located on the side of the first scan line GA1 facing the gate T3-g of the driving transistor. This not only avoids the layout position conflict between the gate T4-g of the data writing transistor and the first scan line GA1, but also effectively compresses the vertical design space occupied by the sub-pixel driving circuit, which is beneficial to the development of high resolution of the display substrate.

[0106] As shown in Figures 2 to 4, in some embodiments, the data writing transistor includes a data active layer 24, and the gate T4-g of the data writing transistor includes a gate body portion T4-g1 and a gate extension portion T4-g2 coupled to each other. The orthographic projection of the gate body portion T4-g1 on the substrate at least partially overlaps with the orthographic projection of the data active layer 24 on the substrate, and the gate extension portion T4-g2 is coupled to the corresponding second scan line GA2.

[0107] The gate body portion T4-g1 and the gate T3-g of the driving transistor are arranged along a first direction, and at least a portion of the gate extension portion T4-g2 is arranged along a second direction with the gate T3-g of the driving transistor, wherein the first direction and the second direction intersect; the gate body portion T4-g1 and the gate extension portion T4-g2 are disposed in the same layer or in different layers.

[0108] For example, the gate extension T4-g2 can be part of the first scan line GA1, that is, the gate extension T4-g2 is located in the first source / drain metal layer, or the gate extension T4-g2 can also be located in other film layers, such as the second gate metal layer.

[0109] For example, the gate body portion T4-g1 and the gate extension portion T4-g2 are formed as an integral structure. The gate body portion T4-g1 includes at least a portion extending along the first direction, and the gate extension portion T4-g2 includes at least a portion extending along a third direction, which intersects the first direction and the second direction.

[0110] For example, the orthographic projection of the gate extension T4-g2 on the substrate does not overlap with the orthographic projection of the data active layer 24 on the substrate.

[0111] The above arrangement allows the gate T4-g of the data writing transistor to be positioned around the gate T3-g of the driving transistor, and to be positioned along the boundary extension direction of the gate T3-g of the driving transistor, thereby maximizing the use of the surrounding space of the gate T3-g of the driving transistor and facilitating the development of high resolution of the display substrate.

[0112] As shown in Figures 4, 6, 8 and 9, in some embodiments, the sub-pixel driving circuit further includes a first conductive connection portion 31 and a first reset transistor (i.e., a first transistor T1). A first end of the first conductive connection portion 31 is coupled to the gate T3-g of the driving transistor, and a second end of the first conductive connection portion 31 is coupled to the second terminal of the first reset transistor. The second scan line GA2 is at least partially disposed around the second end of the first conductive connection portion 31.

[0113] For example, the gate T4-g of the data writing transistor is disposed in the same layer and with the same material as the first scan line GA1, the second scan line GA2 is disposed in a different layer than the first scan line GA1, and the second scan line GA2 is disposed in the same layer and with the same material as the first conductive connection portion 31. The first conductive connection portion 31 is disposed in the same layer and with the same material as the first source / drain metal layer in the display substrate.

[0114] The above-mentioned arrangement of the second scan line GA2 at least partially surrounds the second end of the first conductive connection portion 31, so that the second scan line GA2 can bypass the first conductive connection portion 31. This not only avoids short circuit between the second scan line GA2 and the first conductive connection portion 31, but also ensures that the second scan line GA2 maintains a suitable safe distance from the first conductive connection portion. This prevents the transition of the scan signal transmitted on the second scan line GA2 from affecting the potential of the first conductive connection portion 31, thus ensuring the working stability and reliability of the sub-pixel driving circuit.

[0115] As shown in Figures 4, 6, 7, 8, and 9, in some embodiments, the second scan line GA2 includes a plurality of straight-edge portions GA21 and a plurality of curved-edge portions GA22. The straight-edge portions GA21 and the curved-edge portions GA22 are alternately arranged along a first direction. The curved-edge portions GA22 are arranged around the second end of the first conductive connection portion 31. The straight-edge portion GA21 includes a protruding end GA21-T. At least a portion of the orthographic projection of the protruding end GA21-T on the substrate is arranged along a second direction with the orthographic projection of the gate T3-g of the driving transistor on the substrate. The protruding end GA21-T is coupled to the gate T4-g of the data writing transistor.

[0116] For example, the adjacent straight edge portion GA21 and the curved edge portion GA22 are coupled together, and the straight edge portion GA21 and the curved edge portion GA22 are formed as an integral structure.

[0117] For example, the curved edge portion GA22 partially surrounds the second end of the first conductive connection portion 31. The straight edge portion GA21 includes at least a portion extending along the first direction. The first conductive connection portion 31 includes at least a portion extending along the second direction.

[0118] For example, at least a portion of the orthographic projection of the protruding end GA21-T on the substrate is located between the orthographic projection of the curved portion GA22 on the substrate and the orthographic projection of the gate T3-g of the driving transistor on the substrate.

[0119] For example, the orthographic projection of the protruding end GA21-T on the substrate has an overlapping area with the orthographic projection of the gate extension T4-g2 on the substrate, and the protruding end GA21-T and the gate extension T4-g2 are coupled through a via in the overlapping area.

[0120] The above configuration allows the curved edge portion GA22 of the second scan line GA2 to form a "gate"-like routing pattern, preventing the transitions of the scan signal transmitted on the second scan line GA2 from affecting the potential of the first conductive connection portion 31, thus ensuring the operational stability and reliability of the sub-pixel driving circuit. It also ensures the electrical connection between the second scan line GA2 and the gate T4-g of the data writing transistor.

[0121] As shown in Figures 8 and 12, in some embodiments, the display substrate includes a reset signal line RST, the gate of the first reset transistor is coupled to the corresponding reset signal line RST, the orthographic projection of the curved edge portion GA22 on the substrate overlaps with the orthographic projection portion of the reset signal line RST on the substrate; and / or, the orthographic projection of the curved edge portion GA22 on the substrate overlaps with the orthographic projection portion of the first scan line GA1 on the substrate.

[0122] For example, the display substrate includes multiple reset signal lines RST, which are arranged along the second direction, and each reset signal line RST includes at least a portion extending along the first direction. Each of the multiple reset signal lines RST corresponds one-to-one with a multi-row sub-pixel driving circuit, and each reset signal line RST is coupled to each sub-pixel driving circuit in its corresponding row of sub-pixel driving circuits.

[0123] For example, the overlap area between the orthographic projection of the curved portion GA22 on the substrate and the orthographic projection of the reset signal line RST on the substrate is less than or equal to 10% of the area of ​​the curved portion GA22. Further, the overlap area between the orthographic projection of the curved portion GA22 on the substrate and the orthographic projection of the reset signal line RST on the substrate may be less than or equal to 5% of the area of ​​the curved portion GA22.

[0124] For example, the overlap area between the orthographic projection of the curved edge portion GA22 on the substrate and the orthographic projection of the first scan line GA1 on the substrate is less than or equal to 30% of the area of ​​the curved edge portion GA22. Further, the overlap area between the orthographic projection of the curved edge portion GA22 on the substrate and the orthographic projection of the first scan line GA1 on the substrate may be set to be less than or equal to 20% of the area of ​​the curved edge portion GA22.

[0125] The above configuration can minimize crosstalk between the second scan line GA2 and the reset signal line RST, as well as crosstalk between the second scan line GA2 and the first scan line GA1.

[0126] As shown in Figures 7, 8, 10 and 11, in some embodiments, the display substrate further includes a power line VDD, the orthographic projection of the power line VDD on the substrate having a first overlapping area with the orthographic projection of the first conductive connection portion 31 on the substrate, the first overlapping area being greater than or equal to 80% of the area of ​​the first conductive connection portion 31.

[0127] For example, the first overlapping area is greater than or equal to 90% of the area of ​​the first conductive connection portion 31.

[0128] For example, the display substrate includes multiple power lines VDD, which are arranged along the first direction and include at least a portion extending along the second direction. Each of the multiple power lines VDD corresponds to one of the multiple columns of sub-pixel driving circuits, and each power line VDD is coupled to each sub-pixel driving circuit in its corresponding column.

[0129] For example, the power line VDD is disposed in the same layer and with the same material as the source and drain metal layers in the display substrate.

[0130] The aforementioned setting ensures that the first overlapping area is greater than or equal to 80% of the area of ​​the first conductive connection portion 31, enabling the power line VDD to better shield the potential on the first conductive connection portion 31 (i.e., the potential of node N1). Therefore, in the display substrate provided by the above embodiment, a reasonable layout can achieve better shielding of the potential of node N1 through the power line VDD, reducing the risk of crosstalk in the sub-pixel driving circuit during the display process.

[0131] As shown in Figures 10 to 12, in some embodiments, the display substrate further includes a first initialization signal line Vinit1, the first initialization signal line Vinit1 including at least a portion extending along a second direction; the first electrode of the first reset transistor is coupled to the first initialization signal line Vinit1.

[0132] For example, the display substrate includes a plurality of first initialization signal lines Vinit1, which are arranged along a first direction. Each first initialization signal line Vinit1 includes at least a portion extending along a second direction. Each first initialization signal line Vinit1 corresponds one-to-one with a plurality of sub-pixel driving circuits, and each first initialization signal line Vinit1 is coupled to each sub-pixel driving circuit in the corresponding column of sub-pixel driving circuits.

[0133] For example, the orthographic projection of the first initialization signal line Vinit1 on the substrate is located between the orthographic projection of the gate T3-g of the driving transistor on the substrate and the orthographic projection of the data line DA on the substrate. By arranging the first initialization signal line Vinit1 in the above manner, the crosstalk generated by the transition of the data signal transmitted on the data line DA to the N1 node can be shielded by the first initialization signal line Vinit1.

[0134] For example, the display substrate further includes a power line VDD and a first initialization signal line Vinit1. The power line VDD and the data line DA are disposed on the same layer and made of the same material, and the first initialization signal line Vinit1 is located between the power line VDD and the data line DA. For example, the first initialization signal line Vinit1 is disposed on the same layer and made of the same material as the second source / drain metal layer in the display substrate.

[0135] For example, the overlap area between the orthographic projection of the power line VDD on the substrate and the underlying metal layer (such as the light-shielding layer LS, the first gate metal layer, the second gate metal layer, and the first source / drain metal layer) is greater than or equal to 50% of the area of ​​the power line VDD. Further, the overlap area between the orthographic projection of the power line VDD on the substrate and the underlying metal layer can be set to be greater than or equal to 70% of the area of ​​the power line VDD, but is not limited to this. The above configuration is beneficial for improving the transmittance of high-resolution display substrates.

[0136] As shown in Figures 4 to 11, in some embodiments, the display substrate further includes a second initialization signal line Vinit2, a third initialization signal line Vinit3, and a third scan line GA3, wherein the third scan line GA3 includes at least a portion extending along the first direction; the sub-pixel further includes a light-emitting element; the sub-pixel driving circuit further includes a second reset transistor (i.e., a seventh transistor T7) and a third reset transistor (i.e., an eighth transistor T8), wherein the gate of the second reset transistor and the gate of the third reset transistor are both coupled to the same corresponding third scan line GA3; the first terminal of the second reset transistor is coupled to the second initialization signal line Vinit2, and the second terminal of the second reset transistor is coupled to the anode Ano of the light-emitting element; the first terminal of the third reset transistor is coupled to the third initialization signal line Vinit3, and the second terminal of the third reset transistor is coupled to the first terminal of the driving transistor.

[0137] For example, the display substrate further includes a plurality of second initialization signal lines Vinit2, which are arranged along a second direction and include at least a portion extending along the first direction. Each of the plurality of second initialization signal lines Vinit2 corresponds to one of the multi-row sub-pixel driving circuits, and each second initialization signal line Vinit2 is coupled to a second reset transistor in a corresponding row of sub-pixel driving circuits.

[0138] For example, the display substrate further includes a plurality of third initialization signal lines Vinit3, which are arranged along a second direction and include at least a portion extending along the first direction. Each of the plurality of third initialization signal lines Vinit3 corresponds one-to-one with a multi-row sub-pixel driving circuit, and each third initialization signal line Vinit3 is coupled to a third reset transistor in a corresponding row of sub-pixel driving circuit.

[0139] For example, the display substrate further includes a plurality of third scan lines GA3, which are arranged along the second direction and include at least a portion extending along the first direction. The plurality of third scan lines GA3 are coupled to the multi-row sub-pixel driving circuit, and are respectively coupled to the gate of each second reset transistor and the gate of each third reset transistor in the corresponding row sub-pixel driving circuit.

[0140] By using the second initialization signal transmitted through the second initialization signal line Vinit2 to reset the anode (i.e., node N4) of the light-emitting element, the luminous brightness of the sub-pixels can be guaranteed during low grayscale display. By setting the second initialization signal line Vinit2 to the same layer and material as the first source / drain metal layer in the display substrate, the conductivity of the second initialization signal line Vinit2 is improved, which is beneficial to improving the display uniformity of the display substrate.

[0141] In some embodiments, the second scan line is disposed on a different layer from the first scan line, and the orthographic projection of the second scan line on the substrate at least partially overlaps with the orthographic projection of the first scan line on the substrate.

[0142] For example, the display substrate includes a second gate metal layer and a first source / drain metal layer, the second initialization signal line is disposed in the same layer and with the same material as the first source / drain metal layer, and the third initialization signal line is disposed in the same layer and with the same material as the second gate metal layer.

[0143] The second initialization signal line and the third initialization signal line are made of different layers of metal. This allows the second initialization signal line and the third initialization signal line, which are both used to transmit constant voltage signals, to adopt a stacked routing design. That is, the orthographic projection of the second initialization signal line on the substrate and the orthographic projection of the third initialization signal line on the substrate at least partially overlap, which is beneficial to improving the transmittance of the display substrate.

[0144] As shown in Figures 2, 4, 6 and 8, in some embodiments, the display substrate further includes a power line VDD; the first reset transistor includes a first reset active layer 21, the first reset active layer 21 includes a third channel portion 213, a fourth channel portion 214 and a second conductor portion 215, the second conductor portion 215 being coupled to the third channel portion 213 and the fourth channel portion 214 respectively;

[0145] The orthographic projection of the second conductor portion 215 on the substrate at least partially overlaps with the orthographic projection of the second initialization signal line Vinit2 on the substrate; and / or, the orthographic projection of the second conductor portion 215 on the substrate at least partially overlaps with the orthographic projection of the third initialization signal line Vinit3 on the substrate; and / or, the orthographic projection of the second conductor portion 215 on the substrate at least partially overlaps with the orthographic projection of the power line VDD on the substrate.

[0146] For example, the first reset transistor includes a dual-gate transistor, the orthographic projection of the gate of the first reset transistor on the substrate covers the orthographic projection of the third channel portion 213 on the substrate and the orthographic projection of the fourth channel portion 214 on the substrate. The second conductor portion 215 is formed integrally with the third channel portion 213 and the fourth channel portion 214. For example, the second conductor portion 215 forms an n-type structure with the third channel portion 213 and the fourth channel portion 214, the third channel portion 213 and the fourth channel portion 214 being arranged along the first direction.

[0147] The above configuration allows the second conductor portion 215 to be shielded by the second initialization signal line Vinit2 and / or the third initialization signal line Vinit3, which helps to improve the working stability of the first reset transistor.

[0148] As shown in Figures 2, 5, and 6, in some embodiments, the display substrate further includes a power line VDD and a first conductive connection portion 31. A first end of the first conductive connection portion 31 is coupled to the gate T3-g of the driving transistor, and a second end of the first conductive connection portion 31 is coupled to the second terminal of the compensation transistor. The sub-pixel driving circuit further includes a storage capacitor Cst. The first plate Cst1 of the storage capacitor Cst is coupled to the gate T3-g of the driving transistor, and the second plate Cst2 of the storage capacitor Cst is coupled to the corresponding power line VDD.

[0149] The compensation active layer 22 further includes a conductor extension 224, which is coupled to the first conductor portion 223. The orthographic projection of the conductor extension 224 on the substrate at least partially overlaps with the orthographic projection of the second electrode Cst2 on the substrate; and / or

[0150] The orthographic projection of the first conductor portion 223 on the substrate does not overlap with the orthographic projection of the first conductive connection portion 31 on the substrate; and / or,

[0151] The orthographic projection of the second electrode plate Cst2 on the substrate overlaps at least partially with the orthographic projection of the first conductor portion 223 on the substrate.

[0152] For example, the orthographic projection of the first electrode plate Cst1 on the substrate overlaps at least partially with the orthographic projection of the second electrode plate Cst2 on the substrate.

[0153] For example, the conductor extension 224 is formed as an integral structure with the first conductor portion 223.

[0154] For example, the orthographic projection of the conductor extension 224 on the substrate is located between the orthographic projection of the first conductor portion 223 on the substrate and the orthographic projection of the gate T3-g of the driving transistor on the substrate.

[0155] The above configuration increases the capacitance formed by the first conductor portion 223. This configuration is beneficial to improving the capacitance formed by the first conductor portion 223 during the light emission stage, and can also increase the stability of the node voltage of the first conductor portion 223, effectively improving the low-frequency flicker problem.

[0156] As shown in Figures 1, 2 and 13, in some embodiments, the display substrate further includes a light-shielding layer LS, the orthographic projection of the light-shielding layer LS on the substrate at least partially overlaps with the orthographic projection of the active layer 23 of the driving transistor on the substrate, and at least partially overlaps with the orthographic projection of the compensation active layer 22 on the substrate.

[0157] For example, the light-shielding layer LS is connected to a power signal. The light-shielding layer LS is located between the active layer and the substrate.

[0158] The above configuration enables the light-shielding layer LS to block and shield the active layer 23 of the driving transistor and the compensation active layer 22, thereby improving the working stability of the driving transistor and the compensation transistor.

[0159] For example, the overlap area between the orthographic projection of the light-shielding layer LS on the substrate and the orthographic projection of the metal layer in the display substrate on the substrate is greater than or equal to 60% of the area of ​​the light-shielding layer LS. Further, the overlap area between the orthographic projection of the light-shielding layer LS on the substrate and the orthographic projection of the metal layer in the display substrate on the substrate can be set to be greater than or equal to 80% of the area of ​​the light-shielding layer LS. This arrangement is beneficial for improving the optical transmittance of the display substrate.

[0160] As shown in Figure 4, in some embodiments, the sub-pixel driving circuit further includes a power control transistor (i.e., the fifth transistor T5) and a light-emitting control transistor (i.e., the sixth transistor T6). The display substrate also includes multiple light-emitting control signal lines EM, which are arranged along the second direction, and each light-emitting control signal line EM includes at least a portion extending along the first direction. Each of the multiple light-emitting control signal lines EM corresponds one-to-one with the multiple rows of sub-pixel driving circuits, and each light-emitting control signal line EM is coupled to each power control transistor and each light-emitting control transistor in the corresponding row of sub-pixel driving circuits.

[0161] As shown in Figures 12, 13, 16, 17, and 18, in some embodiments, the sub-pixel further includes a light-emitting element, which includes an anode Ano; the sub-pixel driving circuit further includes a light-emitting control transistor and a second conductive connection portion 32, wherein the first terminal of the light-emitting control transistor is coupled to the second terminal of the driving transistor, the first end of the second conductive connection portion 32 is coupled to the second terminal of the light-emitting control transistor, and the second end of the second conductive connection portion 32 is coupled to the anode Ano through a first via Via1;

[0162] The sub-pixel also includes a pixel opening region 40, the orthographic projection of the pixel opening region 40 on the substrate does not overlap with the orthographic projection of the first via Via1 on the substrate.

[0163] For example, the display substrate includes a pixel defining layer that defines the pixel opening region 40.

[0164] The above-mentioned setting ensures that the orthographic projection of the pixel opening area 40 on the substrate does not overlap with the orthographic projection of the first via Via1 on the substrate, which helps to improve the flatness of the anode Ano in the sub-pixel, thereby improving the display uniformity of the display substrate.

[0165] As shown in Figures 2, 4, 17, and 18, in some embodiments, the sub-pixel further includes a light-emitting element, the light-emitting element including an anode Ano; at least some of the sub-pixels' anode Ano includes an anode main portion Ano1 and an anode virtual portion Ano2; the orthographic projection of the anode main portion Ano1 on the substrate at least partially overlaps with the orthographic projection of the compensation active layer 22 included in its subordinate sub-pixel on the substrate; the orthographic projection of the anode virtual portion Ano2 on the substrate at least partially overlaps with the orthographic projection of the compensation active layer 22 included in its adjacent sub-pixel along the first direction on the substrate.

[0166] For example, the anode body portion Ano1 and the anode virtual portion Ano2 are formed as an integral structure.

[0167] For example, the orthographic projection of the anode main body portion Ano1 on the substrate at least partially overlaps with the orthographic projection of the first conductor portion 223 in the compensation active layer 22 of its subordinate sub-pixel on the substrate. The orthographic projection of the anode main body portion Ano1 on the substrate at least partially overlaps with the orthographic projection of the first channel portion 221 in the compensation active layer 22 of its subordinate sub-pixel on the substrate. The orthographic projection of the anode main body portion Ano1 on the substrate at least partially overlaps with the orthographic projection of the second channel portion 222 in the compensation active layer 22 of its subordinate sub-pixel on the substrate.

[0168] For example, the orthographic projection of the anode virtual portion Ano2 on the substrate at least partially overlaps with the orthographic projection of the first conductor portion 223 in the compensation active layer 22 of the sub-pixel adjacent to it along the first direction on the substrate. The orthographic projection of the anode virtual portion Ano2 on the substrate at least partially overlaps with the orthographic projection of the first channel portion 221 in the compensation active layer 22 of the sub-pixel adjacent to it along the first direction on the substrate. The orthographic projection of the anode virtual portion Ano2 on the substrate at least partially overlaps with the orthographic projection of the second channel portion 222 in the compensation active layer 22 of the sub-pixel adjacent to it along the first direction on the substrate.

[0169] In the display substrate provided in the above embodiments, the corresponding compensation active layer 22 is shielded by the anode main body Ano1 and the anode virtual part Ano2, which can effectively prevent the display substrate from displaying abnormalities under strong light.

[0170] In some embodiments, the display substrate includes red sub-pixels, green sub-pixels, and blue sub-pixels; at least some of the sub-pixels include red sub-pixels and blue sub-pixels, and the adjacent sub-pixels include green sub-pixels.

[0171] For example, the orthographic projection of the anode main portion Ano1 in the red sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the compensation active layer 22 included in its sub-pixel onto the substrate; the orthographic projection of the anode virtual portion Ano2 in the red sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the compensation active layer 22 included in the adjacent green sub-pixel along the first direction onto the substrate.

[0172] For example, the orthographic projection of the anode main portion Ano1 in the blue sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the compensation active layer 22 included in its sub-pixel onto the substrate; the orthographic projection of the anode virtual portion Ano2 in the blue sub-pixel onto the substrate at least partially overlaps with the orthographic projection of the compensation active layer 22 included in the adjacent green sub-pixel along the first direction onto the substrate.

[0173] As shown in Figure 21, exemplarily, the display substrate includes, sequentially stacked along a direction away from the substrate 70, a buffer layer BF, an active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, an anode layer ANO, a light-emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, etc. The display substrate may also include a passivation layer PVX, but is not limited thereto.

[0174] As shown in Figure 2, the active layer 25 of the power control transistor, the active layer 26 of the light emission control transistor, the active layer 27 of the second reset transistor, and the active layer 28 of the third reset transistor are illustrated in Figure 2.

[0175] As shown in Figures 7 and 14 to 16, Figure 7 illustrates the third conductive connection 33, the fourth conductive connection 34, the fifth conductive connection 35, the sixth conductive connection 36, the seventh conductive connection 37, and the eighth conductive connection 38.

[0176] The third conductive connection part 33 is coupled to the second plate Cst2 of the storage capacitor Cst through the ninth via Via9, the third conductive connection part 33 is coupled to the second electrode of the power control transistor through the twelfth via Via12, and the third conductive connection part 33 is coupled to the power line VDD through the fifteenth via Via15.

[0177] The fourth conductive connection portion 34 is coupled to the first terminal of the driving transistor through the tenth via Via10, and the fourth conductive connection portion 34 is coupled to the second terminal of the third reset transistor through the thirteenth via Via13.

[0178] The fifth conductive connection part 35 is coupled to the second electrode of the light-emitting control transistor through the eleventh via Via11, and the fifth conductive connection part 35 is coupled to the second conductive connection part 32 through the eighteenth via Via18. The second conductive connection part 32 is coupled to the anode corresponding to the first via Via1.

[0179] The sixth conductive connection portion 36 is coupled to the first terminal of the data writing transistor through the seventh via Via7, and the sixth conductive connection portion 36 is coupled to the data line DA through the seventeenth via Via17.

[0180] The seventh conductive connection part 37 is coupled to the first pole of the first reset transistor through the fourth via Via4, and the seventh conductive connection part 37 is coupled to the first initialization signal line Vinit1 through the sixteenth via Via16.

[0181] The eighth conductive connection part 38 is coupled to the third initialization signal line Vinit3 through the second via Via2, and the eighth conductive connection part 38 is coupled to the first pole of the eighth transistor T8 through the third via Via3.

[0182] The first conductive connection portion 31 is coupled to the second terminal of the first reset transistor through the fifth via Via5, and the first conductive connection portion 31 is coupled to the gate T3-g of the driving transistor through the eighth via Via8.

[0183] The gate T4-g of the data writing transistor is coupled to the second scan line GA2 through the sixth via Via6.

[0184] The first terminal of the second reset transistor is coupled to the second initialization signal line Vinit2 through the fourteenth via Via14.

[0185] This disclosure also provides a display substrate, including: a substrate and a plurality of sub-pixels, a second scan line, and a data line all disposed on the substrate. The second scan line includes at least a portion extending along a first direction. Each sub-pixel includes a sub-pixel driving circuit, which includes a first conductive connection portion, a driving transistor, a compensation transistor, and a data writing transistor.

[0186] The first terminal of the compensation transistor is coupled to the second terminal of the driving transistor, and the second terminal of the compensation transistor is coupled to the gate of the driving transistor through the first conductive connection portion; the compensation transistor includes a compensation active layer, the compensation active layer includes a first channel portion, a second channel portion and a first conductor portion, the first conductor portion being coupled to the first channel portion and the second channel portion respectively; at least a portion of the orthographic projection of the first conductor portion on the substrate is located between the orthographic projection of the second scan line on the substrate and the orthographic projection of the gate of the driving transistor on the substrate;

[0187] The gate of the data writing transistor is coupled to the corresponding second scan line, the first electrode of the data writing transistor is coupled to the corresponding data line, and the second electrode of the data writing transistor is coupled to the first electrode of the driving transistor; at least a portion of the second scan line is arranged around one end of the first conductive connection portion.

[0188] As can be seen from the specific structure of the display substrate described above, in the display substrate provided in this embodiment, at least a portion of the orthogonal projection of the first conductor portion on the substrate is located between the orthogonal projection of the second scan line on the substrate and the orthogonal projection of the gate of the driving transistor on the substrate. Compared with the conventional layout, the above arrangement allows the compensation transistor to be formed as a double-gate inverted structure. That is, within the same sub-pixel driving circuit layout area, both the first conductor portion and the first compensation gate can be located in the area between the second scan line and the gate of the driving transistor, effectively compressing the vertical design space occupied by the sub-pixel driving circuit, which is beneficial to the high resolution development of the display substrate.

[0189] In the display substrate provided in this embodiment, at least a portion of the second scan line is arranged around one end of the first conductive connection portion, so that the second scan line can bypass the first conductive connection portion. This not only avoids short circuit between the second scan line and the first conductive connection portion, but also ensures that the second scan line maintains a suitable safe distance from the first conductive connection portion. This prevents the jump of the scan signal transmitted on the second scan line from affecting the potential of the first conductive connection portion, thus ensuring the working stability and reliability of the sub-pixel driving circuit.

[0190] In some embodiments, the display substrate further includes a power line; the sub-pixel driving circuit further includes a storage capacitor, a first plate of the storage capacitor being coupled to the gate of the driving transistor, and a second plate of the storage capacitor being coupled to a corresponding power line; the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the first conductor portion on the substrate; and / or,

[0191] The orthographic projection of the first conductor portion on the substrate overlaps at least partially with the orthographic projection of the first conductive connection portion on the substrate.

[0192] The above configuration helps to increase the capacitance formed by the first conductor portion during the light-emitting stage, and at the same time increases the stability of the node voltage of the first conductor portion and the voltage stability of the first conductive connection portion, which can effectively improve the low-frequency flicker problem.

[0193] In some embodiments, the display substrate further includes a power line; the sub-pixel driving circuit further includes a storage capacitor, a first plate of the storage capacitor being coupled to the gate of the driving transistor, and a second plate of the storage capacitor being coupled to a corresponding power line; the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the first conductor portion on the substrate; and / or,

[0194] The orthographic projection of the first conductor portion onto the substrate does not overlap with the orthographic projection of the first conductive connection portion onto the substrate; and / or,

[0195] The orthographic projection of the first conductor portion onto the substrate at least partially overlaps with the orthographic projection of the power line onto the substrate; and / or,

[0196] The orthographic projection of the first conductive connection portion on the substrate overlaps at least partially with the orthographic projection of the power line on the substrate.

[0197] It is worth noting that the specific structure of the first conductive connection portion 31 in the above embodiment can be seen in FIG22, but is not limited to this structure.

[0198] The above configuration helps to increase the capacitance formed by the first conductor portion during the light-emitting stage, and at the same time increases the stability of the node voltage of the first conductor portion and the voltage stability of the first conductive connection portion, which can effectively improve the low-frequency flicker problem.

[0199] This disclosure also provides a display device, including the display substrate provided in the above embodiments.

[0200] In the display substrate provided in the above embodiments, the compensation transistor includes a compensation active layer. At least a portion of the orthographic projection of the first conductor portion of the compensation active layer onto the substrate is located between the orthographic projection of the first scan line onto the substrate and the orthographic projection of the gate of the driving transistor onto the substrate. Compared with conventional layout methods, the above arrangement allows the compensation transistor to be formed as a double-gate inverted structure. That is, within the same sub-pixel driving circuit layout area, both the first conductor portion and the first compensation gate can be disposed in the area between the first scan line and the gate of the driving transistor, effectively compressing the vertical design space occupied by the sub-pixel driving circuit, which is beneficial to the development of high resolution of the display substrate. Moreover, since the gate of the compensation transistor is coupled to the first scan line, the first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor, that is, the compensation transistor itself is coupled to the first scan line and the driving transistor, therefore, disposing at least a portion of the compensation active layer in the area between the first scan line and the gate of the driving transistor will not cause defects due to the difference in their potentials. Therefore, the display substrate provided in the above embodiments takes into account the working principle, working state, and possible defects of the sub-pixel driving circuit and signal lines, and makes reasonable arrangements for the design, thereby improving the resolution and avoiding defects.

[0201] The display device provided in this disclosure, when including the above-described display substrate, also has the above-described beneficial effects, which will not be repeated here.

[0202] It should be noted that the signal line extending along the X direction means that the signal line includes a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along the X direction, and the length of the main part extending along the X direction is greater than the length of the secondary part extending in other directions.

[0203] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0204] It should be noted that the layout area occupied by the sub-pixel driving circuit can be a region capable of accommodating the sub-pixel driving circuit. For example, this region can be a rectangular region, but it is not limited to this.

[0205] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0206] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0207] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0208] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0209] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0210] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0211] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising: The substrate and a plurality of sub-pixels and a first scan line are disposed on the substrate. The first scan line includes at least a portion extending along a first direction. The sub-pixel includes a sub-pixel driving circuit. The sub-pixel driving circuit includes a driving transistor and a compensation transistor. The gate of the compensation transistor is coupled to the corresponding first scan line. The first electrode of the compensation transistor is coupled to the second electrode of the driving transistor. The second electrode of the compensation transistor is coupled to the gate of the driving transistor. The compensation transistor includes a compensation active layer, which includes a first channel portion, a second channel portion, and a first conductor portion. The first conductor portion is coupled to the first channel portion and the second channel portion, respectively. At least a portion of the orthographic projection of the first conductor portion on the substrate is located between the orthographic projection of the first scan line on the substrate and the orthographic projection of the gate of the driving transistor on the substrate.

2. The display substrate according to claim 1, wherein, The compensation transistor includes a first compensation gate and a second compensation gate, wherein the orthographic projection of the first compensation gate on the substrate covers the orthographic projection of the first channel portion on the substrate, and the orthographic projection of the second compensation gate on the substrate covers the orthographic projection of the second channel portion on the substrate. The first compensation gate is coupled to the corresponding first scan line, and at least a portion of the first compensation gate is located between the coupled first scan line and the gate of the driving transistor, wherein the first scan line is multiplexed as the second compensation gate.

3. The display substrate according to claim 1, wherein, The display substrate further includes a data line and a second scan line, the second scan line including at least a portion extending along the first direction, the sub-pixel driving circuit further includes a data writing transistor, the gate of the data writing transistor is coupled to the corresponding second scan line, the first electrode of the data writing transistor is coupled to the corresponding data line, and the second electrode of the data writing transistor is coupled to the first electrode of the driving transistor. Within the same sub-pixel, the gate of the data writing transistor is located on the side of the first scan line facing the gate of the driving transistor.

4. The display substrate according to claim 3, wherein, The data writing transistor includes a data active layer, and the gate of the data writing transistor includes a gate body portion and a gate extension portion coupled to each other. The orthographic projection of the gate body portion on the substrate overlaps at least partially with the orthographic projection of the data active layer on the substrate. The gate extension portion is coupled to the corresponding second scan line. The gate body portion and the gate of the driving transistor are arranged along a first direction, and at least a portion of the gate extension portion is arranged along a second direction with the gate of the driving transistor, wherein the first direction and the second direction intersect. The gate body portion and the gate extension portion are disposed in the same layer or in different layers.

5. The display substrate according to claim 3, wherein, The sub-pixel driving circuit further includes a first conductive connection portion and a first reset transistor. A first end of the first conductive connection portion is coupled to the gate of the driving transistor, and a second end of the first conductive connection portion is coupled to the second terminal of the first reset transistor. The second scan line is at least partially disposed around the second end of the first conductive connection portion.

6. The display substrate according to claim 5, wherein, The gate of the data writing transistor is disposed in the same layer and with the same material as the first scan line, the second scan line is disposed in a different layer from the first scan line, and the second scan line is disposed in the same layer and with the same material as the first conductive connection portion.

7. The display substrate according to claim 5, wherein, The second scan line includes a plurality of straight edges and a plurality of curved edges, the straight edges and the curved edges being alternately arranged along a first direction, the curved edges being arranged around the second end of the first conductive connection portion, the straight edges including a protruding end, at least a portion of the orthographic projection of the protruding end on the substrate being arranged along a second direction with the orthographic projection of the gate of the driving transistor on the substrate, and the protruding end being coupled to the gate of the data writing transistor.

8. The display substrate according to claim 5, wherein, The display substrate further includes a first initialization signal line, the first initialization signal line including at least a portion extending along a second direction; the first electrode of the first reset transistor is coupled to the first initialization signal line; The orthographic projection of the first initialization signal line on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the data line on the substrate.

9. The display substrate according to claim 8, wherein, The display substrate further includes a power line and a first initialization signal line. The power line and the data line are disposed on the same layer and made of the same material, and the first initialization signal line is located between the power line and the data line.

10. The display substrate according to claim 5, wherein, The display substrate further includes a second initialization signal line, a third initialization signal line, and a third scan line, the third scan line including at least a portion extending along the first direction; the sub-pixel further includes a light-emitting element; the sub-pixel driving circuit further includes a second reset transistor and a third reset transistor, the gate of the second reset transistor and the gate of the third reset transistor are both coupled to the same corresponding third scan line; the first electrode of the second reset transistor is coupled to the second initialization signal line, and the second electrode of the second reset transistor is coupled to the anode of the light-emitting element; the first electrode of the third reset transistor is coupled to the third initialization signal line, and the second electrode of the third reset transistor is coupled to the first electrode of the driving transistor.

11. The display substrate according to claim 10, wherein, The second scan line is disposed on a different layer from the first scan line, and the orthographic projection of the second scan line on the substrate overlaps at least partially with the orthographic projection of the first scan line on the substrate. The display substrate includes a second gate metal layer and a first source / drain metal layer. The second initialization signal line is disposed in the same layer and with the same material as the first source / drain metal layer. The third initialization signal line is disposed in the same layer and with the same material as the second gate metal layer.

12. The display substrate according to claim 10, wherein, The display substrate further includes a power line; the first reset transistor includes a first reset active layer, the first reset active layer includes a third channel portion, a fourth channel portion and a second conductor portion, the second conductor portion being coupled to the third channel portion and the fourth channel portion respectively; The orthographic projection of the second conductor portion onto the substrate at least partially overlaps with the orthographic projection of the second initialization signal line onto the substrate. And / or, the orthographic projection of the second conductor portion on the substrate at least partially overlaps with the orthographic projection of the third initialization signal line on the substrate; And / or, the orthographic projection of the second conductor portion on the substrate at least partially overlaps with the orthographic projection of the power line on the substrate.

13. The display substrate according to claim 1, wherein, The display substrate further includes a power line and a first conductive connection portion, a first end of the first conductive connection portion being coupled to the gate of the driving transistor, and a second end of the first conductive connection portion being coupled to the second electrode of the compensation transistor; the sub-pixel driving circuit further includes a storage capacitor, a first electrode of the storage capacitor being coupled to the gate of the driving transistor, and a second electrode of the storage capacitor being coupled to the corresponding power line. The compensation active layer further includes a conductor extension, which is coupled to the first conductor portion. The orthographic projection of the conductor extension on the substrate at least partially overlaps with the orthographic projection of the second electrode plate on the substrate. And / or, The orthographic projection of the first conductor portion on the substrate does not overlap with the orthographic projection of the first conductive connection portion on the substrate. And / or, The orthographic projection of the second electrode plate on the substrate overlaps at least partially with the orthographic projection of the first conductor portion on the substrate.

14. The display substrate according to claim 1, wherein, The display substrate further includes a light-shielding layer, the orthographic projection of which on the substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor on the substrate, and at least partially overlaps with the orthographic projection of the compensation active layer on the substrate.

15. The display substrate according to claim 1, wherein, The sub-pixel further includes a light-emitting element, which includes an anode; the sub-pixel driving circuit further includes a light-emitting control transistor and a second conductive connection portion, wherein the first terminal of the light-emitting control transistor is coupled to the second terminal of the driving transistor, the first end of the second conductive connection portion is coupled to the second terminal of the light-emitting control transistor, and the second end of the second conductive connection portion is coupled to the anode through a first via. The sub-pixel also includes a pixel opening region, the orthographic projection of which on the substrate does not overlap with the orthographic projection of the first via on the substrate.

16. The display substrate according to claim 1, wherein, The sub-pixel further includes a light-emitting element, which includes an anode; at least some of the sub-pixels have an anode body portion and an anode virtual portion. The orthographic projection of the anode main body on the substrate overlaps at least partially with the orthographic projection of the compensation active layer included in its sub-pixel on the substrate. The orthographic projection of the anode virtual portion onto the substrate at least partially overlaps with the orthographic projection of the compensation active layer included in the sub-pixel adjacent to it along the first direction onto the substrate.

17. The display substrate according to claim 16, wherein, The display substrate includes red sub-pixels, green sub-pixels, and blue sub-pixels; at least some of the sub-pixels include red sub-pixels and blue sub-pixels, and the adjacent sub-pixels include green sub-pixels.

18. A display substrate, comprising: The substrate and a plurality of sub-pixels, a second scan line, and a data line are disposed on the substrate. The second scan line includes at least a portion extending along a first direction. The sub-pixel includes a sub-pixel driving circuit, which includes a first conductive connection portion, a driving transistor, a compensation transistor, and a data writing transistor. The first terminal of the compensation transistor is coupled to the second terminal of the driving transistor, and the second terminal of the compensation transistor is coupled to the gate of the driving transistor through the first conductive connection portion; the compensation transistor includes a compensation active layer, the compensation active layer includes a first channel portion, a second channel portion and a first conductor portion, the first conductor portion being coupled to the first channel portion and the second channel portion respectively; at least a portion of the orthographic projection of the first conductor portion on the substrate is located between the orthographic projection of the second scan line on the substrate and the orthographic projection of the gate of the driving transistor on the substrate; The gate of the data writing transistor is coupled to the corresponding second scan line, the first terminal of the data writing transistor is coupled to the corresponding data line, and the second terminal of the data writing transistor is coupled to the first terminal of the driving transistor. At least a portion of the second scan line is disposed around one end of the first conductive connection portion.

19. The display substrate according to claim 18, wherein, The display substrate further includes a power line; the sub-pixel driving circuit further includes a storage capacitor, the first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the corresponding power line; the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the first conductor portion on the substrate. And / or, The orthographic projection of the first conductor portion on the substrate overlaps at least partially with the orthographic projection of the first conductive connection portion on the substrate.

20. The display substrate according to claim 18, wherein, The display substrate further includes a power line; the sub-pixel driving circuit further includes a storage capacitor, the first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the corresponding power line; the orthographic projection of the second plate on the substrate at least partially overlaps with the orthographic projection of the first conductor portion on the substrate. And / or, The orthographic projection of the first conductor portion on the substrate does not overlap with the orthographic projection of the first conductive connection portion on the substrate. And / or, The orthographic projection of the first conductor portion onto the substrate, and the power line onto the substrate. The orthographic projections on the substrate overlap at least partially.

21. A display device comprising a display substrate as claimed in any one of claims 1 to 20.

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