Heterogeneous multi-core device and scheduling method

Abstract

The present application provides a heterogeneous multi-core device and a scheduling method. The heterogeneous multi-core device comprises a plurality of cores; the plurality of cores comprise at least one high-performance core and at least one energy-efficient core; the maximum power consumption of any core among the at least one high-performance core is greater than that of any core among the at least one energy-efficient core, and the maximum computing power of any core among the at least one high-performance core is higher than that of any core among the at least one energy-efficient core. A first core among the plurality of cores may allocate a first computing resource for a first thread and allocate a second computing resource for a second thread; the first computing resource and the second computing resource belong to a second core among the plurality of cores; the second core is the first core or another core different from the first core. The second core may execute the first thread and the second thread in parallel. The cores in the heterogeneous multi-core device can execute a plurality of threads in parallel by using any type of core, thereby effectively improving the utilization rate of computing resources in the heterogeneous multi-core device.

Description

Heterogeneous multi-core device and scheduling method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on July 28, 2023, with application number 202310945360.8 and application name “A heterogeneous multi-core device and scheduling method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of chip technology, and in particular to a heterogeneous multi-core device and a scheduling method. Background Art

[0004] With the development of electronic technology and the growth of user needs, electronic devices are able to achieve more and more functions. When electronic devices realize different functions, they have different requirements for the computing power of the processor. In order to meet the diverse functional requirements of electronic devices, various types of processor cores (referred to as cores) are set in electronic devices, that is, a heterogeneous multi-core architecture is adopted. In a heterogeneous multi-core architecture, multiple cores with different processing capabilities can be set. For example, energy-efficient cores (i.e., cores with lower power consumption) and high-performance cores (i.e., cores with higher performance) are set. When the computing power required for the thread corresponding to the function to be realized by the electronic device is relatively small, the electronic device uses the energy-efficient core to execute the thread, which can reduce system energy consumption; when the computing power required for the thread corresponding to the function to be realized by the electronic device is relatively large, the electronic device uses the high-performance core to execute the thread, which can better meet the performance requirements of the thread.

[0005] However, the types of processor cores in electronic devices are limited, making it difficult to meet the diverse computing power requirements of various threads, which still leads to performance or power consumption waste in the processor cores of electronic devices.

[0006] Summary of the Invention

[0007] Embodiments of the present application provide a heterogeneous multi-core device and a scheduling method to improve the utilization of computing resources of the heterogeneous multi-core device.

[0008] In a first aspect, an embodiment of the present application provides a heterogeneous multi-core device, which includes multiple cores, the multiple cores including at least one high-performance core and at least one energy-efficiency core, the maximum power consumption of any core of the at least one high-performance core is greater than the maximum power consumption of any core of the at least one energy-efficiency core, and the maximum computing capability of any core of the at least one high-performance core is higher than the maximum computing capability of any core of the at least one energy-efficiency core; wherein, a first core among the multiple cores is used to allocate a first computing resource to a first thread and a second computing resource to a second thread, the first computing resource and the second computing resource belong to a second core among the multiple cores, and the second core is the first core or another core different from the first core; the second core is used to execute the first thread and the second thread in parallel, wherein the first computing resource is used to execute the first thread and the second computing resource is used to execute the second thread.

[0009] The heterogeneous multi-core device may be a chip or a chip module.

[0010] In an embodiment of the present application, the cores in a heterogeneous multi-core device can utilize any type of core to execute multiple threads in parallel, which can effectively improve the utilization rate of computing resources in the heterogeneous multi-core device and thereby effectively improve the peak computing power of the heterogeneous multi-core device.

[0011] In one possible design, the multiple cores also include at least one medium-performance core; the maximum power consumption of any of the at least one high-performance core is greater than the maximum power consumption of any of the at least one medium-performance core, and the maximum computing capability of any of the at least one high-performance core is greater than the maximum computing capability of any of the at least one medium-performance core; and the maximum power consumption of any of the at least one medium-performance core is greater than the maximum power consumption of any of the at least one energy-efficiency core, and the maximum computing capability of any of the at least one medium-performance core is greater than the maximum computing capability of any of the at least one energy-efficiency core. In this design, by providing medium-performance cores in a heterogeneous multi-core device, resource allocation to threads is more flexible, allowing adaptation to the diverse performance requirements of different threads.

[0012] In one possible design, the first core is specifically used to: allocate first computing resources to the first thread on the second core according to the performance requirements of the first thread; and allocate second computing resources to the second thread on the second core according to the performance requirements of the second thread. In this design, computing resources are flexibly allocated to each thread in combination with the performance requirements of each thread, rather than configuring fixed resources for each thread, which can adapt to the diverse needs of different threads. Specifically, the first core can determine the second core among multiple cores, for example, select the second core according to the performance requirements of the first thread and the performance requirements of the second thread, and the performance of the second core can match the performance requirements of the first thread and the performance requirements of the second thread. For another example, first computing resources and second computing resources are respectively allocated to the first thread and the second thread on the second core according to the performance requirements of the first thread and the performance requirements of the second thread, so as to meet the specific performance requirements of the two threads.

[0013] Optionally, the performance requirement of the first thread is characterized by at least one of the delay sensitivity, business scenario, or user experience of the first thread, and the performance requirement of the second thread is characterized by at least one of the delay sensitivity, business scenario, or user experience of the second thread.

[0014] In one possible design, the first computing resource includes a first dedicated computing resource, and the second computing resource includes a second dedicated computing resource that is different from the first dedicated computing resource. The first dedicated computing resource and the second dedicated computing resource have different proportions within the hardware resources of the second core. In this design, different dedicated computing resources are allocated to the first thread and the second thread, ensuring that the first thread and the second thread do not interfere with each other during execution.

[0015] In one possible design, the first computing resource and the second computing resource comprise shared computing resources; the second core is further configured to execute the first thread and the second thread in parallel by time-sharing multiplexing the shared computing resources; the first thread has a higher priority than the second thread; and during the time-sharing multiplexing, the first thread's use of the shared computing resources takes precedence over the second thread's use of the shared computing resources. In this design, the computing resources shared by the first and second threads can be time-sharing multiplexed based on their priorities, effectively improving computing resource utilization in a heterogeneous multi-core device.

[0016] In one possible design, the shared computing resource includes at least one of the following: an instruction translation lookaside buffer (ITLB), an instruction cache (ICache), a branch target buffer (BTB), a register rename table (RRT), a physical register file (RPF), a data translation lookaside buffer (DTLB), or a cache (DCache). In this design, the first thread and the second thread can share one or more hardware resources, effectively improving resource utilization in a heterogeneous multi-core device.

[0017] In one possible design, the second core supports both simultaneous multi-threading (SMT) mode and single-threaded (ST) mode. The second core can also control switching between SMT and ST modes based on the number of threads currently running in the operating system. In this design, the second core can be controlled to switch between SMT and ST modes based on the number of threads currently running in the operating system in a heterogeneous multi-core device, effectively reducing unnecessary power consumption of the second core.

[0018] In one possible design, the second core is further configured to: when a first thread causes a blockage in the front-end pipeline of the second core, and a third thread causes a blockage in the back-end pipeline of a third core among the multiple cores, schedule the third thread for execution on the second core, or schedule the first thread for execution on the third core. The third core is a core different from the second core in a heterogeneous multi-core device. In this design, the multiple threads to be executed are scheduled to the appropriate core for execution based on the thread execution status of the second and third cores, thereby better utilizing the core's computing resources.

[0019] In one possible design, the first thread and the second thread have the same security level. In this design, by setting the same security level for the first thread and the second thread, the first thread and the second thread can run in an environment with the same security level, thereby avoiding security risks caused by the first thread and the second thread running in environments with different security levels.

[0020] In one possible design, the aforementioned security level is Trusted Execution Environment (TEE) mode. In this design, by setting the security features of the first and second threads to TEE mode, the security risks caused by the first thread being executed in the REE and the second thread being executed in the REE when the second core executes the first and second threads in parallel can be avoided.

[0021] In a second aspect, an embodiment of the present application also provides a scheduling method, which includes: allocating a first computing resource to a first thread, and allocating a second computing resource to a second thread; wherein the first computing resource and the second computing resource belong to a first core or a second core among a plurality of cores included in a heterogeneous multi-core device; the plurality of cores include at least one high-performance core and at least one energy-efficiency core, the maximum power consumption of any core in the at least one high-performance core is greater than the maximum power consumption of any core in the at least one energy-efficiency core, and the maximum computing capability of any core in the at least one high-performance core is higher than the maximum computing capability of any core in the at least one energy-efficiency core; executing the first thread and the second thread in parallel, wherein the first computing resource is used to execute the first thread, and the second computing resource is used to execute the second thread.

[0022] In one possible design, the multiple cores also include at least one medium-performance core, the maximum power consumption of any of the at least one high-performance cores is greater than the maximum power consumption of any of the at least one medium-performance cores, and the maximum computing capability of any of the at least one high-performance cores is higher than the maximum computing capability of any of the at least one medium-performance cores; the maximum power consumption of any of the at least one medium-performance cores is greater than the maximum power consumption of any of the at least one energy-efficiency cores, and the maximum computing capability of any of the at least one medium-performance cores is higher than the maximum computing capability of any of the at least one energy-efficiency cores.

[0023] In one possible design, allocating a first computing resource to a first thread includes allocating the first computing resource to the first thread on the second core based on the performance requirements of the first thread; allocating a second computing resource to a second thread includes allocating the second computing resource to the second thread on the second core based on the performance requirements of the second thread. Specifically, a second core is selected based on the performance requirements of the first thread and the performance requirements of the second thread, and the performance of the second core can match the performance requirements of the first thread and the performance requirements of the second thread. For another example, the first computing resource and the second computing resource are respectively allocated to the first thread and the second thread on the second core based on the performance requirements of the first thread and the performance requirements of the second thread to meet the specific performance requirements of the two threads.

[0024] In one possible design, the first computing resource includes a first dedicated computing resource, and the second computing resource includes a second dedicated computing resource different from the first dedicated computing resource; the first dedicated computing resource and the second dedicated computing resource have different proportions in the hardware resources of the first core or the second core.

[0025] In one possible design, the first computing resource and the second computing resource include shared computing resources; the method also includes: executing the first thread and the second thread in parallel by time-sharing multiplexing the shared computing resources; wherein the priority of the first thread is higher than the priority of the second thread; in time-sharing multiplexing, the time when the first thread uses the shared computing resources takes precedence over the time when the second thread uses the shared computing resources.

[0026] In one possible design, the shared computing resources include at least one of the following: an instruction translation bypass buffer ITLB, an instruction cache memory ICache, a branch target buffer BTB, a register renaming table RRT, a physical register file RPF, a data translation bypass buffer DTLB, or a cache memory DCache.

[0027] In one possible design, the second core supports simultaneous multi-threaded SMT mode and single-threaded ST mode; the method also includes: controlling the second core to switch between the SMT mode and the ST mode according to the number of threads currently running in the operating system.

[0028] In one possible design, the method further includes: when the first thread causes a block in the front-end pipeline of the second core and the third thread causes a block in the back-end pipeline of a third core among the multiple cores, scheduling the third thread for execution on the second core, or scheduling the first thread for execution on the third core, where the third core is different from the second core.

[0029] In one possible design, the first thread and the second thread have the same security level.

[0030] In one possible design, this security level is Trusted Execution Environment (TEE) mode.

[0031] In a third aspect, an embodiment of the present application further provides a scheduling device, which includes a scheduling unit and an execution unit; wherein: the scheduling unit is used to allocate a first computing resource to a first thread, and allocate a second computing resource to a second thread; wherein the first computing resource and the second computing resource belong to a first core or a second core among a plurality of cores included in a heterogeneous multi-core device; the plurality of cores include at least one high-performance core and at least one energy-efficiency core, the maximum power consumption of any core in the at least one high-performance core is greater than the maximum power consumption of any core in the at least one energy-efficiency core, and the maximum computing capability of any core in the at least one high-performance core is higher than the maximum computing capability of any core in the at least one energy-efficiency core; the execution unit is used to execute the first thread and the second thread in parallel, wherein the first computing resource is used to execute the first thread, and the second computing resource is used to execute the second thread.

[0032] In one possible design, the multiple cores also include at least one medium-performance core, the maximum power consumption of any of the at least one high-performance cores is greater than the maximum power consumption of any of the at least one medium-performance cores, and the maximum computing capability of any of the at least one high-performance cores is higher than the maximum computing capability of any of the at least one medium-performance cores; the maximum power consumption of any of the at least one medium-performance cores is greater than the maximum power consumption of any of the at least one energy-efficiency cores, and the maximum computing capability of any of the at least one medium-performance cores is higher than the maximum computing capability of any of the at least one energy-efficiency cores.

[0033] In one possible design, the scheduling unit is specifically configured to: allocate a first computing resource to the first thread on the second core based on the performance requirements of the first thread; and allocate a second computing resource to the second thread on the second core based on the performance requirements of the second thread. Specifically, the second core is selected based on the performance requirements of the first thread and the performance requirements of the second thread, and the performance of the second core can match the performance requirements of the first thread and the performance requirements of the second thread. For another example, the first computing resource and the second computing resource are allocated to the first thread and the second thread on the second core, respectively, based on the performance requirements of the first thread and the performance requirements of the second thread, so as to meet the specific performance requirements of the two threads.

[0034] In one possible design, the first computing resource includes a first dedicated computing resource, and the second computing resource includes a second dedicated computing resource different from the first dedicated computing resource; the first dedicated computing resource and the second dedicated computing resource have different proportions in the hardware resources of the first core or the second core.

[0035] In one possible design, the first computing resource and the second computing resource include shared computing resources; the execution unit is further used to: execute the first thread and the second thread in parallel by time-sharing multiplexing the shared computing resources; wherein the priority of the first thread is higher than the priority of the second thread; in time-sharing multiplexing, the time when the first thread uses the shared computing resources takes precedence over the time when the second thread uses the shared computing resources.

[0036] In one possible design, the shared computing resources include at least one of the following: an instruction translation bypass buffer ITLB, an instruction cache memory ICache, a branch target buffer BTB, a register renaming table RRT, a physical register file RPF, a data translation bypass buffer DTLB, or a cache memory DCache.

[0037] In one possible design, the scheduling unit is also used to: when the first thread causes a blockage in the front end of the pipeline of the second core, and the third thread causes a blockage in the back end of the pipeline of the third core among the multiple cores, schedule the third thread to be executed on the second core, or schedule the first thread to be executed on the third core; wherein the third core is different from the second core.

[0038] In one possible design, the first thread and the second thread have the same security level.

[0039] In one possible design, this security level is Trusted Execution Environment (TEE) mode.

[0040] In a fourth aspect, an embodiment of the present application further provides a computing device, which includes a heterogeneous multi-core device as described in the first aspect and any optional design of the first aspect, or includes a scheduling device as described in the third aspect and any optional design of the third aspect.

[0041] In a fifth aspect, an embodiment of the present application further provides a computer-readable storage medium, which includes instructions that, when executed on a computer, enable the computer to execute the operating steps of the method described in the second aspect and any optional design of the second aspect.

[0042] The beneficial effects of each possible design in the second to fifth aspects of this application can be referred to the first aspect and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1 is a schematic diagram of a system architecture applicable to an embodiment of the present application;

[0044] FIG2 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0045] FIG3 is a schematic diagram of the structure of a processor provided in an embodiment of the present application;

[0046] FIG4A is a schematic diagram of a structure of a heterogeneous multi-core device according to an embodiment of the present application;

[0047] FIG4B is a second structural diagram of a heterogeneous multi-core device provided in an embodiment of the present application;

[0048] FIG4C is a schematic diagram of the structure of a scheduling device provided in an embodiment of the present application;

[0049] FIG5 is a flow chart of a scheduling method provided in an embodiment of the present application;

[0050] FIG6 is a schematic diagram of a configuration of computing resources provided in an embodiment of the present application;

[0051] FIG7 is a schematic diagram of a pipeline micro-architecture of a processor core provided in an embodiment of the present application;

[0052] FIG8 is a schematic diagram of thread scheduling of a multi-core processor provided in an embodiment of the present application;

[0053] FIG9 is a schematic diagram of a scenario in which two computing resources in a processor core provided by the present application are both running in a TEE;

[0054] FIG10 is a schematic diagram of a scenario in which REE mode and TEE mode are simultaneously run on a processor core;

[0055] FIG11 is a schematic diagram of a scenario in which two REE modes are simultaneously run on a processor core provided by the present application. DETAILED DESCRIPTION

[0056] The following explains some of the terms used in the embodiments of the present application to facilitate understanding by those skilled in the art.

[0057] 1) Processor, which can be located in a complete system on chip (SoC) or in multiple independent chips, performs data calculation, processing or control functions, and includes a processor core and / or memory.

[0058] 2) Processor core, or simply core, refers to the core part of a processor. A processor can contain one or more processor cores, each with its own execution logic, register files, and computing resources. Each processor core can execute one or more threads or instructions.

[0059] 3) Simultaneous multiple threading (SMT), also known as hyperthreading, can be understood as multiple threads executed in parallel by a processor core. A processor core can be configured to execute one thread at a time or multiple threads simultaneously. A processor core configured to execute one thread at a time is said to be in single-threaded (ST) mode. A processor core configured to execute multiple threads simultaneously is said to be in SMT mode.

[0060] 4) Thread-level parallelism (TLP) is a parallel technology based on processor core resource management and scheduling. Its purpose is to achieve thread-level parallelism, allowing one core to execute multiple threads simultaneously to fully utilize all processor core resources.

[0061] 5) A trusted execution environment (TEE) is a secure computing environment designed to provide a highly protected and isolated execution environment to ensure the security of sensitive data and critical applications. TEEs protect sensitive data and critical operations through hardware and software mechanisms, preventing intrusion and tampering of data and computations by malware, attackers, and physical attacks. The TEE mode resides in a secure area within the processor core and memory of an electronic device, ensuring that sensitive data is stored, processed, and protected in a trusted environment. The TEE mode enables the secure execution of authorized security software (trusted applications (TAs)), thereby providing end-to-end security by enforcing protection, confidentiality, integrity, and data access permissions. Specifically, the TEE provides a secure world based on hardware isolation to protect the security of sensitive data and the correct execution of programs. Implementing a TEE requires partitioning the computing device's hardware and software resources into a secure world and a non-secure world. These two worlds have independent system resources (such as registers, physical memory, and peripherals), and data cannot be freely exchanged between the secure and non-secure worlds. The code and resources in the secure world are protected by strict access control policies. Processes in the non-secure world are prohibited from accessing the secure world to ensure that sensitive resources stored in the secure world are not illegally accessed or stolen, which can effectively reduce the disclosure of security system vulnerabilities, external attacks and virus intrusions. For example, TEE stores sensitive information such as user identity, keys and certificates in a secure area. This sensitive information can only be accessed or modified by the TA authorized by the TEE, and the TEE provides encryption and integrity protection mechanisms for the operation and processing of this sensitive information. In addition, TEE can also provide security services for operating systems in normal execution environments (such as Android). For example, the keys stored in the TEE can be used to encrypt user information in the normal execution environment (such as sensitive information such as address books and text messages), ensuring the security of sensitive information stored in the normal execution environment.

[0062] 6) A rich execution environment (REE) refers to a general execution environment within a computing device that provides general computing and application execution. Compared to a trusted execution environment (TEE), a rich execution environment is more general and open, lacking the same stringent security protections and isolation mechanisms as a TEE. REEs provide a general operating system and runtime environment, such as Windows, Linux, and Android, allowing users to install and run a variety of third-party applications. REEs are typically the default execution environment for computing devices, offering a wide range of applications and functionality to meet users' general computing needs. However, compared to TEEs, REEs are less secure, lacking specialized hardware and software protection mechanisms. Therefore, handling sensitive data and critical operations requires additional security measures. Therefore, a TEE environment offers a higher level of security than a REE, as the hardware and software resources accessible by the TEE are separate from those accessible by the REE. Client applications (CAs) within the REE (such as fingerprint collection and payment applications) can interact with the TA within the TEE by calling interfaces. Each TA has one or more corresponding CAs in the REE. In the REE environment, by calling the CA interface, the information can be transmitted to the TEE environment to execute the TA, complete the corresponding function and then return the calculation result.

[0063] 7) In the embodiments of the present application, "at least one" refers to one or more, and "at least two" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can represent: a, b, c, a and b, a and c, b and c, or a, b and c, where a, b, c can be single or multiple.

[0064] 8) The modifiers such as "first" and "second" mentioned in the embodiments of the present application are used to distinguish between multiple modified contents, and are not used to limit the size, shape, content, order, timing, priority, quantity or importance of the multiple modified contents. For example, the first core and the second core are only used to distinguish between cores that perform different operations, and do not represent the difference in priority or importance of the cores without combining other limiting features. In addition, in the embodiments of the present application, the word "exemplary" is used to indicate an example, illustration or explanation. Any embodiment or design described in this application as an "example" should not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Specifically, the use of the word "example" is intended to present concepts in a concrete way.

[0065] The technical solutions in the embodiments of the present application are described below with reference to the accompanying drawings.

[0066] Figure 1 shows a schematic diagram of a system architecture applicable to an embodiment of the present application, which includes a computing device 100, a third-party server 200, and a cloud server 300. The computing device 100 refers to various computers, mobile devices, and IoT devices, such as desktops, laptops, smartphones, tablets, sensors, etc. The computing device 100 can run various applications to meet user needs. The third-party server 200 is a physical server managed and maintained by an independent service provider. The third-party server 200 is used to maintain applications developed by application developers. For example, the third-party server 200 can be a server that maintains WeChat applications or game applications. The cloud server 300 is a virtual server based on cloud computing technology. The cloud server 300 can perform security testing, security audits, security tagging, grouping, and other operations on the applications maintained by the third-party server 200. The cloud server 300 can perform security tagging and grouping operations on the applications based on the application's frequency of use, daily active users, attack records, and special permissions. For example, the cloud server 300 can mark the security level of applications with attack records as low and group applications with low security levels. Alternatively, the cloud server 300 can mark the security level of applications without attack records as high and group applications with low security levels. For another example, the cloud server 300 can group multiple frequently used applications into one group and multiple less frequently used applications into another group. In one possible implementation, the computing device 100 can simultaneously run multiple applications in the same group to meet the various needs of users.

[0067] As shown in FIG2 , the computing device 100 may include a processor 101 and a memory 102. The processor 101 may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips, or may include any one or more of the above devices, and the embodiments of the present application are not specifically limited thereto.

[0068] The memory 102 is used to store program instructions and data, etc. Specifically, the program instructions may include program code, which includes computer operating instructions. The processor 101 can execute the program instructions stored in the memory 102 and use the data stored in the memory 102 to implement the functions of the computing device 100. The memory 102 can be a volatile memory or a non-volatile memory, or the memory 102 can include volatile and non-volatile memory. Optionally, the computing device also includes a communication interface, and the memory 102 is coupled to the processor 101 via the communication interface so that the processor 101 can read the program instructions stored in the memory 102 through the communication interface.

[0069] It should be understood that the connection medium between the processor 101, memory 102, and communication interface is not limited in the embodiments of the present application. In Figure 2, the embodiment of the present application shows that the memory 102, processor 101, and communication interface are connected via a communication bus. The bus is represented by a bold line in Figure 2. The connection method between other components is only a schematic illustration and is not intended to be limiting. The bus may include an address bus, a data bus, a control bus, etc. For ease of representation, only one bold line is used in Figure 2, but this does not mean that there is only one bus or one type of bus.

[0070] In an embodiment of the present application, the processor 101 may include one chip or multiple chips, and the processor 101 may be implemented using a heterogeneous multi-core architecture. For example, FIG3 is a schematic diagram of a possible structure of the processor 101. In FIG3, the processor 101 includes a chip 14 and a chip 15. The chips 14 and 15 are connected by a bus. The bus may be any one or more of a data bus, a power bus, a control bus, and a status signal bus. The bus may also be other types of buses that connect devices within the processor 101, such as Intel Quick Path Interconnect (QPI).

[0071] Each chip in processor 101 adopts a heterogeneous multi-core architecture. The following uses chip 14 and chip 15 as examples to illustrate the components and connections within each chip. Chip 14 includes a heterogeneous multi-core device 140, memory 144, and a memory manager 143. The heterogeneous multi-core device 140, memory 144, and memory manager 143 are interconnected via an on-chip bus. Heterogeneous multi-core device 140 includes multiple processor cores (e.g., processor core 141 and processor core 142). When each processor core is configured in SMT mode, each processor core can execute multiple threads in parallel. The hardware resources in each hardware unit used to process each thread in a processor core are logically a logical CPU, which can also be called computing resources. The computing resources used by the same processor core when executing different threads can be the same or different. For example, the logical CPU in processor core 141 includes computing resources 1411 and computing resources 1412. Processor core 141 can use computing resources 1411 to execute thread 1, and processor core 141 can use computing resources 1412 to execute thread 2. The logical CPU in processor core 142 includes computing resources 1421 and computing resources 1422. Processor core 142 can use computing resources 1421 to execute thread 3, and processor core 142 can use computing resources 1422 to execute thread 4. Memory 144 refers to internal memory that directly exchanges data with computing resources in heterogeneous multi-core device 140. It can read and write data at any time and at a high speed, and serves as temporary data storage for the operating system or other running programs. Memory 144 can be, for example, static random access memory (SRAM). Memory manager 143 is used to manage and plan data transmission from memory 144 to any of computing resources 1411, computing resources 1412, computing resources 1421, and computing resources 1422. Memory manager 143 can be a separate chip outside chip 14, or as shown in FIG3 , it can be a module integrated into chip 14.

[0072] Chip 15 includes a heterogeneous multi-core device 150, a memory 154, and a memory manager 153. The heterogeneous multi-core device 150, the memory 154, and the memory manager 153 are interconnected via an on-chip bus. The heterogeneous multi-core device 150 includes multiple processor cores (e.g., processor core 151 and processor core 152). When each processor core is configured in SMT mode, each processor core can execute multiple threads in parallel. The hardware resources in each hardware unit used to process each thread in a processor core are logically a logical CPU, which can also be called computing resources. The computing resources used when executing different threads in the same processor core can be the same or different. For example, the logical CPU in processor core 151 includes computing resources 1511 and computing resources 1512. Processor core 151 can use computing resources 1511 to execute thread 5, and processor core 151 can use computing resources 1512 to execute thread 6. The logical CPU in processor core 152 includes computing resources 1521 and computing resources 1522. Processor core 152 can use computing resources 1521 to execute thread 7, and processor core 152 can use computing resources 1522 to execute thread 8. Memory 154 refers to internal memory that directly exchanges data with the computing resources in heterogeneous multi-core device 150. It can read and write data at any time and at a high speed, and serves as temporary data storage for the operating system or other running programs. Memory 154 can be, for example, SRAM. Memory manager 153 is used to manage and plan data transmission from memory 154 to any of computing resources 1511, computing resources 1512, computing resources 1521, and computing resources 1522. Memory manager 153 can be a separate chip outside chip 15, or, as shown in FIG3 , can be a module integrated into chip 15.

[0073] In some possible embodiments, heterogeneous multi-core device 140 or heterogeneous multi-core device 150 may be a separate chip or chip module outside of chip 14 and chip 15. That is, the heterogeneous multi-core device and the memory and memory manager may not be located on the same chip, so that the memory and memory manager may be located on an additional chip. It should be understood that the number of chips in processor 101 may be greater or less, and the number of processor cores in heterogeneous multi-core device 140 or heterogeneous multi-core device 150 may be greater or less, and the embodiments of the present application do not impose specific limitations.

[0074] The processor cores in processor 101 can run an operating system to implement various software functions of processor 101. The operating system can run various applications and convert tasks generated by the applications into threads to be executed and assign them to the processor cores for execution. The processor cores running the operating system can be one or more processor cores in processor 101. For example, the operating system can be run by any one of processor cores 141, 142, 151, or 152. In another example, the operating system can run on both processor core 141 and processor core 142 simultaneously.

[0075] It should be understood that, based on the energy consumption and performance of the multiple processor cores in the heterogeneous multi-core device 140 or 150, the multiple processor cores in the heterogeneous multi-core device 140 or 150 can be classified into at least one of high-performance cores, energy-efficiency cores, and medium-performance cores. For example, the structure of the heterogeneous multi-core device 140 can also be shown in FIG4A . In FIG4A , the heterogeneous multi-core device 140 includes high-performance cores 201 and energy-efficiency cores 202, thereby forming a large-small core architecture. The high-performance cores 201 include at least one high-performance core, such as high-performance core 2011 and high-performance core 2012; the energy-efficiency cores 202 include at least one energy-efficiency core, such as energy-efficiency core 2021 and energy-efficiency core 2022. The maximum power consumption of any of the at least one high-performance core is greater than the maximum power consumption of any of the at least one energy-efficiency core, and the maximum computing power of any of the at least one high-performance core is greater than the maximum computing power of any of the at least one energy-efficiency core. In other words, the high-performance cores have higher performance, while the energy-efficiency cores have lower performance than the high-performance cores but higher energy efficiency. In this way, the characteristics of high-performance cores and energy-efficiency cores can be combined to allocate appropriate computing resources to the threads to be executed, making the resource allocation of the threads to be executed more flexible and giving full play to the performance of large and small cores.

[0076] Optionally, the heterogeneous multi-core device 140 may further include medium-performance cores 203, which include at least one medium-performance core, for example, medium-performance core 2031 and medium-performance core 2032. The maximum power consumption of any of the at least one high-performance core is greater than the maximum power consumption of any of the at least one medium-performance core, and the maximum computing capability of any of the at least one high-performance core is greater than the maximum computing capability of any of the at least one medium-performance core; the maximum power consumption of any of the at least one medium-performance core is greater than the maximum power consumption of any of the at least one energy-efficiency core, and the maximum computing capability of any of the at least one medium-performance core is greater than the maximum computing capability of any of the at least one energy-efficiency core. Thus, by providing high-performance cores, energy-efficiency cores, and medium-performance cores in the heterogeneous multi-core device, resource allocation to threads becomes more flexible, and the high-performance cores, energy-efficiency cores, and medium-performance cores can form a three-cluster architecture that can better adapt to the diverse performance requirements of different threads.

[0077] In some embodiments, the high-performance core 201 may also be referred to as a large core, the medium-performance core 203 may also be referred to as a medium core, and the energy-efficiency core 202 may also be referred to as a small core. For example, FIG4B shows a schematic diagram of the structure of the heterogeneous multi-core device 140 including a large core, a medium core, and a small core. In (a) of FIG4B , the large core and the medium core in the heterogeneous multi-core device 140 support SMT, while the small core does not support SMT; in (b) of FIG4B , the small core in the heterogeneous multi-core device 140 supports SMT, while the large core and the medium core do not support SMT; in (c) of FIG4B , the small core, the large core, and the medium core in the heterogeneous multi-core device 140 all support SMT. It can be seen that there are multiple implementation methods for the heterogeneous multi-core device 140 when it is used to implement the SMT mode.

[0078] As shown in FIG4C , one or more cores in the heterogeneous multi-core device 140 may further include a scheduling device 220 as shown in FIG4C . The scheduling device 220 includes a scheduling unit 221 and an execution unit 222. The scheduling unit 221 and the execution unit 222 may be implemented in software or in a combination of hardware and software. The relevant software may include software computer instructions that run on one or more cores of the heterogeneous multi-core device. These two approaches are described below.

[0079] 1. Software method

[0080] Specifically, the scheduling unit 221 may be implemented by a scheduling algorithm executed by a first core in the heterogeneous multi-core device 140 and may include software computer instructions corresponding to the first core. The execution unit 222 may be implemented by pipeline micro-architecture software executed by a second core in the heterogeneous multi-core device 140 and may include software computer instructions corresponding to the second core.

[0081] 2. Combination of Hardware and Software

[0082] Specifically, the scheduling unit 221 can be implemented by running corresponding software on the first core of the heterogeneous multi-core device 140, that is, it includes a combination of the first core and the corresponding software. The execution unit 222 can be implemented by running corresponding software on the second core of the heterogeneous multi-core device 140, that is, it includes a combination of the second core and the corresponding software.

[0083] In conjunction with the computing device 100 and the heterogeneous multi-core device 140, embodiments of the present application provide a scheduling method for improving the utilization of computing resources in the heterogeneous multi-core device, thereby increasing the peak computing power of the heterogeneous multi-core device. The scheduling method provided by embodiments of the present application will be described below with reference to FIG5 .

[0084] Figure 5 is one of the flow charts of a scheduling method provided by an embodiment of the present application, which can be implemented by an operating system or other types of driver software or application software, and executed by a processor core (such as the processor core 141 in Figure 3) running the operating system. In Figure 5, the scheduling scheme provided by an embodiment of the present application is introduced by taking the first core and the second core in the heterogeneous multi-core device 140 as an example. Among them, the first core can be any one of the high-performance cores, medium-performance cores, or energy-efficiency cores in the heterogeneous multi-core device 140, and the second core can be the first core or another core in the heterogeneous multi-core device 140 that is different from the first core, and the other core can also be any one of the high-performance cores, medium-performance cores, or energy-efficiency cores. The scheduling method includes:

[0085] S501: A first core allocates a first computing resource to a first thread, wherein the first thread may include one or more threads.

[0086] S502: The first core allocates a second computing resource to a second thread, wherein the second thread may include one or more threads.

[0087] In the embodiment of the present application, when the first core runs an operating system, the first thread and the second thread may be multiple threads created by the operating system. The first thread and the second thread may be threads corresponding to the same task of the same application, or may be threads corresponding to different tasks of the same application, or may be threads corresponding to different applications.

[0088] In one possible implementation, a first core may allocate first computing resources to the first thread on the second core based on the performance requirements of the first thread, and allocate second computing resources to the second thread on the second core based on the performance requirements of the second thread. This allows flexible allocation of computing resources to each thread based on its performance requirements, rather than assigning fixed resources to each thread, to accommodate the diverse needs of different threads. Optionally, the performance requirements of the first thread are characterized by at least one of the first thread's latency sensitivity, business scenario, or user experience, and the performance requirements of the second thread are characterized by at least one of the second thread's latency sensitivity, business scenario, or user experience. In summary, when the performance requirements of multiple threads are higher, such as requiring low latency, high computing speed, or high computing power, it is necessary to select a higher-performance core from the multiple cores and allocate computing resources to the multiple threads on that core. The performance of the selected core matches the performance requirements of the multiple threads, meaning it can meet the performance requirements of the multiple threads without wasting performance due to excess performance. For example, when multiple threads need to be executed, the first core selects a suitable core, namely the second core, from the multiple cores, and uses the computing resources of the selected core to serve the multiple threads to implement the SMT mode. The selected core can be the first core itself or another core, which is not limited in this embodiment. When the first core determines that the performance requirements of the multiple threads are relatively low, the selected core is an energy-efficient core with lower performance to reduce power consumption; when the first core determines that the performance requirements of the multiple threads are medium, the selected core is a medium-performance core with medium performance to achieve a compromise between performance and power consumption; when the first core determines that the performance requirements of the multiple threads are high, the selected core is a high-performance core to give priority to meeting the performance requirements. After determining the selected second core, the first core further allocates first computing resources and second computing resources to the first thread and the second thread on the second core according to the performance requirements of the first thread and the performance requirements of the second thread, respectively, to meet the specific needs of each thread itself.

[0089] As can be seen from the foregoing description, the computing capabilities and power consumption of the high-performance cores, medium-performance cores, and energy-efficiency cores in the heterogeneous multi-core device 140 vary to a certain extent. Specifically, the maximum computing capability of the high-performance cores is higher than that of the medium-performance cores, which in turn is higher than that of the energy-efficiency cores. The maximum power consumption of the high-performance cores is lower than that of the medium-performance cores, which in turn is lower than that of the energy-efficiency cores. Therefore, a first core can allocate computing resources to a first thread based on the performance requirements of the first thread and the characteristics of the high-performance cores, medium-performance cores, and energy-efficiency cores in the heterogeneous multi-core device 140. Similarly, the first core can allocate computing resources to a second thread based on the performance requirements of the second thread and the characteristics of the high-performance cores, medium-performance cores, and energy-efficiency cores in the heterogeneous multi-core device 140. In this way, matching the performance requirements of the first and second threads with the resources of the various core types in the heterogeneous multi-core device 140 can effectively improve resource utilization in the heterogeneous multi-core device 140.

[0090] For example, if the first thread has a high sensitivity to delay, the first core can allocate the computing resources of the high-performance core (i.e., large core) to the first thread, so that the first thread can be executed quickly, effectively reducing the execution time of the first thread, and thus effectively meeting the delay sensitivity of the first thread. Correspondingly, if the second thread has a low sensitivity to delay, the first core can allocate the computing resources of the medium-performance core (i.e., medium core) or energy-efficiency core (i.e., small core) to the second thread. Since the power consumption of the medium-performance core (i.e., medium core) or energy-efficiency core (i.e., small core) is relatively low, using the computing resources of the medium-performance core (i.e., medium core) or energy-efficiency core (i.e., small core) to execute the second thread can effectively reduce the power consumption generated when the second thread is executed.

[0091] For example, if the first thread's business scenario is a call, and the second thread's business scenario is an application update, and the first thread's business scenario has higher real-time requirements than the second thread's business scenario, the first core can allocate computing resources from high-performance cores (i.e., large cores) to the first thread, and computing resources from medium-performance cores (i.e., mid-cores) or energy-efficient cores (i.e., small cores) to the second thread. This allows the first thread to execute quickly, effectively meeting the real-time requirements of the first thread's business scenario; and while meeting the real-time requirements of the second thread's business scenario, the power consumption generated by the second thread's execution can be effectively reduced.

[0092] For example, if the first thread is a game application thread and the second thread is a system update thread, and the user experience requirements of the first thread are higher than those of the second thread, the first core can allocate computing resources of the high-performance core (i.e., large core) to the first thread, and allocate computing resources of the medium-performance core (i.e., mid-core) or energy-efficient core (i.e., small core) to the second thread. In this way, the first thread can be executed quickly, effectively meeting the user experience requirements of the first thread; and the power consumption generated by the execution of the second thread can be effectively reduced while meeting the user experience requirements of the second thread.

[0093] As shown in FIG6 , in some possible implementations, the computing resources of the high-performance core (i.e., the big core (b-core)), the medium-performance core (i.e., the medium core (m-core)), and the energy-efficiency core (i.e., the small core (s-core)) can be represented by the dimensionless value of the central processing unit capacity (CPU capacity). Here, the CPU capacity of the big core is 12, the CPU capacity of the medium core is 8, and the CPU capacity of the small core is 4. Furthermore, the first core can flexibly allocate the computing resources of the big core, the medium core, and the small core to form computing resources with a CPU capacity of 1-12 as shown in FIG6 , so that the heterogeneous multi-core device can provide diverse computing power supply capabilities, thereby meeting the computing power requirements of multiple threads.

[0094] Accordingly, the first core may allocate computing resources to the first thread or the second thread according to the table shown in FIG6 .

[0095] For example, the CPU capacity corresponding to the performance requirement of the first thread is 12, and the first computing resources allocated by the first core to the first thread are all computing resources of a large core.

[0096] For another example, the performance requirement of the first thread corresponds to a CPU capacity of 11, and the performance requirement of the second thread corresponds to a CPU capacity of 1. The first computing resources allocated by the first core to the first thread are 11 / 12 of the computing resources of a large core, and the first computing resources allocated by the first core to the second thread are 1 / 12 of the computing resources of a large core.

[0097] For another example, the performance requirement of the first thread corresponds to a CPU capacity of 10, and the performance requirement of the second thread corresponds to a CPU capacity of 2. The first computing resource allocated by the first core to the first thread is the computing resources of 10 / 12 of a large core, and the first computing resource allocated by the first core to the second thread is the computing resources of 2 / 12 of a large core.

[0098] For another example, the performance requirement of the first thread corresponds to a CPU capacity of 9, and the performance requirement of the second thread corresponds to a CPU capacity of 3. The first computing resources allocated by the first core to the first thread are 9 / 12 of the computing resources of a large core, and the first computing resources allocated by the first core to the second thread are 3 / 12 of the computing resources of a large core.

[0099] For another example, the performance requirement of the first thread corresponds to a CPU capacity of 8, and the performance requirement of the second thread corresponds to a CPU capacity of 4. The first computing resources allocated by the first core to the first thread are all the computing resources of a medium core, and the second computing resources allocated by the first core to the second thread are all the computing resources of a small core. Alternatively, the first computing resources allocated by the first core to the first thread are the computing resources of 8 / 12 of a large core, and the second computing resources allocated by the first core to the second thread are the computing resources of 4 / 12 of a large core.

[0100] For another example, the performance requirement of the first thread corresponds to a CPU capacity of 7, and the performance requirement of the second thread corresponds to a CPU capacity of 5. The first computing resource allocated by the first core to the first thread is 7 / 12 of the computing resources of a large core, and the second computing resource allocated by the first core to the second thread is 5 / 12 of the computing resources of a large core. Alternatively, the first computing resource allocated by the first core to the first thread is 7 / 8 of the computing resources of a medium core, and the second computing resource allocated by the first core to the second thread is 5 / 8 of the computing resources of a medium core.

[0101] For another example, the performance requirement of the first thread corresponds to a CPU capacity of 6, and the performance requirement of the second thread corresponds to a CPU capacity of 6. The first computing resource allocated by the first core to the first thread is the computing resources of a large core (6 / 12), and the second computing resource allocated by the first core to the second thread is the computing resources of a large core (6 / 12). Alternatively, the first computing resource allocated by the first core to the first thread is the computing resources of a medium core (6 / 8), and the second computing resource allocated by the first core to the second thread is the computing resources of a medium core (6 / 8).

[0102] For another example, the performance requirement of the first thread corresponds to a CPU capacity of 5, and the performance requirement of the second thread corresponds to a CPU capacity of 7. The first computing resource allocated by the first core to the first thread is 5 / 12 of the computing resources of a large core, and the second computing resource allocated by the first core to the second thread is 7 / 12 of the computing resources of a large core. Alternatively, the first computing resource allocated by the first core to the first thread is 5 / 8 of the computing resources of a medium core, and the second computing resource allocated by the first core to the second thread is 7 / 8 of the computing resources of a medium core.

[0103] For another example, the performance requirement of the first thread corresponds to a CPU capacity of 4, and the performance requirement of the second thread corresponds to a CPU capacity of 8. The first computing resources allocated by the first core to the first thread are all the computing resources of a small core, and the second computing resources allocated by the first core to the second thread are all the computing resources of a medium core. Alternatively, the first computing resources allocated by the first core to the first thread are 4 / 12 of the computing resources of a large core, and the second computing resources allocated by the first core to the second thread are 8 / 12 of the computing resources of a large core.

[0104] For another example, the performance requirement of the first thread corresponds to a CPU capacity of 3, and the performance requirement of the second thread corresponds to a CPU capacity of 9. The first computing resource allocated to the first thread by the first core is any one of 3 / 12 of the computing resources of a large core, 3 / 8 of the computing resources of a medium core, and 3 / 4 of the computing resources of a small core. The second computing resource allocated to the second thread by the first core is 9 / 12 of the computing resources of a large core.

[0105] For another example, the performance requirement of the first thread corresponds to a CPU capacity of 2, and the performance requirement of the second thread corresponds to a CPU capacity of 10. The first computing resources allocated by the first core to the first thread can be any one of 2 / 12 of the computing resources of a large core, 2 / 8 of the computing resources of a medium core, and 2 / 4 of the computing resources of a small core. The second computing resources allocated by the first core to the second thread are 10 / 12 of the computing resources of a large core.

[0106] For another example, the performance requirement of the first thread corresponds to a CPU capacity of 1, and the performance requirement of the second thread corresponds to a CPU capacity of 11. The first computing resources allocated by the first core to the first thread can be any one of 1 / 12 of the computing resources of a large core, 1 / 8 of the computing resources of a medium core, and 1 / 4 of the computing resources of a small core. The second computing resources allocated by the first core to the second thread are 11 / 12 of the computing resources of a large core.

[0107] It should be understood that the specific values ​​of the CPU capacity of the big core, the medium core, and the small core in FIG6 are merely examples, rather than limitations on the CPU capacity of the big core, the medium core, and the small core.

[0108] In an embodiment of the present application, the first computing resource includes a first dedicated computing resource, the second computing resource includes a second dedicated computing resource, and the first dedicated computing resource is different from the second dedicated computing resource. In this way, different dedicated computing resources are allocated to the first thread and the second thread, so that the first thread and the second thread do not interfere with each other when executed by the second core. The first dedicated computing resource and the second dedicated computing resource are both hardware resources of the second core, but the first dedicated computing resource and the second dedicated computing resource have different proportions in the hardware resources of the second core.

[0109] The hardware resources of the second core include various hardware units in the pipeline architecture for the second core to execute multiple threads in parallel. For example, FIG7 illustrates a pipeline architecture for the second core to execute multiple threads in parallel, including an instruction translation lookaside buffer (ITLB), a data translation lookaside buffer (DTLB), an instruction cache (ICache), a data cache (DCache), a branch target buffer (BTB), a register rename table (RRT), a reorder buffer (ROB), and a physical register file (PRF). The ITLB is used to cache the conversion relationship between the virtual address and the physical address of instructions, the DTLB is used to cache the conversion relationship between the virtual address and the physical address of data, the ICache is used to cache instructions, the DCache is used to cache recently used data, and the BTB is used to store the address of a successful branch instruction and its branch target address in a buffer, which is identified by the address of the branch instruction. The RRT is used to implement register renaming, renaming the source and target registers (i.e., virtual registers) in the instruction to the corresponding physical registers. The ROB is used to store instruction results and instruction execution order information to implement out-of-order execution of instructions and ensure instruction correctness. The PRF is used for register allocation, register renaming, and operand tracking. Therefore, taking the hardware units corresponding to the pipeline architecture in Figure 7 as an example, the hardware resources of the second core include the ITLB, ICache, BTB, RRT, PRF, DTLB, and DCache. Correspondingly, the first dedicated computing resource or the second dedicated computing resource may include at least one of the following: ITLB, ICache, BTB, RRT, PRF, DTLB, or DCache.

[0110] Optionally, the first core may allocate computing resources to the first thread and the second thread based on their priorities. For example, when the priority of the first thread is higher than the priority of the second thread, the proportion of the first dedicated computing resources in the hardware resources of the second core is higher than the proportion of the second dedicated computing resources in the hardware resources of the second core. The priority of the first thread or the priority of the second thread can be characterized by at least one of latency sensitivity, business scenario, or user experience.

[0111] For example, the first thread is a thread for a calling application, and the second thread is a thread for a reading application. The delay sensitivity of the first thread is higher than that of the second thread, so the priority of the first thread is higher than that of the second thread; accordingly, the first dedicated computing resources are 70% of the resources in the ITLB and 70% of the resources in the DTLB, and the second dedicated computing resources are 30% of the resources in the ITLB and 30% of the resources in the DTLB.

[0112] For another example, the business scenario of the first thread is a call scenario, and the business scenario of the second thread is an application update scenario. The real-time requirement of the business scenario of the first thread is higher than the real-time requirement of the business scenario of the second thread, then the priority of the first thread is higher than the priority of the second thread; accordingly, the first dedicated computing resources include 60% of the resources in ITLB, 60% of the resources in DTLB, 60% of the resources in ICache, and 60% of the resources in DCache, and the second dedicated computing resources include 40% of the resources in ITLB, 40% of the resources in DTLB, 40% of the resources in ICache, and 40% of the resources in DCache.

[0113] For another example, the first thread is a thread for a gaming application, and the second thread is a thread for a system update. If the user experience requirement of the first thread is higher than that of the second thread, the priority of the first thread is higher than that of the second thread. Accordingly, the first dedicated computing resources include 80% of the resources in the ITLB, 80% of the resources in the DTLB, 80% of the resources in the ICache, and 80% of the resources in the DCache. The second dedicated computing resources include 20% of the resources in the ITLB, 20% of the resources in the DTLB, 20% of the resources in the ICache, and 20% of the resources in the DCache.

[0114] S503: The second core executes the first thread and the second thread in parallel. In S503, the second core uses the first computing resource to execute the first thread, and uses the second computing resource to execute the second thread.

[0115] In S503, the second core executes the first thread and the second thread in parallel, which can effectively improve the utilization rate of computing resources in the heterogeneous multi-core device, thereby effectively improving the peak computing power of the heterogeneous multi-core device.

[0116] As can be seen from the foregoing description, the first computing resource includes a first dedicated computing resource, and the second computing resource includes a second dedicated computing resource. Accordingly, the second core uses the first dedicated computing resource to execute the first thread, and the second core uses the second dedicated computing resource to execute the second thread.

[0117] Furthermore, the first and second computing resources may also include shared computing resources, which are hardware resources of the second core. Accordingly, the second core uses the first dedicated computing resources and the shared computing resources to execute the first thread, and the second core uses the second dedicated computing resources and the shared computing resources to execute the second thread. The second core may time-share the shared computing resources when executing the first and second threads in parallel.

[0118] Optionally, when the priority of the first thread is higher than the priority of the second thread, the time the first thread uses the shared computing resources takes precedence over the time the second thread uses the shared computing resources, that is, the time the second core uses the shared computing resources to execute the first thread takes precedence over the time the second core uses the shared computing resources to execute the second thread. Furthermore, when the priority of the first thread and the priority of the second thread are the same, embodiments of the present application do not restrict the time the second core uses the shared computing resources to execute the first thread or the time the second core uses the shared computing resources to execute the second thread.

[0119] Please continue to refer to Figure 7. When the hardware resources of the second core include ITLB, ICache, BTB, RRT, PRF, DTLB, and DCache, the shared computing resources may include at least one of ITLB, ICache, BTB, RRT, PRF, DTLB, or DCache.

[0120] For example, if the shared computing resources include ICache, BTB, RRT, PRF, and DCache, the second core can execute the first thread and the second thread in parallel by time-sharing multiplexing ICache, BTB, RRT, PRF, and DCache; and when the priority of the first thread is higher than the priority of the second thread, the time when the second core uses ICache to execute the first thread takes precedence over the time when the second core uses ICache to execute the second thread, the time when the second core uses BTB to execute the first thread takes precedence over the time when the second core uses BTB to execute the second thread, the time when the second core uses RRT to execute the first thread takes precedence over the time when the second core uses RRT to execute the second thread, the time when the second core uses PRF to execute the first thread takes precedence over the time when the second core uses PRF to execute the second thread, and the time when the second core uses DCache to execute the first thread takes precedence over the time when the second core uses DCache to execute the second thread.

[0121] For another example, if the shared computing resources include BTB, RRT, and PRF, the second core can execute the first thread and the second thread in parallel by time-sharing multiplexing BTB, RRT, and PRF; and when the priority of the first thread is higher than the priority of the second thread, the time when the second core uses BTB to execute the first thread takes precedence over the time when the second core uses BTB to execute the second thread, the time when the second core uses RRT to execute the first thread takes precedence over the time when the second core uses RRT to execute the second thread, and the time when the second core uses PRF to execute the first thread takes precedence over the time when the second core uses PRF to execute the second thread.

[0122] For another example, the shared computing resources include RRT and PRF, and the second core executes the first thread and the second thread in parallel by time-sharing multiplexing RRT and PRF; the priority of the first thread is the same as the priority of the second thread, and the time when the second core uses RRT to execute the first thread can be earlier or later than the time when the second core uses RRT to execute the second thread, and the time when the second core uses PRF to execute the first thread is earlier or later than the time when the second core uses PRF to execute the second thread.

[0123] In an embodiment of the present application, the basic unit of the second core execution program is a thread. A thread can be regarded as an independent execution sequence, which contains a series of instructions that need to be executed on the second core. As the basic unit of the operation to be performed on the processor, the instruction is a machine code represented by binary, which is used to indicate the specific operation to be performed by the second core, such as addition, multiplication, memory reading and writing, etc. The instruction usually includes an opcode (used to specify the type of operation) and an operand (used to specify the source and target of the operation). Accordingly, when the second core executes multiple threads in parallel, the second core can execute multiple instructions of multiple threads in parallel. In the second core, a series of instructions can be generated for each thread to be executed, and the series of instructions of the thread are sent to the instruction pipeline of the second core for execution. The instruction pipeline includes multiple processing stages, and each stage performs specific operations of the instruction (such as instruction fetch, decoding, execution, memory access and write back, etc.). In the second core that supports multi-threading, the thread scheduler can select instructions of multiple threads to alternately execute the processing stages of different threads, that is, execute instructions of different threads in different clock cycles.

[0124] Please continue to refer to Figure 7. In Figure 7, thread 1 is used as an example for the first thread and thread 2 is used as an example for the second thread. The following describes the specific process by which the second core can execute the first and second threads in parallel from the perspective of instruction execution of threads 1 and 2, in conjunction with Figure 7. This process includes:

[0125] (1) Instruction fetch:

[0126] During the instruction fetch phase, the second core is responsible for fetching instructions from threads 1 and 2 and caching them in the ITLB. Furthermore, during the instruction fetch phase, the second core uses its branch predictor to predict the target addresses of the branch instructions for threads 1 and 2. It then uses the BTB to store the address of the successful branch instruction and its target address in a buffer. The buffer uses the address of the branch instruction as an identifier to facilitate retrieving instructions for the correct branch path.

[0127] The second core can combine the priorities of Thread 1 and Thread 2 to implement the instruction fetch phase for Thread 1 and Thread 2. For example, if Thread 1's priority is higher than Thread 2's, the second core will prioritize fetching Thread 1's instructions from memory, and only fetch Thread 2's instructions from memory after Thread 1's instructions are fully fetched. Alternatively, the second core can prioritize fetching Thread 1's instructions from memory, and only fetch Thread 2's instructions from memory if Thread 1's instructions cannot be fetched from memory. For another example, if Thread 1 and Thread 2 have the same priority, the second core will alternately fetch Thread 1 and Thread 2's instructions from memory.

[0128] (2) Instruction decode and register renaming:

[0129] During the decode phase, the second core decodes the instructions from thread 1 and thread 2, converting them into internal control signals and operands. Furthermore, the decode phase also includes a register renaming phase. During this phase, the RRT renames the source and destination registers (i.e., virtual registers) in the instructions from thread 1 and thread 2 to their corresponding physical registers. This avoids data dependencies between the instructions from thread 1 and thread 2, improving instruction-level parallelism.

[0130] In the decoding stage and the renaming stage, in the case of out-of-order execution, the instructions of thread 1 and thread 2 may enter the ROB in any order, and the results are submitted in the order of the original instruction sequence after execution is completed.

[0131] (3) dispatch:

[0132] During the dispatch phase, the second core is responsible for dispatching the instructions obtained after decoding the instructions of thread 1 and thread 2 to the execution unit (EU) for execution. The EU includes various functional units, such as the arithmetic logic unit (ALU) and floating point unit (FPU). Accordingly, the EU can perform arithmetic operations, logical operations, bit shift operations, etc. corresponding to various instructions. When the second core executes multiple threads in parallel, each thread can independently use the EU to achieve instruction-level parallel processing. For example, the instructions of thread 1 are executed by EU0, and the instructions of thread 2 are executed by EU1.

[0133] Furthermore, during the dispatch phase, the second core processes the memory access instructions (i.e., load instructions and store instructions) of thread 1 and thread 2 through the load-store unit (LSU), implements read and write operations between the second core and the memory, and is responsible for handling the transmission and caching of data related to thread 1 and thread 2. When the load instruction executed by the LSU needs to access memory, it uses the DTLB for address translation, converts the virtual address into the corresponding physical address, and then accesses it in the physical address space. Since the Dcache stores recently used data, when the load instruction executed by the LSU needs to read data, it will first look for the required data in the Dcache. If the data is in the Dcache, the LSU can obtain the data directly from the Dcache, thereby avoiding the delay of accessing the main memory. If the data is not in the Dcache, the LSU will obtain the data from the main memory and load the data into the Dcache for subsequent access. The LSU also maintains a store queue (SQ) and a load queue (LQ), effectively managing the execution order of store and load instructions, improving instruction-level parallelism and memory access efficiency, thereby enhancing processor performance. The SQ processes store instructions, tracking the target address and data to be written for each store instruction while maintaining the execution order. It also checks data dependencies between store instructions, ensuring that previous load instructions complete before stores to avoid data races and memory consistency issues. The LQ processes load instructions, tracking the target address of each load instruction, maintaining the execution order, and checking data dependencies between load instructions and stores to ensure that load instructions are executed only after the corresponding store instructions complete, ensuring that the correct data is read. When the second core executes multiple threads in parallel, each thread can independently use the LSU to achieve independent memory access. For example, instructions for thread 1 are executed through LSU0, and instructions for thread 2 are executed through LSU2.

[0134] The second core can combine the priorities of Thread 1 and Thread 2 to implement a priority dispatch phase for Thread 1 and Thread 2. For example, if Thread 1's priority is higher than Thread 2's, the second core will prioritize dispatching Thread 1's instructions to LSU0, and after Thread 1's instructions are dispatched, dispatch Thread 2's instructions to LSU1. Alternatively, the second core can prioritize dispatching Thread 1's instructions to LSU0, and when the waiting time for Thread 1's access instructions in the SQ exceeds a preset threshold, dispatch Thread 2's instructions to LSU1. For another example, if Thread 1 and Thread 2 have the same priority, the second core will alternately dispatch Thread 1's instructions to LSU0 and Thread 2's instructions to LSU1.

[0135] Also, during the dispatch phase, each instruction of Thread 1 and Thread 2 needs to be allocated a set of physical registers to store operands and results. At this time, PRF will maintain a pool of available physical registers and allocate these physical registers to instructions. Also, PRF can use register renaming technology to rename logical registers to physical registers, which can avoid data dependencies between the instructions of Thread 1 and Thread 2, so that the instructions of Thread 1 and Thread 2 can be executed in parallel. In addition, PRF can track the physical registers used by the instructions of Thread 1 and Thread 2 as operands, so as to ensure that the operands of the instructions of Thread 1 and Thread 2 are accurate and consistent with the results of the previous instruction execution.

[0136] (4) Retirement:

[0137] During the retirement phase, instructions executed by Thread 1 and Thread 2 are marked as committed and written to status registers or related data in memory. If an exception or interrupt occurs during execution, the retirement phase handles these exceptions, ensuring that the exception handler is executed correctly and aborting or restarting the pipeline if necessary. Furthermore, even if out-of-order execution occurs in the pipeline, the retirement phase ensures that the results of the instructions are committed correctly according to the original program order.

[0138] The "memory" referred to in the above process can be understood as the memory in the chip integrated into the heterogeneous multi-core device where the second core is located, for example, memory 144 or memory 154 in Figure 3. In some possible embodiments, the heterogeneous multi-core device 140 also includes a third core. The third core is another core that is not used for the second core. The other core can be any of the high-performance cores, medium-performance cores, or energy-efficiency cores in the heterogeneous multi-core device 140. The third core also supports SMT mode. As shown in Figure 8 (a), when the second core is executing thread 1, the third core is executing thread 3. As shown in Figure 8 (b), if thread 1 causes a block in the front-end pipeline of the second core and thread 3 causes a block in the back-end pipeline of the third core, the second core can schedule thread 3 to execute on the second core, that is, the second core executes thread 1 and thread 3 in parallel; alternatively, the second core can schedule thread 1 to execute on the third core, that is, the third core executes thread 1 and thread 3 in parallel. Among them, thread 1 causing a blockage in the front-end of the pipeline of the second core includes but is not limited to the following situations: in the value retrieval stage, thread 1's instructions cannot be retrieved from memory, or the instructions cached in the ITLB have reached the upper limit and thread 1's instructions cannot be placed in the ITLB; in the decoding stage, an error occurs in decoding thread 1's instructions. Also, thread 3 causing a blockage in the back-end of the pipeline of the third core includes but is not limited to the following situations: the waiting time of thread 3's access instruction in the SQ is greater than a first preset value, or the waiting time of thread 3's load instruction in the LQ is greater than a second preset value, or the third core cannot access thread 3-related data from the DCache. In this way, combining the execution status of thread 1 and thread 3, scheduling thread 1 and thread 3 to execute on the same core can further improve the resource utilization and system performance of the heterogeneous multi-core device 140.

[0139] In some possible embodiments, the second core supports SMT mode and ST mode, and the second core can control the second core to switch between SMT mode and ST mode according to the number of threads currently running in the operating system. For example, taking the large core and the medium core as an example of the second core, the threads currently running in the operating system include thread 1, thread 2, thread 3, and thread 4, the large core runs in SMT mode, so that the large core can execute thread 1 and thread 2 in parallel; and the medium core runs in SMT mode, so that the medium core can execute thread 3 and thread 4 in parallel. For another example, taking the large core as an example of the second core, the threads currently running in the operating system include thread 1 and thread 2, the large core runs in SMT mode, so that the large core can execute thread 1 and thread 2 in parallel. For another example, taking the large core and the medium core as an example of the second core, the threads currently running in the operating system include thread 1 and thread 2, the large core runs in ST mode, so that the large core executes thread 1; and the medium core runs in ST mode, so that the medium core executes thread 2. For another example, if the second core is a large core and the threads currently running in the operating system include thread 1, the large core will run in ST mode, causing the large core to execute thread 1. In this way, when the number of threads currently running in the operating system is small, the second core can be controlled to run in ST mode, which can effectively reduce the power consumption of the second core.

[0140] As described above, REE refers to the common execution environment, which includes the operating system and user-space applications. The ARM architecture defines exception levels (EL) 0, EL1, EL2, and EL3. Each exception level has different permissions and functions, supporting different operations and tasks. EL0 is known as the unprivileged exception level, corresponding to ordinary user-space applications. EL1 is the privileged level of the operating system kernel. At the EL1 level, the operating system kernel can directly access hardware resources and manage and schedule EL0-level applications. EL2 is the virtualization privilege level. At the EL2 level, a virtualization hypervisor can run to support virtualization technologies, such as running virtual machines on the ARM architecture. EL3 is the highest privilege level, also known as secure monitor mode, and is the only exception level with the ability to switch between secure and non-secure execution states.

[0141] As mentioned above, a TEE is a trusted execution environment (TEE), corresponding to the REE, used to handle security-sensitive tasks and data. The TEE and REE can operate in two different security domains: the TEE corresponds to the secure world, and the REE corresponds to the non-secure world. Accordingly, the ARM architecture defines security exception levels 0 (Secure EL0, S-EL0), S-EL1, S-EL2, and S-EL3 within the secure world for the TEE. S-EL0 is the lowest privilege level for the TEE. At SEL0, the TEE can execute ordinary userspace tasks in the secure domain, with certain privileges required to handle security-sensitive operations and data. S-EL1 is the TEE privilege level. At S-EL1, the TEE can execute kernel-level tasks in the secure domain, with a higher privilege level used to manage and protect operations and resources within the TEE. S-EL2 is the TEE's virtualization privilege level. At S-EL2, a virtualization supervisor can run to support virtualization technologies, such as running virtual machines in the secure domain. S-EL3 is the highest privilege level of TEE, which can run a security supervisor. It is the only exception level that has the ability to switch between secure execution state and non-secure execution state.

[0142] Figure 9 is a schematic diagram of a scenario in which the second core runs two computing resources in an embodiment of the present application. In Figure 9, the second core includes computing resource 1 and computing resource 2, which can also be called hardware threads (also called logical threads). The second core uses computing resource 1 to execute the first thread, and the second core uses computing resource 2 to execute the second thread. Both computing resource 1 and computing resource 2 have REE mode and TEE mode.

[0143] In Figure 9, REE mode includes EL1 and EL2. EL1 is used to run the REE operating system (OS) (e.g., Linux), and EL2 is used to run a virtualization supervisor. TEE mode includes S-EL1, S-EL2, and S-EL3. S-EL1 runs the TEE OS and secure partition (SP), S-EL2 runs a virtualization supervisor, and S-EL3 runs a security monitor. The SP provides hardware-level security isolation and protection. The security monitor is used to switch between REE mode and TEE mode.

[0144] If both the first and second threads correspond to tasks in REE mode, and the second core executes them concurrently, if one of the threads triggers the CA / TA process, the computing resource corresponding to that thread will enter TEE mode. This will result in the second core executing both TEE and REE modes simultaneously. For example, if the first thread triggers the CA / TA process, computing resource 1 will enter TEE mode, while computing resource 2 corresponding to the second thread will remain in REE mode. Simultaneously running in both REE and TEE modes (as shown in Figure 10) exposes data in TEE mode to the risk of unauthorized access, such as through side-channel probing. The CA / TA process involves the following: the CA registers the corresponding TA in the TEE. A secure communication channel is established between the CA and the TEE to facilitate secure interaction with the TA. The CA sends a request to the TEE to launch the corresponding TA, including the TA's identifier and required parameters. The TEE verifies the TA's identifier in the request and ensures the TA's integrity and authenticity. If verification is successful, the TEE loads the TA and transfers control to the TA's execution environment. The TA performs specific security functions and operations in the TEE. It can use the security API provided by the TEE to perform security operations such as key generation, encryption and decryption, and digital signatures. The TA returns the results to the CA for subsequent processing. After the TA completes a specific operation, the CA can request to terminate and uninstall the TA.

[0145] As can be seen from the above, there is a security risk when the first thread and the second thread are executed in environments with different security levels. Therefore, in an embodiment of the present application, the same security level can be set for the first thread and the second thread, so that the first thread and the second thread can run in an environment with the same security level, thereby preventing the security risks caused by the first thread and the second thread being executed in environments with different security levels. For example, the security level of the first thread and the second thread can both be set to TEE mode.

[0146] Since the second core uses computing resource 1 to execute the first thread, and the second core uses computing resource 2 to execute the second thread, the security levels of computing resource 1 and computing resource 2 can be adjusted so that the security levels of the first thread and the second thread are both in TEE mode. Continuing with Figure 9, the process of adjusting the security levels of computing resource 1 and computing resource 2 includes:

[0147] Step ①: Computing resource 1 switches from REE mode to TEE mode.

[0148] Specifically, computing resource 1 switches from EL1 in REE mode to S-EL2 in TEE mode, that is, computing resource 1 enters the secure world from the non-secure world. In this way, computing resource 1 can run in TEE.

[0149] Step ②: Computing resource 1 triggers the process interruption of computing resource 2.

[0150] Specifically, the second core can trigger an inter-processor interrupt (IPI) in the scheduler of the second core before computing resource 1 enters TEE mode based on the topology of the multi-processor identity register (MPIDR), triggering computing resource 2 to dispatch the second thread currently executing on it and power off computing resource 2. When computing resource 1 enters TEEOS through S-EL2, it checks the status of computing resource 2. If computing resource 2 is still not powered off, a fast interrupt request (FIQ) is configured for computing resource 2 to interrupt computing resource 2 from EL1 in REE mode.

[0151] Among them, MPIDR usually contains information such as processor number, cluster number and level number, which can help operating systems and software effectively manage and schedule tasks of multi-core processors.

[0152] Step ③: Computing resource 2 switches from REE mode to TEE mode.

[0153] Specifically, computing resource 2 switches from EL1 in REE mode to S-EL2 in TEE mode, that is, computing resource 2 enters the secure world from the non-secure world. In this way, computing resource 2 can run in TEE.

[0154] Step ④: Computing resource 1 and computing resource 2 run in TEE OS.

[0155] Specifically, computing resource 1 enters TEE mode from EL1 in REE mode and then enters TEE OS from S-EL2 in TEE mode, running computing resource 1 in TEE OS. At this time, the second core uses computing resource 1 to execute the first thread, and the security level of the first thread is TEE mode. Similarly, computing resource 2 has either been powered off or has been forced to wait in TEE state after entering TEE mode from EL1 in REE mode to S-EL2 in TEE mode. If the power-on process of computing resource 2 is triggered midway, it will also trigger computing resource 2 to be forced to wait in TEE state when the process passes through S-EL2. At this time, the second core uses computing resource 2 to execute the second thread, and the security level of the second thread is TEE mode.

[0156] Step 5: Computing resource 1 and computing resource 2 switch from TEE mode to REE mode.

[0157] Specifically, after the second core uses computing resource 1 to execute the first thread and uses computing resource 2 to execute the second thread, computing resource 1 and computing resource 2 synchronously exit from TEE mode to EL1 in REE mode.

[0158] In the above process, the second core can run computing resource 1 and computing resource 2 in TEE mode at the same time (as shown in Figure 11), so that the first thread executed by computing resource 1 and the second thread executed by computing resource 2 have the same security level (i.e., TEE mode), which can eliminate the security risks caused by the different security levels of the first thread and the second thread when the second core executes the first thread and the second thread in parallel.

[0159] According to the method provided in the embodiments of the present application, the present application also provides a computer-readable storage medium, which stores program code. When the program code runs on a computer, the computer executes the method of any one of the above method embodiments.

[0160] An embodiment of the present application also provides an electronic device, which is used to execute the method of any one of the above method embodiments.

[0161] As used in this specification, the terms "component," "module," "system," and the like are used to refer to computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and a computing device can be a component. One or more components can reside in a process and / or an execution thread, and a component can be located on one computer and / or distributed between two or more computers. In addition, these components can be executed from various computer-readable media having various data structures stored thereon. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component across a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0162] Those skilled in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0163] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0164] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0165] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0166] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0167] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0168] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A heterogeneous multi-core device, characterized in that: The method comprises a plurality of cores, wherein the plurality of cores comprises at least one high-performance core and at least one energy-efficiency core, the maximum power consumption of any core in the at least one high-performance core is greater than the maximum power consumption of any core in the at least one energy-efficiency core, and the maximum computing capability of any core in the at least one high-performance core is greater than the maximum computing capability of any core in the at least one energy-efficiency core; wherein: A first core among the multiple cores is used to allocate a first computing resource to a first thread and a second computing resource to a second thread, wherein the first computing resource and the second computing resource belong to a second core among the multiple cores, and the second core is the first core or another core different from the first core; The second core is used to execute the first thread and the second thread in parallel, wherein the first computing resource is used to execute the first thread, and the second computing resource is used to execute the second thread.

2. The device according to claim 1, characterized in that The multiple cores also include at least one medium-performance core, the maximum power consumption of any of the at least one high-performance core is greater than the maximum power consumption of any of the at least one medium-performance core, and the maximum computing capability of any of the at least one high-performance core is higher than the maximum computing capability of any of the at least one medium-performance core; the maximum power consumption of any of the at least one medium-performance core is greater than the maximum power consumption of any of the at least one energy-efficiency core, and the maximum computing capability of any of the at least one medium-performance core is higher than the maximum computing capability of any of the at least one energy-efficiency core.

3. The device according to claim 1 or 2, characterized in that The first core is specifically used for: Allocating the first computing resource to the first thread on the second core according to the performance requirement of the first thread; The second computing resource is allocated to the second thread on the second core according to the performance requirement of the second thread.

4. The device according to any one of claims 1 to 3, characterized in that: The first computing resource includes a first dedicated computing resource, and the second computing resource includes a second dedicated computing resource different from the first dedicated computing resource; the first dedicated computing resource and the second dedicated computing resource have different proportions in the hardware resources of the second core.

5. The device according to any one of claims 1 to 4, characterized in that: The first computing resource and the second computing resource include shared computing resources; the second core is further used to: execute the first thread and the second thread in parallel by time-sharing the shared computing resources; wherein the priority of the first thread is higher than the priority of the second thread; in the time-sharing, the time when the first thread uses the shared computing resources takes precedence over the time when the second thread uses the shared computing resources.

6. The device according to claim 5, characterized in that The shared computing resources include at least one of the following: Instruction translation bypass buffer ITLB, instruction cache memory ICache, branch target buffer BTB, register renaming table RRT, physical register file RPF, data translation bypass buffer DTLB, or cache memory DCache.

7. The device according to any one of claims 1 to 6, characterized in that: The second core is further used for: When the first thread causes a blockage in the pipeline front end of the second core and the third thread causes a blockage in the pipeline back end of the third core among the multiple cores, the third thread is scheduled to be executed on the second core, or the first thread is scheduled to be executed on the third core, wherein the third core is different from the second core.

8. The device according to any one of claims 1 to 7, characterized in that: The first thread and the second thread have the same security level.

9. The device according to claim 8, characterized in that The security level is Trusted Execution Environment (TEE) mode.

10. A scheduling method, characterized in that: The method comprises: Allocating a first computing resource to a first thread, and allocating a second computing resource to a second thread; wherein the first computing resource and the second computing resource belong to a first core or a second core among a plurality of cores included in a heterogeneous multi-core device; the plurality of cores include at least one high-performance core and at least one energy-efficiency core, the maximum power consumption of any core in the at least one high-performance core is greater than the maximum power consumption of any core in the at least one energy-efficiency core, and the maximum computing capability of any core in the at least one high-performance core is greater than the maximum computing capability of any core in the at least one energy-efficiency core; The first thread and the second thread are executed in parallel, wherein the first computing resource is used to execute the first thread and the second computing resource is used to execute the second thread.

11. The method according to claim 10, characterized in that The multiple cores also include at least one medium-performance core, the maximum power consumption of any of the at least one high-performance core is greater than the maximum power consumption of any of the at least one medium-performance core, and the maximum computing capability of any of the at least one high-performance core is higher than the maximum computing capability of any of the at least one medium-performance core; the maximum power consumption of any of the at least one medium-performance core is greater than the maximum power consumption of any of the at least one energy-efficiency core, and the maximum computing capability of any of the at least one medium-performance core is higher than the maximum computing capability of any of the at least one energy-efficiency core.

12. The method according to claim 10 or 11, characterized in that Allocating the first computing resource to the first thread includes: allocating the first computing resource to the first thread on the second core according to the performance requirement of the first thread; The allocating the second computing resource to the second thread includes: allocating the second computing resource to the second thread on the second core according to the performance requirement of the second thread.

13. The method according to any one of claims 10 to 12, characterized in that: The first computing resource includes a first dedicated computing resource, and the second computing resource includes a second dedicated computing resource different from the first dedicated computing resource; the first dedicated computing resource and the second dedicated computing resource have different proportions in the hardware resources of the first core or the second core.

14. The method according to any one of claims 10 to 13, characterized in that: The first computing resource and the second computing resource include shared computing resources; the method further comprising: The first thread and the second thread are executed in parallel by time-sharing the shared computing resources; wherein the priority of the first thread is higher than the priority of the second thread; in the time-sharing, the time when the first thread uses the shared computing resources takes precedence over the time when the second thread uses the shared computing resources.

15. The method according to claim 14, characterized in that The shared computing resources include at least one of the following: Instruction translation bypass buffer ITLB, instruction cache memory ICache, branch target buffer BTB, register renaming table RRT, physical register file RPF, data translation bypass buffer DTLB, or cache memory DCache.

16. The method according to any one of claims 10 to 15, characterized in that: The method further comprises: When the first thread causes a blockage in the pipeline front end of the second core and the third thread causes a blockage in the pipeline back end of a third core among the multiple cores, the third thread is scheduled to be executed on the second core, or the first thread is scheduled to be executed on the third core, wherein the third core is different from the second core.

17. The method according to any one of claims 10 to 16, characterized in that: The first thread and the second thread have the same security level.

18. The method according to claim 17, characterized in that The security level is Trusted Execution Environment (TEE) mode.

19. A scheduling device, characterized in that: include: A scheduling unit, configured to allocate a first computing resource to a first thread, and allocate a second computing resource to a second thread; wherein the first computing resource and the second computing resource belong to a first core or a second core among a plurality of cores included in a heterogeneous multi-core device; the plurality of cores include at least one high-performance core and at least one energy-efficiency core, the maximum power consumption of any core in the at least one high-performance core is greater than the maximum power consumption of any core in the at least one energy-efficiency core, and the maximum computing capability of any core in the at least one high-performance core is greater than the maximum computing capability of any core in the at least one energy-efficiency core; An execution unit is used to execute the first thread and the second thread in parallel, wherein the first computing resource is used to execute the first thread and the second computing resource is used to execute the second thread.

20. The device according to claim 19, characterized in that The multiple cores also include at least one medium-performance core, the maximum power consumption of any of the at least one high-performance core is greater than the maximum power consumption of any of the at least one medium-performance core, and the maximum computing capability of any of the at least one high-performance core is higher than the maximum computing capability of any of the at least one medium-performance core; the maximum power consumption of any of the at least one medium-performance core is greater than the maximum power consumption of any of the at least one energy-efficiency core, and the maximum computing capability of any of the at least one medium-performance core is higher than the maximum computing capability of any of the at least one energy-efficiency core.

21. The device according to claim 19 or 20, characterized in that The scheduling unit is specifically used for: Allocating the first computing resource to the first thread on the second core according to the performance requirement of the first thread; The second computing resource is allocated to the second thread on the second core according to the performance requirement of the second thread.

22. The device according to any one of claims 19 to 21, characterized in that The first computing resource includes a first dedicated computing resource, and the second computing resource includes a second dedicated computing resource different from the first dedicated computing resource; the first dedicated computing resource and the second dedicated computing resource have different proportions in the hardware resources of the first core or the second core.

23. The device according to any one of claims 19 to 22, characterized in that The first computing resource and the second computing resource include shared computing resources; the execution unit is further used for: The first thread and the second thread are executed in parallel by time-sharing the shared computing resources; wherein the priority of the first thread is higher than the priority of the second thread; in the time-sharing, the time when the first thread uses the shared computing resources takes precedence over the time when the second thread uses the shared computing resources.

24. The device according to claim 23, characterized in that The shared computing resources include at least one of the following: Instruction translation bypass buffer ITLB, instruction cache memory ICache, branch target buffer BTB, register renaming table RRT, physical register file RPF, data translation bypass buffer DTLB, or cache memory DCache.

25. The device according to any one of claims 19 to 24, characterized in that The scheduling unit is also used for: When the first thread causes a blockage in the pipeline front end of the second core and the third thread causes a blockage in the pipeline back end of the third core among the multiple cores, the third thread is scheduled to be executed on the second core, or the first thread is scheduled to be executed on the third core, wherein the third core is different from the second core.

26. The device according to any one of claims 19 to 25, characterized in that The first thread and the second thread have the same security level.

27. The device according to claim 26, characterized in that The security level is Trusted Execution Environment (TEE) mode.

28. A computing device, characterized in that The computing device includes a heterogeneous multi-core device as described in any one of claims 1-9 or a scheduling device as described in any one of claims 19-27.

29. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes instructions, which, when executed on a computer, enable the computer to execute the operating steps of any one of the methods of claims 10 to 18.

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