Drive circuit and display panel

Abstract

A drive circuit and a display panel. The drive circuit comprises at least two transistors (100), a storage capacitor (200), and at least one compensation capacitor (300). The storage capacitor (200) is electrically connected to a gate of at least one transistor (100) and is configured to store the gate potential of the connected transistor (100); and the at least one compensation capacitor (300) is connected in parallel to the storage capacitor (200). The drive circuit is set to comprise at least one compensation capacitor (300) connected in parallel with the storage capacitor (200), such that the capacitance value of the storage capacitor (200) is increased, i.e., the charge storage capability of the storage capacitor (200) is increased; and therefore, the gate voltage of the transistor connected to an electrode plate of the storage capacitor (200) can be more stable, thereby facilitating improvement of the picture display quality of the display panel.

Description

Driving circuit and display panel

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 31, 2023, with application number 202310953268.6, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of display technology, for example, to a driving circuit and a display panel. Background Art

[0003] With the development of display technology, users' requirements for picture display quality are getting higher and higher.

[0004] The display panel includes a driving circuit including a storage capacitor for storing charges.

[0005] However, in the related art, there is a problem that the storage capacitor has a relatively small charge storage capacity.

[0006] Summary of the Invention

[0007] The present application provides a driving circuit and a display panel to increase the storage capacitance in the driving circuit, thereby improving the charge storage capacity and enhancing the picture display quality.

[0008] In a first aspect, an embodiment of the present application provides a driving circuit comprising at least two transistors, a storage capacitor and at least one compensation capacitor, wherein the storage capacitor is electrically connected to the gate of at least one transistor for storing the gate potential of the connected transistor; and at least one compensation capacitor is connected in parallel with the storage capacitor.

[0009] In a second aspect, an embodiment of the present application further provides a display panel comprising the driving circuit of the first aspect.

[0010] The driving circuit and display panel of the embodiment of the present application, by setting the driving circuit to include at least one compensation capacitor connected in parallel with the storage capacitor, is equivalent to increasing the capacitance value of the storage capacitor, that is, equivalent to increasing the charge storage capacity of the storage capacitor, so that the gate voltage of the transistor connected to the electrode plate of the storage capacitor can be more stable, which is beneficial to improving the picture display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG1 is a schematic diagram of a driving circuit provided in an embodiment of the present application.

[0012] FIG2 is a top view of a driving circuit provided in an embodiment of the present application;

[0013] FIG3 is a schematic structural diagram of the conductive structure layer in FIG2 ;

[0014] FIG4 is a cross-sectional view taken along AA′ in FIG2 ;

[0015] FIG5 is a cross-sectional view taken along BB' in FIG2

[0016] FIG6 is a cross-sectional view taken along CC' of FIG2;

[0017] FIG7 is a top view of another driving circuit provided in an embodiment of the present application;

[0018] FIG8 is a schematic structural diagram of the conductive structure layer in FIG7;

[0019] FIG9 is a cross-sectional view taken along DD' of FIG7;

[0020] FIG10 is a cross-sectional view taken along EE' in FIG7;

[0021] FIG11 is a schematic structural diagram of another driving circuit provided in an embodiment of the present application;

[0022] FIG12 is a top view of another driving circuit provided in an embodiment of the present application;

[0023] FIG13 is a schematic structural diagram of the conductive structure layer in FIG12;

[0024] FIG14 is a cross-sectional view taken along FF' in FIG12;

[0025] FIG15 is a cross-sectional view taken along HH' in FIG12;

[0026] FIG16 is a schematic structural diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] As described in the background technology, in the related art, there is a situation where the storage capacitor has a small charge storage capacity. The reason for the above situation is that the size of the storage capacitor affects the charge storage capacity of the storage capacitor. The storage capacity of the storage capacitor for charge is positively correlated with the size of the storage capacitor, that is, the larger the storage capacitor, the stronger the charge storage capacity; the smaller the storage capacitor, the weaker the charge storage capacity. In the related art, a transistor in the driving circuit is usually connected to one storage capacitor, and the capacitance value of the storage capacitor cannot be made very large, which limits the storage capacity of the storage capacitor for charge. When the driving circuit is a pixel circuit, the storage capacity of the storage capacitor is small, which will make the display panel prone to flickering when displaying. When the driving circuit is a circuit that provides a driving signal to the pixel circuit, the storage capacity of the storage capacitor is small, which will cause the driving signal provided to the pixel circuit to be unstable, affecting the normal operation of the pixel circuit, and also affecting the display quality of the picture.

[0028] Based on the above reasons, an embodiment of the present application provides a driving circuit. Figure 1 is a structural schematic diagram of a driving circuit provided by an embodiment of the present application. Referring to Figure 1, the driving circuit includes at least two transistors 100, a storage capacitor 200 and at least one compensation capacitor 300. The storage capacitor 200 is electrically connected to the gate of at least one transistor 100 and is configured to store the gate potential of the connected transistor 100; at least one compensation capacitor 300 is connected in parallel with the storage capacitor 200.

[0029] The driving circuit may be a pixel circuit in a display panel. FIG1 schematically illustrates a structure in which the driving circuit is a pixel circuit, and FIG1 exemplarily illustrates a case in which the driving circuit includes two transistors 100. In other embodiments of the present application, the driving circuit may include more transistors 100. The display panel may also be a circuit in the display panel that outputs a driving signal to the pixel circuit. Exemplarily, the driving circuit may be a gate driving circuit for providing a gate driving signal. When the gate driving signal is a scanning signal, the gate driving circuit is a scanning circuit; when the gate driving signal is a light-emitting control signal, the driving circuit is a light-emitting control driving circuit.

[0030] Continuing with reference to FIG1 , the driving circuit further includes a storage capacitor 200 and at least one compensation capacitor 300, wherein the at least one compensation capacitor 300 is connected in parallel with the storage capacitor 200. This is equivalent to increasing the capacitance of the storage capacitor 200, which is equivalent to increasing the charge storage capacity of the storage capacitor 200, so that the gate voltage of the transistor 100 connected to the storage capacitor 200 can be more stable. When the driving circuit is a pixel circuit, the phenomenon of screen flickering can be improved; when the driving circuit is a circuit that provides a driving signal to the pixel circuit, it can provide a more stable driving signal to the pixel circuit, thereby allowing the pixel circuit to operate normally.

[0031] The driving circuit of this embodiment, by setting the driving circuit to include at least one compensation capacitor connected in parallel with the storage capacitor, is equivalent to increasing the capacitance value of the storage capacitor, that is, equivalent to increasing the charge storage capacity of the storage capacitor, so that the gate voltage of the transistor connected to the electrode plate of the storage capacitor can be more stable, which is beneficial to improving the picture display quality of the display panel.

[0032] For example, the vertical distance between the two plates of the compensation capacitor is smaller than the vertical distance between the two plates of the storage capacitor.

[0033] The capacitance value of a capacitor is negatively correlated with the vertical distance between the two plates of the capacitor. Under the same conditions as other factors affecting the capacitance value, the larger the vertical distance between the two plates of the capacitor, the smaller the capacitance value of the capacitor; the smaller the vertical distance between the two plates of the capacitor, the larger the capacitance value of the capacitor. In this embodiment, the vertical distance between the two plates of the compensation capacitor is smaller than the vertical distance between the two plates of the storage capacitor, which can make it easier for the compensation capacitor to have a larger capacitance value. After the storage capacitor is connected in parallel with the compensation capacitor, the capacitance value of the storage capacitor is significantly increased, which is more conducive to improving the charge storage capacity, and thus more conducive to improving the picture display quality.

[0034] As the requirements for picture display quality are getting higher and higher, the demand for high-resolution display products is also getting higher and higher. Therefore, it is necessary to compress the pixel size, and accordingly, the size of the driving circuit also needs to be compressed. Based on this, the present application proposes a structure in which at least part of the circuit components in the driving circuit are vertically stacked. Figure 2 is a top view of a driving circuit provided in an embodiment of the present application, and Figure 3 is a structural schematic diagram of the conductive structure layer in Figure 2, wherein Figure 3 shows the conductive structure layers in Figure 2 in order from bottom to top, Figure 4 is a cross-sectional view obtained by cutting Figure 2 along AA', and Figure 5 is a cross-sectional view obtained by cutting Figure 2 along BB'. Referring to Figures 2-5, for example, at least two transistors 100 are vertically stacked; in a first direction x1, the orthographic projections of the at least two vertically stacked transistors 100 are at least partially overlapped; wherein the first direction x1 is the direction in which the at least two transistors 100 are vertically stacked.

[0035] For example, at least two transistors 100 in the driving circuit are vertically stacked, and along the first direction x1 in which the at least two transistors 100 are vertically stacked, the orthographic projections of the at least two vertically stacked transistors 100 are at least partially overlapped, so that compared with the flat arrangement of the circuit devices in the driving circuit, the orthographic projection area of ​​the entire driving circuit in the first direction x1 can be reduced, that is, the planar area occupied by the entire driving circuit can be reduced, and then the size of the driving circuit can be reduced, which is conducive to realizing a high-resolution display panel structure.

[0036] Figure 6 is a cross-sectional view obtained by cutting along CC' of Figure 2. Continuing to refer to Figures 2 to 6, for example, the driving circuit also includes a shielding structure 400, which is connected to a fixed voltage signal; in the first direction x1, the shielding structure is between adjacent transistors 100; the orthographic projection of the shielding structure 400 in the first direction x1 covers at least part of the orthographic projection of the gates of the transistors 100 on both sides of the shielding structure 400 in the first direction x1; wherein, the transistors 100 on both sides of the shielding structure 400 are transistors 100 located on both sides of the shielding structure 400 in the first direction x1.

[0037] For example, in a driver circuit, the gates of different transistors 100 typically receive different signals. When at least two transistors 100 are stacked vertically, the signals received by the different transistors 100 may interact with each other, affecting the normal operation of the driver circuit. Furthermore, when at least two transistors 100 of a driver circuit are stacked vertically, the gate of one transistor 100 may be closer to the active layer of another transistor 100 in the first direction x1, causing the original single-gate transistor 100 to become a dual-gate transistor 100 structure, which also affects the normal operation of the driver circuit. To avoid the above problems, in this embodiment, a driving circuit is provided including a shielding structure 400, and the shielding structure 400 is located between adjacent transistors 100 in the first direction x1; the orthographic projection of the shielding structure 400 in the first direction x1 covers the orthographic projection of the gates of the transistors 100 on both sides of the shielding structure 400 in the first direction x1, and the shielding structure 400 is connected to a fixed voltage signal. In this way, changes in the gate potential of the transistor 100 on one side of the shielding structure 400 will not affect the gate potential of the transistor 100 on the other side of the shielding structure 400; and the original single-gate transistor 100 can be prevented from becoming a dual-gate transistor 100, thereby reducing the size of the driving circuit while ensuring that the transistors 100 vertically stacked in the driving circuit do not affect each other, thereby ensuring that the driving circuit can operate normally.

[0038] The driving circuit shown in Figures 2-6 corresponds to the driving circuit shown in Figure 1. Figures 2-6 schematically illustrate a driving circuit including two compensation capacitors. Referring to Figures 1-6, the driving circuit includes a driving transistor 110. The source of the driving transistor 110 is connected to a first power line VDD, which is also connected to the source of the driving transistor 110. The drain of the driving transistor 110 is connected to a first electrode of a light-emitting device 500, and the second electrode of the light-emitting device 500 is connected to a second power line VSS. The signal connected to the first power line VDD is a fixed first power supply voltage, and the signal connected to the second power line VSS is a fixed second power supply voltage. The shielding structure 400 can be electrically connected to either the first power line VDD or the second power line VSS. This arrangement eliminates the need for additional power supply lines in the display panel to provide a fixed voltage signal to the shielding structure 400 and signal lines to transmit the signal, simplifying the display panel's wiring and further reducing the size of the driving circuit. The driving circuit structure shown in Figure 6 schematically illustrates a driving circuit structure in which the shielding structure 400 is connected to the first power line VDD.

[0039] Continuing with Figures 2-6 , transistor 100 includes an active layer. For example, the orthographic projections of the active layers of at least two transistors 100 along a first direction x1 at least partially overlap. This arrangement can further reduce the orthographic projection area of ​​the entire driver circuit along the first direction x1, thereby reducing the planar area occupied by the entire driver circuit, thereby reducing the size of the driver circuit and further facilitating the implementation of a high-resolution display panel structure. The active layer of driver transistor 110 is designated as first active layer 112, and the active layer of switch transistor 120 is designated as second active layer 122.

[0040] Continuing to refer to FIG. 2 to FIG. 6 , for example, the driving circuit includes a first compensation capacitor 310 ; the first compensation capacitor 310 includes a first plate 311 and a second plate 312 ; the storage capacitor 200 includes a third plate 210 and a fourth plate 220 ;

[0041] The third electrode plate 210 is reused as the first electrode plate 311 or is electrically connected to the first electrode plate 311 ; in the first direction x1 , the second electrode plate 312 and the fourth electrode plate 220 are located on the same side or different sides of the first electrode plate 311 , and the second electrode plate 312 is electrically connected to the fourth electrode plate 220 .

[0042] For example, when the third plate 210 of the storage capacitor 200 is reused as the first plate 311, there is no need to separately provide the first plate 311 of the first compensation capacitor 310. This can reduce the film layer of the drive circuit required when the first plate 311 of the first compensation capacitor 310 is additionally provided and / or the orthographic projection area of ​​the drive circuit required to be increased in the first direction x1 when the first plate 311 of the first compensation capacitor 310 is additionally provided, thereby further reducing the size of the circuit. When the third plate 210 is an additional structure electrically connected to the first plate 311, the film layer where the third plate 210 is located can be flexibly provided, thereby facilitating the realization of a first compensation capacitor 310 with a larger capacitance.

[0043] Depending on the stacking arrangement of the transistor 100 in the driving circuit, and the connection relationship between the storage capacitor 200 and the compensation capacitor 300 and the transistor 100, along the first direction x1, the second electrode plate 312 and the fourth electrode plate 220 can be arranged on the same side of the first electrode plate 311, or on different sides of the first electrode plate 311. The second electrode plate 312 and the fourth electrode plate 220 are electrically connected, and this electrical connection can be achieved through a via structure, or by indirectly connecting the second electrode plate 312 and the fourth electrode plate 220 to the same conductive structure.

[0044] For example, the driving circuit includes a second compensation capacitor 320 , and the second compensation capacitor 320 includes a fifth plate 321 and a sixth plate 322 ; the fifth plate 321 is electrically connected to the third plate 210 and is located between the third plate 210 and the fourth plate 220 , and the fourth plate 220 is reused as the sixth plate 322 .

[0045] For example, the fourth plate 220 of the storage capacitor 200 is reused as the sixth plate 322 of the second compensation capacitor 320, and the fifth plate 321 is electrically connected to the third plate 210. In the first direction x1, the fifth plate 321 is located between the third plate 210 and the fourth plate 220, which can ensure that the vertical distance between the fifth plate 321 and the sixth plate 322 is smaller than the vertical distance between the third plate 210 and the fourth plate 220, thereby ensuring that the second compensation capacitor 320 can more easily have a larger capacitance value, so that after the second compensation capacitor 320 is connected in parallel with the storage capacitor 200, the capacitance value of the storage capacitor 200 can be significantly increased, thereby improving the charge storage capacity.

[0046] 1 to 6 , for example, the driving circuit includes a pixel circuit, and the pixel circuit includes a driving transistor 110 and at least one switching transistor 120 ; the driving transistor 110 and the at least one switching transistor 120 are vertically stacked.

[0047] In the pixel circuit, the driving transistor 110 and the switching transistor 120 have different electrical properties. The driving transistor 110 has a longer channel length, so the orthographic projection of the driving transistor 110 in the first direction x1 is larger, that is, the driving transistor 110 occupies a larger planar area. In this embodiment, the driving transistor 110 and at least one switching transistor 120 are arranged vertically stacked so that the overlapping portion of the orthographic projections of the driving transistor 110 and the switching transistor 120 in the first direction x1 does not occupy additional planar area, which helps reduce the size of the pixel circuit, thereby reducing the pixel size and facilitating the realization of a high-resolution display panel structure.

[0048] For example, the switching transistor 120 included in the pixel circuit includes a data writing transistor T0, the gate 121 of the data writing transistor T0 is connected to the scan line SCAN, the first electrode 123 of the data writing transistor T0 is connected to the data line VDATA, and the second electrode 124 of the data writing transistor T0 is connected to the gate 111 of the driving transistor 110; the first electrode 113 of the driving transistor 110 is connected to the first power line VDD, the second electrode 114 of the driving transistor 110 is connected to the first electrode 510 of the light-emitting device 500, and the second electrode of the light-emitting device 500 is connected to the second power line VSS.

[0049] The data write transistor T0 is turned on or off according to the scan signal transmitted on the scan line SCAN. When the data write transistor T0 is turned on, the data voltage on the data line VDATA is transmitted to the gate 111 of the driving transistor 110 through the data write transistor T0. The driving transistor 110 can generate a driving current based on the voltage of its own gate 111 and the first electrode 113 to output the light-emitting device 500. The pixel circuit of this embodiment includes only two transistors 100, namely, one data write transistor T0 and one driving transistor 110. The number of devices included in the pixel circuit is relatively small, which is more conducive to realizing a small-sized pixel circuit, and thus realizing a high-resolution display panel structure. It can be applied to display products of virtual reality (VR), augmented reality (AR), and mixed reality (MR).

[0050] In which, the signal transmitted on the first power line VDD is a fixed first power voltage, and the signal transmitted on the second power line VSS is a fixed second power voltage. As described above, for example, the shielding structure 400 is electrically connected to the first power line VDD or the second power line VSS, so that the wiring of the display panel is simplified, which is beneficial for further reducing the size of the driving circuit.

[0051] Based on the above technical solution, for example, when the shielding structure 400 is connected to the first power line VDD, the shielding structures 400 of different pixel circuits are connected to each other in a set direction, where the set direction intersects with the extending direction of the first power line VDD.

[0052] For example, pixel circuits are arranged in an array in a display panel, wherein a first power line VDD extends along the column direction of the pixel circuit array. The shielding structures 400 of pixel circuits in the same row are interconnected, that is, the shielding structures 400 are interconnected in the row direction of the pixel circuit array (that is, the direction is set to the row direction of the pixel circuits arranged in columns). This allows the shielding structures 400 and the first power line VDD to be interconnected to form a mesh structure, which is equivalent to reducing the resistance of the first power line VDD, thereby facilitating a reduction in the voltage drop when the first power line VDD transmits the first power voltage, thereby improving the uniformity of the image display and further enhancing the image display quality.

[0053] 2 to 6 , for example, the pixel circuit further includes a substrate 600 , and the driving transistor 110 is located between the substrate 600 and the switching transistor 120 .

[0054] For example, the driving transistor 110 in the pixel circuit generates a driving current, thereby driving the light-emitting device 500 to emit light, so that the display panel can realize display. The requirements for the device electrical properties and uniformity of the driving transistor 110 in the display panel are higher. In this embodiment, on the basis of vertically stacking at least two transistors 100 in the pixel circuit, the driving transistor 110 is set between the substrate 600 and the switching transistor 120, that is, the film layer where the driving transistor 110 is located is located between the substrate 600 and the film layer where the switching transistor 120 is located. There is no need to set a patterned film layer between the driving transistor 110 and the substrate 600, that is, the film layer on the side of the driving transistor 110 close to the substrate 600 is a flat film layer, or the driving transistor 110 is directly prepared on the flat substrate 600, which can make the electrical properties and uniformity of the driving transistor 110 better, thereby being more conducive to improving the display image quality.

[0055] Based on the above technical solution, for example, the driving transistor 110 has a bottom-gate structure or a top-gate structure, and the switching transistor 120 has a top-gate structure. In other embodiments of the present application, the switching transistor 120 may also have a bottom-gate structure, which is not specifically limited in this application. The top-gate or bottom-gate structure of the driving transistor 110 and the switching transistor 120 can be specifically configured according to actual needs.

[0056] Continuing with reference to Figures 2-6 , for example, the driving transistor 110 includes an N-type transistor 100, the driving circuit includes a first compensation capacitor 310, the gate 111 of the driving transistor 110 is multiplexed as a first electrode 311 and a third electrode 210; the first electrode 510 of the light-emitting device 500 is multiplexed as a fourth electrode 220, and the first electrode 510 of the light-emitting device 500 is located on a side of the switching transistor 120 away from the driving transistor 110; the second electrode 312 is electrically connected to the fourth electrode 220, and the second electrode 312 is located between the gate 111 of the driving transistor 110 and the substrate 600. The first electrode 510 of the light-emitting device 500 is the anode of the light-emitting device 500, and the second electrode of the light-emitting device 500 is the cathode of the light-emitting device 500.

[0057] In the pixel circuit, the gate 111 of the driving transistor 110 has a large area and can be used as a plate of a capacitor. In this embodiment, the gate 111 of the driving transistor 110 is directly reused as the first plate 311 and the third plate 210, reducing the need for additional film layers of the first plate 311 and the third plate 210. This allows the thickness of the vertical stack of the driving circuit to be less than that of the first plate 311 and the third plate 210, thereby reducing the size of the pixel circuit and improving the resolution while ensuring that the display panel is relatively thin. In the first direction x1, the distance between the third plate 210 and the fourth plate 220 of the storage capacitor 200 is relatively far, that is, the vertical distance between the third plate 210 and the fourth plate 220 of the storage capacitor 200 is relatively far, resulting in a smaller capacitance value of the storage capacitor 200. The second plate 312 is electrically connected to the fourth plate 220 to form a parallel structure of the first compensation capacitor 310 and the storage capacitor 200. The driving transistor 110 is a bottom-gate transistor 100. The driving transistor 110 is between the switching transistor 120 and the substrate 600. There are fewer film layers set between the driving transistor 110 and the substrate 600. The second electrode 312 is located between the gate of the driving transistor 110 and the substrate 600, so that the distance between the second electrode 312 and the gate of the driving transistor 110 is smaller, making it easier to realize a first compensation capacitor 310 with a larger capacitance.

[0058] Continuing to refer to Figures 2 to 6, for example, the driving circuit includes a second compensation capacitor 320, the first electrode 510 of the light-emitting device 500 is reused as the sixth plate 322 of the second compensation capacitor 320, and the fifth plate 321 is electrically connected to the first electrode (the first electrode 123 of the data writing transistor T0) or the second electrode (the second electrode 124 of the data writing transistor T0) of the switching transistor 120.

[0059] As shown in Figure 5, the first electrode 510 of the light-emitting device 500 is reused as the fourth plate 220 of the storage capacitor 200 and the sixth plate 322 of the second compensation capacitor 320, and the fifth plate 321 is electrically connected to the first electrode (the first electrode 123 of the data writing transistor T0) or the second electrode (the second electrode 124 of the data writing transistor T0) of the switching transistor 120. Among them, the first electrode of the switching transistor 120 (the first electrode 123 of the data writing transistor T0) can be a source or a drain, and the second electrode of the switching transistor 120 (the second electrode 124 of the data writing transistor T0) can be a drain or a source. In this embodiment, the driving transistor 110 is located between the substrate 600 and the switching transistor 120, and the light-emitting device 500 is located on the side of the switching transistor 120 away from the substrate 600. Therefore, relative to the driving transistor 110, the switching transistor 120 is closer to the first electrode 510 of the light-emitting device 500. The first electrode (the first electrode 123 of the data write transistor T0) and the second electrode (the second electrode 124 of the data write transistor T0) of the switching transistor 120 are closer to the first electrode 510 of the light-emitting device 500 than the gate 111 of the driving transistor 110. Therefore, the second compensation capacitor 320 can easily achieve a larger capacitance value than the storage capacitor 200. When the second compensation capacitor 320 is connected in parallel with the storage capacitor 200, the capacitance value of the storage capacitor 200 is increased. In addition, corresponding to the driving circuit shown in Figures 2 to 6, that is, the driving transistor 110 is located between the substrate 600 and the switching transistor 120, and the driving transistor 110 is a bottom-gate driving circuit structure and the switching transistor 120 is a top-gate driving circuit structure, the first electrode (the first electrode 123 of the data write transistor T0) and the second electrode (the second electrode 124 of the data write transistor T0) of the switching transistor 120 are located in the metal layer closest to the first electrode 510 of the light-emitting device 500 among the metal layers forming the transistor 100 and the capacitor, making it easier for the second compensation capacitor 320 to achieve a larger capacitance value.

[0060] For example, the fifth electrode plate 321 is electrically connected to the second electrode 124 of the data writing transistor T0. In some embodiments of the present application, the fifth electrode plate 321 and the lead structure of the second electrode 124 of the data writing transistor T0 are integrated into one structure. Therefore, during the manufacturing process of the driving circuit, the fifth electrode plate 321 and the lead structure of the second electrode 124 of the data writing transistor T0 can be manufactured as a single pattern, which is conducive to simplifying the mask structure and manufacturing process.

[0061] Figure 7 is a top view of another driving circuit provided in an embodiment of the present application, and Figure 8 is a structural schematic diagram of the conductive structure layer in Figure 7, wherein Figure 8 shows the conductive structure layer in Figure 7 in order from bottom to top, Figure 9 is a cross-sectional view obtained by cutting Figure 7 along DD', and Figure 10 is a cross-sectional view obtained by cutting Figure 7 along EE'. The driving circuit shown in Figures 7 to 10 can correspond to Figure 1, and Figures 7 to 10 exemplarily illustrate a case where the driving circuit includes two compensation capacitors. Referring to Figures 7 to 10, for example, in the driving circuit, the pixel circuit also includes a substrate 600, and the switching transistor 120 is located between the substrate 600 and the driving transistor 110. That is, relative to the driving transistor 110, the switching transistor 120 is closer to the substrate 600.

[0062] Based on the above technical solution, for example, the driving transistor 110 is a bottom-gate structure or a top-gate structure, and the switch transistor 120 is a top-gate structure. In other embodiments of the present application, the switch transistor 120 may also be a bottom-gate structure, which is not specifically limited in the present application.

[0063] 7-9 , for example, the driving circuit includes a first compensation capacitor 310, the gate 111 of the driving transistor 110 is reused as a first plate 311 and a third plate 210, the second plate 312 is electrically connected to the fourth plate 220, and the second plate 312 is located between the fourth plate 220 and the first plate 311; the driving transistor 110 includes an N-type transistor 100, the first electrode 510 of the light-emitting device 500 is reused as the fourth plate 220, and the first electrode 510 of the light-emitting device 500 is located on the side of the driving transistor 110 away from the switching transistor 120.

[0064] As described in the above embodiment, the gate electrode 111 of the driving transistor 110 is directly reused as the first electrode plate 311 and the third electrode plate 210, reducing the need for additional film layers for the first and third electrodes 311 and 210, thereby reducing the thickness of the vertically stacked driving circuit. In this embodiment, the second electrode plate 312 is electrically connected to the fourth electrode plate 220, and the second electrode plate 312 is located between the fourth electrode plate 220 and the first electrode plate 311. This ensures that the vertical distance between the first electrode plate 311 and the second electrode plate 312 of the first compensation capacitor 310 is less than the vertical distance between the third electrode plate 210 and the fourth electrode plate 220 of the storage capacitor 200. This makes it easier for the first compensation capacitor 310 to achieve a larger capacitance value than the storage capacitor 200. When the driving transistor 110 is an N-type transistor 100, the first electrode 510 of the light-emitting device 500 is reused as the fourth electrode plate 220. This can reduce the film layers required for the additional fourth electrode plate 220, further facilitating a thinner display panel.

[0065] Continuing with reference to Figures 7-10 , for example, the first electrode 510 of the light-emitting device 500 is multiplexed as the sixth plate 322 of the second compensation capacitor 320, and the fifth plate 321 is electrically connected to the first electrode (the first electrode 123 of the data write transistor T0) or the second electrode (the second electrode 124 of the data write transistor T0) of the switching transistor 120. The beneficial effects of this arrangement are the same as those of the driving circuit structure shown in Figure 5 , in which the first electrode 510 of the light-emitting device 500 is multiplexed as the sixth plate 322 of the second compensation capacitor 320, and the fifth plate 321 is electrically connected to the first electrode (the first electrode 123 of the data write transistor T0) or the second electrode (the second electrode 124 of the data write transistor T0) of the switching transistor 120, and are not further described here.

[0066] For example, the fifth electrode plate 321 is electrically connected to the second electrode 124 of the data writing transistor T0. In some embodiments of the present application, the fifth electrode plate 321 and the second electrode 124 of the data writing transistor T0 are an integral structure.

[0067] Referring to Figures 6 to 8, the orthographic projections of the fifth plate 321 and the second plate 312 on the substrate 600 overlap. With this arrangement, in addition to the structure of the first compensation capacitor 310 and the second compensation capacitor 320, the second plate 312 and the fifth plate 321 form another compensation capacitor, so that the storage capacitor 200 is equivalent to being further enlarged, further improving the charge storage capacity. In addition, the compensation capacitor formed by the overlap of the fifth plate 321 and the second plate 312 is additionally formed when the first compensation capacitor 310 and the second compensation capacitor 320 are set in the drive circuit. There is no need to add a new film layer structure. Under the premise of further improving the charge storage capacity, the thickness of the drive circuit will not be increased, ensuring that the display panel is relatively light and thin.

[0068] FIG11 is a schematic diagram of the structure of another driving circuit provided in an embodiment of the present application. FIG12 is a top view of another driving circuit provided in an embodiment of the present application. FIG13 is a schematic diagram of the structure of the conductive structure layer in FIG12, wherein FIG13 shows the conductive structure layers in FIG12 in order from bottom to top. FIG14 is a cross-sectional view of FIG12 taken along FF', and FIG15 is a cross-sectional view of FIG12 taken along HH'. Referring to FIG11-15, for example, in this driving circuit, the driving transistor 110 is located between the substrate 600 and the switching transistor 120. Both the driving transistor 110 and the switching transistor 120 have a top-gate structure. The driving transistor 110 includes a P-type transistor 100. The gate 111 of the driving transistor 110 is multiplexed as a first electrode plate 311 and a third electrode plate 210. The shielding structure 400 is electrically connected to the first power line VDD, and the shielding structure 400 serves as the second electrode plate 312. The fourth electrode plate 220 is electrically connected to the first power line VDD.

[0069] In order to achieve the shielding effect between the vertically stacked transistors 100, the area of ​​the shielding structure 400 is relatively large. For example, the orthographic projection of the shielding structure 400 on the substrate 600 covers the orthographic projection of the gate of the transistor 100 on both sides of the shielding structure 400. Reusing the shielding structure 400 as the second electrode 312 can, on the one hand, reduce the additional film layer structure required for the additional second electrode 312. On the other hand, because the area of ​​the shielding structure 400 is large enough, the capacitance of the formed compensation capacitor 300 can be relatively large, thereby playing a good compensation role for the capacitance of the storage capacitor 200, which is equivalent to improving the charge storage capacity of the storage capacitor 200. Among them, the fourth electrode 220 can be in the same layer as the second electrode 124 of the data write transistor T0. In some embodiments, the fourth electrode 220 can be an integrated structure with the second electrode 124 of the data write transistor T0.

[0070] On the basis of the above embodiment, for example, the first power line VDD and the data line VDATA both extend along the second direction y1; the active layer of the driving transistor 110 (i.e., the first active layer 112) includes a first active portion 1121, a second active portion 1122, and a third active portion 1123, the second active portion 1122 connects the first active portion 1121 and the third active portion 1123, the first active portion 1121 and the third active portion 1123 extend along the second direction y1, and the second active portion 1122 extends along the third direction z1, the second direction y1 intersects the third direction z1 and is perpendicular to the first direction x1; in the first direction x1, the orthographic projection of the third active portion 1123 is located between the orthographic projections of the first power line VDD and the data line VDATA; in the first direction On x1, the first active portion 1121 at least partially overlaps with the orthographic projection of the first power line VDD; the first active portion 1121 is electrically connected to the first power line VDD, and the third active portion 1123 is electrically connected to the first electrode 510 of the light-emitting device 500; the active layer of the data write transistor T0 (i.e., the second active layer 122) includes a fourth active portion 1221 and a fifth active portion 1222, the fourth active portion 1221 extends along the second direction y1, and the fifth active portion 1222 extends along the third direction z1; in the first direction x1, the fourth active portion 1221 at least partially overlaps with the orthographic projection of the third active portion 1123, the fourth active portion 1221 is electrically connected to the gate 111 of the driving transistor 110, and the fifth active portion 1222 is electrically connected to the data line VDATA.

[0071] The first active portion 1121 at least partially overlaps with the orthographic projection of the first power line VDD. The orthographic projection of the third active portion 1123 in the first direction x1 is located between the orthographic projections of the first power line VDD and the data line VDATA. This reduces the planar area occupied by the driver circuit, facilitating a reduction in the size of the driver circuit and, in turn, improving the resolution of the display panel. Furthermore, in this embodiment, the fourth active portion 1221 of the active layer in the data write transistor T0 overlaps with the orthographic projection of the third active portion 1123 in the active layer in the driver transistor 110 in the first direction x1. This results in the orthographic projections of the active layers of the driver transistor 110 and the data write transistor T0 in the first direction x1 overlapping, facilitating a reduction in the size of the driver circuit.

[0072] Based on the above technical solution, for example, the scan line SCAN extends along the third direction z1 , and in the first direction x1 , the orthographic projection of the scan line SCAN overlaps with the orthographic projections of the first active portion 1121 and the fourth active portion 1221 .

[0073] For example, in the first direction x1, the orthographic projection of the scan line SCAN overlaps with the orthographic projection of the fourth active portion 1221, thereby forming a data write transistor T0. The orthographic projection of the scan line SCAN overlaps with the orthographic projections of the first active portion 1121 and the fourth active portion 1221, that is, the orthographic projection of the scan line SCAN in the first direction x1 overlaps with the orthographic projection of the drive circuit in the first direction x1. Compared with a structure in which the scan line SCAN is disposed outside the drive circuit, the additional area occupied by the scan line SCAN can be reduced, which is beneficial for further improving the resolution of the display panel. When the data write transistor T0 is a top-gate transistor 100, the layer where the scan line SCAN is located is located on the side of the active layer of the data write transistor T0 away from the substrate 600; when the data write transistor T0 is a bottom-gate transistor 100, the layer where the scan line SCAN is located is located on the side of the active layer of the data write transistor T0 close to the substrate 600.

[0074] Continuing to refer to Figures 2 to 6, and Figures 11 to 15, for example, the first active portion 1121 is electrically connected to the first power line VDD through the first via M1, the third active portion 1123 is electrically connected to the first electrode 510 of the light-emitting device 500 through the second via M2; the fourth active portion 1221 is electrically connected to the gate 111 of the driving transistor 110 through the third via M3, and the fifth active portion 1222 is electrically connected to the data line VDATA through the fourth via M4.

[0075] For example, in the topology of the driver circuit, vias also occupy a certain area. In this embodiment, the first active portion 1121 and the first power line VDD, the third active portion 1123 and the light-emitting device 500, the fourth active portion 1221 and the gate 111 of the driver transistor 110, and the fifth active portion 1222 and the data line VDATA are each electrically connected via a via. This reduces the number of vias provided in the driver circuit, thereby further reducing the size of the driver circuit, thereby reducing the pixel size and improving the resolution.

[0076] On the basis of the above technical solution, for example, the shielding structure 400 is electrically connected to the first power supply VDD through the fifth via M5, thereby further reducing the size of the driving circuit.

[0077] Based on the above technical solution, for example, conductive structures located in different layers are electrically connected through vias filled with conductive material. The conductive structure includes the active layer of the transistor 100 and the metal layer in the drive circuit. The metal layer of the drive circuit includes the gate, first electrode, and second electrode of the transistor 100, the plate of the storage capacitor 200, the plate of the compensation capacitor 300, and various signal lines (including a first power line VDD, a second power line VSS, a data line VDATA, a scan line SCAN, etc.). The conductive structures in different layers are electrically connected through vias, and the vias are filled with conductive material.

[0078] For example, the driving circuit further includes a via protection structure 700 . The via protection structure 700 is located in the metal layer between the active layer of the transistor 100 and the substrate 600 . The conductive material in the via is electrically connected to the via protection structure 700 .

[0079] For example, an insulating layer is provided between any two adjacent conductive layers of the driving circuit. The insulating layer may be made of an inorganic material or an organic material. When forming a via hole, the insulating layer needs to be etched. The provision of the via protection structure 700 can prevent excessive etching of the insulating layer, thereby preventing over-etching.

[0080] The above embodiments describe a case where the driver circuit includes a pixel circuit. In other embodiments of the present application, the driver circuit includes a gate driver circuit, which includes a plurality of switching transistors, at least two of which are vertically stacked; the gate driver circuit includes at least one fixed potential input terminal, and the shielding structure is electrically connected to the fixed potential input terminal.

[0081] The gate drive circuit may include a high-level input terminal and a low-level input terminal, and the voltages input to the high-level input terminal and the low-level input terminal are both fixed-level signals. In this embodiment, the shielding structure is electrically connected to the fixed-potential input terminal of the gate drive circuit. This eliminates the need for additional signal lines in the gate drive circuit due to the provision of the shielding structure, ensuring that the area occupied by the gate drive circuit is small. Because the gate drive circuit is located in the non-display area of ​​the display panel, the small area occupied by the gate drive circuit can facilitate the realization of a narrow bezel on the display panel.

[0082] The present application also provides a display panel. FIG16 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. The display panel 10 includes a driving circuit according to any of the above embodiments of the present application and has the beneficial effects of the driving circuit according to any of the above embodiments of the present application, which will not be described in detail here. The display panel can be used in the mobile phone shown in FIG16, and can also be used in computers or wearable display devices.

Claims

1. A driving circuit, comprising at least two transistors, a storage capacitor and at least one compensation capacitor, wherein the storage capacitor is electrically connected to the gate of at least one of the transistors and is configured to store the gate potential of the connected transistor; and at least one of the compensation capacitors is connected in parallel with the storage capacitor.

2. The driving circuit according to claim 1, wherein: The vertical distance between the two plates of the compensation capacitor is smaller than the vertical distance between the two plates of the storage capacitor.

3. The driving circuit according to claim 2, wherein: At least two of the transistors are vertically stacked; in a first direction, orthographic projections of the at least two vertically stacked transistors at least partially overlap; The first direction is a direction in which at least two of the transistors are vertically stacked; The driving circuit further comprises a shielding structure, the shielding structure is connected to a fixed voltage signal; in a first direction, the shielding structure is between adjacent transistors; The orthographic projection of the shielding structure in the first direction covers at least part of the orthographic projection of the gates of the transistors on both sides of the shielding structure in the first direction; wherein the transistors on both sides of the shielding structure are the transistors located on both sides of the shielding structure in the first direction.

4. The driving circuit according to claim 3, wherein: The transistors include an active layer, and orthographic projections of the active layers of at least two of the transistors in the first direction at least partially overlap.

5. The driving circuit according to claim 3, wherein: At least one of the compensation capacitors includes a first compensation capacitor; the first compensation capacitor includes a first plate and a second plate, and the storage capacitor includes a third plate and a fourth plate; The third electrode plate is reused as the first electrode plate or is electrically connected to the first electrode plate; in the first direction, the second electrode plate and the fourth electrode plate are located on the same side or different sides of the first electrode plate, and the second electrode plate is electrically connected to the fourth electrode plate; and / or, At least one of the compensation capacitors includes a second compensation capacitor, and the second compensation capacitor includes a fifth electrode plate and a sixth electrode plate; the fifth electrode plate is electrically connected to the third electrode plate and is located between the third electrode plate and the fourth electrode plate, and the fourth electrode plate is reused as the sixth electrode plate.

6. The driving circuit according to claim 5, wherein: The driving circuit includes a pixel circuit, the pixel circuit includes the at least two transistors, the at least two transistors include a driving transistor and at least one switching transistor; the driving transistor and the at least one switching transistor are vertically stacked; Wherein, the switch transistor included in the pixel circuit includes a data writing transistor, the gate of the data writing transistor is connected to the scan line, the first electrode of the data writing transistor is connected to the data line, and the second electrode of the data writing transistor is connected to the gate of the driving transistor; A first electrode of the driving transistor is connected to a first power line, a second electrode of the driving transistor is connected to a first electrode of the light emitting device, and a second electrode of the light emitting device is connected to a second power line. 7 . The driving circuit according to claim 6 , wherein the shielding structure is electrically connected to the first power line or the second power line.

8. The driving circuit according to claim 6, when the shielding structure is connected to the first power line, the shielding structures of different pixel circuits are connected to each other in a set direction, wherein the set direction intersects with an extending direction of the first power line.

9. The driving circuit according to claim 6, wherein: The first power line and the data line extend along a second direction respectively; the active layer of the driving transistor includes a first active portion, a second active portion and a third active portion, the second active portion connects the first active portion and the third active portion, the first active portion and the third active portion extend along the second direction, the second active portion extends along a third direction, the second direction intersects the third direction and is perpendicular to the first direction respectively; in the first direction, the orthographic projection of the third active portion is located between the orthographic projections of the first power line and the data line; In the first direction, the first active portion at least partially overlaps with an orthographic projection of the first power line; the first active portion is electrically connected to the first power line, and the third active portion is electrically connected to a first electrode of the light emitting device; The active layer of the data writing transistor includes a fourth active portion and a fifth active portion, the fourth active portion extends along the second direction, and the fifth active portion extends along the third direction; in the first direction, the fourth active portion and the orthographic projection of the third active portion at least partially overlap, the fourth active portion is electrically connected to the gate of the driving transistor, and the fifth active portion is electrically connected to the data line.

10. The driving circuit according to claim 9, wherein: The scan line extends along the third direction, and in the first direction, an orthographic projection of the scan line overlaps with an orthographic projection of the first active portion and an orthographic projection of the fourth active portion, respectively.

11. The driving circuit according to claim 9, wherein: The first active portion is electrically connected to the first power line through a first via hole, the third active portion is electrically connected to the first electrode of the light-emitting device through a second via hole; the fourth active portion is electrically connected to the gate of the driving transistor through a third via hole, and the fifth active portion is electrically connected to the data line through a fourth via hole.

12. The driving circuit according to claim 6, wherein: The pixel circuit further includes a substrate, and the driving transistor is located between the substrate and the switching transistor.

13. The driving circuit according to claim 12, wherein: The driving transistor is a bottom gate structure or a top gate structure, and the switching transistor is a top gate structure; The gate of the driving transistor is multiplexed into the first electrode plate and the third electrode plate; The driving transistor comprises an N-type transistor, the first electrode of the light-emitting device is reused as the fourth electrode plate, and the first electrode of the light-emitting device is located on a side of the switch transistor away from the driving transistor; the second electrode plate is electrically connected to the fourth electrode plate, and the second electrode plate is located between the gate of the driving transistor and the substrate; the first electrode of the light-emitting device is reused as the sixth electrode plate of the second compensation capacitor, and the fifth electrode plate is electrically connected to the first electrode or the second electrode of the switch transistor; Alternatively, the driving transistor includes a P-type transistor, the shielding structure is electrically connected to the first power line, and the shielding structure serves as the second electrode plate; and the fourth electrode plate is electrically connected to the first power line.

14. The driving circuit according to claim 12, wherein: The fifth electrode is electrically connected to the second electrode of the data writing transistor.

15. The driving circuit according to claim 6, wherein: The pixel circuit further includes a substrate, and the switch transistor is located between the substrate and the drive transistor.

16. The driving circuit according to claim 15, wherein: The driving transistor is a bottom gate structure or a top gate structure, and the switching transistor is a top gate structure; The gate of the driving transistor is multiplexed into the first electrode plate and the third electrode plate, the second electrode plate is electrically connected to the fourth electrode plate, and the second electrode plate is located between the fourth electrode plate and the first electrode plate; The driving transistor includes an N-type transistor, the first electrode of the light-emitting device is reused as the fourth electrode plate, and the first electrode of the light-emitting device is located on a side of the driving transistor away from the switching transistor; the first electrode of the light-emitting device is reused as the sixth electrode plate of the second compensation capacitor, and the fifth electrode plate is electrically connected to the first electrode or the second electrode of the switching transistor; the orthographic projections of the fifth electrode plate and the second electrode plate on the substrate overlap; Alternatively, the driving transistor includes a P-type transistor, the shielding structure is electrically connected to the first power line, and the shielding structure serves as the second electrode plate; and the fourth electrode plate is electrically connected to the first power line.

17. The driving circuit according to claim 15, wherein: The fifth electrode is electrically connected to the second electrode of the data writing transistor.

18. The driving circuit according to claim 3, wherein: Conductive structures located at different layers are electrically connected through vias filled with conductive material; The driving circuit further includes a via protection structure, which is located in a metal layer between an active layer of the transistor and a substrate, and the conductive material in the via is electrically connected to the via protection structure.

19. The driving circuit according to claim 3, wherein: The driving circuit comprises a gate driving circuit, wherein the gate driving circuit comprises a plurality of switch transistors, and at least two of the switch transistors are vertically stacked; The gate drive circuit includes at least one fixed potential input terminal, and the shielding structure is connected to the fixed potential input terminal. Electrical connection.

20. A display panel comprising the driving circuit according to any one of claims 1 to 19.

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