Synchronous transport mode (STM) service splitting and recombination method and apparatus

Abstract

Provided in the embodiments of the present invention are a synchronous transport mode (STM) service splitting and recombination method and apparatus. The method comprises: constructing a splitting and recombination matrix on the basis of service parameters of an STM service, wherein the splitting and recombination matrix comprises a read address matrix, a selection matrix and a write address matrix, which have the same specification; and performing splitting and recombination on the STM service on the basis of the splitting and recombination matrix. By means of the present invention, the problems in the relevant art of, when splitting and recombination are performed on an STM service, memory spaces being wasted and the working efficiency being low are solved, and the effects of saving on memory spaces and improving the working efficiency are achieved.

Description

Synchronous transmission module (STM) service splitting and reorganization method and device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on the Chinese patent application (CN202310951813.8) filed on July 31, 2023, entitled “Method and Device for Splitting and Reorganizing Synchronous Transmission Module STM Services”, and claims the priority of the patent application. All the contents disclosed therein are incorporated into this disclosure by reference. Technical Field

[0003] The embodiments of the present invention relate to the field of communications, and in particular to a method and device for splitting and reassembling synchronous transmission module (STM) services. Background Art

[0004] The information structure hierarchy used by the Synchronous Digital Hierarchy (SDH) protocol is called the Synchronous Transport Mode (STM-N, N = 1, 4, 16, 64). The most basic module is the STM-1. Four STM-1s are synchronously multiplexed to form an STM-4. Sixteen STM-1s or four STM-4s are synchronously multiplexed to form an STM-16. Four STM-16s are synchronously multiplexed to form an STM-64. One challenge facing SDH technology in communication chip applications is the separation of STM1s into STM1s, STM4s into STM1 or STM4s, STM16s into STM1, STM4, or STM16s, and STM64s into STM1, STM4, STM16, or STM64s.

[0005] In related technologies, splitting and reorganizing STM services can be done using two matrices: one matrix representing the rows of the matrix after splitting, and another matrix representing the columns of the matrix after splitting, ensuring a one-to-one correspondence between the elements of the matrix before and after splitting. However, this solution wastes storage space and is inefficient.

[0006] Summary of the Invention

[0007] The embodiment of the present invention provides a synchronous transport module (STM) service splitting and reorganization method and device, so as to at least solve the problems of wasting storage space and low working efficiency when performing STM service splitting and reorganization in related technologies.

[0008] According to one embodiment of the present invention, a method for splitting and reorganizing a synchronous transmission module (STM) service is provided, comprising: constructing a splitting and reorganization matrix according to service parameters of the STM service, wherein the splitting and reorganization matrix includes a read address matrix, a selection matrix, and a write address matrix with the same specifications; and splitting and reorganizing the STM service according to the splitting and reorganization matrix.

[0009] According to another embodiment of the present invention, a synchronous transmission module STM service splitting and reorganization device is provided, including: a matrix acquisition module, configured to construct a splitting and reorganization matrix according to the service parameters of the STM service, wherein the splitting and reorganization matrix includes a read address matrix, a selection matrix, and a write address matrix with the same specifications; a splitting and reorganization module, configured to split and reorganize the STM service according to the splitting and reorganization matrix.

[0010] According to yet another embodiment of the present invention, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above method embodiments when run.

[0011] According to another embodiment of the present invention, a wavelength division transmission device is provided, including a microcontroller unit (MCU) and an optical transmission network (OTN) chip. The MCU sends a control instruction to the OTN chip, instructing the OTN chip to execute the steps in any of the above method embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG1 is a schematic diagram of the STM splitting principle in the related art;

[0013] FIG2 is a schematic diagram showing the principle of splitting STM1 into STM1 in the related art;

[0014] FIG3 is a schematic diagram showing the principle of splitting STM4 into STM1 in the related art;

[0015] FIG4 is a schematic diagram showing the principle of splitting STM4 into STM4 in the related art;

[0016] 5 is a hardware structure block diagram of a computer terminal of an STM service splitting and reorganization method according to an embodiment of the present invention;

[0017] 6 is a flowchart of a method for splitting and reorganizing an STM service according to an embodiment of the present invention;

[0018] 7 is a structural block diagram of an STM service splitting and reassembling apparatus according to an embodiment of the present invention;

[0019] FIG8 is a block diagram of a wavelength division transmission device according to an embodiment of the present invention;

[0020] FIG9 is a schematic diagram showing the principle of splitting STM16 into STM1 according to an embodiment of a scenario of the present invention;

[0021] FIG10 is a schematic diagram showing the principle of splitting STM16 into STM1 according to an embodiment of a scenario of the present invention;

[0022] FIG11 is a schematic diagram showing the principle of splitting STM4 into STM1 according to an embodiment of a scenario of the present invention;

[0023] 12 is a schematic diagram of the STM business split structure of an embodiment of the present invention;

[0024] FIG13 is a schematic diagram of the STM business splitting software architecture of an embodiment of a scenario of the present invention;

[0025] FIG14 is a schematic diagram of a write address matrix creation process according to an embodiment of the present invention;

[0026] 15 is a schematic diagram of a selection matrix and a read address matrix creation process according to an embodiment of the present invention;

[0027] 16 is a schematic diagram of a process for generating an STM16 split parent matrix by a patch overlay method according to an embodiment of the present invention;

[0028] FIG17 is a schematic diagram of the selection matrix and write address matrix creation process of the STM service reorganization in a scenario embodiment of the present invention. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with embodiments.

[0030] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0031] With the development of communications, the information required to be transmitted is not only voice, but also text, data, images, and video. Among various broadband fiber-optic access network technologies, SDH is the most widely used. The advent of SDH addressed the bottleneck in access between users and the core network caused by bandwidth limitations of the home media, which could not keep pace with the growth of the backbone network and user services. It also improved the utilization of the vast bandwidth on the transmission network. Since its introduction in the 1990s, SDH has become a mature, standardized technology, widely adopted in backbone networks.

[0032] In the related art, the project hardware solution uses a 128-bit bit width to process the STM frame structure. Figure 1 is a schematic diagram of the STM splitting principle in the related art. As shown in Figure 1, a total of 16 random access memories (RAMs) are used. The 128-bit data input in each beat is sequentially written into the 16 11-bit RAMs on the left. The data of the same beat is written at the same address of the 16 RAMs. Through the crossover rule, the data on the left will be written to the same 16 11-bit RAMs on the right.

[0033] Regarding the relationship between the hardware design of this project and the frame structure multiplexing of STM, the splitting of various STM services has different corresponding relationships. In each figure, the matrix on the left represents the RAM where the service is located before splitting, with a total of 16 rows (16 RAM blocks). Each column of the left matrix is ​​the data arriving at each clock beat; the matrix on the right represents the RAM where the service is located after splitting, also with 16 rows (16 RAM blocks). The same color indicates the write operation at the same clock beat; for cross-reading and writing, the same clock beat cannot read the same RAM on the left side. Similarly, the data on the right side cannot be written to the same RAM at the same clock beat, that is, reading and writing RAM are required to be evenly distributed on the 16 RAM blocks.

[0034] Figure 2 is a schematic diagram of the principle of splitting STM1 into STM1 in the related art. As shown in Figure 2, the STM1 service is split into STM1. Since the STM frame structure before and after the split (left and right RAM) is consistent, it is only necessary to move the data of the left RAM to the right RAM intact.

[0035] Figure 3 is a schematic diagram of the principle of splitting STM4 into STM1 in the related art. As shown in Figure 3, the four STM1s reused in the STM4 in the left RAM are split into the right RAM. According to the rules shown in Figure 3, the actions completed by the four clock beats are distinguished by four colors of different depths.

[0036] FIG4 is a schematic diagram of the principle of splitting STM4 into STM4 in the related art. As shown in FIG4 , for splitting the STM4 service into STM4, the splitting rule is shown in FIG4 , which is the same as splitting STM1 into STM1 in FIG2 .

[0037] STM16 splitting includes different scenarios for splitting an STM16 into STM1, STM4, and STM16. The process for splitting an STM16 into STM16s follows the same principles and rules as splitting an STM1 into STM1s and an STM4 into STM4s. When splitting an STM16 into STM4s, the STM16 has 16 rows, and every four rows from top to bottom constitute a position. This means there are four positions in the STM16, which are multiplexed with the STM4 positions. Therefore, there are a total of 15 possible combinations.

[0038] The STM64 service splitting is not described in detail with diagrams. This service is multiplexed and interleaved across four STM16s. Other scenarios are not covered for now. The STM16 service splitting can be divided into the 17 scenarios mentioned above. Therefore, the STM64 service splitting can be divided into 17*17*17*17 scenarios.

[0039] As mentioned above, STM1 has one splitting situation, STM4 has two splitting situations, STM16 has 17 splitting situations, and STM64 has 17*17*17*17 situations. The details are shown in Table 1 below.

[0040] Table 1 Number of STM service splitting scenarios

[0041] To solve this splitting and reorganization problem, a two-matrix solution can be used: one matrix represents the rows of the matrix after the split, and another matrix represents the columns of the matrix after the split, thus ensuring a one-to-one correspondence between the elements of the matrix before and after the split. However, this solution has two fatal drawbacks: ① The two matrices in all split cases must be enumerated and saved, which inevitably results in a large amount of space waste. The fourth column of Table 1 lists the space occupied by the two-matrix solution for saving all split matrices for each business. ② The hardware can only read and write the same RAM block once per clock tick. The same clock tick cannot guarantee access to all RAM on both sides, which greatly reduces the efficiency and flexibility of the hardware.

[0042] Therefore, the three-matrix splitting scheme (read address matrix, selection matrix, and write address matrix) proposed in the embodiment of the present invention can solve the problem of low hardware efficiency and ensure that each clock cycle can complete the reading of one element from each of the 16 RAMs before the split and the writing of one element to each of the 16 RAMs after the split. Table 2 lists the comparison of the number of clock beats required for the hardware of the two schemes to complete various business splitting.

[0043] For a comparison of the number of hardware working clock beats for the two-matrix solution and the three-matrix solution, see Table 2:

[0044] Table 2 Comparison of the number of hardware working clock beats between the two-matrix solution and the three-matrix solution

[0045] Although the three-matrix splitting solution solves the problem of low hardware efficiency, the storage space required for exhaustively splitting the matrix is ​​1.5 times that required by the two-matrix splitting solution. Therefore, the present invention proposes to use a splitting and reorganization algorithm to solve the problem of excessive memory usage of the three-matrix solution. The matrix regeneration algorithm is used to generate three split matrices under different splitting scenarios, eliminating the need to allocate memory space to store the split matrices.

[0046] As for reorganization, reorganization is the reverse process of splitting, and the principle is the same as splitting, which will not be described here. Unlike the prior art, the present invention designs a matrix splitting algorithm that uses three matrices for splitting to ensure that the splitting and reorganization of various types of services (STM1, STM4, STM16, STM64) are correct.

[0047] The method embodiments provided in the embodiments of the present disclosure can be executed on a mobile terminal, a computer terminal, or a similar computing device. Taking operation on a computer terminal as an example, FIG5 is a hardware block diagram of a computer terminal for an STM service splitting and reorganization method according to an embodiment of the present invention. As shown in FIG5 , the computer terminal may include one or more (only one is shown in FIG5 ) processors 502 (processor 502 may include, but is not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 504 for storing data. The computer terminal may also include a transmission device 506 and input / output devices 508 for communication functions. Those skilled in the art will appreciate that the structure shown in FIG5 is merely illustrative and does not limit the structure of the computer terminal. For example, the computer terminal may include more or fewer components than shown in FIG5 , or have a configuration different from that shown in FIG5 .

[0048] Memory 504 can be used to store computer programs, such as application software programs and modules, such as the computer program corresponding to the STM service splitting and reorganization method in the embodiments of the present invention. Processor 502 executes the computer program stored in memory 504 to execute various functional applications and data processing, thereby implementing the aforementioned method. Memory 504 may include high-speed random access memory (RAM) and non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, memory 504 may further include memory located remotely from processor 502, which can be connected to the computer terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0049] The transmission device 506 is used to receive or send data via a network. Specific examples of the aforementioned network may include a wireless network provided by a communications provider of a computer terminal. In one embodiment, the transmission device 506 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 506 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0050] In this embodiment, a method for splitting and reorganizing an STM service running on the above-mentioned computer terminal is provided. FIG6 is a flow chart of the method for splitting and reorganizing an STM service according to an embodiment of the present invention. As shown in FIG6 , the flow chart includes the following steps:

[0051] Step S602: constructing a splitting and reassembling matrix according to the service parameters of the STM service, wherein the splitting and reassembling matrix includes a read address matrix, a selection matrix, and a write address matrix having the same specifications;

[0052] In an exemplary embodiment, the type of STM service, the type of internal STM service, and the time slot position of the internal STM service, wherein the internal STM service is obtained by splitting the STM service.

[0053] In actual implementation, internal STM services are also STM services, mapped to higher-order STM services. An STM1 service can only map one STM1, an STM4 service can map four STM1s or one STM4, an STM16 service can map 16 STM1s, four STM4s, or one STM16, and an STM64 service can map 64 STM1s, 16 STM4s, four STM16s, or one STM64. STM16 services can also be a mix of STM1 and STM4 services, and STM64 services can be mapped to a mix of services other than STM64 services.

[0054] In an exemplary embodiment, constructing the splitting and reassembling matrix according to the service parameters includes: when the type of the STM service is the same as the type of the internal STM service, constructing a read address matrix, a selection matrix, and a write address matrix of the same specifications according to the specifications of the first RAM.

[0055] In the actual implementation process, the situation where the type of STM business is the same as the type of internal STM business can at least include: splitting STM1 into STM1, splitting STM4 into STM4, splitting STM16 into STM16, etc. In such a case, the read address matrix, selection matrix, and write address matrix of the same specifications can be directly constructed according to the specifications of the first RAM, and then split and reorganized.

[0056] In an exemplary embodiment, the splitting and reorganization matrix is ​​constructed according to the service parameters, including: when the type of the STM service is different from the type of the internal STM service, constructing a row sequence matrix according to the type of the internal STM service, wherein the element value of the row sequence matrix is ​​an integer multiple of the number of rows where the element is located and the sum of the number of columns where the element is located; patching the row sequence matrix according to the time slot position of the internal STM service to obtain a parent matrix; and obtaining a read address matrix and a selection matrix according to the parent matrix.

[0057] In the actual implementation process, the situation where the type of STM service is different from the type of internal STM service at least includes: splitting STM4 into STM1, splitting STM16 into STM4 or STM1, etc., among which, for the case of splitting STM4 into STM1, the element value of the row sequence matrix is ​​an integer multiple of the number of rows where the element is located and the sum of the number of columns where the element is located, specifically, the element value of the row sequence matrix is ​​4 times the number of rows where the element is located and the sum of the number of columns where the element is located.

[0058] In the actual implementation process, for a 16*16 matrix (the parent matrix when splitting out 16 STM1s) covering another 16*16 matrix (the parent matrix when splitting out 4 STM4s). Let the parent matrix generated by the rule of STM16 splitting 16 STM1s be matrix_1, and let the parent matrix generated by the rule of STM16 splitting 4 STM4s be matrix_2. Since the number of STM4 services mapped in STMl6 is unknown, vc4_4c_ts_mask is used instead. When vc4_4c_ts_mask == 0, it means that all the mapped STM16 services are STM1s, then the parent matrix matrix_1 can be generated according to the rule of STM16 splitting STM1s; vc4_4c_ts_mask! When =0, it means that STM4 is mapped in the STM16 service. If an STM4 is mapped in time slot 1, columns 0-3 of matrix_2 are overwritten with columns 0-3 of matrix_1 to handle this split scenario. Similarly, if an STM4 is mapped in time slot 2, columns 4-7 of matrix_2 are overwritten with columns 4-7 of matrix_1 to handle this split scenario. Similarly, if an STM4 is mapped in time slots 1, 2, 3, and 4, matrix_2 is completely overwritten with matrix_1 to handle this split scenario. That is, the meaning of patch coverage is: if a high-order STM is not split into the lowest-order STM, that is, STM1, the parent matrix split into the high-order STM is used to overwrite the parent matrix split into the low-order STM.

[0059] In the above embodiment, the actual implementation is only to replace matrix_1 by 4 columns (the elements in the 4 columns corresponding to each STM4 are positionally transformed). In the actual implementation process, matrix_2 is not generated first, but matrix_1 is generated in advance. The position of the elements in the patch time slot is transformed based on matrix_1, which is equivalent to using matrix_2 to patch matrix_1.

[0060] In an exemplary embodiment, a read address matrix and a selection matrix are obtained based on a parent matrix, including: performing a rounding operation on each element of the parent matrix, assigning the obtained integer value as a new element to the read address matrix, wherein the row value in the read address matrix is ​​the remainder value of the modulo operation on each element of the parent matrix, and the column value is the column value of each element in the parent matrix; performing a modulo operation on each element of the parent matrix, and filling the corresponding element in the new matrix with the obtained remainder corresponding to the position of the parent matrix, thereby obtaining a selection matrix.

[0061] In the actual implementation process, a selection matrix can be obtained by taking the modulo 16 value of each element of the parent matrix; taking the modulo 16 value of each element of the parent matrix, and using the value as the row of the read address matrix, and then rounding the value of the parent matrix to 16 and assigning it to the read address matrix.

[0062] In an exemplary embodiment, a splitting and reorganization matrix is ​​constructed based on service parameters, including: when the type of STM service is different from the type of internal STM service, constructing a column matrix based on the type of STM service, wherein the number of columns of the column matrix is ​​determined based on the type of STM service, and the value of an element of the column matrix is ​​equal to the number of the column in which the element is located; and circularly shifting each row of elements of the column matrix to the left based on the type of internal STM service to obtain a write address matrix.

[0063] In actual implementation, the aforementioned circular left shift scenarios include at least the following: ① In the STM1-to-STM1, STM4-to-STM4, STM16-to-STM16, and STM64-to-STM64 scenarios, no circular left shift is required. ② In the STM16-to-STM1 and STM16-to-STM4 scenarios, rows 0-15 require circular left shifts by the order 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, and 15, respectively. ③ In the STM4-to-STM1 scenario, rows 0-15 require circular left shifts by the order 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, and 3, respectively. That is, in units of N, a cyclic left shift is required for each STM split from a higher-order STM to a lower-order STM. For splitting from STM-N to STM-n, where N and n are both positive integers, the left shift amount starts at 0 and increases by 1 for each row in the STM16-to-STM1 and STM16-to-STM4 scenarios. For the STM4-to-STM1 scenario, the left shift amount increases by 1 for each N / n rows until the left shift amount reaches N-1.

[0064] In an exemplary embodiment, a splitting and reassembling matrix is ​​constructed according to service parameters, including: when the type of the STM service is different from the type of the internal STM service and the type of the STM service is STM64, the STM64 is split into four STM16s, and then a splitting and reassembling matrix is ​​constructed for the STM16; and the four groups of splitting and reassembling matrices obtained are merged respectively to obtain a splitting and reassembling matrix for the STM64.

[0065] Step S604: Split and reassemble the STM service according to the split and reassemble matrix.

[0066] In an exemplary embodiment, splitting and reassembling the STM service according to the splitting and reassembling matrix includes: reading elements from the first RAM according to the read address matrix; performing row transformation on the elements according to the selection matrix; and writing the elements after the row transformation into the second RAM according to the write address matrix.

[0067] Through the above steps, a method for splitting and reorganizing STM services is provided. A splitting and reorganizing matrix is ​​constructed based on the service parameters of the STM services, wherein the splitting and reorganizing matrix includes a read address matrix, a selection matrix, and a write address matrix with the same specifications. The STM services are then split and reorganized according to the splitting and reorganizing matrix. This method solves the problems of wasted storage space and low work efficiency in the related art when splitting and reorganizing STM services, thereby saving storage space and improving work efficiency.

[0068] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0069] This embodiment also provides an STM service splitting and reassembling device for implementing the aforementioned embodiments and preferred implementations. Details already described will not be repeated. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. While the devices described in the following embodiments are preferably implemented using software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0070] Figure 7 is a structural block diagram of an STM service splitting and reorganization device according to an embodiment of the present invention. As shown in Figure 7, the splitting and reorganization device 70 includes: a matrix acquisition module 710, which is configured to construct a splitting and reorganization matrix according to the service parameters of the STM service, wherein the splitting and reorganization matrix includes a read address matrix, a selection matrix, and a write address matrix with the same specifications; a splitting and reorganization module 720, which is configured to split and reorganize the STM service according to the splitting and reorganization matrix.

[0071] In an exemplary embodiment, the splitting and reassembling module 720 may further include: a reading unit, a transformation unit, and a writing unit, wherein the reading unit is configured to read elements from the first RAM according to the read address matrix, the transformation unit is configured to perform row transformation on the elements according to the selection matrix, and the writing unit is configured to write the elements that have completed row transformation into the second RAM according to the write address matrix.

[0072] In an exemplary embodiment, the matrix acquisition module 710 includes a first acquisition unit, wherein the first acquisition unit is configured to construct a read address matrix, a selection matrix, and a write address matrix of the same specifications according to the specifications of the first RAM when the type of the STM service is the same as the type of the internal STM service.

[0073] In an exemplary embodiment, the matrix acquisition module 710 includes a parent matrix acquisition unit, which is configured to construct a row order matrix according to the type of the internal STM service when the type of the STM service is different from the type of the internal STM service, wherein the element value of the row order matrix is ​​an integer multiple of the number of rows where the element is located and the sum of the number of columns where the element is located; and the row order matrix is ​​patched according to the time slot position of the internal STM service to obtain the parent matrix.

[0074] In an exemplary embodiment, the matrix acquisition module 710 includes a read address matrix acquisition unit, which is configured to perform a rounding operation on each element of the parent matrix, and assign the obtained integer value as a new element to the read address matrix, wherein the row value in the read address matrix is ​​the remainder value of the modulo operation on each element of the parent matrix, and the column value is the column value of each element in the parent matrix.

[0075] In an exemplary embodiment, the matrix acquisition module 710 includes a selection matrix acquisition unit configured to perform a modulo operation on each element of the parent matrix, and fill the obtained remainder corresponding to the position of the parent matrix into the corresponding element in the new matrix to obtain the selection matrix.

[0076] In an exemplary embodiment, the matrix acquisition module 710 includes a write address matrix acquisition unit, which is configured to construct a column matrix according to the type of the STM business when the type of the STM business is different from the type of the internal STM business, wherein the number of columns of the column matrix is ​​determined according to the type of the STM business, and the element value of the column matrix is ​​equal to the column number in which the element is located; and each row element of the column matrix is ​​circularly shifted left according to the type of the internal STM business to obtain the write address matrix.

[0077] In the above embodiments, the specific implementation methods and specific processes of the functions in different modules and units can be found in the implementation methods and specific processes in the above method embodiments, which will not be repeated here.

[0078] It should be noted that the above modules can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0079] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above method embodiments when running.

[0080] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0081] An embodiment of the present invention further provides a wavelength division transmission device, comprising a microcontroller unit (MCU) and an optical transport network (OTN) chip. The MCU sends control instructions to the OTN chip, instructing the OTN chip to execute the steps of any of the above-described method embodiments. Figure 8 is a block diagram of a wavelength division transmission device according to an embodiment of the present invention. As shown in Figure 8, the wavelength division transmission device 80 includes a microcontroller unit (MCU) 810 and an OTN chip 820.

[0082] In actual implementation, the OTN chip 820 may execute a computer program to implement the steps of any of the above method embodiments. The computer program may be stored in an MCU or other processing device such as a programmable logic device (FPGA).

[0083] In an exemplary embodiment, the wavelength division transmission device may be an integrated wavelength division transmission device. Alternatively, the STM service splitting and reassembling method may be implemented using an integrated intelligent optical transmission platform or other types of electronic communication devices. For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementations, and this embodiment will not be further elaborated here.

[0084] Obviously, those skilled in the art will appreciate that the various modules or steps of the present invention described above can be implemented using a general-purpose computing device, can be centralized on a single computing device, or can be distributed across a network of multiple computing devices. They can be implemented using program code executable by the computing device, and thus, can be stored in a storage device and executed by the computing device. In some cases, the steps shown or described herein can be performed in a different order than that shown, or can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0085] In order to enable those skilled in the art to better understand the technical solution of the present invention, it is described below in conjunction with specific scenario embodiments.

[0086] Scenario Example 1

[0087] According to the above embodiments, whether the splitting problem is solved using two or three matrices, the existing exhaustive matrix splitting solution consumes a large amount of memory space. Furthermore, the two-matrix solution also reduces the flexibility and efficiency of hardware operations. Furthermore, the software reset process also requires corresponding storage space to store these matrices, increasing product costs. Saving and restoring these matrices also consumes a significant amount of processing time, impacting the performance of the product's soft reset. Therefore, an effective solution is urgently needed to reduce the memory usage of service splitting and reorganization. The novel algorithm proposed in the embodiments of the present invention addresses these shortcomings of existing solutions by regenerating three matrices. These redundant splitting and reorganization matrices are no longer retained, requiring only a small amount of memory space to store a few intermediate matrices (intermediate data generated by the algorithm). The algorithm then regenerates the splitting and reorganization matrices to meet the needs of various service splitting operations. Furthermore, the software reset no longer requires saving and restoring any matrices during the splitting and reorganization process. This significantly reduces memory usage during the splitting and reorganization process, lowering product costs and software reset time, improving the product's soft reset performance and highlighting its competitiveness. At the same time, the three-matrix solution allows the splitting and reorganization process to be completed in batches of N (N = 1, 4, 16, 64) clock beats, greatly enhancing the hardware's operating efficiency and making the product's business processing performance indicators even more outstanding. At the same time, the algorithm is more scalable. After equipment upgrades, the algorithm can still be applied to the splitting and reorganization of STM256 services or larger granularity services. Since reorganization is the reverse process of splitting, we can use splitting as an example to discuss in detail the technical solution implementation of the scenario embodiment of the present invention.

[0088] Fig. 9 is a schematic diagram of the principle of splitting STM16 into STM1 according to an embodiment of the present invention scenario. As shown in Figure 9, the RAM before and after the split is regarded as 2 matrices, then the splitting and reorganization can be simply understood as the transformation relationship between the two matrices. Since the RAM on both sides of the read and write are evenly distributed on 16 RAMs in the same clock cycle, the present invention uses three same-specification matrices (read address matrix, write address matrix, selection matrix). To complete this corresponding relationship, the number of columns of these three matrices represents the action that needs to be completed in which clock beat. The dark grid data in the left RAM is read and written to the dark grid of the right RAM. The read address matrix is ​​used to provide the number of columns of the left matrix where the read element is located. After the selection matrix performs row conversion, the number of columns of the right matrix provided by the write address matrix is ​​used to write the read element to the right matrix. The whole read and write process is strictly written from top to bottom in accordance with the number of rows of the left and right matrices.

[0089] FIG10 is a schematic diagram of the principle of splitting STM16 into STM1 according to an embodiment of the present invention. As shown in FIG10 , the hardware reads the element [1 15 , 2 16 , 31, 42, 53, 64, 75, 86, 97, 108, 119, 12 10 , 13 11 , 14 12 , 15 13 , 16 14 ], after selecting the transformation rule provided by the third column of the matrix [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1], the read elements are transformed into [31, 42, 53, 64, 75, 86, 97, 108, 119, 12 10 , 13 11 , 14 12 , 15 13 , 16 14 , 1 15 , 2 16 Then, according to the third column of the write address matrix, the elements [31, 42, 53, 64, 75, 86, 97, 108, 119, 12 10 , 13 11 , 14 12 , 15 13 , 16 14 , 1 15 , 2 16 ] is written to the matrix (RAM) on the right. Splitting an STM16 into an STM1 requires 16 clock cycles, which requires exactly 16 1*16 matrices to support the split. That is, the read address matrix, write address matrix, and select matrix are all 16*16 in size.

[0090] In the actual implementation process, there is only one case of splitting STM1 into STM1, and three split matrices can be directly generated.

[0091] Figure 11 is a schematic diagram of the principle of splitting STM4 into STM1 according to an embodiment of the scenario of the present invention. As shown in Figure 11, after the split RAM is cyclically shifted left by the number of rows / 4 units every four rows, the value of each column element is consistent. Therefore, after establishing a row sequence matrix, a parent matrix can be obtained by cyclically shifting left by the number of rows / 4 units every four rows, and then the selection matrix and the read address matrix can be obtained; as for the write address matrix, a column matrix is ​​first created, and then the write address matrix in this scenario can be obtained by cyclically shifting left by the number of rows / 4 units every four rows.

[0092] For STM4 splitting into STM4, it is obvious that each row of the read address matrix and the write address matrix starts at 0 and increases by 1, while the selection matrix is ​​a matrix with columns from 0 to 15. Based on this, it is easy to generate split matrices for these two splitting scenarios. The same is true for STM16 splitting into STM16.

[0093] In particular, when the STM16 is split into STM1 or STM4, it can be clearly observed that the split RAM shifts one element to the left in each row, which just moves the elements of the same depth color to one column. It can be confirmed that the first row of the write address matrix during splitting in this scenario is 0 to 15, and each of the remaining rows is arranged according to the rule of shifting the elements to the left in increments of one unit. This also easily solves the problem of generating the write address matrix in this scenario.

[0094] For the STM16-to-STM1 split scenario, the selection matrix and read address matrix are obtained from a parent matrix. When the STM16 is split into STM1s, the parent matrix is ​​initially a row-ordered matrix (a Z-shaped, ascending matrix). Each row of the row-ordered matrix is ​​cyclically left-shifted by a certain number of elements to create a parent matrix. If the subscripts of the element values ​​in the split RAM are considered rows, the values ​​of this matrix are consistent with those of the transformed parent matrix. Taking the modulo 16 modulo 16 modulo 16 modulo 16 modulo 16 modulo 16 modulo 16, the resulting values ​​are used as rows of the read address matrix. The parent matrix values ​​are then assigned to the read address matrix after 16-based integers. This operation ensures that the column coordinates of the two matrices are consistent, but involves a row coordinate transformation, which is the inverse of the row swapping process for the selection matrix. This process of generating the selection matrix and read address matrix from the parent matrix applies to any STM splitting service. Therefore, another core aspect of the algorithm is how to generate the parent matrix.

[0095] As described above, the parent matrix is ​​generated when an STM16 is split into STM4s. After the split, the RAM is circularly shifted one element at a time, moving elements of the same depth color to the same column. The matrix before the circular left shift has a strong correspondence with the STM4's time slot position in the STM1. If the STM4 is in time slot #1 of the STM16 (the first four rows), the parent matrix corresponding to columns 1 to 4 will be inconsistent with the parent matrix when the STM16 is split into STM1s. If the STM4 is in time slot #2 of the STM16, the parent matrix corresponding to columns 5 to 8 will be inconsistent with the parent matrix when the STM16 is split into STM1s. The next two STM4 time slots have four inconsistent columns. Based on this pattern, the 15 possible combinations of STM16 splits into STM4s can be easily resolved using patch overlays.

[0096] The parent matrix when STM16 is split into STM16 is simpler, because the color depth of each column of the RAM on the right is the same, so there is no need to perform a circular left shift transformation, and a column order matrix (an increasing order matrix arranged in an N-shaped pattern) can be directly generated.

[0097] The reorganization process is the inverse process of the entire splitting algorithm. The split write address matrix is ​​the reorganized read address matrix, and the split read address matrix is ​​the reorganized write address matrix. Conversely, the reorganized selection matrix also comes from a parent matrix. The reorganized parent matrix is ​​used to generate the reorganized selection matrix and the write address matrix. There is a slight difference between the generation of the reorganization selection matrix by the parent matrix and the generation of the split selection matrix by the split parent matrix, which is specifically described in the scenario embodiment 2.

[0098] Scenario Example 2

[0099] The application scenarios of the scenario embodiments of the present invention can meet the scenarios of STM1 being split into STM1, STM4 being split into STM1, STM4 being split into STM4, STM16 being split into STM1, STM16 being split into STM4, STM16 being split into STM16, STM64 being split into STM1, STM64 being split into STM4, STM64 being split into STM16, and STM64 being split into STM64.

[0100] Figure 12 is a schematic diagram of the STM service splitting structure of the scenario embodiment of the present invention. As shown in Figure 12, stm_type refers to the service type before splitting (STM-N, N = 1, 4, 16, 64), vc_type refers to the STM type mapped multiplexed in the STM before splitting, that is, the service type STM after splitting, and vc4_4c_ts_mask is the time slot position mark of STM4 in the STM16 service.

[0101] Figure 13 is a schematic diagram of the STM business splitting software architecture of a scenario embodiment of the present invention. As shown in Figure 13, the present invention adopts a divide-and-conquer approach to the different scenarios for various businesses, and performs classification processing according to the business type STM, wherein the splitting matrix of the STM64 business is decomposed into 4 STM16 businesses. After the splitting matrix is ​​acquired, it is interleaved into a 16*64 splitting matrix; the generator of the different selection read address matrices and selection matrix of the vc business type multiplexed internally for the STM4 business evidence: when the STM16 business is split, if the internally multiplexed business type is not STM16 and vc4_4c_ts_mask is not equal to 0, it represents that the internally multiplexed business type is STM4, or a mixture of STM4 and STM1, and each bit of vc4_4c_ts_mask represents a time slot number of STM4, a total of 4 bits representing 4 time slot numbers, and the 4 time slot positions of the parent matrix are patched according to the valid state of the 4 bits (a bit value of 1 represents valid).

[0102] Figure 14 is a schematic diagram of the write address matrix creation process of an embodiment of the scenario of the present invention. As shown in Figure 14, the generation of the split write address matrix is ​​also divided and conquered according to the business type. The first step is to create a column matrix. The difference is that the number of matrix columns created when the business type is different is inconsistent; among them, the STM4 business and the STM16 business will choose whether to perform a certain regular circular left shift on the initial matrix according to the internal multiplexing business type; similarly, the split write address matrix generation of the STM64 business is also split into 4 STM16s for processing and then restored in an interleaved manner.

[0103] FIG15 is a schematic diagram of the selection matrix and read address matrix creation process in an embodiment of a scenario of the present invention. As shown in FIG15 , except for the direct generation of the selection matrix and read address matrix when the STM1 service is split, the two matrices for the other service splits are generated by a parent matrix, and then the selection matrix and read address matrix are obtained by a unified algorithm processing of the parent matrix:

[0104] Split selection matrix:

[0105] Take the modulo 16 value of each element of the parent matrix;

[0106] sel_mtrx[row][col]=parent_mtrx[row][col]%16.

[0107] Split read address matrix:

[0108] Take the modulo 16 value of each element of the parent matrix and use the value as the row of the read address matrix. Then, round the value of the parent matrix to 16 and assign it to the read address matrix.

[0109] row_temp=parent_mtrx[row][col]%16,

[0110] rd-addr_mtrx[row_temp][col]=p_parent_mtrx[row][col] / 16.

[0111] Where row represents the row of the matrix, col represents the column of the matrix, sel_mtrx represents the selection matrix, parent_mtrx represents the parent matrix, and row_temp is a temporary variable.

[0112] As shown in Figure 15, the generation rules for parent matrices vary. In particular, the generation of the STM16 parent matrix differs from that of other services. When the internal multiplexing service is not an STM16, the parent matrix generation selects the row sequence matrix for patching based on the timeslot number flag set in vc4_4c_ts_mask. Similarly, the generation of the selection matrix and read address matrix for the STM64 service still relies on the STM16 service, decomposing it into four STM16s before interleaving it back.

[0113] FIG16 is a schematic diagram of a process flow of generating an STM16 split parent matrix using a patch overlay method according to an embodiment of a scenario of the present invention. As shown in FIG16 , when STM16 is split into STM1, the parent matrix is ​​a row-sequential matrix. When vc4_4c_ts_mask is not equal to 0, it indicates that the service after the STM16 split is STM4. The four columns of the row-sequential matrix are overlaid according to the time slot number position indicated by vc4_4c_ts_mask. The specific overlay method is parent matrix [row][col+i*4]=col*64+((row / 4)*16)+(row%4)+i*4. Wherein row represents row and col represents column.

[0114] FIG17 is a schematic diagram of the creation process of the selection matrix and the write address matrix for STM service reorganization in a scenario embodiment of the present invention. As shown in FIG17 , the acquisition of the reorganized write address matrix is ​​the same as the split read address matrix shown in FIG15 . The acquisition process of the selection matrix is ​​also the same as the acquisition process of the split selection matrix. The only difference is that the assignment of values ​​to the reorganized selection matrix is ​​different from that to the split selection matrix:

[0115] Recombinant selection matrix:

[0116] row_temp=parent_mtrx[row][col]%16,

[0117] sel_mtrx[row_temp][col]=row.

[0118] Where row represents the row of the matrix, clo represents the column of the matrix, sel_mtrx represents the selection matrix, parent_mtrx represents the parent matrix, and row_temp is a temporary variable.

[0119] The value assigned is the row number of the element in the original parent matrix.

[0120] In summary, the STM service splitting and reorganization method provided by the embodiments of the present invention can improve hardware operating efficiency: it supports three matrix splitting schemes, enabling hardware to operate with higher efficiency, accelerating the speed of service splitting and reorganization, and achieving better performance indicators for the product. It can also solve the problem of large memory usage: a new splitting and reorganization method through matrix regeneration is proposed to address the large memory usage defect of existing solutions. Only a small amount of memory space is required to store a small number of intermediate matrices (intermediate data generated by the algorithm process), and redundant split matrices are no longer stored. It can also improve software reset performance indicators: by regenerating the split matrix through the algorithm, various service splitting requirements are met, and the save and restore time performance of the software reset is also significantly improved. The software reset no longer needs to save and restore any matrices in this process. It has certain universal scalability: the algorithm scheme of the present invention is also applicable to higher-order matrix splitting and reorganization, such as the upgraded STM256 service. The algorithm is expanded to generate three 16*256 split matrices to deal with the splitting of STM256 services, while meeting various splitting scenarios and saving more memory consumption.

[0121] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A synchronous transmission module (STM) service splitting and reorganization method, comprising: Constructing a splitting and reorganizing matrix according to the service parameters of the STM service, wherein the splitting and reorganizing matrix includes a read address matrix, a selection matrix, and a write address matrix having the same specifications; The STM service is split and reorganized according to the split and reorganization matrix.

2. The method according to claim 1, wherein: The service parameters include: The type of STM service, the type of internal STM service, and the time slot position of the internal STM service, wherein the internal STM service is obtained by splitting the STM service.

3. The method according to claim 1, wherein: Splitting and reorganizing the STM service according to the splitting and reorganizing matrix includes: Reading elements from a first random access memory RAM according to the read address matrix; Performing row transformation on the elements according to the selection matrix; The elements for which the row transformation is completed are written into the second RAM according to the write address matrix.

4. The method according to claim 2, wherein: Constructing the splitting and reorganizing matrix according to the service parameters includes: In the case that the type of the STM service is the same as the type of the internal STM service, the read address matrix, the selection matrix, and the write address matrix of the same specifications are constructed according to the specifications of the first RAM.

5. The method according to claim 2, wherein: Constructing the splitting and reorganizing matrix according to the service parameters includes: In the case where the type of the STM service is different from the type of the internal STM service, constructing a row order matrix according to the type of the internal STM service, wherein an element value of the row order matrix is ​​a sum of an integer multiple of the number of rows where the element is located and the number of columns where the element is located; Performing patch coverage on the row order matrix according to the time slot position of the internal STM service to obtain a parent matrix; The read address matrix and the selection matrix are obtained according to the parent matrix.

6. The method according to claim 5, wherein: Obtaining the read address matrix and the selection matrix according to the parent matrix includes: Performing a rounding operation on each element of the parent matrix, and assigning the obtained integer value as a new element to the read address matrix, wherein the row value in the read address matrix is ​​the remainder value of the modulo operation on each element of the parent matrix, and the column value is the column value of each element in the parent matrix; A modulo operation is performed on each element of the parent matrix, and the obtained remainders are filled into corresponding elements in the new matrix at positions corresponding to the parent matrix, so as to obtain the selection matrix.

7. The method according to claim 2, wherein: Constructing the splitting and reorganizing matrix according to the service parameters includes: In the case where the type of the STM service is different from the type of the internal STM service, constructing a column matrix according to the type of the STM service, wherein the number of columns of the column matrix is ​​determined according to the type of the STM service, and the value of an element of the column matrix is ​​equal to the number of the column where the element is located; The write address matrix is ​​obtained by circularly shifting the elements of each row of the column matrix to the left according to the type of the internal STM service.

8. The method according to claim 2, wherein: Constructing the splitting and reorganizing matrix according to the service parameters includes: When the type of the STM service is different from the type of the internal STM service and the type of the STM service is STM64, the STM64 is split into four STM16s, and then the splitting and reorganization matrix is ​​constructed for the STM16; The obtained 4 groups of splitting and recombination matrices are merged respectively to obtain the splitting and recombination matrix of the STM64.

9. A synchronous transmission module (STM) service splitting and reorganization device, comprising: A matrix acquisition module, configured to construct a splitting and reorganizing matrix according to the service parameters of the STM service, wherein the splitting and reorganizing matrix includes a read address matrix, a selection matrix, and a write address matrix having the same specifications; The splitting and reorganization module is configured to split and reorganize the STM service according to the splitting and reorganization matrix.

10. A computer-readable storage medium having a computer program stored therein, wherein: When the computer program is executed by a processor, the method described in any one of claims 1 to 8 is implemented.

11. A wavelength division transmission device, comprising a micro control unit MCU and an optical transmission network OTN chip, wherein the MCU sends a control instruction to the OTN chip to instruct the OTN chip to execute the method described in any one of claims 1 to 8.

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