Trench capacitor and manufacturing method therefor

Abstract

A trench capacitor and a manufacturing method therefor. The manufacturing method comprises: providing a substrate; forming a first trench in an insulating layer on a first metal wire, so as to expose the first metal wire; forming a double-layer capacitor on the insulating layer on the periphery of the first trench and in the first trench, and a first electrode being electrically connected to the first metal wire; and forming a fourth metal wire to connect a second metal wire to a second electrode and forming a fifth metal wire to connect a third metal wire to a third electrode. Three electrodes of the double-layer capacitor are led out downwards by using the first to third metal wires in the substrate, which reduces the difficulty of process integration and is conducive to improving the capacitance density and design freedom of the double-layer capacitor.

Description

Trench capacitor and method of manufacturing the same

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on July 31, 2023, with application number 202310948101.0 and invention name “Double-layer capacitor and its manufacturing method”, the entire contents of which are incorporated by reference into this application.

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on July 31, 2023, with application number 202310948097.8 and invention name “Trench Capacitor and Its Manufacturing Method”, the entire contents of which are incorporated by reference into this application.

[0003] This application claims priority to the Chinese patent application filed with the China Patent Office on July 31, 2023, with application number 202310948142.X and invention name “Trench Capacitor and Its Manufacturing Method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0004] The present application relates to the technical field of integrated circuit manufacturing, and in particular to a trench capacitor and a manufacturing method thereof. Background Art

[0005] Capacitors are common passive components widely used in integrated circuits. In some specialized applications, high-capacitance capacitors are required to improve product performance, such as signal storage, noise reduction, and coupling reduction. Planar capacitors require a large area to achieve high capacitance, sacrificing design space. Therefore, trench capacitors are the optimal choice for high capacitance.

[0006] The existing trench capacitors can not only have their capacitance density further improved, but also their manufacturing process can be further optimized.

[0007] Summary of the Invention

[0008] The purpose of this application is to provide a trench capacitor and a manufacturing method thereof, so as to improve its capacitance density and optimize its manufacturing process.

[0009] To solve the above technical problems, the present application provides a method for manufacturing a trench capacitor, comprising:

[0010] Providing a substrate, wherein first to third metal lines arranged in the same layer and an insulating layer covering the first to third metal lines are formed on the substrate;

[0011] forming a first trench in the insulating layer on the first metal line to expose the first metal line;

[0012] Conformally forming a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode on the insulating layer around the first trench and in the first trench to form a double-layer capacitor, wherein the first electrode is electrically connected to the first metal line;

[0013] A fourth metal line is formed to connect the second metal line and the second electrode, and a fifth metal line is formed to connect the third metal line and the third electrode.

[0014] According to another aspect of the present application, the present application further provides a trench capacitor, comprising:

[0015] substrate;

[0016] First to third metal wires are arranged in the same layer in the substrate;

[0017] an insulating layer covering the first to third metal wires and having a first trench formed in the insulating layer exposing the first metal wire;

[0018] a double-layer capacitor formed in the first trench and on the insulating layer around it, comprising a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode formed conformally in sequence, wherein the first electrode is electrically connected to the first metal line;

[0019] A fourth metal line and a fifth metal line, wherein the fourth metal line electrically connects the second metal line and the second electrode, and the fifth metal line electrically connects the third metal line and the third electrode.

[0020] In summary, the present application forms a first trench exposing the first metal wire in the insulating layer on the first metal wire, and forms a double-layer capacitor in the first trench and on the insulating layer around the first trench. The first electrode of the double-layer capacitor is connected to the first metal wire at the bottom of the first trench, forming a fourth metal wire electrically connecting the second electrode and the second metal wire and a fifth metal wire electrically connecting the third electrode and the third metal wire. As a result, the three electrodes of the double-layer capacitor are led downward using the first to third metal wires in the substrate, and the lead-out of the double-layer trench capacitor and the wiring of the metal wires on the insulating layer are completed without adding additional process steps, which reduces the difficulty of process integration and is conducive to improving the capacitance density and design freedom of the double-layer capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Those skilled in the art should understand that the drawings are provided for a better understanding of the present application and do not constitute any limitation on the scope of the present application.

[0022] FIG1 is a flow chart of a method for manufacturing a trench capacitor provided in Example 1 of the present application;

[0023] 2a to 2g and 3a to 3e are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing a trench capacitor provided in Example 1 of the present application;

[0024] FIG4 is a schematic diagram of a first through hole provided in Example 2 of the present application;

[0025] FIG5 is a flow chart of a method for manufacturing a trench capacitor provided in Example 3 of the present application;

[0026] 6a to 6j and 7a to 7c are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing a trench capacitor provided in Example 3 of the present application;

[0027] 8a to 8h are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing a trench capacitor provided in the fourth embodiment of the present application;

[0028] FIG9 is a flow chart of a method for manufacturing a trench capacitor according to a fifth embodiment of the present application;

[0029] 10a to 10m are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing a trench capacitor provided in Example 5 of the present application;

[0030] 11a to 11k are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing a trench capacitor provided in Example 6 of the present application.

[0031] In the figure: 10-substrate; 11-second metal line; 12-first metal line; 13-third metal line; 21-dielectric barrier layer; 22-insulating layer; 23-second trench; 24-first trench; 25-third trench; AA-second region; BB-first region; CC-third region; 26-first electrode material layer; 26a-first electrode; 27-first dielectric material layer; 27a-first dielectric layer; 28-first mask; 29-second electrode material layer; 29a-third Second electrode; 30-second mask; 31-second dielectric material layer; 31a-second dielectric layer; 32, 32a-third mask; 33-third electrode material layer; 33a-third electrode; 34-fourth mask; 35-third dielectric material layer; 35a-side wall; 36-third dielectric layer; 37-first through hole; 38-second through hole; 39-metal material layer; 40-fourth metal wire; 41-fifth metal wire; 42: third through hole; 43: second metal material layer. DETAILED DESCRIPTION

[0032] To make the purposes, advantages, and features of this application more clear, the present application is further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of this application. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to be presented with different emphases and may sometimes use different scales.

[0033] As used in this application, the singular forms "a", "an", and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features specified as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0034] Example 1

[0035] FIG1 is a flow chart of a method for manufacturing a trench capacitor provided in a first embodiment of the present application.

[0036] As shown in FIG1 , the method for manufacturing a trench capacitor provided in an embodiment of the present application includes:

[0037] S110: Providing a substrate, wherein first to third metal wires arranged in the same layer and an insulating layer covering the first to third metal wires are formed on the substrate;

[0038] S120: forming a first trench in the insulating layer on the first metal line to expose the first metal line;

[0039] S130: Conformally forming a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode in sequence on the insulating layer around the first trench and in the first trench to form a double-layer capacitor, wherein the first electrode is electrically connected to the first metal line;

[0040] S140 : forming a fourth metal line electrically connecting the second metal line and the second electrode, and forming a fifth metal line electrically connecting the third metal line and the third electrode.

[0041] Figures 2a to 2g and Figures 3a to 3e are structural schematic diagrams corresponding to corresponding steps of the manufacturing method of the trench capacitor provided by the implementation of this application. Next, the manufacturing method of the trench capacitor will be described in detail in combination with Figures 2a to 2g and Figures 3a to 3e.

[0042] First, referring to FIG. 2 a , step S110 is performed to provide a substrate 10 , in which a first metal line 12 , a second metal line 11 , and a third metal line 13 arranged in the same layer and an insulating layer 22 covering the first metal line 12 , the second metal line 11 , and the third metal line 13 are formed.

[0043] The substrate 10 may be any suitable base material known to those skilled in the art, for example, at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SiOI), silicon-germanium-on-insulator (SiGeOI), silicon-germanium-on-insulator (SiGeO), and germanium-on-insulator (GeOI). In this embodiment, the material of the substrate 10 is described using silicon (silicon substrate) as an example.

[0044] A device layer and an interconnect layer electrically connected to the device layer are formed in the substrate 10. The interconnect layer is located above the device layer and can be formed using a damascene process. The first metal line 12, the second metal line 11, and the third metal line 13 can be three metal wirings arranged at intervals in the Nth layer (N is greater than or equal to 1) of the interconnect layer. The first metal line 12 is located between the second metal line 11 and the third metal line 13. The material of the three metal wirings can include, for example, copper. In this embodiment, the first metal line 12, the second metal line 11, and the third metal line 13 can be three top-layer metal wirings arranged at intervals. A dielectric barrier layer 21 and an insulating layer 22 are sequentially formed on the first metal line 12, the second metal line 11, and the third metal line 13. The material of the dielectric barrier layer 21 is used to block the escape of metal ions and serve as an etch stop layer during etching. The material of the dielectric barrier layer 21 can include, for example, silicon nitride or silicon carbonitride. The material of the insulating layer 22 is different from that of the dielectric barrier layer 21 and can include, for example, silicon oxide or silicon oxynitride.

[0045] In addition, in other examples of this embodiment, multiple (at least two) second metal wires 11, multiple first metal wires 12 and multiple third metal wires 13 may be provided as needed, and multiple identical metal wires are connected in parallel.

[0046] Next, referring to FIG. 2 b , step S120 is performed to form a plurality of first trenches 24 in the insulating layer 22 on the first metal lines 12 to expose the first metal lines 12 .

[0047] Specifically, a photolithography process can be used to define a first groove area (not shown) on the insulating layer 22 on the first metal line 12, that is, the area where the subsequent double-layer capacitor is located, and then a dry etching process is used to sequentially etch the insulating layer 22 and the dielectric barrier layer 21 to form a plurality of spaced first grooves 24 and expose the first metal line 12.

[0048] In practice, the lateral width of the first trench region may be greater than the lateral width of some first metal lines 12 , ie, part of the first trench 24 is located above the insulating layer 22 around the first metal line 12 (not directly above it).

[0049] Next, step S130 is performed to conformally form a first electrode 26 a, a first dielectric layer 27 a, a second electrode 29 a, a second dielectric layer 31 a, and a third electrode 33 a on the insulating layer 22 around the first trench 24 and in the first trench 24 to form a double-layer capacitor. The first electrode 26 a is electrically connected to the first metal line 12.

[0050] Specifically, referring to FIG. 2 c , a first electrode material layer 26 is formed to conformally cover the surface of the insulating layer 22 and the inner wall of the first trench 24 . Any suitable process can be used to form a thin film conductive layer serving as the first electrode material layer 26 . The first electrode material layer 26 may include one or more thin film conductive layers, and the material may be, for example, one or more of titanium, titanium nitride, tantalum, or tantalum nitride. The formation process may include physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The first electrode material layer 26 may be relatively thin to form a double-layer trench capacitor, and the thickness may be, for example, 100 to 400 angstroms.

[0051] Referring to Figure 2d, a patterning process is performed on the first electrode material layer 26 to form first electrodes 26a covering the inner walls of the first trenches 24 and the insulating layer 22 around the first trenches 24. A mask can be formed to cover a number of the first trenches 24 and the first electrode material layer 26 on the insulating layer 22 between the first trenches 24. The remaining first electrode material layer 26 on the insulating layer 22 not covered by the mask is then removed. The mask is then removed, and the first electrode material layer 26 covering the inner walls of the first trenches 24 and the insulating layer 22 between the first trenches 24 serves as the first electrode 26a. The first electrode 26a is electrically connected to the first metal line 12 at the bottom of the first trench 24, so that the first electrode 26a is led out via the first metal line 12. In addition, the first electrode 26a can also extend to cover the insulating layer 22 around the outermost first trenches 24 to facilitate positioning of the mask boundary and facilitate the patterning process.

[0052] Referring to Figure 2e, a first dielectric material layer 27, a second electrode material layer 29, a second dielectric material layer 31, and a third electrode material layer 33 are sequentially conformally formed to cover the surfaces of the insulating layer 22 and the first electrode 26a. The third electrode material layer 33 completely fills the first trench 24 to form a substantially planar top. The first dielectric material layer 27 and / or the second dielectric material layer 31 can be made of a dielectric material with a relatively high dielectric constant, such as greater than or equal to 3.9, such as silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or rhodium oxide. The second electrode material layer 29 and the third electrode material layer 33 can be made of a material similar to that of the first electrode material layer 26.

[0053] Referring to Figure 2f, a patterning process is performed on the third electrode material layer 33 and the second dielectric material layer 31 to form a third electrode 33a and a second dielectric layer 31a, while exposing the second electrode material layer 29. A mask can be formed to cover the area corresponding to the first electrode 26a, namely, the first trench 24 and the area corresponding to the periphery of the first trench 24. The exposed third electrode material layer 33 and second dielectric material layer 31 are then removed. The mask is then removed, and the remaining third electrode material layer 33 serves as the third electrode 33a, while the remaining second dielectric material layer 31 serves as the second dielectric layer 31a. The third electrode 33a and the second dielectric layer 31a have similar areas and are larger than the first electrode 26a, providing sufficient facing area between the electrodes, thereby increasing the capacitance.

[0054] Referring to Figure 2g, a patterning process is performed on the second electrode material layer 29 and the first dielectric material layer 27 to form a second electrode 29a and a first dielectric layer 27a. A mask can be formed to cover the third electrode 33a and a portion of the second electrode material layer 29, i.e., the area covered by the mask is slightly larger than the corresponding area of ​​the third electrode 33a. The exposed second electrode material layer 29 and first dielectric material layer 27 are removed, and the mask is then removed. The remaining second electrode material layer 29 serves as the second electrode 29a, and the remaining first dielectric material layer 27 serves as the first dielectric layer 27a. The area of ​​the second electrode 29a is larger than the area of ​​the third electrode 33a. In other words, the edges of the second electrode 29a and the third electrode 33a form a stepped shape, including a lower stepped surface and an upper stepped surface (two steps). The edge of the second electrode 29a is located on the lower stepped surface, and the edge of the third electrode 33a is located on the upper stepped surface.

[0055] Thus, a double-layer trench capacitor consisting of a first electrode 26a, a first dielectric layer 27a, a second electrode 29a, a second dielectric layer 31a and a third electrode 33a is formed in the first trench 24 and on the insulating layer 22 around the first trench 24, so as to increase the capacitance value (capacitance density) on the same substrate 10 area.

[0056] Next, step S140 is performed to form a fourth metal wire 40 connecting the second metal wire 11 and the second electrode 29a, and to form a fifth metal wire 41 connecting the third metal wire 13 and the third electrode 33a. The specific steps include:

[0057] Step 1: When forming a double-layer capacitor, the surfaces of the third electrode 33a and a portion of the second electrode 29a are exposed. In FIG2f , when the third electrode material layer 33 and the second dielectric material layer 31 are patterned, the third electrode 33a is exposed. In FIG2g , when the second electrode material layer 29 and the first dielectric material layer 27 are patterned, a portion of the second electrode 29a is exposed.

[0058] Step 2: Form a third dielectric layer 36 to cover the surface of the double-layer capacitor, and form a plurality of first through holes 37 in the third dielectric layer 36 on both sides of the first metal line 12 to expose the second electrode 29a and the third electrode 33a respectively.

[0059] Specifically, referring to Figure 3a, a third dielectric layer 36 is formed to cover the surface of the double-layer capacitor, including the third electrode 33a and the exposed second electrode 29a. The third dielectric layer 36 may also extend to cover the insulating layer 22 outside the double-layer capacitor. As the cover layer of the double-layer capacitor, the third dielectric layer 36 is used to electrically isolate the second electrode 29a from the third electrode 33a and to form contact holes for connecting the second electrode 29a to the third electrode 33a. The third dielectric layer 36 may be a single-layer dielectric or a multi-layer dielectric. Its material may include one or more of silicon oxide, silicon nitride, silicon carbonitride, or silicon oxynitride. It may be formed using a suitable process, such as chemical vapor deposition or atomic layer deposition.

[0060] Referring to Figure 3b, a plurality of first through-holes 37 are formed in the third dielectric layer 36 on both sides of the first metal line 12, respectively exposing the second electrode 29a and the third electrode 33a. A mask can be formed to cover the surface of the third dielectric layer 36. The mask has a plurality of openings on the side near the second metal line 11 to expose the third dielectric layer 36 on the lower step surface, and a plurality of openings on the side near the third metal line 13 to expose the third dielectric layer 36 on the upper step surface. A dry etching process is then performed using the mask to remove the exposed third dielectric layer 36, thereby forming a plurality of first through-holes 37, respectively exposing the third electrode 33a and the second electrode 29a. Specifically, the first through-holes 37 on one side of the first metal line 12 and near the second metal line 11 expose the second electrode 29a (lower step surface), while the first through-holes 37 on the other side of the first metal line 12 and near the third metal line 13 expose the third electrode 33a (upper step surface). Furthermore, the number of first through-holes 37 exposing the corresponding electrodes can be greater than or equal to two rows.

[0061] Step 3: Form a plurality of second through holes 38 in the insulating layer 22 to expose the second metal wires 11 and the third metal wires 13 respectively.

[0062] Referring to FIG. 3 c , a patterning process may be performed to form a plurality of second through-holes 38 in the dielectric barrier layer 21, the insulating layer 22, and the third dielectric layer 36 on the second metal line 11 to expose the second metal line 11. A plurality of second through-holes 38 may be formed in the dielectric barrier layer 21, the insulating layer 22, and the third dielectric layer 36 on the third metal line 13 to expose the third metal line 13. Due to the greater depth of the second through-holes 38, the opening size of the second through-holes 38 may be larger than the opening size of the first through-holes 37 to facilitate subsequent filling of the second through-holes 38 with metal.

[0063] Step 4: Using the first through-hole 37 and the second through-hole 38 , form a fourth metal wire 40 to electrically connect the second metal wire 11 and the second electrode 29 a , and form a fifth metal wire 41 to electrically connect the third metal wire 13 and the third electrode 33 a .

[0064] Specifically, referring to Figure 3d, a first metal material layer 39 is formed to cover the surface of the third dielectric layer 36, the inner walls of the first through-hole 37, and the second through-hole 38, thereby connecting the second metal wire 11, the third metal wire 13, the second electrode 29a, and the third electrode 33a. If portions of the insulating layer 22 are not covered by the third dielectric layer 36, the first metal material layer 39 may also cover the exposed insulating layer 22. The first metal material layer 39 may be made of a metal suitable for connection to an external circuit, such as aluminum or an aluminum alloy. In this embodiment, the first metal wire 12, the second metal wire 11, and the third metal wire 13 are made of copper, and the first metal material layer 39 includes a tantalum nitride layer, a tantalum layer, an aluminum layer, a titanium layer, and a titanium nitride layer, which are sequentially conformally formed. In practice, because the dimensions (depth and opening width) of the first through-hole 37 are smaller and the dimensions of the second through-hole 38 are larger, the first metal material layer 39 may completely fill the first through-hole 37 or may only cover the inner walls of the second through-hole 38 without completely filling the second through-hole 38.

[0065] Referring to Figure 3e, a patterning process is performed on the first metal material layer 39 to form a fourth metal line 40 connecting the second metal line 11 and the second electrode 29a, and a fifth metal line 41 connecting the third metal line 13 and the third electrode 33a. Specifically, the patterning process of the first metal material layer 39 includes disconnecting the first metal material layer 39 connecting the two first vias 37, and using the first metal material layer 39 adjacent to the second metal line 11 and connecting the second metal line 11 and the second electrode 29a as the fourth metal line 40. The first metal material layer 39 adjacent to the third metal line 13 and connecting the third metal line 13 and the third electrode 33a is used as the fifth metal line 41.

[0066] In addition, during the patterning process of the first metal material layer 39, the first metal material layer 39 can also be used to simultaneously form a metal pad on the insulating layer 22 (or the third dielectric layer 36), and other top-layer metal lines are electrically led out to the metal pad for connection to an external circuit.

[0067] In the first embodiment of the present application, a first trench 24 is formed in the insulating layer 22 on the first metal line 12 to expose the first metal line 12, and a double-layer capacitor is formed in the first trench 24 and on the insulating layer 22 around the first trench 24. The first electrode 26a of the double-layer capacitor is connected to the first metal line 12 at the bottom of the first trench 24, and the second electrode 29a and the third electrode 33a of the double-layer capacitor are both exposed upward. Then, a third dielectric layer 36 is formed to cover the double-layer capacitor, and first through holes 37 are formed in the third dielectric layer 36 to expose the second electrode 29a and the third electrode 33a, respectively. Then, the first through holes 37 are formed in the second dielectric layer 36 to expose the second electrode 29a and the third electrode 33a, respectively. The second through hole 38 in the insulating layer 22 on the metal wire 11 and the first metal wire 12 forms a fourth metal wire 40 connecting the second electrode 29a and the second metal wire 11, and a fifth metal wire 41 connecting the third electrode 33a and the third metal wire 13. As a result, the three electrodes of the double-layer capacitor are led downward using the first metal wire 12, the second metal wire 11 and the third metal wire 13 in the substrate. The lead-out of the double-layer trench capacitor and the wiring of the metal wires on the insulating layer 22 are completed without adding additional process steps, which reduces the difficulty of process integration and is conducive to improving the capacitance density and design freedom of the double-layer capacitor.

[0068] Example 2

[0069] Embodiment 2 provides a method for manufacturing a trench capacitor.

[0070] The manufacturing method of the double-layer capacitor provided in this embodiment is similar to the method provided in the first embodiment, and the main difference is that in the second embodiment, the fourth metal wire 40 is electrically connected to the second metal wire 11 and the third electrode 33a, and the fifth metal wire 41 is electrically connected to the third metal wire 13 and the second electrode 29a (i.e., a structure similar to the left-right symmetry of the capacitor in the first embodiment is formed).

[0071] The steps in the second embodiment that are different from those in the first embodiment specifically include: in step 2, as shown in FIG4 , a plurality of first through holes 37 are formed in the third dielectric layer 36 on both sides of the first metal line 12 to expose the second electrode 29 a and the third electrode 33 a respectively, and the plurality of first through holes 37 close to the second metal line 11 expose the third electrode 33 a (upper step surface), while the plurality of first through holes 37 close to the third metal line 13 expose the second electrode 29 a (lower step surface); thus, in step 4, when the first metal material layer 39 is patterned to form the fourth metal line 40 and the fifth metal line 41, the fourth metal line 40 can be formed to electrically connect the second metal line 11 and the third electrode 33 a, and the fifth metal line 41 can be formed to electrically connect the third metal line 13 and the second electrode 29 a.

[0072] Example 3

[0073] FIG5 is a flow chart of a method for manufacturing a trench capacitor provided in the third embodiment of the present application.

[0074] As shown in FIG5 , the method for manufacturing a trench capacitor provided in the third embodiment includes:

[0075] S510: Providing a substrate, wherein first to third metal wires arranged in the same layer and an insulating layer covering the first to third metal wires are formed on the substrate;

[0076] S520: forming a second trench in the insulating layer on the second metal line to expose the second metal line, and forming a first trench in the insulating layer on the first metal line to expose the first metal line;

[0077] S530: Forming a single-layer capacitor on the second trench and the insulating layer around it, and forming a double-layer capacitor on the first trench and the insulating layer around it, the double-layer capacitor including a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode that are conformally formed in sequence, the single-layer capacitor including the second electrode, the second dielectric layer and the third electrode that are conformally formed in sequence, the first electrode being electrically connected to the first metal wire using the first trench, and the second electrode being electrically connected to the second metal wire using the second trench; wherein the second electrode of the double-layer capacitor extends into the second trench to form the second electrode of the single-layer capacitor and also serves as a fourth metal wire.

[0078] S540: forming a third through hole in the insulating layer on the third metal line to expose the third metal line;

[0079] S550 : forming a fifth metal line to cover the third through hole and the third electrode to electrically connect the third electrode and the third metal line.

[0080] The difference between this third embodiment and the first embodiment is that: in this third embodiment, a double-layer capacitor is formed on the first trench and the insulating layer around it, and a single-layer capacitor is formed on the second trench and the insulating layer around it; thus, the second electrode of the double-layer capacitor extends into the second trench, forming the second electrode of the single-layer capacitor while also serving as the fourth metal wire; in this third embodiment, only a third through hole needs to be formed in the insulating layer on the third metal wire to expose the third metal wire, so as to form a fifth metal wire to electrically connect the third electrode and the third metal wire.

[0081] Next, the manufacturing method of the trench capacitor will be described in detail with reference to Figures 6a to 6j and 7a to 7c, wherein Figures 6a to 6j and 7a to 7c are schematic structural diagrams corresponding to the corresponding steps of the manufacturing method of the trench capacitor provided in this embodiment.

[0082] First, referring to FIG. 6 a , step S510 is performed to provide a substrate 10 having first metal lines 12, second metal lines 11, and third metal lines 13 arranged in the same layer and an insulating layer 22 covering the first metal lines 12, second metal lines 11, and third metal lines 13. For details, refer to step S110 of the first embodiment.

[0083] 6 b , step S520 is performed to form a plurality of first trenches 24 in the insulating layer 22 on the first metal line 12 to expose the first metal line 12 , and a plurality of second trenches 23 in the insulating layer 22 on the second metal line 11 to expose the second metal line 11 .

[0084] Specifically, a photolithography process can be used to define two etching areas (not shown) on the insulating layer 22 on the first metal line 12 and the second metal line 11, respectively. Then, a dry etching process is used to sequentially etch the insulating layer 22 and the dielectric barrier layer 21 to form a plurality of spaced first trenches 24 to expose the first metal line 12 and a plurality of spaced second trenches 23 to expose the second metal line 11. The first trench 24 and the second trench 23 can have the same opening size. The area where the first trench 24 and the insulating layer 22 are located can be a first area BB, which is used to subsequently form a double-layer capacitor thereon, and the area where the second trench 23 and the insulating layer 22 are located can be a second area AA, which is used to subsequently form a single-layer capacitor thereon, wherein the first area BB and the second area AA can be spaced apart or connected.

[0085] Furthermore, as needed, in practice, the second area AA may correspond to multiple second metal lines 11, and the coverage area of ​​the second area AA may be larger than the area covered by the second metal lines. That is, only a portion of the second trenches 23 directly above the second metal lines 11 expose the second metal lines 11, while other second trenches 23 offset from the second metal lines 11 do not expose the second metal lines 11. The same applies to the first area BB and the first trenches 24.

[0086] Next, step S530 is executed to form a double-layer capacitor on the first trench 24 and the insulating layer 22 around it, and a single-layer capacitor on the second trench 23 and the insulating layer 22 around it. The double-layer capacitor includes a first electrode 26a, a first dielectric layer 27a, a second electrode 29a, a second dielectric layer 31a, and a third electrode 33a that are conformally formed in sequence. The single-layer capacitor includes a second electrode 29a, a second dielectric layer 31a, and a third electrode 33a that are conformally formed in sequence. The first electrode 26a is electrically connected to the first metal line 12, and the second electrode 29a is electrically connected to the second metal line 11.

[0087] Specifically, referring to FIG6c , a first electrode material layer 26 is formed to conformally cover the surface of the insulating layer 22, the inner walls of the first trench 24, and the second trench 23. Any suitable process can be used to form a thin film conductive layer serving as the first electrode material layer 26. The first electrode material layer 26 may include one or more thin film conductive layers, and the material may include, for example, one or more of titanium, titanium nitride, tantalum, or tantalum nitride. The formation process may include physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The first electrode material layer 26 may be relatively thin to form a double-layer trench capacitor, and the thickness may be, for example, 100 to 400 angstroms.

[0088] Referring to Figure 6d , a patterning process is performed on the first electrode material layer 26, retaining the first electrode material layer 26 in the first region BB and the second region AA. The first electrode material layer 26 on the inner wall of the first trench 24 and on the insulating layer 22 between the first trenches 24 serves as the first electrode 26a. The first electrode material layer 26 in the second trench 23 is electrically connected to the second metal line 11, and the first electrode 26a is electrically connected to the first metal line 12. Furthermore, the first electrode 26a may extend to cover the insulating layer 22 surrounding the outermost first trench 24 to facilitate the patterning process. In some examples, it is feasible to omit the first electrode material layer 26 in the second region AA. However, retaining the first electrode material layer 26 in the second region AA allows the second region AA and the first region BB to have similar structures, facilitating the simultaneous formation of capacitors in the second region AA and the first region BB. Furthermore, the first electrode material layer 26 at the bottom of the second trench 23 also serves as a protective layer for the second metal line 11.

[0089] Referring to FIG6e , a first dielectric material layer 27 is formed to cover the surface of the insulating layer 22 and the inner walls of the first trench 24 and the second trench 23, that is, to cover the surface of the insulating layer 22, the first area BB, and the second area AA. The first dielectric material layer 27 can be made of a dielectric material with a relatively high dielectric constant, such as greater than or equal to 3.9. The material can be, for example, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or rhodium oxide.

[0090] Referring to Figure 6f, a first mask 28 is formed to cover the first dielectric material layer 27 in the first area BB. An etching process is then performed to remove the first dielectric material layer 27 on the surface of the insulating layer 22 and the bottom wall of the second trench 23, exposing the first electrode material layer 26. The first dielectric material layer 27 in the first area BB serves as the first dielectric layer 27a. The area covered by the first mask 28 is larger than the area covered by the first electrode 26a, so that the first dielectric layer 27a completely covers the first electrode 26a. Furthermore, during the dry etching of the first dielectric material layer 27 in the second area AA, the first dielectric material layer 27 at the bottom of the second trench 23 and on the surface of the first electrode material layer 26 is removed, exposing the first electrode material layer 26 at the bottom of the second trench 23. The first dielectric material layer 27 may remain, partially remain, or not remain on the sidewalls of the second trench 23. In practice, using the dry etching process to remove the first dielectric material layer 27 as an example, the first dielectric material layer 27 may remain or partially remain on the sidewalls of the second trench 23.

[0091] Referring to FIG. 6 g , first mask 28 is removed, and a second electrode material layer 29 is conformally formed to cover the surface of insulating layer 22, the inner walls of first trench 24, and second trench 23. Specifically, the second electrode material layer 29 covers the surface of insulating layer 22, first area BB, and second area AA. The material of second electrode material layer 29 may be similar to that of first electrode material layer 26.

[0092] Referring to Figure 6h, a second mask 30 is formed covering the first region BB, the second region AA, and the second electrode material layer 29 therebetween. An etching process is then performed to remove the exposed second electrode material layer 29. The first region BB, the second region AA, and the second electrode material layer 29 therebetween serve as the second electrode 29a. The second electrode 29a is electrically connected to the second metal line 11 via the first electrode material layer 26 at the bottom of the second trench 23. This allows the second electrodes 29a of capacitors subsequently formed on the first metal line 12 and the second metal line 11 to be electrically connected to the second metal line 11. In this embodiment, the second electrode 29a in the second region AA serves as the second electrode 29a of a single-layer capacitor, the second electrode 29a in the first region BB serves as the second electrode 29a of a double-layer capacitor, and the second electrode material layer 29 between the first region BB and the second region AA and the second electrode 29a in the second region AA serve as a fourth metal line. If the first electrode material layer 26 remains within the second trench 23, the first electrode material layer 26 remaining within the second trench 23 also constitutes a portion of the fourth metal line. In this way, the second electrode 29 a is electrically connected to the second metal wire 11 through the first electrode material layer 26 .

[0093] Referring to FIG. 6i , the second mask 30 is removed, and a second dielectric material layer 31 and a third electrode material layer 33 are conformally formed to cover the surface of the insulating layer 22, the inner walls of the first trench 24, and the second trench 23. In other words, they cover the surface of the insulating layer 22, the first area BB, and the second area AA. The material of the second dielectric material layer 31 may refer to the material of the first dielectric material layer 27, and the material of the third electrode material layer 33 may refer to the material of the first electrode material layer 26.

[0094] Referring to FIG6j , a third mask 32 is formed to cover the first region BB, the second region AA, and the third electrode material layer 33 therebetween. An etching process is then performed to remove the exposed third electrode material layer 33 and the second dielectric material layer 31 thereunder. The third electrode material layer 33 in the first region BB, the second region AA, and the region therebetween serves as the third electrode 33a, while the second dielectric material layer 31 in the first region BB, the second region AA, and the region therebetween serves as the second dielectric layer 31a. It should be noted that the area covered by the third mask 32 is slightly larger than that covered by the second mask 30, so that the formed second dielectric layer 31a can completely cover the second electrode 29a, thereby preventing exposure of the second electrode 29a.

[0095] As a result, a single-layer trench capacitor consisting of the second electrode 29a, the second dielectric layer 31a, and the third electrode 33a is formed in the second region AA on the second metal line 11. A double-layer trench capacitor consisting of the first electrode 26a, the first dielectric layer 27a, the second electrode 29a, the second dielectric layer 31a, and the third electrode 33a is formed in the first region BB on the first metal line 12. The second electrode 29a of the single-layer trench capacitor and the double-layer trench capacitor are electrically led downward through the second metal line 11, and the first electrode 26a of the double-layer capacitor is electrically led downward through the first metal line 12. Furthermore, a single-layer planar capacitor consisting of the second electrode 29a, the second dielectric layer 31a, and the third electrode 33a is formed in the region between the first region BB and the second region AA. The parallel connection of the single-layer trench capacitor, the single-layer planar capacitor, and the double-layer trench capacitor significantly increases the capacitance value (capacitance density) within the same substrate 10 area.

[0096] Next, step S540 is performed to form a third through hole 42 in the insulating layer 22 on the third metal line 13 to expose the third metal line 13 .

[0097] 7 a , the third mask 32 is removed, and a patterning process is performed to form at least one third through hole 42 in the dielectric barrier layer 21 and the insulating layer 22 on the third metal line 13 to expose the third metal line 13 .

[0098] Next, step S550 is performed to utilize the third through-hole 42 to form a fifth metal wire 41 to cover the third through-hole 42 and the third electrode 33 a so as to electrically connect the third electrode 33 a and the third metal wire 13 .

[0099] Specifically, referring to Figure 7b , a second metal material layer 43 is formed to cover the surface of the insulating layer 22, the surface of the third electrode 33a, and the inner wall of the third through-hole 42. The second metal material layer 43 can be made of a metal suitable for connection to an external circuit, such as aluminum. In this embodiment, the first metal wire 12, the second metal wire 11, and the third metal wire 13 are made of copper. The second metal material layer 43 includes a tantalum nitride layer, a tantalum layer, an aluminum layer, a titanium layer, and a titanium nitride layer, which are sequentially conformally formed.

[0100] Referring to FIG. 7 c , a patterning process is performed on the second metal material layer 43 to retain the second metal material layer 43 in the first area BB, the second area AA, and the areas therebetween as the fifth metal line 41 for electrically connecting the third electrode 33 a and the third metal line 13 , thereby electrically leading the third electrode 33 a of the single-layer trench capacitor, the single-layer planar capacitor, and the double-layer trench capacitor downward.

[0101] In addition, during the patterning process of the second metal material layer 43 , the second metal material layer 43 can also be used to simultaneously form a metal pad on the insulating layer 22 , and other top-layer metal lines are electrically led out to the metal pad for connection with external circuits.

[0102] In the third embodiment of the present application, a first trench 24 exposing the first metal line 12 is formed in the insulating layer 22 on the first metal line 12, and a second trench 23 exposing the second metal line 11 is formed in the insulating layer 22 on the second metal line 11. A double-layer trench capacitor is formed in the first trench 24 and in the insulating layer 22 around the first trench 24, and a single-layer trench capacitor is formed in the second trench 23 and on the insulating layer 22 around the second trench 23. The single-layer trench capacitor and the double-layer trench capacitor are connected in parallel, and the single-layer trench capacitor is directly formed by using the second electrode 29a, the second dielectric layer 31a and the third electrode 33a of the double-layer trench capacitor. In addition, in the two capacitors, the first electrode 26 a is connected to the first metal wire 12 at the bottom of the first trench 24, the second electrode 29a is connected to the second metal wire 11 at the bottom of the second trench 23, and the third electrode 33a is connected to the third metal wire 13 through the fifth metal wire 41 using the third through-hole 42 in the insulating layer 22. Thus, the three electrodes of the above-mentioned double-layer capacitor and single-layer capacitor are led downward using the first metal wire 12, the second metal wire 11 and the third metal wire 13 in the substrate 10, and the lead-out of the double-layer trench capacitor and the wiring of the metal wires on the insulating layer are completed without adding additional process steps, thereby increasing the capacitance density of the trench capacitor, reducing the difficulty of process integration, and helping to improve the degree of freedom of trench capacitor design.

[0103] Example 4

[0104] A fourth embodiment of the present application provides a method for manufacturing a trench capacitor.

[0105] The method for manufacturing a trench capacitor provided in Example 4 of the present application is similar to the method provided in Example 3, with the main difference being that the steps for forming a single-layer capacitor and a double-layer capacitor in step S530 of Example 4 are different. Specifically, in Example 4, the second electrode, the second dielectric layer, and the third electrode are formed simultaneously, and a sidewall is formed to isolate the second electrode from the third electrode.

[0106] The manufacturing method of the trench capacitor will be described in detail below with reference to FIG8a to FIG8h , wherein FIG8a to FIG8h are schematic structural diagrams corresponding to the corresponding steps of forming a single-layer capacitor and a double-layer capacitor provided in Example 4 of the present application.

[0107] Specifically, referring to FIG8 a , a first electrode material layer 26 is formed to conformally cover the surface of the insulating layer 22, the inner walls of the first trench 24, and the second trench 23. Any suitable process can be used to form a thin film conductive layer serving as the first electrode material layer 26. The first electrode material layer 26 may include one or more thin film conductive layers, and the material may include, for example, one or more of titanium, titanium nitride, tantalum, or tantalum nitride. The formation process may include physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The first electrode material layer 26 may be relatively thin to form a double-layer trench capacitor, and the thickness may be, for example, 100 to 400 angstroms.

[0108] Referring to Figure 8b , a patterning process is performed on the first electrode material layer 26, retaining the first electrode material layer 26 in the first region BB and the second region AA. The first electrode material layer 26 on the inner wall of the first trench 24 and on the insulating layer 22 between the first trenches 24 serves as the first electrode 26a. The first electrode material layer 26 in the second trench 23 is electrically connected to the second metal line 11, and the first electrode 26a is electrically connected to the first metal line 12. Furthermore, the first electrode 26a may extend to cover the insulating layer 22 surrounding the outermost first trench 24 to facilitate the patterning process. In some examples, it is possible to omit the first electrode material layer 26 in the second region AA. However, retaining the first electrode material layer 26 in the second region AA allows the second region AA and the first region BB to have similar structures, facilitating the simultaneous formation of capacitors in the second region AA and the first region BB. Furthermore, the first electrode material layer 26 at the bottom of the second trench 23 also serves as a protective layer for the second metal line 11.

[0109] Referring to FIG8c , a first dielectric material layer 27 is formed to cover the surface of the insulating layer 22 and the inner walls of the first trench 24 and the second trench 23, that is, to cover the surface of the insulating layer 22, the first area BB, and the second area AA. The first dielectric material layer 27 can be made of a dielectric material with a relatively high dielectric constant, such as greater than or equal to 3.9. Examples of the material include silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or rhodium oxide.

[0110] Referring to Figure 8d, a first mask 28 is formed to cover the first dielectric material layer 27 in the first area BB. An etching process is then performed to remove the first dielectric material layer 27 on the surface of the insulating layer 22 and the bottom wall of the second trench 23, exposing the first electrode material layer 26. The first dielectric material layer 27 in the first area BB serves as the first dielectric layer 27a. The area covered by the first mask 28 is larger than the area covered by the first electrode 26a, so that the first dielectric layer 27a completely covers the first electrode 26a. Furthermore, during the dry etching of the first dielectric material layer 27 in the second area AA, the first dielectric material layer 27 at the bottom of the second trench 23 and on the surface of the first electrode material layer 26 is removed, exposing the first electrode material layer 26 at the bottom of the second trench 23. The first dielectric material layer 27 may remain, partially remain, or not remain on the sidewalls of the second trench 23. In practice, using the dry etching process to remove the first dielectric material layer 27 as an example, the first dielectric material layer 27 may remain or partially remain on the sidewalls of the second trench 23.

[0111] Referring to Figure 8e, the first mask 28 is removed, and a second electrode material layer 29, a second dielectric material layer 31, and a third electrode material layer 33 are sequentially and conformally formed to cover the surface of the insulating layer 22, the inner walls of the first trench 24, and the second trench 23, that is, to cover the surface of the insulating layer 22, the first area BB, and the second area AA. The materials of the second electrode material layer 29 and the third electrode material layer 33 may refer to those of the first electrode material layer 26, and the materials of the second dielectric material layer 31 may refer to those of the first dielectric material layer 27, and are not further described here.

[0112] Referring to FIG8f , a second mask 30 is formed to cover the first region BB, the second region AA, and the third electrode material layer 33 therebetween. An etching process is then performed to sequentially remove the exposed third electrode material layer 33 and the underlying second electrode material layer 29 and second dielectric material layer 31. The second electrode material layer 29, the second dielectric material layer 31, and the third electrode material layer 33 remain in the first region BB, the second region AA, and the region therebetween, thereby forming a second electrode 29a, a second dielectric layer 31a, and a third electrode 33a. The second electrode 29a is electrically connected to the second metal line 11. The coverage area of ​​the second mask 30 is larger than the coverage area of ​​the first dielectric layer 27a (first mask 28), so that the second electrode 29a completely covers the first dielectric layer 27a. After the second electrode 29a, the second dielectric layer 31a, and the third electrode 33a are etched, the outer surface of the third electrode 33a, the sidewalls of the third electrode 33a, the second dielectric layer 31a, and the second electrode 29a are exposed.

[0113] Referring to Figure 8g , the second mask 30 is removed, leaving a third dielectric material layer 35 conformally covering the surface of the insulating layer 22, the surface of the third electrode 33a, and the sidewalls of the second electrode 29a. The third dielectric material layer 35 also covers the sidewalls of the third electrode 33a and the second dielectric layer 31a. The third dielectric material layer 35 can be made of any suitable single or multiple layers of material suitable for forming sidewall spacers, such as silicon nitride, silicon oxide, or the like.

[0114] Referring to FIG8h, a dry etching process is performed to remove the insulating layer 22 and the third dielectric material layer 35 on the surface of the third electrode 33a, exposing the surface of the third electrode 33a. The third dielectric material layer 35 remaining on the sidewalls of the second electrode 29a, the second dielectric layer 31a, and the third electrode 33a serves as a sidewall 35a for isolating the second electrode 29a from the third electrode 33a, and ensuring that the second electrode 29a is completely covered by the dielectric material (the sidewall 35a and the second dielectric layer 31a).

[0115] As a result, a double-layer trench capacitor consisting of the first electrode 26a, the first dielectric layer 27a, the second electrode 29a, the second dielectric layer 31a, and the third electrode 33a is formed in the first region BB on the first metal line 12. A single-layer trench capacitor consisting of the second electrode 29a, the second dielectric layer 31a, and the third electrode 33a is formed in the second region AA on the second metal line 11. The second electrode 29a of the single-layer trench capacitor and the double-layer trench capacitor are electrically led downward through the second metal line 11, and the first electrode 26a of the double-layer capacitor is electrically led downward through the first metal line 12. Furthermore, a single-layer planar capacitor consisting of the second electrode 29a, the second dielectric layer 31a, and the third electrode 33a is formed in the region between the first region BB and the second region AA. The parallel connection of the single-layer trench capacitor, the single-layer planar capacitor, and the double-layer trench capacitor significantly increases the capacitance value (capacitance density) within the same substrate 10 area.

[0116] The rest of the manufacturing process of this embodiment is similar to that of the third embodiment. Please refer to the third embodiment for details and will not be described in detail here.

[0117] Example 5

[0118] FIG9 is a flow chart of a method for manufacturing a trench capacitor provided in Example 5 of the present application.

[0119] As shown in FIG9 , the method for manufacturing a trench capacitor provided in the fifth embodiment includes:

[0120] S910: Providing a substrate, wherein first to third metal lines arranged in the same layer and an insulating layer covering the first to third metal lines are formed on the substrate;

[0121] S920: forming a first trench in the insulating layer to expose the first metal line, a second trench to expose the second metal line, and a third trench to expose the third metal line;

[0122] S930: A double-layer capacitor is formed on the first trench and the insulating layer around it, and a single-layer capacitor is formed on the second trench and the insulating layer around it, the double-layer capacitor includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode that are conformally formed in sequence, and the single-layer capacitor includes the second electrode, the second dielectric layer and the third electrode that are conformally formed in sequence, the first electrode is electrically connected to the first metal wire using the first trench, the second electrode is electrically connected to the second metal wire using the second trench, and the third electrode is electrically connected to the third metal wire using the third trench; wherein the second electrode of the double-layer capacitor extends into the second trench to form the second electrode of the single-layer capacitor and also serves as the fourth metal wire; the third electrode extending to the third trench serves as the fifth metal wire.

[0123] The difference between the fifth embodiment and the third embodiment is that, in the fifth embodiment, a third trench is formed to expose the third metal line simultaneously with the formation of the first trench and the second trench, and the third trench is covered with a third electrode material to achieve electrical connection between the third electrode and the third metal line. In addition, the steps for forming the single-layer capacitor and the double-layer capacitor in the fifth embodiment are different. Specifically, in the fifth embodiment, the first electrode, the first dielectric layer, the second electrode, the second dielectric layer, and the third electrode are formed layer by layer.

[0124] 10a to 10m are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing a trench capacitor provided in Example 5 of the present application. Next, the method for manufacturing the trench capacitor will be described in detail in conjunction with FIG. 10a to 10m.

[0125] First, referring to FIG. 10 a , step S910 is performed to provide a substrate 10 having first metal lines 12, second metal lines 11, and third metal lines 13 arranged in the same layer and an insulating layer 22 covering the first metal lines 12, second metal lines 11, and third metal lines 13. For details, refer to step S110 of the first embodiment.

[0126] 10 b , step S920 is performed to form a plurality of first trenches 24 in the insulating layer 22 to expose the first metal line 12 , a plurality of second trenches 23 to expose the second metal line 11 , and a plurality of third trenches 25 to expose the third metal line 13 .

[0127] Specifically, a photolithography process can be used to define three etching regions (not shown) on the insulating layer 22 over the first metal line 12, the second metal line 11, and the third metal line 13. A dry etching process is then used to sequentially etch the insulating layer 22 and the dielectric barrier layer 21 to form a plurality of spaced-apart first trenches 24 exposing the first metal line 12, a plurality of spaced-apart second trenches 23 exposing the second metal line 11, and a plurality of spaced-apart third trenches 25 exposing the first metal line 13. The first trenches 24, the second trenches 23, and the third trenches 25 can have the same opening size. The first trenches 24 and the surrounding insulating layer 22 area can be a first region BB, for subsequently forming a double-layer capacitor thereon. The second trenches 23 and the surrounding insulating layer 22 area can be a second region AA, for subsequently forming a single-layer capacitor thereon. The third trenches 25 and the surrounding insulating layer 22 area can be a third region CC, for subsequently electrically connecting to the third metal line 13. The first region BB, the second region AA, and the third region CC can be spaced apart or arranged in a continuous relationship.

[0128] Furthermore, as needed, in practice, the second area AA may correspond to multiple second metal lines 11, and the coverage area of ​​the second area AA may be larger than the area covered by the second metal lines. That is, only a portion of the second trenches 23 directly above the second metal lines 11 expose the second metal lines 11, while other second trenches 23 offset from the second metal lines 11 do not expose the second metal lines 11. The first area BB and the first trenches 24, and the third area CC and the third trenches 25 may be configured similarly.

[0129] Next, step S930 is executed to form a double-layer capacitor on the first trench 24 and the insulating layer 22 around it, and a single-layer capacitor on the second trench 23 and the insulating layer 22 around it. The double-layer capacitor includes a first electrode 26a, a first dielectric layer 27a, a second electrode 29a, a second dielectric layer 31a, and a third electrode 33a that are conformally formed in sequence. The single-layer capacitor includes a second electrode 29a, a second dielectric layer 31a, and a third electrode 33a that are conformally formed in sequence. The first electrode 26a is electrically connected to the first metal line 12, the second electrode 29a is electrically connected to the second metal line 11, and the third electrode 33a is electrically connected to the third metal line 13 via the third trench 25.

[0130] Specifically, referring to FIG10c, a first electrode material layer 26 is formed to cover the surface of the insulating layer 22, the inner walls of the first trench 24, the second trench 23, and the third trench 25. Any suitable process can be used to form a thin film conductive layer serving as the first electrode material layer 26. The first electrode material layer 26 may include one or more thin film conductive layers, and the material may include, for example, one or more of titanium, titanium nitride, tantalum, or tantalum nitride. The formation process may include physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The first electrode material layer 26 may be relatively thin to form a double-layer trench capacitor, and the thickness may be, for example, 100 to 400 angstroms.

[0131] Referring to FIG. 10 d , a patterning process is performed on the first electrode material layer 26. The first electrode material layer 26 in the first region BB, the second region AA, and the third region CC is retained. The first electrode material layer 26 in the first region BB serves as the first electrode 26 a. The first electrode 26 a is electrically connected to the first metal line 12. The first electrode material layer 26 in the second trench 23 is electrically connected to the second metal line 11. The first electrode material layer 26 in the third trench 25 is electrically connected to the third metal line 13. Furthermore, the first electrode 26 a may extend to cover the insulating layer 22 located around the outermost first trench 24 to facilitate the patterning process. In some examples, it is feasible not to retain the first electrode material layer 26 in the second area AA and the third area CC. However, retaining the first electrode material layer 26 in the second area AA and the third area CC can make the second area AA and the third area CC have a structure similar to the first area BB, which is conducive to the simultaneous formation of corresponding structures in the second trench 23, the first trench 24 and the third trench 25. Moreover, the first electrode material layer 26 located on the bottom of the second trench 23 and the third trench 25, in addition to being used for subsequent electrical connection of the second metal wire 11 and the third metal wire 13, can also serve as a protective layer for the second metal wire 11 and the third metal wire 13.

[0132] Referring to FIG10e , a first dielectric material layer 27 is formed to cover the surface of the insulating layer 22 and the inner walls of the first trench 24, the second trench 23, and the third trench 25, that is, to cover the surface of the insulating layer 22, the first region BB, the second region AA, and the third region CC. The first dielectric material layer 27 can be made of a dielectric material with a relatively high dielectric constant, such as greater than or equal to 3.9. The material can be, for example, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or rhodium oxide.

[0133] Referring to FIG10f , a first mask 28 is formed to cover the first dielectric material layer 27 in the first region BB, and an etching process is performed to remove the exposed first dielectric material layer 27. The first dielectric material layer 27 in the first region BB serves as the first dielectric layer 27a, exposing the first electrode material layer 26 at the bottoms of the second trench 23 and the third trench 25. The first mask 28 covers an area larger than the area covered by the first electrode 26a, so that the first dielectric layer 27a completely covers the first electrode 26a. Furthermore, during the dry etching of the first dielectric material layer 27 in the second region AA and the third region CC, the first dielectric material layer 27 at the bottoms of the second trench 23 and the third trench 25, the insulating layer 22, and the surface of the first electrode material layer 26 are removed, exposing the first electrode material layer 26 at the bottoms of the second trench 23 and the third trench 25. The first dielectric material layer 27 may remain, partially remain, or not remain on the sidewalls of the second trench 23 and the third trench 25. In practice, taking the dry etching process as an example to remove the first dielectric material layer 27 , the first dielectric material layer 27 may remain or partially remain on the sidewalls of the second trench 23 and the third trench 25 .

[0134] Referring to FIG. 10g , the first mask 28 is removed, and a second electrode material layer 29 is formed to cover the surface of the insulating layer 22 and the inner walls of the first trench 24, the second trench 23, and the third trench 25. Specifically, the second electrode material layer 29 covers the surface of the insulating layer 22, the first area BB, the second area AA, and the third area CC. The material and thickness of the second electrode material layer 29 may refer to the material and thickness of the first electrode material layer 26.

[0135] Referring to Figure 10h, a second mask 30 is formed to cover the first region BB, the second region AA, and the second electrode material layer 29 therebetween. The exposed second electrode material layer 29 is then removed, leaving the second electrode material layer 29 in the first region BB, the second region AA, and the region therebetween as the second electrode 29a. The first electrode material layer 26 at the bottom of the third trench 25 is exposed. The second electrode 29a is electrically connected to the second metal line 11 using the first electrode material layer 26 at the bottom of the second trench 23, so that the second electrode 29a of the capacitor subsequently formed in the second region AA and the first region BB is electrically connected to the second metal line 11. Using dry etching as an example, the second electrode material layer 29 on the insulating layer 22 in the third region CC is removed, exposing (or partially retaining) the second electrode material layer 29 on the sidewalls of the third trench 25. Alternatively, the second electrode material layer 29 at the bottom of the third trench 25 may be left blank, partially retained, or retained. In this embodiment, the second electrode material layer 29 between the first region BB and the second region AA and the second electrode 29a in the second region AA serve as the fourth metal line. When the first electrode material layer 26 remains in the second trench 23 , the first electrode material layer 26 remaining in the second trench 23 also constitutes a portion of the fourth metal line. In this way, the second electrode 29 a is electrically connected to the second metal line 11 through the first electrode material layer 26 .

[0136] Referring to FIG. 10i , the second mask 30 is removed, and a second dielectric material layer 31 is conformally formed to cover the surface of the insulating layer 22 and the inner walls of the first trench 24, the second trench 23, and the third trench 25. In other words, the second dielectric material layer 31, the first region BB, the second region AA, and the third region CC are covered. The material and thickness of the second dielectric material layer 31 may refer to the material and thickness of the first dielectric material layer 27.

[0137] Referring to Figure 10j, a third mask 32 is formed to cover the first area BB, the second area AA, and the second dielectric material layer 31 therebetween. The exposed second dielectric material layer 31 is then removed, leaving the first area BB, the second area AA, and the second dielectric material layer 31 therebetween as the second dielectric layer 31a. This exposes the first electrode material layer 26 at the bottom of the third trench 25. The third mask 32 completely covers the second electrode 29a. Specifically, the area covered by the third mask 32 is slightly larger than the area covered by the second mask 30 (second electrode 29a). This allows the formed second dielectric layer 31a to completely cover the second electrode 29a, thereby preventing exposure of the second electrode 29a and completely electrically isolating it from the subsequent third electrode 33a. Of course, the second dielectric material layer 31 may remain on the sidewalls of the third trench 25.

[0138] Referring to Figure 10k , the third mask 32 is removed, and a third electrode material layer 33 is conformally formed to cover the surface of the insulating layer 22, the inner walls of the first trench 24, the second trench 23, and the third trench 25. Specifically, the third electrode material layer 33 covers the surface of the insulating layer 22, the first region BB, the second region AA, and the third region CC. The material and thickness of the third electrode material layer 33 may refer to the material and thickness of the first electrode material layer 26. In practice, the thickness of the third electrode material layer 33 may be greater than or equal to the thickness of the first electrode material layer 26 (or the second electrode material layer 29) so that the third electrode material layer 33 completely fills the second trench 23, the first trench 24, and the third trench 25. In this embodiment, the third electrode material layer 33 between the first region BB and the third region CC, as well as the third electrode material layer 33 in the third region CC, collectively form a fifth metal line. If the first electrode material layer 26 remains in the third trench 25, the remaining first electrode material layer 26 in the third trench 25 also constitutes a portion of the fifth metal line. In this way, the third electrode 33 a is electrically connected to the third metal wire 13 through the third electrode material layer.

[0139] Referring to FIG101 , a fourth mask 34 is formed to cover the first region BB, the second region AA, the third region CC, and the third electrode material layer 33 therebetween. The exposed third electrode material layer 33 is removed, and the first region BB, the second region AA, the third region CC, and the third electrode material layer 33 therebetween serve as the third electrode 33 a. The third electrode 33 a is electrically connected to the third metal line 13 using the first electrode material layer 26 at the bottom of the third trench 25 .

[0140] Referring to FIG. 10 m , the fourth mask 34 is removed. Consequently, a single-layer trench capacitor consisting of the second electrode 29 a, the second dielectric layer 31 a, and the third electrode 33 a is formed in the second area AA on the second metal line 11. A double-layer trench capacitor consisting of the first electrode 26 a, the first dielectric layer 27 a, the second electrode 29 a, the second dielectric layer 31 a, and the third electrode 33 a is formed in the first area BB on the first metal line 12. The second electrode 29 a of the single-layer trench capacitor and the double-layer trench capacitor are electrically led downward through the second metal line 11, the first electrode 26 a of the double-layer trench capacitor is electrically led downward through the first metal line 12, and the third electrode 33 a of the single-layer trench capacitor and the double-layer trench capacitor are electrically led downward through the third trench 25. Furthermore, a single-layer planar capacitor consisting of the second electrode 29 a, the second dielectric layer 31 a, and the third electrode 33 a is formed in the region between the first area BB and the second area AA. The single-layer trench capacitor, the single-layer planar capacitor, and the double-layer trench capacitor are connected in parallel, which can significantly increase the capacitance value on the same substrate 10 area, that is, the capacitance density.

[0141] In the fifth embodiment of the present application, a first trench 24 exposing the first metal wire 12 is formed in the insulating layer 22 on the first metal wire 12, a second trench 23 exposing the second metal wire 11 is formed in the insulating layer 22 on the second metal wire 11, and a third trench 25 exposing the third metal wire 13 is formed in the insulating layer 22 on the third metal wire 13. A double-layer capacitor is formed in the first trench 24 and in the insulating layer 22 around the first trench 24, and a single-layer capacitor is formed in the second trench 23 and on the insulating layer 22 around the second trench 23. The single-layer trench capacitor is connected in parallel with the double-layer trench capacitor. The single-layer trench capacitor is directly formed by using the second electrode 29a, the second dielectric layer 31a and the third electrode 33a of the double-layer trench capacitor. In addition, in the two capacitors, the first electrode 2 6a is connected to the first metal wire 12 at the bottom of the first trench 24 by using the first trench 24, the second electrode 29a is connected to the second metal wire 11 at the bottom of the second trench 23 by using the second trench 23, and the third electrode 33a is connected to the third metal wire 13 at the bottom of the third trench 25 by using the third trench 25. As a result, the first to third electrodes of the double-layer capacitor and the second electrode 29a and the third electrode 33a of the single-layer capacitor are led downward by using the first metal wire 12, the second metal wire 11 and the third metal wire 13 in the substrate 10, realizing the lead-out of the double-layer trench capacitor and the wiring of the metal wires on the insulating layer without adding additional process steps, thereby increasing the capacitance density of the trench capacitor, reducing the difficulty of process integration, and being conducive to improving the degree of freedom of trench capacitor design.

[0142] Example 6

[0143] Embodiment 6 of the present application provides a method for manufacturing a trench capacitor.

[0144] The method for manufacturing a trench capacitor provided in Example 6 of the present application is similar to the method provided in Example 5, with the main difference being the steps for forming a single-layer capacitor and a double-layer capacitor in step S930 of Example 5. Specifically, in Example 6, the second electrode and the second dielectric layer are formed simultaneously, and after forming the third electrode, a sidewall is formed to isolate the second electrode from the third electrode.

[0145] The manufacturing method of the trench capacitor will be described in detail below with reference to FIG. 11 a to FIG. 11 k . FIG. 11 a to FIG. 11 k are schematic structural diagrams corresponding to the steps of forming a single-layer capacitor and a double-layer capacitor provided in Example 6.

[0146] Specifically, referring to FIG. 11 a , a first electrode material layer 26 is formed to cover the surface of the insulating layer 22, the inner walls of the first trench 24, the second trench 23, and the third trench 25. Any suitable process can be used to form a thin film conductive layer serving as the first electrode material layer 26. The first electrode material layer 26 may include one or more thin film conductive layers, and the material may include, for example, one or more of titanium, titanium nitride, tantalum, or tantalum nitride. The formation process may include physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The first electrode material layer 26 may be relatively thin to form a double-layer trench capacitor, and the thickness may be, for example, 100 to 400 angstroms.

[0147] Referring to FIG. 11 b , a patterning process is performed on the first electrode material layer 26. The first electrode material layer 26 in the first region BB, the second region AA, and the third region CC is retained. The first electrode material layer 26 in the first region BB serves as the first electrode 26 a. The first electrode 26 a is electrically connected to the first metal line 12. The first electrode material layer 26 in the second trench 23 is electrically connected to the second metal line 11. The first electrode material layer 26 in the third trench 25 is electrically connected to the third metal line 13. Furthermore, the first electrode 26 a may extend to cover the insulating layer 22 located around the outermost first trench 24 to facilitate the patterning process. In some examples, it is feasible not to retain the first electrode material layer 26 in the second area AA and the third area CC. However, retaining the first electrode material layer 26 in the second area AA and the third area CC can make the second area AA and the third area CC have a structure similar to the first area BB, which is conducive to the simultaneous formation of corresponding structures in the second trench 23, the first trench 24 and the third trench 25. Moreover, the first electrode material layer 26 located on the bottom of the second trench 23 and the third trench 25, in addition to being used for subsequent electrical connection of the second metal wire 11 and the third metal wire 13, can also serve as a protective layer for the second metal wire 11 and the third metal wire 13.

[0148] Referring to FIG11c , a first dielectric material layer 27 is formed to cover the surface of the insulating layer 22 and the inner walls of the first trench 24, the second trench 23, and the third trench 25, that is, to cover the surface of the insulating layer 22, the first region BB, the second region AA, and the third region CC. The first dielectric material layer 27 can be made of a dielectric material with a relatively high dielectric constant, such as greater than or equal to 3.9. Examples of the material include silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or rhodium oxide.

[0149] Referring to FIG. 11 d , a first mask 28 is formed to cover the first dielectric material layer 27 in the first region BB, and an etching process is performed to remove the exposed first dielectric material layer 27. The first dielectric material layer 27 in the first region BB serves as the first dielectric layer 27a, exposing the first electrode material layer 26 at the bottoms of the second trench 23 and the third trench 25. The first mask 28 covers an area larger than the area covered by the first electrode 26a, so that the first dielectric layer 27a completely covers the first electrode 26a. Furthermore, during the dry etching of the first dielectric material layer 27 in the second region AA and the third region CC, the first dielectric material layer 27 located at the bottoms of the second trench 23 and the third trench 25, the insulating layer 22, and the surface of the first electrode material layer 26 is removed, exposing the first electrode material layer 26 at the bottoms of the second trench 23 and the third trench 25. The sidewalls of the second trench 23 and the third trench 25 may retain, partially retain, or not retain the first dielectric material layer 27. In practice, taking the dry etching process as an example to remove the first dielectric material layer 27 , the first dielectric material layer 27 may remain or partially remain on the sidewalls of the second trench 23 and the third trench 25 .

[0150] Referring to Figure 11e, the first mask 28 is removed, and a second electrode material layer 29 and a second dielectric material layer 31 are conformally formed sequentially to cover the surface of the insulating layer 22, the inner walls of the first trench 24, the second trench 23, and the third trench 25, that is, to cover the surface of the insulating layer 22, the first area BB, the second area AA, and the third area CC. The material and thickness of the second electrode material layer 29 can refer to the material and thickness of the first electrode material layer 26, and the material and thickness of the second dielectric material layer 31 can refer to the material and thickness of the first dielectric material layer 27, and are not further described here.

[0151] Referring to FIG. 11f , a second mask 30 is formed to cover the first region BB, the second region AA, and the second dielectric material layer 31 therebetween. The exposed second dielectric material layer 31 and the second electrode material layer 29 thereunder are removed, leaving the first region BB, the second region AA, and the second electrode material layer 29 and the second dielectric material layer 31 therebetween. The second electrode material layer 29 in the first region BB, the second region AA, and the second electrode material layer 29 therebetween serves as the second electrode 29a, and the second dielectric material layer 31 in the first region BB, the second region AA, and the second electrode material layer 31 therebetween serves as the second dielectric layer 31a. The second electrode 29a is electrically connected to the second metal line 11, and the first electrode material layer 26 is exposed at the bottom of the third trench 25. The coverage area of ​​the second mask 30 is larger than the coverage area of ​​the first dielectric layer 27a (first mask 28), so that the second electrode 29a completely covers the first dielectric layer 27a. After etching to form the second electrode 29a and the second dielectric layer 31a, the surface of the second dielectric layer 31a and the sidewalls of the second dielectric layer 31a and the second electrode 29a are exposed. Taking dry etching as an example, the third region CC is exposed outside the second mask 30, so that the second electrode material layer 29 and the second dielectric material layer 31 on the insulating layer 22 and the bottom of the third trench 25 are removed, while the second electrode material layer 29 and the second dielectric material layer 31 on the sidewalls of the third trench 25 are retained or partially retained, so that the second trench 23, the first trench 24 and the third trench 25 have as similar film layers as possible, so as to facilitate the simultaneous formation of corresponding structures.

[0152] Referring to Figure 11g, the second mask 30 is removed, and a third dielectric material layer 35 is formed to conformally cover the surface of the insulating layer 22, the inner walls of the first trench 24, the second trench 23, and the third trench 25. Of course, the third dielectric material layer 35 also covers the sidewalls of the second electrode 29a and the second dielectric layer 31a. The third dielectric material layer 35 can be made of any suitable single or multiple layers of dielectric material suitable for forming the sidewalls 35a, such as silicon nitride, silicon oxide, etc. In a preferred embodiment, the material of the third dielectric material layer 35 can be the same as that of the second dielectric layer 31a, and can be, for example, a high-k dielectric to facilitate etching and improve capacitance.

[0153] Referring to FIG. 11 h , an anisotropic dry etching process is performed to remove the surface of the insulating layer 22, the surface of the second dielectric layer 31 a, and the third dielectric material layer 35 at the bottom of the third trench 25, exposing the surface of the insulating layer 22, the surface of the second dielectric layer 31 a, and the first electrode material layer 26 at the bottom of the third trench 25. The third dielectric material layer 35 retained on the sidewalls of the second electrode 29 a and the second dielectric layer 31 a serves as a sidewall 35 a for isolating the second electrode 29 a from the third electrode 33 a, and completely covering the second electrode 29 a.

[0154] Referring to FIG. 11i , a third electrode material layer 33 is conformally formed to cover the surface of the insulating layer 22, the inner walls of the first trench 24, the second trench 23, and the third trench 25, that is, to cover the surface of the insulating layer 22, the first region BB, the second region AA, and the third region CC. The material and thickness of the third electrode material layer 33 may refer to the material and thickness of the first electrode material layer 26. In practice, the thickness of the third electrode material layer 33 may be greater than or equal to the thickness of the first electrode material layer 26 (or the second electrode material layer 29) so that the third electrode material layer 33 completely fills the second trench 23, the first trench 24, and the third trench 25.

[0155] Referring to FIG. 11 j , a third mask 32 a is formed to cover the first region BB, the second region AA, the third region CC, and the third electrode material layer 33 therebetween. The exposed third electrode material layer 33 is removed, and the third electrode material layer 33 in the first region BB, the second region AA, the third region CC, and the third electrode material layer 33 therebetween serves as a third electrode 33 a. The third electrode 33 a is electrically connected to the third metal line 13 via the first electrode material layer 26 at the bottom of the third trench 25. It should be noted that the third mask of the fifth embodiment is indicated by 32 , and the third mask of the sixth embodiment is indicated by 32 a .

[0156] Referring to Figure 11k , the third mask 32a is removed. Consequently, a single-layer trench capacitor consisting of the second electrode 29a, the second dielectric layer 31a, and the third electrode 33a is formed in the second area AA on the second metal line 11. A double-layer trench capacitor consisting of the first electrode 26a, the first dielectric layer 27a, the second electrode 29a, the second dielectric layer 31a, and the third electrode 33a is formed in the first area BB on the first metal line 12. The second electrode 29a of the single-layer trench capacitor and the double-layer trench capacitor are electrically led downward through the second metal line 11, the first electrode 26a of the double-layer trench capacitor is electrically led downward through the first metal line 12, and the third electrode 33a of the single-layer trench capacitor and the double-layer trench capacitor are electrically led downward through the third trench 25. Furthermore, a single-layer planar capacitor consisting of the second electrode 29a, the second dielectric layer 31a, and the third electrode 33a is formed in the region between the first area BB and the second area AA. The single-layer trench capacitor, the single-layer planar capacitor, and the double-layer trench capacitor are connected in parallel, which can significantly increase the capacitance value on the same projected area of ​​the substrate 10, that is, the capacitance density.

[0157] The rest of the manufacturing process of this embodiment is similar to that of the fifth embodiment. Please refer to the fifth embodiment for details and will not be described in detail here.

[0158] Example 7

[0159] The trench capacitor provided in the seventh embodiment of the present application can be formed by the method provided in the first embodiment, and reference can be made to the structural schematic diagram of the trench capacitor shown in FIG3 e .

[0160] Specifically, as shown in FIG3e , the trench capacitor may include a substrate 10, a first metal line 12, a second metal line 11, and a third metal line 13, an insulating layer 22, a double-layer capacitor, a fourth metal line 40, and a fifth metal line 41. The first metal line 12, the second metal line 11, and the third metal line 13 are arranged in the same layer in the substrate 10; the insulating layer 22 covers the first metal line 12, the second metal line 11, and the third metal line 13, and a plurality of first trenches 24 are formed in the insulating layer 22 to expose the first metal line 12; the double-layer capacitor is formed on the insulating layer 22 in and around the first trenches 24, and includes a first electrode 26a, a first dielectric layer 27a, a second electrode 29a, a second dielectric layer 31a, and a third electrode 33a, which are conformally formed in sequence. The first electrode 26a is electrically connected to the first metal line 12; the fourth metal line 40 is electrically connected to the second metal line 11 and the second electrode 29a; and the fifth metal line 41 is electrically connected to the third metal line 13 and the third electrode 33a.

[0161] In some embodiments, the trench capacitor further includes a third dielectric layer 36, which covers the double-layer capacitor. A plurality of first through-holes 37 are formed in the third dielectric layer 36 to expose the second electrode 29a and the third electrode 33a respectively. A plurality of second through-holes 38 are also formed in the insulating layer 22 to expose the second metal wire 11 and the third metal wire 13 respectively. The fourth metal wire 40 utilizes the first through-hole 37 and the second through-hole 38 to electrically connect the second metal wire 11 and the second electrode 29a. The fifth metal wire 41 utilizes the first through-hole 37 and the second through-hole 38 to electrically connect the third metal wire 13 and the third electrode 33a.

[0162] Example 8

[0163] The trench capacitor provided in the eighth embodiment of the present application can be formed using the method provided in the second embodiment. The trench capacitor of the eighth embodiment differs from the trench capacitor of the seventh embodiment in that the fourth metal line 40 of the trench capacitor of the eighth embodiment is electrically connected to the second metal line 11 and the third electrode 33a using the first through-hole 37 and the second through-hole 38, and the fifth metal line 41 is electrically connected to the third metal line 13 and the second electrode 29a using the first through-hole 37 and the second through-hole 38.

[0164] Example 9

[0165] The trench capacitor provided in the ninth embodiment of the present application can be formed using the manufacturing method provided in the third embodiment.

[0166] Specifically, as shown in FIG. 7 c , the trench capacitor may include a substrate 10 , a first metal line 12 , a second metal line 11 , a third metal line 13 , an insulating layer 22 , a double-layer capacitor, and a single-layer capacitor. The first metal line 12, the second metal line 11, and the third metal line 13 are arranged in the same layer in the substrate 10. An insulating layer 22 covers the first metal line 12, the second metal line 11, and the third metal line 13. A first trench 24 is formed in the insulating layer 22 to expose the first metal line 12, and a second trench 23 is formed to expose the second metal line 11. A double-layer capacitor (double-layer trench capacitor) is formed on the insulating layer 22 in and around the first trench 24, including a first electrode 26a, a first dielectric layer 27a, a second electrode 29a, a second dielectric layer 31a, and a third electrode 33a that are conformally formed in sequence. The first electrode 26a is electrically connected to the first metal line 12 via the first trench 24. A single-layer capacitor (single-layer trench capacitor) is formed on the insulating layer 22 in and around the second trench 23, including a second electrode 29a, a second dielectric layer 31a, and a third electrode 33a that are conformally formed in sequence. The second electrode 29a is electrically connected to the second metal line 11 via the second trench 23.

[0167] Furthermore, a single-layer planar capacitor consisting of the second electrode 29a, the second dielectric layer 31a, and the third electrode 33a is formed in the region between the second trench 23 and the first trench 24. The first dielectric layer 27a completely covers the first electrode 26a (including its sidewalls), and the second dielectric layer 31a completely covers the second electrode 29a (including its sidewalls), thereby achieving better electrical isolation between the first electrode 26a, the second electrode 29a, and the third electrode 33a.

[0168] In some embodiments, the trench capacitor also includes a fifth metal wire 41, and a plurality of third through holes 42 are formed in the insulating layer 22 to expose the third metal wire 13 and the fifth metal wire 41. The fifth metal wire 41 covers the inner wall of the third through hole 42 and the surface of the third electrode 33a to electrically connect the third metal wire 13 and the third electrode 33a.

[0169] Example 10

[0170] The trench capacitor provided in the tenth embodiment of the present application can be formed using the method provided in the fourth embodiment. Referring to Figure 8h, the difference between the trench capacitor of the tenth embodiment and the ninth embodiment is that the second dielectric layer 31a of the trench capacitor of the tenth embodiment only covers the surface of the second electrode 29a but does not cover the sidewalls of the second electrode 29a. That is, the edges of the second electrode 29a, the second dielectric layer 31a, and the third electrode 33a form a vertical or nearly vertical step, thereby forming a sidewall 35a covering the sidewalls (steps) of the second electrode 29a, the second dielectric layer 31a, and the third electrode 33a. The sidewall 35a and the second dielectric layer 31a are used to electrically isolate the second electrode 29a and the third electrode 33a.

[0171] Example 11

[0172] The trench capacitor provided in the eleventh embodiment of the present application may be formed by the manufacturing method provided in the fifth embodiment, and reference may be made to the structural schematic diagram of the trench capacitor shown in FIG10 m .

[0173] Specifically, as shown in FIG10m, the trench capacitor may include a substrate 10, a first metal line 12, a second metal line 11 and a third metal line 13, an insulating layer 22, a double-layer capacitor, and a single-layer capacitor. The first metal line 12, the second metal line 11 and the third metal line 13 are arranged in the same layer in the substrate 10; the insulating layer 22 covers the first metal line 12, the second metal line 11 and the third metal line 13 and has a plurality of (at least one) first trenches 24 formed in the insulating layer 22 to expose the first metal line 12, a plurality of (at least one) second trenches 23 to expose the second metal line 11 and a plurality of (at least one) third trenches 25 to expose the third metal line 13; a double-layer capacitor (double-layer trench capacitor) is formed on the insulating layer 22 (first region BB) in and around the first trench 24, including a first electrode 26a, a first dielectric layer 27a, a second electrode 29a, a third dielectric layer 28a, and a second dielectric layer 29b formed in sequence. The second dielectric layer 31a and the third electrode 33a are formed. The first electrode 26a is electrically connected to the first metal line 12 via the first trench 24, the second electrode 29a is electrically connected to the second metal line 11 via the second trench 23, and the third electrode 33a is electrically connected to the third metal line 13 via the third trench 25. A single-layer capacitor (single-layer trench capacitor) is formed on the insulating layer 22 (second area AA) in and around the second trench 23. The single-layer capacitor (single-layer trench capacitor) comprises the second electrode 29a, the second dielectric layer 31a, and the third electrode 33a, which are conformally formed in sequence. This capacitor is connected in parallel with the double-layer capacitor in the first area BB, sharing the second electrode 29a, the second dielectric layer 31a, and the third electrode 33a of the double-layer capacitor. Furthermore, a single-layer planar capacitor, consisting of the second electrode 29a, the second dielectric layer 31a, and the third electrode 33a, can also be formed in the area between the second trench 23 and the first trench 24 (the area between the second area AA and the first area BB). The first dielectric layer 27a completely covers the first electrode 26a (including its surface and sidewalls) and the second dielectric layer 31a completely covers the second electrode 29a (including its surface and sidewalls), thereby achieving better electrical isolation among the first electrode 26a, the second electrode 29a and the third electrode 33a.

[0174] Example 12

[0175] The trench capacitor provided in the twelfth embodiment of the present application can be formed using the method provided in the sixth embodiment. Referring to FIG11k , the trench capacitor of the twelfth embodiment differs from the eleventh embodiment in that the second dielectric layer 31a of the trench capacitor of the twelfth embodiment only covers the surface of the second electrode 29a but does not cover the sidewalls of the second electrode 29a. That is, the edges of the second electrode 29a, the second dielectric layer 31a, and the third electrode 33a form a vertical or nearly vertical step. As a result, a sidewall 35a can also be formed to cover the sidewalls (steps) of the second electrode 29a and the second dielectric layer 31a, for electrically isolating the second electrode 29a from the third electrode 33a.

[0176] The above description is only a description of the preferred embodiment of the present application and is not intended to limit the scope of the present application. Any changes or modifications made by ordinary technicians in the field of the present application based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a trench capacitor, characterized in that: include: Providing a substrate, wherein first to third metal wires arranged in the same layer and an insulating layer covering the first to third metal wires are formed in the substrate; forming a first trench in the insulating layer on the first metal line to expose the first metal line; Conformally forming a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode on the insulating layer around the first trench and in the first trench in sequence to form a double-layer capacitor, wherein the first electrode is electrically connected to the first metal line; A fourth metal line is formed to connect the second metal line and the second electrode, and a fifth metal line is formed to connect the third metal line and the third electrode.

2. The method for manufacturing a trench capacitor according to claim 1, wherein: The steps of forming the fourth metal line to connect the second metal line and the second electrode, and forming the fifth metal line to connect the third metal line and the third electrode include: When forming the double-layer capacitor, exposing the surface of the third electrode and a portion of the second electrode; forming a third dielectric layer to cover the double-layer capacitor, and forming a plurality of first through holes in the third dielectric layer on both sides of the first metal line to expose the second electrode and the third electrode respectively; Forming a plurality of second through holes in the insulating layer to expose the second metal line and the third metal line respectively; The first through hole and the second through hole are used to form the fourth metal wire to connect the second metal wire and the second electrode, and the fifth metal wire is formed to connect the third metal wire and the third electrode.

3. The method for manufacturing a trench capacitor according to claim 2, wherein: The steps of using the first through hole and the second through hole to form the fourth metal wire to connect the second metal wire and the second electrode, and forming the fifth metal wire to connect the third metal wire and the third electrode include: Forming a first metal material layer to cover the surface of the insulating layer, the surface of the third dielectric layer, and the inner walls of the first through hole and the second through hole; A patterning process is performed on the first metal material layer to form a fourth metal line connecting the second metal line and the second electrode and a fifth metal line connecting the third metal line and the third electrode.

4. The method for manufacturing a trench capacitor according to claim 3, wherein: When the patterning process is performed on the first metal material layer, a metal pad is also simultaneously formed on the surface of the insulating layer for connection with an external circuit.

5. The method for manufacturing a trench capacitor according to any one of claims 2 to 4, characterized in that: The steps of forming the double layer capacitor include: forming a first electrode material layer to cover the surface of the insulating layer and the inner wall of the first groove; Performing a patterning process on the first electrode material layer to form an insulating layer where the first electrode covers the inner wall of the first trench and the periphery of the first trench; Conformally forming a first dielectric material layer, a second electrode material layer, a second dielectric material layer and a third electrode material layer in sequence to cover the surfaces of the insulating layer and the first electrode; Performing a patterning process on the third electrode material layer and the second dielectric material layer to form the third electrode and the second dielectric layer, and exposing the second electrode material layer; A patterning process is performed on the second electrode material layer and the first dielectric material layer to form the second electrode and the first dielectric layer.

6. The method for manufacturing a trench capacitor according to claim 5, wherein: The edges of the second electrode and the third electrode form a step shape, the edge of the second electrode is located at the lower step surface, and the edge of the third electrode is located at the upper step surface. The third dielectric layer is subjected to a patterning process to synchronously form the first through holes, which are respectively located on both sides of the first metal line, and the first through holes on one side expose the lower step surface, and the first through holes on the other side expose the upper step surface.

7. The method for manufacturing a trench capacitor according to claim 2, wherein: The material of the third dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide nitride.

8. The method for manufacturing a trench capacitor according to claim 1, wherein: The production method further comprises: When the first trench is formed in the insulating layer to expose the first metal line, a second trench is simultaneously formed in the insulating layer to expose the second metal line; A single-layer capacitor is formed on the second groove and the insulating layer around it, and the single-layer capacitor includes the second electrode, the second dielectric layer and the third electrode which are formed conformally in sequence, and the second electrode is electrically connected to the second metal wire by using the second groove; wherein the second electrode of the double-layer capacitor extends into the second groove, forming the second electrode of the single-layer capacitor and also serving as the fourth metal wire.

9. The method for manufacturing a trench capacitor according to claim 8, wherein: The step of connecting the third metal wire and the third electrode with the fifth metal wire comprises: After forming the double-layer capacitor and the single-layer capacitor, forming a third through hole in the insulating layer on the third metal line to expose the third metal line; The fifth metal line is formed to cover the third through hole and the third electrode to electrically connect the third electrode and the third metal line.

10. The method for manufacturing a trench capacitor according to claim 8, wherein: The step of connecting the third metal wire and the third electrode with the fifth metal wire comprises: When the first trench is formed in the insulating layer to expose the first metal line, a third trench is simultaneously formed in the insulating layer to expose the third metal line; When forming the third electrode, the third electrode extends to the third groove, and the third electrode is electrically connected to the third metal wire by using the third groove; wherein the third electrode extending to the third groove serves as the fifth metal wire.

11. The method for manufacturing a trench capacitor according to claim 8, wherein: The insulating layer includes a first region located above the first metal line and a second region located above the second metal line, the first region is provided with the first groove, and the second region is provided with the second groove. The steps of forming the single-layer capacitor and the double-layer capacitor include: Forming a first electrode material layer to cover the surface of the insulating layer, the first trench and the inner wall of the second trench; Performing a patterning process on the first electrode material layer, retaining the first electrode material layer in the first region and the second region, and using the first electrode material layer in the first region as the first electrode, and the first electrode material layer in the second groove is electrically connected to the second metal wire, and the first electrode is electrically connected to the first metal wire; Forming a first dielectric material layer to cover the surface of the insulating layer, the first trench and the inner wall of the second trench; forming a first mask to cover the first dielectric material layer in the first region, and performing an etching process to remove the first dielectric material layer on the surface of the insulating layer and the bottom wall of the second trench to expose the first electrode material layer in the second trench, and using the first dielectric material layer in the first region as the first dielectric layer; removing the first mask to form a second electrode material layer covering the surface of the insulating layer, the first trench and the inner wall of the second trench; forming a second mask to cover the first region, the second region and the second electrode material layer therebetween, removing the exposed second electrode material layer, and using the first region, the second region and the second electrode material layer therebetween as the second electrode, the second electrode being electrically connected to the first electrode material layer in the second trench and the second metal line; Removing the second mask, and conformally forming a second dielectric material layer and a third electrode material layer in sequence to cover the surface of the insulating layer, the first trench, and the inner wall of the second trench; forming a third mask to cover the first region, the second region and the third electrode material layer therebetween, removing the exposed third electrode material layer and the second dielectric material layer thereunder, and using the first region, the second region and the third electrode material layer therebetween as the third electrode, and using the first region, the second region and the second dielectric material layer therebetween as the second dielectric layer, wherein the third mask completely covers the second electrode; The third mask is removed.

12. The method for manufacturing a trench capacitor according to claim 8, wherein: The insulating layer includes a first region located above the first metal line and a second region located above the second metal line, the first region is provided with the first groove, and the second region is provided with the second groove. The steps of forming the single-layer capacitor and the double-layer capacitor include: Forming a first electrode material layer to cover the surface of the insulating layer, the first trench and the inner wall of the second trench; Performing a patterning process on the first electrode material layer, retaining the first electrode material layer in the first region and the second region, and using the first electrode material layer in the first region as the first electrode, and the first electrode material layer in the second groove is electrically connected to the second metal wire, and the first electrode is electrically connected to the first metal wire; Forming a first dielectric material layer to cover the surface of the insulating layer, the first trench and the inner wall of the second trench; forming a first mask to cover the first dielectric material layer in the first region, and performing an etching process to remove the first dielectric material layer on the surface of the insulating layer and the bottom wall of the second trench to expose the first electrode material layer, and using the first dielectric material layer in the first region as the first dielectric layer; Removing the first mask, and conformally forming a second electrode material layer, a second dielectric material layer, and a third electrode material layer in sequence to cover the surface of the insulating layer, the first trench, and the inner wall of the second trench; forming a second mask to cover the first region, the second region and the third electrode material layer therebetween, removing the exposed third electrode material layer and the second electrode material layer and the second dielectric material layer thereunder, and retaining the first region, the second region and the second electrode material layer, the second dielectric material layer and the third electrode material layer therebetween to form the second electrode, the second dielectric layer and the third electrode, wherein the second electrode is electrically connected to the first electrode material layer and the second metal line in the second trench; removing the second mask to form a third dielectric material layer to conformally cover the surface of the insulating layer, the surface of the third electrode and the sidewall of the second electrode; Perform a dry etching process to remove the insulating layer and the third dielectric material layer on the surface of the third electrode, and The third dielectric material layer retained on the side wall of the second electrode serves as a side wall.

13. The method for manufacturing a trench capacitor according to claim 8, wherein: The insulating layer includes a first region located above the first metal line and a second region located above the second metal line, the first region is provided with the first groove, and the second region is provided with the second groove. The steps of forming the single-layer capacitor and the double-layer capacitor include: Forming a first electrode material layer to cover the surface of the insulating layer, the first trench and the inner wall of the second trench; Performing a patterning process on the first electrode material layer, retaining the first electrode material layer in the first region and the second region, and using the first electrode material layer in the first region as the first electrode, the first electrode is electrically connected to the first metal wire, and the first electrode material layer in the second groove is electrically connected to the second metal wire; Forming a first dielectric material layer to cover the surface of the insulating layer, the first trench and the inner wall of the second trench; Forming a first mask to cover the first dielectric material layer in the first area, and performing an etching process to remove the exposed first dielectric material layer, using the first dielectric material layer in the first area as the first dielectric layer, and exposing the first electrode material layer at the bottom of the second trench; removing the first mask and forming a second electrode material layer to cover the surface of the insulating layer, the first trench and the inner wall of the second trench; forming a second mask to cover the first region, the second region and the second electrode material layer therebetween, removing the exposed second electrode material layer, using the first region, the second region and the second electrode material layer therebetween as the second electrode, the second electrode being electrically connected to the first electrode material layer of the second groove and the second metal line; removing the second mask, and conformally forming a second dielectric material layer to cover the surface of the insulating layer, the first trench, and the inner wall of the second trench; forming a third mask to cover the first region, the second region and the second dielectric material layer therebetween, removing the exposed second dielectric material layer, and using the first region, the second region and the second dielectric material layer therebetween as the second dielectric layer, wherein the third mask completely covers the second electrode; removing the third mask, and conformally forming a third electrode material layer to cover the surface of the insulating layer, the first trench, and the inner wall of the second trench; forming a fourth mask to cover the first region, the second region and the third electrode material layer therebetween, removing the exposed third electrode material layer, and using the first region, the second region and the third electrode material layer therebetween as the third electrode; The fourth mask is removed.

14. The method for manufacturing a trench capacitor according to claim 8, wherein: The insulating layer includes a first region located above the first metal line and a second region located above the second metal line, the first region is provided with the first groove, and the second region is provided with the second groove. The steps of forming the single-layer capacitor and the double-layer capacitor include: Forming a first electrode material layer to cover the surface of the insulating layer, the first trench and the inner wall of the second trench; Performing a patterning process on the first electrode material layer, retaining the first electrode material layer in the first region and the second region, and using the first electrode material layer in the first region as the first electrode, the first electrode is electrically connected to the first metal wire, and the first electrode material layer in the second groove is electrically connected to the second metal wire; Forming a first dielectric material layer to cover the surface of the insulating layer, the first trench and the inner wall of the second trench; forming a first mask to cover the first dielectric material layer in the first region, and performing an etching process to remove the exposed first dielectric material layer, using the first dielectric material layer in the first region as the first dielectric layer, and exposing the first electrode material layer at the bottom of the second trench; Removing the first mask, and conformally forming a second electrode material layer and a second dielectric material layer in sequence to cover the surface of the insulating layer, the first trench, and the inner wall of the second trench; forming a second mask to cover the first region, the second region and the second dielectric material layer therebetween, removing the exposed second dielectric material layer and the second electrode material layer thereunder, and retaining the first region, the second region and the second electrode material layer and the second dielectric material layer therebetween to form the second electrode and the second dielectric layer, wherein the second electrode is electrically connected to the first electrode material layer of the second trench and the second metal line; removing the second mask and forming a third dielectric material layer to conformally cover the surface of the insulating layer, the first trench and the inner wall of the second trench; Performing an anisotropic dry etching process to remove the exposed third dielectric material layer, and using the third dielectric material layer retained on the second electrode and the sidewall of the second dielectric layer as a sidewall; forming a third electrode material layer to conformally cover the surface of the insulating layer, the first trench and the inner wall of the second trench; forming a third mask to cover the first region, the second region and the third electrode material layer therebetween, removing the exposed third electrode material layer, and using the first region, the second region and the third electrode material layer therebetween as the third electrode; The third mask is removed.

15. The method for manufacturing a trench capacitor according to claim 12 or 14, characterized in that: The material of the third dielectric material layer is the same as that of the second dielectric layer.

16. The method for manufacturing a trench capacitor according to any one of claims 11 to 14, characterized in that: A single-layer planar capacitor composed of the second electrode, the second dielectric layer and the third electrode is also formed between the first region and the second region.

17. The method for manufacturing a trench capacitor according to any one of claims 5 or 11-14, characterized in that: The dielectric constants of the first dielectric layer and the second dielectric layer are greater than or equal to 3.

9.

18. The method for manufacturing a trench capacitor according to any one of claims 1 to 15, characterized in that: A dielectric barrier layer is also provided between the first to third metal wires and the insulating layer.

19. The method for manufacturing a trench capacitor according to any one of claims 1 to 15, characterized in that: The materials of the first electrode, the second electrode and the third electrode include one or any combination of titanium, titanium nitride, tantalum and tantalum nitride.

20. A trench capacitor, characterized in that: include: substrate; First to third metal wires are arranged in the same layer in the substrate; an insulating layer, covering the first to third metal wires and having a first trench formed in the insulating layer to expose the first metal wire; A double-layer capacitor is formed in the first trench and on the insulating layer around it, comprising a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode which are sequentially formed conformally, wherein the first electrode is electrically connected to the first metal line; A fourth metal line and a fifth metal line, wherein the fourth metal line electrically connects the second metal line and the second electrode, and the fifth metal line electrically connects the third metal line and the third electrode.

21. The trench capacitor according to claim 20, wherein: The trench capacitor further comprises: A third dielectric layer covers the double-layer capacitor, and a plurality of first through holes are formed in the third dielectric layer to expose the second electrode and the third electrode respectively; A plurality of second through holes are formed in the insulating layer to expose the second metal line and the third metal line respectively; The fourth metal wire electrically connects the second metal wire and the second electrode by using the first through hole and the second through hole, and the fifth metal wire electrically connects the third metal wire and the third electrode by using the first through hole and the second through hole.

22. The trench capacitor according to claim 20, wherein: A second groove is also formed in the insulating layer to expose the second metal line; The trench capacitor also includes: a single-layer capacitor formed in the second trench and on the insulating layer around it, including the second electrode, the second dielectric layer and the third electrode formed conformally in sequence, and the second electrode is electrically connected to the second metal line using the second trench.

23. The trench capacitor according to claim 22, wherein: A third through hole is also formed in the insulating layer to expose the third metal line; The fifth metal line covers the third through hole and the third electrode to electrically connect the third metal line and the third electrode.

24. The trench capacitor according to claim 22, wherein: A third groove is formed in the insulating layer to expose the third metal line; the third electrode is electrically connected to the third metal line by using the third groove; wherein the third electrode extending to the third groove forms the fifth metal line.

25. The trench capacitor according to claim 22, wherein: The trench capacitor further comprises: The single-layer planar capacitor is arranged on the insulating layer between the second metal wire and the first metal wire, and is composed of the second electrode, the second dielectric layer and the third electrode.

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