Imaging device and electronic apparatus

Abstract

Provided is an imaging device that makes it possible to acquire a high-definition image. An imaging device according to the present invention includes first to third transistors and a capacitor in a pixel circuit, and the first to third transistors are vertical transistors having channel formation regions provided following a side surface of an opening provided in an insulator, which makes it possible to reduce the occupied area. Furthermore, the first transistor and the third transistor have a region in which the first transistor and the third transistor overlap each other, and the second transistor has a region in which the second transistor and the capacitor overlap each other. Therefore, the layout area for the transistors and the capacitor can be reduced, which makes it possible to increase the pixel density.

Description

Imaging devices and electronic devices

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, memory devices, imaging devices, and driving methods thereof or manufacturing methods thereof.

[0003] Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are examples of a semiconductor device. In addition, a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device.

[0004] A technique for forming a transistor using an oxide semiconductor thin film formed over a substrate has attracted attention. For example, Patent Document 1 discloses an imaging device having a pixel circuit including a transistor that includes an oxide semiconductor and has extremely low off-state current.

[0005] JP 2011-119711 A

[0006] In imaging devices such as CMOS image sensors, pixel density is increasing due to demands for high-resolution image acquisition and miniaturization of image sensor chips. Further pixel density requires not only smaller design rules but also innovative transistor structures and 3D element arrangement.

[0007] Therefore, an object of one embodiment of the present invention is to provide an imaging device that can acquire a high-resolution image. Another object is to provide an imaging device having high-density pixels. Another object is to provide a small-sized imaging device. Another object is to provide an imaging device that can operate at high speed. Another object is to provide a highly reliable imaging device. Another object is to provide a novel imaging device or the like. Another object is to provide a novel semiconductor device or the like.

[0008] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc.

[0009] TECHNICAL FIELD One aspect of the present invention relates to an imaging device capable of acquiring a high-definition image.

[0010] One embodiment of the present invention is an imaging device including a first layer, a second layer, and a third layer, the second layer being provided between the first layer and the third layer, the first layer including a first transistor and a second transistor, the second layer including a third transistor and a capacitor, and the third layer including a fourth transistor and a photodiode, in which the first to third transistors each have a channel formation region in a metal oxide formed along a side surface of an opening provided in an insulator, the capacitor is a trench type, the fourth transistor has a channel formation region in a single crystal silicon substrate, and the photodiode has a photoelectric conversion region in the single crystal silicon substrate.

[0011] Preferably, the first transistor and the third transistor have overlapping regions, and the second transistor and the capacitor have overlapping regions.

[0012] Alternatively, it is preferable that the first transistor and the capacitor have an overlapping region, and the second transistor and the third transistor have an overlapping region.

[0013] The cathode of the photodiode can be electrically connected to one of the source or drain of the fourth transistor, the other of the source or drain of the fourth transistor can be electrically connected to the gate of the first transistor, one of the source or drain of the third transistor, and one electrode of the capacitor, and the one of the source or drain of the first transistor can be electrically connected to one of the source or drain of the second transistor.

[0014] The first to fourth transistors, the capacitor, and the photodiode can form a pixel circuit.

[0015] The fourth layer may have the first layer between it and the second layer, and the fourth layer may have a driving circuit and a readout circuit for the pixel circuit.

[0016] The fifth layer may include a fifth layer provided between the first layer and the second layer, the fifth layer may include a memory element, the memory element may include a fifth transistor and a sixth transistor, the fifth transistor and the sixth transistor may have overlapping regions, one of a source or a drain of the fifth transistor may be electrically connected to a gate of the sixth transistor, and the fifth transistor and the sixth transistor may each have a channel formation region in a metal oxide formed along a side surface of an opening provided in an insulator.

[0017] The sixth layer may have the first layer between it and the second layer, and the sixth layer may have readout circuitry for the memory element.

[0018] The metal oxide preferably comprises In, Zn, and M (wherein M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0019] An electronic device including the imaging device and a display portion is also one embodiment of the present invention.

[0020] By using one embodiment of the present invention, an imaging device capable of acquiring a high-resolution image can be provided. Alternatively, an imaging device having high-density pixels can be provided. Alternatively, a small-sized imaging device can be provided. Alternatively, an imaging device capable of high-speed operation can be provided. Alternatively, a highly reliable imaging device can be provided. Alternatively, a novel imaging device or the like can be provided. Alternatively, a novel semiconductor device or the like can be provided.

[0021] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0022] FIG. 1 is a perspective view illustrating a pixel circuit. FIGS. 2A to 2E are diagrams illustrating a vertical transistor. FIG. 2F is a diagram illustrating a capacitor. FIGS. 3A and 3B are circuit diagrams illustrating a pixel circuit. FIG. 4 is a diagram illustrating a pixel circuit. FIGS. 5A and 5B are diagrams illustrating a pixel circuit. FIGS. 6A and 6B are diagrams illustrating a pixel circuit. FIG. 7A is a block diagram illustrating an imaging device. FIG. 7B is a timing chart illustrating the operation of the pixel circuit. FIG. 7C is a diagram illustrating a readout circuit. FIGS. 8A and 8B are block diagrams illustrating an imaging device. FIG. 9 is a diagram illustrating an imaging device. FIGS. 10A to 10C are perspective views (cross-sectional views) illustrating pixels. FIGS. 11A and 11C are circuit diagrams illustrating memory cells. FIGS. 11B and 11D are diagrams illustrating memory cells. FIG. 12 is a timing chart illustrating the operation of a memory cell. FIG. 13 is a diagram illustrating an imaging device. FIG. 14 is a diagram illustrating a memory cell. FIG. 15A is a diagram illustrating a package containing an imaging device. Fig. 15B is a diagram illustrating a module that houses an imaging device. Figs. 16A to 16F are diagrams illustrating an electronic device. Figs. 17A and 17B are diagrams illustrating a moving object.

[0023] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications in form and detail may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be designated by the same reference numerals in different drawings, and repeated description thereof may be omitted. In addition, hatching of the same elements constituting the drawings may be omitted or changed as appropriate in different drawings.

[0024] Furthermore, even if a circuit diagram shows a single element, that element may be configured as multiple elements as long as there is no functional problem. For example, multiple transistors operating as switches may be connected in series or parallel. Also, a capacitor may be divided and placed in multiple locations.

[0025] Furthermore, a single conductor may have multiple functions such as wiring, an electrode, and a terminal, and in this specification, multiple names may be used for the same element. Also, even when elements are shown as being directly connected to each other on a circuit diagram, in reality, the elements may be connected via one or more conductors, and in this specification, such a configuration is also included in the category of direct connection.

[0026] Embodiment 1 In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0027] One embodiment of the present invention is an imaging device with high pixel density. The imaging device includes first to third layers in which elements constituting a pixel circuit are arranged. The first layer includes a first transistor and a second transistor, the second layer includes a third transistor and a capacitor, and the third layer includes a fourth transistor and a photodiode. The second layer is provided between the first and third layers.

[0028] The first to third transistors are vertical transistors having channel formation regions formed along side surfaces of openings in an insulator, thereby reducing the area occupied by the transistors. Furthermore, the first and third transistors have overlapping regions, and the second transistor has an overlapping region with a capacitor. Therefore, the layout area of ​​the transistors and the capacitor can be reduced, thereby increasing pixel density.

[0029] A fourth layer having a memory circuit can also be provided between the first layer and the second layer. The memory circuit has a plurality of memory elements, each of which includes a fifth transistor and a sixth transistor. The fifth and sixth transistors can also be formed as vertical transistors, allowing for a memory circuit with high storage capacity. Vertical transistors have a structure that makes it easy to shorten the channel length and widen the channel width, making it easy to increase the on-current. Therefore, a memory circuit with high speed data writing and high reliability data reading can be formed.

[0030] In this embodiment, for clarity of explanation, the imaging device is divided into multiple layers, but the type, quantity, and position of elements included in each layer are not limited to those described in this embodiment. For example, elements such as insulating layers, wiring, and plugs near the boundaries between layers may belong to layers different from those described in this embodiment. Furthermore, one layer described in this embodiment may be considered to be multiple layers. Furthermore, multiple layers described in this embodiment may be considered to be one layer.

[0031] 1 is a perspective view illustrating a pixel circuit of an imaging device according to one embodiment of the present invention. Elements of the pixel circuit can be provided in a layer 220a, a layer 220b, and a layer 230. The layer 220b is provided between the layer 220a and the layer 230.

[0032] The pixel circuit includes a transistor 103 , a transistor 104 , a transistor 105 , a transistor 106 , a capacitor 108 , and a photodiode 150 .

[0033] The layer 220a can be provided with the transistor 105 and the transistor 106. The layer 220b can be provided with the transistor 104 and the capacitor 108. The layer 230 can be provided with the transistor 103 and the photodiode 150. Note that in FIG. 1, for clarity, insulating layers are omitted and the external appearances of the transistor, the capacitor, and the photodiode are illustrated.

[0034] In a pixel circuit of an imaging device according to one embodiment of the present invention, transistors or a transistor and a capacitor are arranged so as to overlap with each other, whereby the area occupied by the pixel can be reduced, thereby increasing pixel density.

[0035] A pn junction photodiode having a photoelectric conversion region in a silicon substrate can be used as the photodiode 150. The transistor 103 and the photodiode 150 are provided on the same silicon substrate so that one of the source or drain of the transistor 103 and the photodiode 150 is directly connected to each other.

[0036] By directly connecting the photodiode 150 and the transistor 103, it is possible to minimize the number of elements provided between the photodiode 150 and the charge detection unit, thereby reducing noise when the charge generated by the photodiode 150 is transferred to the charge detection unit.

[0037] Here, vertical transistors that can be used for the transistors 104 to 106 and the capacitor 108 will be described.

[0038] A transistor used in one embodiment of the present invention is a transistor in which a semiconductor layer is provided along a side surface of an opening provided in an insulator, and the source electrode and the drain electrode are located at different heights, and a current flowing through the semiconductor layer flows in the height direction. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, such a transistor can be called a vertical transistor, a VFET (Vertical Field Effect Transistor), a vertical channel transistor, a vertical channel transistor, or the like.

[0039] In a vertical transistor, the source electrode, the semiconductor layer, and the drain electrode can be provided in an overlapping manner, and therefore the area occupied can be significantly reduced compared to a planar transistor in which the semiconductor layer is arranged on a plane.

[0040] Furthermore, the channel length of a vertical transistor can be controlled by adjusting the thickness of an insulating layer, etc. This allows for the realization of a transistor with an extremely short channel length, which in turn allows for the realization of a transistor with a small occupancy area and a large on-state current.

[0041] FIG. 2A is a plan view of a transistor 110 that can be used as the transistors 104 to 106. FIG. 2B is a cross-sectional view taken along dashed dotted lines A1-A2 in FIG. 2A. FIG. 2C is a cross-sectional view taken along dashed dotted lines A3-A4 in FIG. 2A. FIG. 2D is a cross-sectional view taken along dashed dotted lines A5-A6 in FIGS. 2B and 2C. Note that some elements are omitted in the plan view of FIG. 2A for clarity. Some elements may also be omitted in the subsequent plan views.

[0042] The transistor 110 includes a conductive layer 320 (conductive layer 320a, conductive layer 320b) on the insulating layer 310, an insulating layer 380 on the conductive layer 320, a conductive layer 340 (conductive layer 340a, conductive layer 340b) on the insulating layer 380, an oxide semiconductor layer 330, an insulating layer 350 on the oxide semiconductor layer 330, and a conductive layer 365 on the insulating layer 350.

[0043] In the transistor 110, the oxide semiconductor layer 330 functions as a semiconductor layer. The conductive layer 365 functions as a gate electrode. The insulating layer 350 functions as a gate insulating layer. The conductive layer 320 functions as one of a source electrode and a drain electrode, and the conductive layer 340 functions as the other of the source electrode and the drain electrode. The conductive layer 365 also functions as a gate wiring.

[0044] The oxide semiconductor layer 330 has a region overlapping with the conductive layer 365 with the insulating layer 350 interposed therebetween. At least part of the region functions as a channel formation region of the transistor 110. One of the region of the oxide semiconductor layer 330 in contact with the conductive layer 320 and the region of the oxide semiconductor layer 330 in contact with the conductive layer 340 functions as a source region and the other functions as a drain region.

[0045] As shown in FIGS. 2B and 2C, an opening 390 is provided in the insulating layer 380 and the conductive layer 340, reaching the conductive layer 320.

[0046] The conductive layer 320 has a conductive layer 320a and a conductive layer 320b on the conductive layer 320a, and a recess is provided in the conductive layer 320b.

[0047] The bottom of opening 390 includes the bottom surface of the recess in conductive layer 320b, and the sidewall of opening 390 includes the side surface of the recess in conductive layer 320b, the side surface of insulating layer 380, and the side surface of conductive layer 340. When the top surface shape of opening 390 is circular, the openings in each layer may or may not be concentric.

[0048] The oxide semiconductor layer 330 , the insulating layer 350 , and the conductive layer 365 , which are components of the transistor 110 , are arranged so that at least a portion of each is located within the opening 390 .

[0049] The oxide semiconductor layer 330 is in contact with the bottom and side surfaces of the recesses of the conductive layer 320b and the top and side surfaces of the conductive layer 340b. The recesses in the conductive layer 320b can increase the area over which the oxide semiconductor layer 330 is in contact with the conductive layer 320b. This can reduce the contact resistance between the oxide semiconductor layer 330 and the conductive layer 320b.

[0050] The conductive layer 320b is preferably formed using a conductive material containing oxygen, which can reduce contact resistance between the oxide semiconductor layer 330 and the conductive layer 320b.

[0051] When the conductive layer 320 and the conductive layer 340 each have a stacked structure, the contact resistance with the oxide semiconductor layer 330 can be reduced by using a conductive material containing oxygen for a layer in the stacked structure that has the largest contact area with the oxide semiconductor layer 330. Therefore, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 320b and the conductive layer 340b.

[0052] Alternatively, when the conductive layer 320 and the conductive layer 340 each have a stacked structure, the contact resistance with the oxide semiconductor layer 330 can be reduced by using a conductive material containing oxygen for a layer in the stacked structure that is closest to the channel formation region. In this structure, the resistance between the source and the drain can be reduced, and thus the on-state current of the transistor can be increased. Therefore, for example, a conductive material containing oxygen is preferably used for the conductive layer 320b and the conductive layer 340a. As the conductive material containing oxygen, a conductive metal oxide (also referred to as an oxide conductor) can be used.

[0053] The transistor 110 includes a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in the oxide semiconductor layer 330 including a channel formation region. Hereinafter, a transistor including an oxide semiconductor in a channel formation region is referred to as an OS transistor.

[0054] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics may be easily changed and the reliability may be deteriorated. In addition, hydrogen atoms near the oxygen vacancies may be converted into defects where hydrogen atoms are introduced into the oxygen vacancies (hereinafter referred to as V Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0055] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with the channel formation region, due to a high concentration of H or impurities such as hydrogen, nitrogen, or a metal element.

[0056] As described above, the oxide semiconductor layer 330 is provided inside the opening 390. In addition, the transistor 110 has a configuration in which one of the source electrode and the drain electrode (the conductive layer 320) is located on the lower side and the other of the source electrode and the drain electrode (the conductive layer 340) is located on the upper side, and thus current flows vertically. In other words, a channel is formed along the side surface of the opening 390.

[0057] The channel length of the transistor 110 can be considered as the distance between the source and drain regions, i.e., the channel length of the transistor 110 is determined by the thickness of the insulating layer 380 on the conductive layer 320.

[0058] Although the minimum dimension of the channel length of a planar transistor is the resolution limit of photolithography, the channel length of the transistor 110 can be set by the film thickness of the insulating layer 380. Therefore, the channel length of the transistor 105 can be made into an extremely fine structure that is equal to or less than the resolution limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 110, thereby improving frequency characteristics.

[0059] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 390. This allows the transistor 110 to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are provided in different regions on a plane. This allows the pixel density of the imaging device to be increased. Furthermore, when the transistor 110 is used as a memory element, a storage device with a large storage capacity per unit area can be obtained.

[0060] 2D , the oxide semiconductor layer 330, the insulating layer 350, and the conductive layer 365 are provided concentrically. In this case, for example, the channel width of the transistor 110 is determined by the periphery of the oxide semiconductor layer 330. That is, the channel width of the transistor 110 can be determined by the width of the opening 390 (or the diameter when the opening 390 is circular in a plan view). The width D of the opening 390 is shown in FIGS. 2B to 2E , and the channel width W of the transistor 110 is shown in FIG. 2D .

[0061] The channel length of the transistor 110 is preferably at least shorter than the channel width of the transistor 110. The channel length of the transistor 110 is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width of the transistor 110. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0062] Although the present embodiment illustrates an example in which the opening 390 is circular in plan view, the present invention is not limited thereto. In plan view, the opening 390 may be, for example, a circle, an approximately circular shape such as an oval, a polygonal shape such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or a polygonal shape with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees). As shown in FIG. 2A and other figures, the opening 390 is preferably circular in plan view. By using a circular shape, the processing precision during the formation of the opening can be improved, allowing for the formation of openings of minute sizes. In this specification and other figures, the term "circular" is not limited to a perfect circle.

[0063] 2E, the transistor 110 may include a conductive layer 355 and an insulating layer 335. The conductive layer 355 can be provided over an insulating layer 380a, and an insulating layer 380b can be provided over the conductive layer 355.

[0064] The opening 390 is provided to penetrate the conductive layer 355, and therefore, a side surface of the conductive layer 355 is exposed on a sidewall of the opening 390. Therefore, by providing the insulating layer 335, the oxide semiconductor layer 330, the insulating layer 350, and the conductive layer 365 in this order from the conductive layer 355 side in the opening 390, the conductive layer 355 can function as a second gate electrode and the insulating layer 335 can function as a second gate insulating layer. In addition, the conductive layer 365 can function as a first gate electrode and the insulating layer 350 can function as a first gate insulating layer.

[0065] One of the first gate electrode and the second gate electrode can function as a back gate. Supplying a constant potential to the back gate facilitates control of the threshold voltage. Furthermore, fluctuations in the threshold voltage can be suppressed, thereby improving the electrical characteristics and reliability of the transistor.

[0066] 2F illustrates a capacitor 111 that can be used as the capacitor 108. The capacitor 111 is a trench type and can be formed by, for example, replacing the oxide semiconductor layer 330 of the transistor 110 with a conductive layer 356.

[0067] The configuration of the capacitor 111 shown in FIG. 2F is an example, in which the conductive layer 365 can function as one electrode, the insulating layer 350 can function as a dielectric layer, the conductive layer 356 can function as the other electrode, and the conductive layer 340 a and the conductive layer 320 can function as wirings connecting to the other electrode.

[0068] Note that Figure 2F illustrates a structure in which the conductive layer 340b is not provided in order to reduce the contact resistance between the conductive layer 356 and the conductive layer 340a; however, in order to reduce the number of steps, a structure in which the conductive layer 340b is provided over the conductive layer 340a using the same manufacturing process as the transistor 110 may be used.

[0069] 3A is a circuit diagram of the pixel circuit shown in Fig. 1. One electrode (cathode) of the photodiode 150 is electrically connected to one of the source or drain of the transistor 103. The other of the source or drain of the transistor 103 is electrically connected to one of the source or drain of the transistor 104, one electrode of the capacitor 108, and the gate of the transistor 105. One of the source or drain of the transistor 105 is electrically connected to one of the source or drain of the transistor 106.

[0070] Here, a wiring that connects the other of the source and the drain of the transistor 103, one electrode of the capacitor 108, and the gate of the transistor 105 is referred to as a node FD. The node FD can function as a charge detection portion.

[0071] The other electrode (anode) of the photodiode 150 is electrically connected to a wiring 121 (not shown in FIG. 1 ). The gate of the transistor 103 is electrically connected to a wiring 127. The other of the source and the drain of the transistor 104 is electrically connected to a wiring 122. The other of the source and the drain of the transistor 105 is electrically connected to a wiring 123. The gate of the transistor 104 is electrically connected to a wiring 126. The gate of the transistor 106 is electrically connected to a wiring 128. The other electrode of the capacitor 108 is electrically connected to a fixed potential line (not shown in FIG. 1 ), such as a GND wiring. The other of the source and the drain of the transistor 106 is electrically connected to a wiring 129.

[0072] The wirings 127, 126, and 128 can function as signal lines that control the conduction of each transistor. The wiring 129 can function as an output line.

[0073] 3A, the cathode side of the photodiode 150 is electrically connected to the transistor 103, and the node FD is reset to a high potential to operate;

[0074] Note that although FIG. 3A shows a configuration in which the cathode of the photodiode 150 is electrically connected to one of the source and drain of the transistor 103, as shown in FIG. 3B , a configuration in which the anode of the photodiode 150 is electrically connected to one of the source and drain of the transistor 103 may also be used.

[0075] In the configuration illustrated in FIG. 3B, the node FD is reset to a low potential for operation, and therefore the wiring 122 is set to a low potential (a potential lower than that of the wiring 121).

[0076] The transistor 103 has a function of writing a signal potential obtained by the photodiode 150 to the node FD. The transistor 104 has a function of resetting the potential of the node FD. The transistor 105 functions as an element of a source follower circuit and can output the potential of the node FD as image data to the wiring 129. The transistor 106 has a function of selecting a pixel from which image data is output.

[0077] The transistors 104 to 106 included in the pixel circuit are preferably OS transistors having an oxide semiconductor in a channel formation region. OS transistors can be formed using thin films, which makes stacking easy. Furthermore, OS transistors have higher mobility than transistors using amorphous silicon, do not require a crystallization process required for manufacturing polycrystalline silicon (LTPS) transistors, and have excellent uniformity in electrical characteristics.

[0078] 4 is a cross-sectional view showing details of the connection configuration between elements in the pixel circuit shown in Fig. 1. The transistor 103 and the photodiode 150 provided in the layer 230 are fabricated separately and then connected to the elements of the layer 220b by a bonding process. The layer 230 and the elements necessary for bonding will be described later and will not be described here.

[0079] In the layer 220a, the transistor 105 and the transistor 106 are electrically connected to each other by sharing a conductive layer 320A that corresponds to the conductive layer 320 shown in Figures 2B and 2C. This connection is the electrical connection between one of the source or drain of the transistor 105 and one of the source or drain of the transistor 106 in the circuit diagram of Figure 3A.

[0080] 2B and 2C can be considered to be part of the wiring 123 and serves as the other of the source and drain electrodes. In the transistor 106, the conductive layer corresponding to the conductive layer 340 shown in FIGS. 2B and 2C can be considered to be part of the wiring 129 and serves as the other of the source and drain electrodes.

[0081] 2B and 2C , the transistor 104 and the capacitor 108 are electrically connected to each other by sharing a conductive layer 320B that corresponds to the conductive layer 320 shown in FIGS. 2B and 2C . The conductive layer 320B is electrically connected to the gate electrode (conductive layer 365A) of the transistor 105 through a conductive layer 115 disposed near the boundary between the layers 220a and 220b. A conductive layer 356 that is one electrode of the capacitor 108 is electrically connected to the other of the source and drain of the transistor 103.

[0082] 3A, this connection is an electrical connection between the other of the source and the drain of the transistor 103, one of the source and the drain of the transistor 104, the gate of the transistor 105, and one electrode of the capacitor 108. Also, a wiring or the like related to this connection corresponds to the node FD.

[0083] 2B and 2C can be considered to be part of the wiring 122 and serves as the other of the source and drain electrodes. Also, a conductive layer corresponding to the conductive layer 365 shown in FIGS. 2B and 2C can be considered to be part of the wiring 126 and serves as a gate electrode.

[0084] In the capacitor 108, the conductive layer 365B corresponding to the conductive layer 365 shown in FIG. 2F can be said to be a part of the fixed potential line, and acts as the other electrode.

[0085] In this manner, the transistor 105 and the transistor 106 are provided in the layer 220a, and the transistor 104 and the capacitor 108 are provided in the layer 220b. By providing an area where the transistor 105 and the transistor 104 overlap with each other and an area where the transistor 106 and the capacitor 108 overlap with each other, the area occupied by the pixel circuit can be reduced.

[0086] Furthermore, by using a vertical transistor in which the source region and the drain region are located at different heights, and a trench capacitor, the conductive layers 365A, 115, 320B, and 356, which are components of the node FD, can be easily connected. Furthermore, the conductive layer 356, which is one electrode of the capacitor 108, can be led out to an upper portion of the layer 220b, and therefore can be easily electrically connected to the transistor 103.

[0087] 5A , in the layer 220a, in the transistor 105, a conductive layer corresponding to the conductive layer 320 shown in FIGS. 2B and 2C may be part of the wiring 123. In the transistor 106, a conductive layer corresponding to the conductive layer 320 shown in FIGS. 2B and 2C may be part of the wiring 129. In this case, the transistors 105 and 106 are electrically connected to each other by sharing a conductive layer 340A corresponding to the conductive layer 340 shown in FIGS. 2B and 2C.

[0088] 4 illustrates a configuration in which the transistor 105 and the transistor 104 overlap with each other and the transistor 106 and the capacitor 108 overlap with each other, but the present invention is not limited to this. For example, as illustrated in FIG. 5B , the transistor 105 and the capacitor 108 may overlap with each other and the transistor 106 and the transistor 104 may overlap with each other.

[0089] 3A, when the capacitance of the node FD excluding the capacitor 108 is sufficiently large, the capacitor 108 can be omitted. In this case, as shown in FIG. 6A, a conductive layer 357 electrically connected to the conductive layer 320B may be provided instead of the capacitor 108.

[0090] Although the transistor 103 has been illustrated as being directly connected to the photodiode 150, the transistor 103 may be formed as a vertical OS transistor similar to other transistors, as shown in FIG. 6B . In this case, the OS transistor with low off-state current can suppress unnecessary charge flow between the node FD and the photodiode 150, thereby enabling charge to be held in the node FD for a long period of time. Therefore, a global shutter method in which data is simultaneously acquired from all pixels and sequentially read out can be easily applied.

[0091] Furthermore, in the configuration shown in FIG. 6B , since it is not necessary to use the same semiconductor layer for the transistor 103 and the photodiode 150, the material of the photodiode 150 is not limited. Therefore, for example, a pn junction photodiode with a selenium-based material as a photoelectric conversion layer may be used for the photodiode 150. Photoelectric conversion devices using selenium-based materials have the characteristic of high external quantum efficiency for visible light. In such photoelectric conversion devices, avalanche multiplication can be used to increase the amplification of electrons relative to the amount of incident light. Furthermore, selenium-based materials have a high optical absorption coefficient, which offers productivity advantages, such as the ability to fabricate a thin-film photoelectric conversion layer.

[0092] Selenium-based materials include crystalline selenium (single crystal selenium, polycrystalline selenium) and amorphous selenium, which are photosensitive to ultraviolet light and visible light. Also usable are compounds of copper, indium, and selenium (CIS) and compounds of copper, indium, gallium, and selenium (CIGS).

[0093] Alternatively, a compound semiconductor may be used as the photoelectric conversion layer of a pn junction photodiode, such as a gallium-arsenic-phosphorus compound (GaAsP), a gallium-phosphorus compound (GaP), an indium-gallium-arsenic compound (InGaAs), a lead-sulfur compound (PbS), a lead-selenium compound (PbSe), an indium-arsenic compound (InAs), an indium-antimony compound (InSb), or a mercury-cadmium-tellurium compound (HgCdTe).

[0094] 7A is a block diagram illustrating an imaging device. The imaging device includes a pixel array 20 having a plurality of pixels 10 arranged in a matrix, a drive circuit 30 that controls the imaging operation of the pixels, and a readout circuit 40.

[0095] The drive circuit 30 has a decoder circuit or a shift register circuit, etc., and can supply signals for performing reset operations, accumulation operations, readout operations, etc. to the pixels 10. The readout circuit 40 has a decoder circuit or a shift register circuit, a CDS circuit (correlated double sampling circuit), an A / D converter circuit, etc. The readout circuit 40 can remove noise and digitally convert analog data read out from the selected pixels 10 to wiring 129, and output the data to the outside via wiring 130.

[0096] Next, an example of the operation of the pixel circuit shown in Fig. 3A will be described with reference to the timing chart of Fig. 7B. Note that all the transistors shown in Fig. 3A are n-channel transistors, and a high potential that is applied to the gate of a transistor to turn it on is represented by "H," and a low potential that is applied to the gate of a transistor to turn it off is represented by "L." It is also assumed that a low potential is always supplied to the wiring 121, and high potentials are always supplied to the wirings 122 and 123.

[0097] In the period T1, when the potential of the wiring 126 is set to “H”, the potential of the wiring 127 is set to “H”, and the potential of the wiring 128 is set to “L”, the transistors 103 and 104 are turned on, and the potential of the wiring 122 is supplied to the node FD (reset operation).

[0098] In the period T2, when the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "H", and the potential of the wiring 128 is set to "L", the transistor 104 is turned off and the supply of the reset potential is cut off. Furthermore, the potential of the node FD decreases in response to the operation of the photodiode 150 (storage operation).

[0099] In the period T3, when the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "L", and the potential of the wiring 128 is set to "L", the transistor 103 is turned off, and the potential of the node FD is determined and held (holding operation). At this time, by using an OS transistor with low off-state current as the transistor connected to the node FD, unnecessary charge outflow from or inflow to the node FD can be suppressed, and the data holding time can be extended.

[0100] In the period T4, when the potential of the wiring 126 is set to “L”, the potential of the wiring 127 is set to “L”, and the potential of the wiring 128 is set to “H”, the transistor 106 is turned on, and the potential of the node FD is read to the wiring 129 by the source follower operation of the transistor 105 (read operation).

[0101] The above is an example of the operation of the pixel circuit shown in FIG. 3A.

[0102] 7C is a diagram illustrating a part of the readout circuit 40 connected to the wiring 129, and shows a circuit diagram of the CDS circuit 400 and a block diagram of an A / D converter 410 electrically connected to the CDS circuit 400. Note that the CDS circuit shown in FIG. 7C is an example, and other configurations may be used.

[0103] The CDS circuit 400 includes a voltage conversion transistor 401, a capacitive coupling capacitor 402, and a potential V ０ The CDS circuit 400 may have a configuration including a transistor 403 that supplies a potential to the A / D converter 410, a transistor 404 that holds a potential to be supplied to the A / D converter 410, and a capacitor 405 for holding the potential. The CDS circuit 400 has an input electrically connected to the pixel 10 and an output electrically connected to the A / D converter 410.

[0104] The potential of the wiring 129 is V ｒｅｓ When the pixel 10 is in a reset state, the potential of the node N (the connection point between the transistors 403 and 404 and the capacitor 402) is V ０ Then, the node N is set to a floating state, and the potential of the wiring 129 is set to V ｄａｔａ When the pixel 10 outputs image data, the potential of the node N becomes V ０ +V ｄａｔａ -Vｒｅｓ Therefore, in the CDS circuit 400, the potential in the reset state can be subtracted from the potential of the imaging data output by the pixel 10, and the noise component can be reduced.

[0105] The A / D converter 410 can be configured to include a comparator circuit and a counter circuit. In the A / D converter 410, the signal potential input to the comparator circuit from the CDS circuit 400 is compared with a swept reference potential. The counter circuit operates in response to the output of the comparator circuit, and can output digital signals to the multiple wirings 130. Alternatively, a high-speed flash A / D converter can be used for the A / D converter 410.

[0106] The elements of the drive circuit 30 and the readout circuit 40 are preferably formed using high-speed, low-power CMOS circuits. The CMOS circuits are preferably formed using transistors having silicon in their channel formation regions (hereinafter referred to as Si transistors). The Si transistors can be formed using, for example, a single-crystal silicon substrate. Alternatively, they can be formed using a single-crystal silicon layer epitaxially grown on the single-crystal silicon substrate.

[0107] The transistors that are elements of the pixel circuit can be formed using OS transistors, and can be provided over the single-crystal silicon substrate on which the above-described Si transistors are provided.

[0108] For example, the imaging device of one embodiment of the present invention can have a stacked structure as shown in Fig. 8A and Fig. 8B . Note that the stacked structure shown in Fig. 8A and Fig. 8B is just an example, and other layers such as a wiring layer may be provided.

[0109] 8A shows a configuration in which the pixel circuit (a stack of layers 220a, 220b, and 230) illustrated in FIG. 1 and other figures is provided on layer 210, and layer 250 is provided on layer 230. Here, layer 210 is a layer having drive circuit 30 and readout circuit 40 formed of Si transistors or the like as described above, and is, for example, a layer including a single-crystal silicon substrate. Layer 250 is a layer having color filters, a microlens array, and the like. Note that layer 208 shown near the boundary between layer 220b and layer 230 represents a bonding layer.

[0110] The details of the laminated structure shown in FIG. 8A will be described with reference to the cross-sectional view of FIG.

[0111] <Layer 210> The layer 210 can have a readout circuit 40 and a driver circuit 30 provided in a layer 511 having a silicon substrate. Here, as part of the circuits, a capacitor 402 and a transistor 403 included in the CDS circuit of the readout circuit 40, and transistors 451 and 452 which are elements of the readout circuit 40 or the driver circuit 30 are shown. One electrode of the capacitor 402 and one of the source or drain of the transistor 403 are electrically connected. The transistors 403, 451, and 452 are Si transistors.

[0112] The layer 210 is provided with insulating layers 512, 513, 514, 515, 516, 517, and 518. The insulating layer 512 functions as a protective film. The insulating layers 513, 514, 515, and 517 function as interlayer insulating films and planarizing films. The insulating layer 516 functions as a dielectric layer of the capacitor 402. The insulating layer 518 functions as a blocking film.

[0113] The protective film may be, for example, a silicon nitride film, a silicon oxide film, or an aluminum oxide film. The interlayer insulating film and the planarizing film may be, for example, an inorganic insulating film such as a silicon oxide film, or an organic insulating film such as an acrylic resin or a polyimide resin. The dielectric layer of the capacitor may be, for example, a silicon nitride film, a silicon oxide film, or an aluminum oxide film. The blocking film is preferably a film that has the function of preventing hydrogen diffusion.

[0114] In Si devices, hydrogen is required to terminate dangling bonds, but hydrogen near an OS transistor can generate carriers in the oxide semiconductor layer, reducing reliability. Therefore, a hydrogen blocking film is preferably provided between the layer where the Si device is formed and the layer where the OS transistor is formed.

[0115] The blocking film may be made of, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like.

[0116] The Si transistor shown in FIG. 9 is a fin type having a channel forming region in the layer 511, but may be a planar type.

[0117] Conductors that can be used as wiring, electrodes, and plugs for electrical connection between devices may be made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements, etc. The conductor is not limited to a single layer, and may also be made of multiple layers composed of different materials.

[0118] <Layer 220a, Layer 220b> The layer 220a is formed on the layer 210, and the layer 220b is formed on the layer 220a. For details of the transistors, capacitors, and the like in the layers 220a and 220b, refer to the description of FIG.

[0119] The transistor 106 provided in the layer 220a functions as a read transistor, and therefore one of the source region or the drain region is electrically connected to the transistor 105, and the other of the source region or the drain region is electrically connected to the other electrode of the capacitor 402 of the CDS circuit provided in the layer 210 via the wiring 129.

[0120] The layer 220b includes conductive layers 531a and 531b and an insulating layer 529a as components of the layer 208. The conductive layer 531a is electrically connected to one electrode of the capacitor 108, and the conductive layer 531b is electrically connected to the wiring 121 that functions as a power supply line. The bonding layer (layer 208) will be described in detail later.

[0121] <Layer 230 > The layer 230 includes the photodiode 150 , the transistor 103 , and insulating layers 541 , 542 , 545 , and 546 .

[0122] The photodiode 150 is a pn junction type photodiode formed on a silicon substrate, and has a p-type region 543 and an n-type region 544. The photodiode 150 is a buried type photodiode, and the thin p-type region 543 provided on the surface side (current extraction side) of the n-type region 544 can suppress dark current and reduce noise.

[0123] The insulating layer 541 functions as a blocking layer. The insulating layer 542 functions as an element isolation layer. The insulating layer 545 functions to suppress the outflow of carriers. The insulating layer 546 functions as an interlayer film.

[0124] Grooves that separate pixels are provided in the silicon substrate, and an insulating layer 545 is provided on the surface of the silicon substrate and in the grooves. The insulating layer 545 can prevent carriers generated in the photodiode 150 from flowing into adjacent pixels. The insulating layer 545 also has the function of preventing stray light from entering. Therefore, the insulating layer 545 can prevent color mixing. An anti-reflection film may be provided between the upper surface of the silicon substrate and the insulating layer 545.

[0125] The element isolation layer can be formed using a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or the like. For example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as polyimide resin or acrylic resin can be used as the insulating layer 545. The insulating layer 545 may have a multi-layer structure.

[0126] The transistor 103 has a channel formation region in the silicon substrate on which the photodiode 150 is provided. An n-type region 544 (corresponding to a cathode) of the photodiode 150 serves as one of the source and drain of the transistor 103, and the other of the source and drain of the transistor 103 is electrically connected to one electrode of the capacitor 108 in the layer 220b through conductive layers 531b and 531a. A p-type region 543 (anode) is electrically connected to the wiring 121 in the layer 220b that functions as a power supply line through conductive layers 532b and 532a.

[0127] The layer 230 includes conductive layers 531b and 531b and an insulating layer 529b as components of the layer 208. The conductive layer 531a is electrically connected to one electrode of the capacitor 108, and the conductive layer 531b is electrically connected to the wiring 121 having a function as a power supply line.

[0128] <Layer 250> The layer 250 is formed on the layer 230. The layer 250 has a light-shielding layer 551, an optical conversion layer 550, and a microlens array 555.

[0129] The light-shielding layer 551 can prevent light from flowing into adjacent pixels. A metal layer such as aluminum or tungsten can be used for the light-shielding layer 551. The metal layer may be stacked with a dielectric film that functions as an anti-reflection film.

[0130] When the photodiode 150 is sensitive to visible light, a color filter can be used in the optical conversion layer 550. A color image can be obtained by assigning color filters of colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to each pixel. For example, as shown in the perspective view (including cross section) of FIG. 10A , a color filter 550R (red), a color filter 550G (green), and a color filter 550B (blue) can be assigned to each pixel.

[0131] Furthermore, when a wavelength cut filter is used in the optical conversion layer 550 in a suitable combination of the photodiode 150 and the optical conversion layer 550, an imaging device can be obtained that can obtain images in various wavelength regions.

[0132] For example, if an infrared filter that blocks light with wavelengths shorter than visible light is used in the optical conversion layer 550, an infrared imaging device can be formed. Also, if a filter that blocks light with wavelengths shorter than near-infrared light is used in the optical conversion layer 550, a far-infrared imaging device can be formed. Also, if an ultraviolet filter that blocks light with wavelengths longer than visible light is used in the optical conversion layer 550, an ultraviolet imaging device can be formed.

[0133] It is also possible to arrange multiple different optical conversion layers within a single imaging device. For example, as shown in FIG. 10B , a color filter 550R (red), a color filter 550G (green), a color filter 550B (blue), and an infrared filter 550IR can be assigned to different pixels. With this configuration, visible light images and infrared light images can be acquired simultaneously.

[0134] 10C, color filter 550R (red), color filter 550G (green), color filter 550B (blue), and ultraviolet filter 550UV can be assigned to different pixels, respectively. In this configuration, visible light images and ultraviolet light images can be acquired simultaneously.

[0135] Furthermore, if a scintillator is used for the optical conversion layer 550, an imaging device can be used for X-ray imaging devices and the like to obtain images that visualize the intensity of radiation. When radiation such as X-rays that has passed through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is obtained by detecting this light with the photodiode 150. An imaging device having this configuration may also be used for a radiation detector or the like.

[0136] A scintillator contains a substance that absorbs the energy of radiation such as X-rays or gamma rays and emits visible or ultraviolet light when irradiated with the radiation. For example, Gd ２ O ２ S: Tb, Gd ２ O ２ S: Pr, Gd ２ O ２ S: Eu, BaFCl: Eu, NaI, CsI, CaF ２ , BaF ２ , CeF ３ , LiF, LiI, ZnO, etc. dispersed in resin or ceramics can be used.

[0137] Imaging using infrared or ultraviolet light can provide the imaging device with inspection functions, security functions, sensor functions, etc. For example, imaging using infrared light can be used for non-destructive testing of produce, sorting of agricultural products (such as a sugar content meter function), vein authentication, medical testing, etc. Furthermore, imaging using ultraviolet light can detect ultraviolet light emitted from a light source or flame, allowing for management of light sources, heat sources, production equipment, etc.

[0138] A microlens array 555 is provided on the optical conversion layer 550. Light passing through each lens of the microlens array 555 passes through the optical conversion layer 550 directly below and is irradiated onto the photodiode 150. By providing the microlens array 555, concentrated light can be incident on the photodiode 150, thereby enabling efficient photoelectric conversion. The microlens array 555 is preferably formed from a resin or glass that is highly translucent to light of the target wavelength.

[0139] <Bonding> Next, bonding of the layer 220b and the layer 230 using the bonding layer (layer 208) will be described.

[0140] The layer 220b includes an insulating layer 529a and conductive layers 531a and 531b. The conductive layers 531a and 531b have regions buried in the insulating layer 529a. The surfaces of the insulating layer 529a and the conductive layers 531a and 531b are flattened so that they are at the same height.

[0141] The layer 230 includes an insulating layer 529b and conductive layers 532a and 532b. The conductive layers 532a and 532b have regions buried in the insulating layer 529b. The surfaces of the insulating layer 529b and the conductive layers 532a and 532b are planarized so that they are at the same height.

[0142] Here, the conductive layers 531a and 531b and the conductive layers 532a and 532b preferably contain the same metal element as a main component, and the insulating layers 529a and 529b preferably contain the same component as a main component.

[0143] For example, the conductive layers 531a, 531b and the conductive layers 532a, 532b can be made of Cu, Al, Sn, Zn, W, Ag, Pt, or Au. Cu, Al, W, or Au is preferred because of ease of bonding. The insulating layers 529a, 529b can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, or the like.

[0144] That is, the conductive layers 531a and 531b and the conductive layers 532a and 532b are preferably made of the same metal material as described above. The insulating layers 529a and 529b are preferably made of the same insulating material as described above. This structure allows bonding of the layer 220b and the layer 230 at the boundary between them.

[0145] The conductive layers 531a, 531b and the conductive layers 532a, 532b may have a multilayer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same metal material. The insulating layers 529a and 529b may also have a multilayer structure with multiple layers, in which case the surface layers (joint surfaces) may be made of the same insulating material.

[0146] By this bonding, electrical connection between the conductive layer 531a and the conductive layer 532a and electrical connection between the conductive layer 531b and the conductive layer 532b can be obtained, and a connection having sufficient mechanical strength between the insulating layer 529a and the insulating layer 529b can be obtained.

[0147] To bond metal layers together, surface activated bonding can be used, in which oxide films and impurity adsorption layers on the surfaces are removed by sputtering or other methods, and the cleaned and activated surfaces are then brought into contact and bonded. Alternatively, diffusion bonding can be used, in which surfaces are bonded using a combination of temperature and pressure. Both methods create bonds at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0148] Furthermore, to bond insulating layers together, a hydrophilic bonding method can be used, in which high flatness is achieved by polishing or other methods, then surfaces that have been hydrophilically treated with oxygen plasma or other methods are brought into contact with each other to form a temporary bond, and the final bond is then achieved by dehydrating them through heat treatment.Hydrophilic bonding also creates bonds at the atomic level, so it is possible to obtain mechanically excellent bonds.

[0149] When the insulating layer 529a and the insulating layer 529b are bonded to each other, an insulating layer and a metal layer are mixed on the bonding surfaces, and therefore, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0150] For example, a method can be used in which the surface is polished, cleaned, the surface of the metal layer is subjected to an anti-oxidation treatment, and then a hydrophilic treatment is performed before bonding. Alternatively, the surface of the metal layer may be made of a resistant metal such as Au and then subjected to a hydrophilic treatment. Note that bonding methods other than those described above may also be used.

[0151] 8B shows a structure in which a layer 240 having a memory circuit is added to the structure in FIG. 8A. The layer 240 can be provided between the layer 210 and the layer 220a.

[0152] The memory circuit included in the layer 240 can temporarily store imaging data acquired by the pixel circuit. By providing a memory circuit for storing imaging data, imaging operations and A / D conversion operations can be processed in parallel, and digital image data can be acquired at high speed.

[0153] The memory circuit is preferably formed of a memory element that has a high degree of integration and can have a large storage capacity in order to store a huge amount of image data.

[0154] 11A illustrates an example of a circuit diagram of a memory cell 650 including a memory element that can be used in the memory circuit. The transistor 610 has a function of reading data. The transistor 620 has a function of writing data.

[0155] 11B is a cross-sectional view showing a connection configuration of a transistor 610 and a transistor 620 that constitute a memory element. The basic structure of the transistor 610 and the transistor 620 can be the structure of the transistor 110 shown in FIGS. 2A to 2D. Although not shown here, the transistor 610 and the transistor 620 can also have a back gate as shown in FIG. 2E.

[0156] One of the source and the drain of the transistor 620 is connected to the gate of the transistor 610. The gate of the transistor 610 can also be said to be a component of the node SN that holds the data potential in the memory cell 650 shown in FIG.

[0157] In this way, two vertical transistors each having a small occupying area can be arranged in a stacked manner, which allows for high integration and increases the memory capacity.

[0158] The wiring 632 connected to the gate of the transistor 620 is a wiring that supplies a write word signal to the memory cell 650 and is also referred to as a write word line (WWL). The write word signal is a signal that controls the timing of writing data to the memory cell 650.

[0159] The wiring 641 connected to the other of the source and the drain of the transistor 620 is a wiring that applies a potential corresponding to a data signal (data) to the memory cell 650, and is also called a write bit line (WBL). The data signal is a high level ("1" or V Ｈ ) or low level ("0" or V Ｌ It is a signal expressed as a binary value (also called a sine wave).

[0160] The wiring 631 connected to one of the source and the drain of the transistor 610 is a wiring that supplies a read word signal to the memory cell 650 and is also referred to as a read word line (RWL). The read word signal is a signal that controls the timing of reading data from the memory cell 650.

[0161] The wiring 642 connected to the other of the source and the drain of the transistor 610 is a wiring for reading out a potential corresponding to a data signal (data) held in the memory cell 650, and is also referred to as a read bit line (RBL). A current flows through the transistor 610 according to the data ("1" or "0") written to the memory cell 650, changing the potential of the precharged wiring 642. The potential can be input to a sense amplifier, thereby reading out the data.

[0162] In the transistor 610, the lower conductive layer (hereinafter, conductive layer A) functioning as one of the source and drain is the wiring 631 (RWL), and the upper conductive layer (hereinafter, conductive layer B) functioning as the other of the source and drain is the wiring 642 (RBL). However, the conductive layer A can also be the wiring 642 (RBL), and the conductive layer B can also be the wiring 631 (RWL).

[0163] However, the conductive layer B is physically close to the gate of the transistor 610, which is an element of the node SN, and the parasitic capacitance generated between the conductive layer B and the node SN is larger than the parasitic capacitance generated between the conductive layer A and the node SN. Therefore, the potential of the node SN is more susceptible to potential fluctuations in the conductive layer B than to potential fluctuations in the conductive layer A. Therefore, it is preferable to use the conductive layer A as a wiring to which a signal with a large amplitude is input. That is, as shown in FIG. 11B, it is preferable to use the conductive layer A as the wiring 631 (RWL) and the conductive layer B as the wiring 642 (RBL). The operation of the memory cell 650 will be described later.

[0164] 11C , the memory cell 650 may include a capacitor 660. By providing the capacitor 660, the capacitance of the node SN can be increased, and the potential fluctuation of the node SN due to parasitic capacitance can be reduced. One electrode of the capacitor 660 is electrically connected to one of the source and drain of the transistor 620 and the gate of the transistor 610. One electrode of the capacitor 660 is electrically connected to a fixed potential line such as a low-potential power line.

[0165] 11D , the capacitor 660 can be provided between the transistor 610 and the transistor 620. The capacitor 660 has a metal-insulator-metal (MIM) structure, and includes an insulating layer 663, which is a dielectric layer, between a conductive layer 661, which is one electrode, and a conductive layer 662, which is the other electrode. The conductive layer 661 also functions as a connection electrode that connects the gate of the transistor 610 and the source or drain of the transistor 620.

[0166] Next, the operation of memory cell 650 will be described. Here, an ideal operation in which the influence of each parasitic capacitance is eliminated will be described. Figure 12 is a timing chart for explaining an example of the operation of memory cell 650 shown in Figure 11A.

[0167] 12 shows potentials applied to the wiring 632 (WWL), the wiring 641 (WBL), and the wiring 631 (RWL), a potential read out to the wiring 642 (RBL), and a potential of the node SN. Note that in FIG. 12, the standby state of the wiring 641 (WBL) is set to a low level (V Ｌ )

[0168] The period T1 is a standby period. The period T2 is a write period. The period T3 is a standby period. The periods T4 and T5 are read periods. The period T6 is a standby period. Note that FIG. 12 illustrates data "1" or "0" written to the memory cell 650 (node ​​SN) via the wiring 641 (WBL). The data written to the memory cell 650 is data "1" when it is at a high level and data "0" when it is at a low level.

[0169] 12 illustrates data "1" or "0" read from the memory cell 650 via the wiring 642 (RBL). The wiring 642 (RBL) is precharged to a high-level potential (for example, a high power supply potential such as VDD) during a read period, and data is read to an external read circuit connected to the wiring 642 (RBL) according to a change in the precharged potential.

[0170] When the data stored in the memory cell 650 (node ​​SN) is data "1", the current flowing through the transistor 610 is large, and therefore the potential of the wiring 642 (RBL) decreases. When the data stored in the memory cell 650 (node ​​SN) is data "0", the current flowing through the transistor 610 is small, and therefore the fluctuation in the potential of the wiring 642 (RBL) is small. In other words, when the data stored in the memory cell 650 (node ​​SN) is data "1", the potential of the wiring 642 (RBL) becomes low. On the other hand, when the data stored in the memory cell 650 (node ​​SN) is data "0", the potential of the wiring 642 (RBL) becomes high (precharged potential).

[0171] In the period T1, the wiring 632 (WWL) is at a low level, and the wiring 641 (WBL) is at a low level (V Ｌ ), the wiring 631 (RWL) is at a high level, and the wiring 642 (RBL) is at a high level. At this time, the transistor 620 is in a non-conducting state. Furthermore, the transistor 610 has the same potential between the source and drain terminals, so no current flows. Note that the potential of the gate (node ​​SN) of the transistor 610 is the potential V written in the previous writing period. Ｈ or V Ｌ is.

[0172] In the period T2, the wiring 632 (WWL) is at a high level, and the wiring 641 (WBL) is at a signal (V Ｈ or V Ｌ ), the wiring 631 (RWL) is at a high level, and the wiring 642 (RBL) is at a high level. At this time, the transistor 620 is turned on, and the potential of the gate (node ​​SN) of the transistor 610 becomes a potential corresponding to the data. Since the source and drain terminals of the transistor 610 have the same potential, no current flows regardless of the gate potential.

[0173] In the period T3, the wiring 632 (WWL) is at a low level, and the wiring 641 (WBL) is at a low level (V Ｌ), the wiring 631 (RWL) is at a high level, and the wiring 642 (RBL) is at a high level. At this time, both the transistors 610 and 620 are off. In the period T3, the potential written to the gate (node ​​SN) of the transistor 610 is held. Since the source and drain terminals of the transistor 610 have the same potential, no current flows regardless of the gate potential.

[0174] In the period T4, the wiring 632 (WWL) is at a low level, and the wiring 641 (WBL) is at a low level (V Ｌ ), the wiring 631 (RWL) is at a high level. The wiring 642 (RBL) is at a high level (precharge potential V ＰＲＥ At this time, the transistor 620 is in a non-conductive state. ＰＲＥ is, for example, VDD, which is at the same potential as the high level of the wiring 642 (RBL). Since the source and drain terminals of the transistor 610 have the same potential, no current flows regardless of the potential of the gate (node ​​SN). In other words, the potential of the wiring 642 does not change.

[0175] In the period T5, the wiring 632 (WWL) is at a low level, and the wiring 641 (WBL) is at a low level (V Ｌ ), and the wiring 631 (RWL) is at a low level. At this time, the transistor 620 is off. Furthermore, in the period T5, the wiring 642 (RBL) is in an electrically floating state. That is, the potential of the wiring 642 changes depending on the current flowing through the transistor 610 of the memory cell 650.

[0176] During the period T5, a potential difference occurs between the source and drain terminals of the transistor 610, causing a current to flow according to the potential of the gate (node ​​SN) of the transistor 610. When the data stored in the memory cell 650 is data "1," a large current flows through the transistor 610, causing the potential of the wiring 642 (RBL) to drop to a low level. This change in the potential of the wiring 642 (RBL) activates a sense amplifier connected to the wiring 642 (RBL), allowing data of the selected memory cell 650 to be read out to the outside.

[0177] When the data stored in the memory cell 650 is "0", the current flowing through the transistor 610 is small, and therefore the potential of the wiring 642 (RBL) hardly changes from the high level (precharged potential).

[0178] In the period T5, in the memory cell 650 in the unselected row, the wiring 631 (RWL) is at high level, and the source and drain terminals of the transistor 610 are at the same potential; therefore, no current flows regardless of the gate potential.

[0179] In the period T6, the wiring 632 (WWL) is at a low level, and the wiring 641 (WBL) is at a low level (V Ｌ ), the wiring 631 (RWL) is at a high level, and the wiring 642 (RBL) is at a high level. At this time, the transistor 620 is in a non-conducting state. Since the source and drain terminals of the transistor 610 have the same potential, no current flows regardless of the gate potential.

[0180] By the above operation, data can be read from the memory cells 650 in the selected row.

[0181] The stacked structure shown in Fig. 8B will be described with reference to the cross-sectional view of Fig. 13. Note that the configuration other than the layer 240 is the same as the stacked structure shown in Fig. 8A and Fig. 9, and therefore description thereof will be omitted. Note that when the imaging device has the layer 240, a drive circuit for the memory cell 650, a readout circuit (sense amplifier), and the like can also be provided in the layer 210.

[0182] 11B can be provided in the layer 240. The structure of the memory cell 650 is shown on the left side, and a circuit diagram is shown on the right side. The other of the source and the drain of the transistor 610 is electrically connected to the source and the drain of the transistor 453 or the transistor 454 provided in the layer 210 via a wiring 642. Here, the transistors 453 and 454 are components of a sense amplifier.

[0183] 14, the memory cells 650 provided in the layer 240 can have a so-called 3D structure in which a plurality of memory cells 650 are arranged in the height direction and horizontal direction (direction perpendicular to the height direction). In this case, the other of the source or the drain of a plurality of transistors 610 arranged in the height direction and horizontal direction can be connected to the wiring 642, and data can be selectively read from only the memory cells 650 to which a read signal is applied from the wiring 631.

[0184] As described above, in the imaging device of one embodiment of the present invention, by using vertical transistors in pixel circuits, the pixel size can be reduced and the pixel density can be increased. By increasing the pixel density of the imaging device, high-resolution images can be acquired. Furthermore, by increasing the pixel density of the imaging device, the imaging device can be miniaturized. Furthermore, by providing a memory device with high memory density including vertical transistors, an imaging device capable of high-speed operation can be realized.

[0185] This embodiment mode can be combined as appropriate with the descriptions of other embodiment modes or examples.

[0186] Embodiment 2 In this embodiment, materials for forming the vertical transistor (transistor 110) described in Embodiment 1 will be described.

[0187] [Oxide Semiconductor Layer 330] The oxide semiconductor layer 330 has a channel formation region. The oxide semiconductor layer 330 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region. The oxide semiconductor layer 330 may have a stacked structure of two or more layers.

[0188] The crystallinity of a semiconductor material used for the oxide semiconductor layer 330 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0189] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. Because the off-state current of an OS transistor is low, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0190] The oxide semiconductor layer preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0191] The oxide semiconductor layer preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0192] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0193] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0194] Examples of metal oxides contained in the oxide semiconductor layer of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, e.g., a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may also include metalloid elements.

[0195] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium aluminum oxide. Examples of usable materials include indium zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0196] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-current and high frequency characteristics.

[0197] Instead of indium, the metal oxide may contain one or more metal elements with higher periodic numbers in the periodic table. Alternatively, the metal oxide may contain, in addition to indium, one or more metal elements with higher periodic numbers in the periodic table. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher periodic number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements with higher periodic numbers in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0198] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0199] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0200] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0201] In the present embodiment, an In—Ga—Zn oxide may be used as an example of the metal oxide.

[0202] For example, the oxide semiconductor layer can have a stacked structure of two or more metal oxide layers with different crystallinity. In this case, the two or more metal oxide layers may have different compositions or may have the same or approximately the same composition. For example, when a metal oxide has a two-layer structure, the surface on which the second metal oxide layer is formed is the surface of the first metal oxide layer, so that the crystallinity of the second metal oxide layer can be increased in some cases. Furthermore, by performing heat treatment (also referred to as crystallization treatment) after forming the second metal oxide layer, the crystallinity of the first layer can be increased.

[0203] For example, a first metal oxide layer is formed using an atomic layer deposition (ALD) method, and a second metal oxide layer having higher crystallinity than the first layer is formed using a sputtering method. Heat treatment can then be performed to improve the crystallinity of the first and second metal oxide layers. In this case, the crystals contained in the second layer grow continuously in the vertical direction toward the first layer, and the boundary between the first and second layers may become indistinguishable by cross-sectional observation.

[0204] Alternatively, a three-layer structure may be formed by depositing a third metal oxide layer on the second metal oxide layer using an ALD method. After the deposition of the third metal oxide layer, heat treatment can be performed to improve the crystallinity of the first to third metal oxide layers. In this case, the crystals contained in the second layer grow continuously vertically toward the first and third layers and then laterally, which may result in the boundary between the first and second layers and the boundary between the second and third layers becoming indistinguishable from cross-sectional observation.

[0205] In this way, by stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity, continuous crystal growth occurs between them in the film thickness direction, and a semiconductor layer with high crystallinity can be formed throughout the entire film thickness. Alternatively, by stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity and then performing heat treatment, continuous crystal growth occurs between them in the film thickness direction, and a semiconductor layer with high crystallinity can be formed throughout the entire film thickness. This makes it possible to realize a highly reliable transistor.

[0206] For example, in a three-layer structure in which a first metal oxide layer is formed by ALD, a second metal oxide layer is formed by sputtering to have a CAAC structure, and a third metal oxide layer is formed by ALD, the second CAAC structure can be used as a nucleus or seed to enhance the crystallinity of the upper and lower metal oxide layers. A metal oxide layer with enhanced crystallinity can be called an axial growth CAAC (AG CAAC).

[0207] The heat treatment is carried out at a temperature of 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. The treatment time is preferably, for example, 1 minute to 1 hour, or 10 minutes to 30 minutes, at a temperature of 350° C. to 550° C.

[0208] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA device may be used.

[0209] Examples of RTA devices that can be used include LRTA (Lamp Rapid Thermal Anneal) devices and GRTA (Gas Rapid Thermal Anneal) devices. LRTA devices are devices that heat workpieces by radiating light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. GRTA devices are devices that perform heat treatment using high-temperature gas.

[0210] Increasing the atomic ratio of zinc in the composition of an oxide semiconductor can improve the crystallinity of the oxide semiconductor. In particular, when the oxide semiconductor has a stacked structure of two or more metal oxide layers as described above, it is preferable that the first metal oxide layer contains zinc. For example, when the first metal oxide layer is formed by an ALD method and the second metal oxide layer is formed by a sputtering method, zinc contained in the first metal oxide layer may diffuse into the second metal oxide layer. This diffusion may occur during sputtering or subsequent heat treatment. The diffusion of zinc from the first metal oxide layer to the second metal oxide layer is expected to improve crystallinity. Alternatively, the diffusion of zinc from the first metal oxide layer to the second metal oxide layer is expected to promote the lateral growth of crystal parts having c-axis orientation, thereby accelerating the formation of CAAC.

[0211] The semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material in the channel formation region. Examples of such another semiconductor material include semiconductors made of simple elements or compound semiconductors. Examples of semiconductors made of simple elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductor is also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0212] Silicon that can be used as a semiconductor material for transistors includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low temperature polysilicon (LTPS).

[0213] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 310, insulating layer 335, insulating layer 350, insulating layer 380a, insulating layer 380b, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film may be used for the insulating layer of the semiconductor device.

[0214] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using high-k materials for the gate insulating layer allows for lower voltages during transistor operation while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) for the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select materials according to the function of the insulating layer. Materials with a low dielectric constant also have high dielectric strength.

[0215] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0216] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0217] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or a metal nitride such as aluminum nitride, silicon nitride oxide, or silicon nitride.

[0218] Specifically, examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0219] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of insulating layers that are likely to have a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0220] Since the insulating layer 310 functions as an interlayer film, it is preferable that the insulating layer 310 has a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. Silicon oxide and silicon oxynitride are both thermally stable, and therefore are suitable for the insulating layer 310.

[0221] The concentration of impurities such as water and hydrogen in the insulating layer 310 is preferably reduced, which can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 330.

[0222] A barrier insulating layer against hydrogen is preferably used as the insulating layer 310. When the insulating layer 310 provided on the outer side of the oxide semiconductor layer 330 has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer 330 can be suppressed.

[0223] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0224] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are defined as a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0225] For example, it is preferable to use a silicon nitride film as the insulating layer 310 .

[0226] The insulating layer 380 preferably includes the above-mentioned barrier insulating layer against hydrogen. The insulating layer 380 is provided so as to surround the oxide semiconductor layer 330. When the insulating layer 380 provided on the outer side of the oxide semiconductor layer 330 has a barrier property against hydrogen, it is possible to suppress diffusion of hydrogen into the oxide semiconductor layer 330. For example, the insulating layer 380 preferably includes one or both of an aluminum oxide film and a silicon nitride film.

[0227] Silicon nitride also has a barrier property against oxygen. Therefore, by using silicon nitride for the insulating layer 380, oxygen can be prevented from being extracted from the oxide semiconductor layer 330, which can prevent excessive oxygen vacancies from being formed in the oxide semiconductor layer 330.

[0228] Furthermore, the use of silicon nitride for the insulating layer 380 can prevent excess oxygen from being supplied to the oxide semiconductor layer 330. Therefore, excess oxygen can be prevented from being contained in the channel formation region of the oxide semiconductor layer 330, which can improve the reliability of the transistor 110.

[0229] The insulating layer 380 preferably includes the above-described insulating oxide insulating film, the oxynitride insulating film, or the insulating layer having a region containing excess oxygen.

[0230] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 380 can be reduced. By depositing at least some of the layers constituting the insulating layer 380 in this manner, oxygen can be supplied from the insulating layer 380 to the channel formation region of the oxide semiconductor layer 330, thereby reducing oxygen vacancies and VoH.

[0231] The concentration of impurities such as water and hydrogen is preferably reduced in the insulating layer 380. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 330.

[0232] For example, it is preferable to use a single-layer structure of a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film as the insulating layer 380. Alternatively, it is preferable to use a three-layer structure in which a silicon nitride film, a silicon oxide film, and a silicon nitride film are stacked in this order as the insulating layer 380. For example, it is preferable to use a three-layer structure in which an aluminum oxide film, a silicon oxide film, and an aluminum oxide film are stacked in this order as the insulating layer 380.

[0233] The insulating layer 350 preferably has a function of capturing and fixing hydrogen. This can reduce the hydrogen concentration in the oxide semiconductor layer 330 (particularly, the hydrogen concentration in the channel formation region of the transistor). Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0234] Examples of materials for insulating layers capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with amorphous structures have dangling bonds in some oxygen atoms, which enhance their ability to capture or adsorb hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, an oxide containing hafnium and silicon (hafnium silicate) is preferably used. Metal oxides may have crystalline regions and / or grain boundaries.

[0235] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0236] When the gate insulating layer has a stacked-layer structure, a layer in contact with the oxide semiconductor layer 330 preferably has a function of capturing and fixing hydrogen. This allows hydrogen contained in the oxide semiconductor layer 330 to be more effectively captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 330 can be reduced. For example, hafnium silicate or the like may be used as the layer of the insulating layer 350 in contact with the oxide semiconductor layer 330. In addition, the layer preferably has an amorphous structure.

[0237] By making the layer amorphous, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the layer. This makes the film thickness distribution of the insulating layer 350 uniform, and it is possible to reduce portions with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer 350. It is also possible to make the film thickness distribution of the film provided on the insulating layer 350 uniform.

[0238] Furthermore, by suppressing the formation of grain boundaries in the layer, leakage current due to defect levels in the grain boundaries can be reduced, and the insulating layer 350 can function as an insulating film with low leakage current.

[0239] Furthermore, since hafnium oxide is a high dielectric constant (high-k) material, hafnium silicate can also be a high dielectric constant (high-k) material depending on the silicon content. Therefore, when hafnium oxide or hafnium silicate is used for the gate insulating layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulating layer. It is also possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer.

[0240] From the above, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulating layer 350, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.

[0241] The above-described barrier insulating layer against hydrogen is preferably used as the insulating layer 350. By using a barrier insulating layer against hydrogen for the insulating layer 350, diffusion of impurities contained in the conductive layer 365 into the oxide semiconductor layer 330 can be suppressed. For example, silicon nitride has a high barrier property against hydrogen and is therefore suitable for the insulating layer 350. Furthermore, the insulating layer 350 may include an insulating layer having a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0242] With such a structure, a semiconductor device having good electrical characteristics, high reliability, little variation in the electrical characteristics of the transistors, and a large on-state current can be provided.

[0243] Additionally, insulating layer 350 may comprise an insulating layer of a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0244] Furthermore, the insulating layer 350 may have an insulating layer having a thermally stable structure between a pair of insulating layers having the functions of capturing and fixing hydrogen.

[0245] The insulating layer 350 preferably has a barrier insulating layer against oxygen, which can suppress oxidation of the conductive layer 340, the conductive layer 365, and the like. When the insulating layer 350 has a stacked structure, a layer in contact with the conductive layer 340 is preferably a barrier insulating layer against oxygen. In particular, among the layers constituting the insulating layer 350, a layer in contact with the conductive layer 340 and a layer in contact with the conductive layer 365 are preferably barrier insulating layers against oxygen.

[0246] The use of a barrier insulating layer against hydrogen and oxygen as a layer of the insulating layer 350 that is in contact with the conductive layer 365 can suppress oxidation of the conductive layer 365. Furthermore, oxygen contained in the oxide semiconductor layer 330 can be prevented from diffusing into the conductive layer 365, which can suppress formation of oxygen vacancies in the oxide semiconductor layer 330.

[0247] Examples of the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0248] The layer of the insulating layer 350 in contact with the conductive layer 340 is preferably less permeable to oxygen than at least the insulating layer 380. The layer has a barrier property against oxygen, which can prevent the side surfaces of the conductive layer 340 from being oxidized and an oxide film from being formed on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 110.

[0249] Each layer constituting the insulating layer 350 is preferably a thin film. For example, by setting the thickness of each insulating layer 350 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0250] The thickness of each layer constituting the insulating layer 350 is preferably more than 0 nm and not more than 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that it is sufficient that each layer constituting the insulating layer 350 has a region with the above-mentioned thickness in at least a portion thereof.

[0251] The insulating layer 350 preferably has a three-layer structure in which, from the oxide semiconductor layer 330 side, a first insulating layer containing a material with a low dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and an insulating layer having a barrier property against hydrogen and oxygen are stacked in this order. Silicon oxide or silicon oxynitride is preferably used as the material with a low dielectric constant for the first insulating layer. The first insulating layer is a layer in contact with the oxide semiconductor layer 330. By using oxide for the first insulating layer, oxygen can be supplied to the oxide semiconductor layer 330. Furthermore, by providing a third insulating layer, oxygen contained in the first insulating layer can be prevented from diffusing into the conductive layer 365, thereby preventing oxidation of the conductive layer 365. Furthermore, a decrease in the amount of oxygen supplied from the first insulating layer to the oxide semiconductor layer 330 can be prevented.

[0252] [Conductive Layer] The conductive layers (conductive layer 320, conductive layer 340, conductive layer 355, conductive layer 365, etc.) included in the semiconductor device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0253] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO®), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0254] Conductive materials based on tungsten, copper, or aluminum are preferred because they have high conductivity.

[0255] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0256] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0257] The conductive layer 320 and the conductive layer 340 are conductive layers in contact with the oxide semiconductor layer 330, and therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 320 and the conductive layer 340.

[0258] By using a conductive material containing oxygen for the conductive layer 320 or the conductive layer 340, the conductive layer 320 or the conductive layer 340 can maintain its conductivity even if it absorbs oxygen. Furthermore, even when an insulating layer containing oxygen, such as hafnium oxide, is used as the insulating layer 310, the conductive layer 320 is preferable because it can maintain its conductivity. For example, ITO, ITSO, IZO (registered trademark), or the like is preferably used for each of the conductive layer 320 and the conductive layer 340.

[0259] When the conductive layer 320 has a two-layer structure of a conductive layer 320a and a conductive layer 320b on the conductive layer 320a, it is preferable to use a highly conductive material for the conductive layer 320a and a conductive material containing oxygen (more preferably, an oxide conductor) for the conductive layer 320b. Specifically, it is preferable to use tungsten for the conductive layer 320a and an oxide conductor (e.g., ITO, ITSO, or IZO (registered trademark)) for the conductive layer 320b.

[0260] When the conductive layer 340 has a two-layer structure including a conductive layer 340a and a conductive layer 340b on the conductive layer 340a, it is preferable to use, for example, a conductive material containing oxygen for the conductive layer 340b and a material having higher conductivity than the conductive layer 340b for the conductive layer 340a. Specifically, it is preferable to use, for example, an oxide conductor (e.g., ITO, ITSO, or IZO (registered trademark)) for the conductive layer 340b and tungsten for the conductive layer 340a. Furthermore, ruthenium, titanium nitride, tantalum nitride, or the like may be used for the conductive layer 340a.

[0261] Note that the conductive layer 340a may be formed using a conductive material containing oxygen, and the conductive layer 340b may be formed using a material having higher conductivity than the conductive layer 340a. In this case, an oxide conductor is used for the layer of the conductive layer 340 that is closest to the channel formation region of the oxide semiconductor layer 330. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor can be increased.

[0262] The conductive layer 365 is preferably made of a highly conductive material such as tungsten. Furthermore, the conductive layer 365 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 365.

[0263] The conductive layer 365 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0264] The conductive layer 365 preferably has high conductivity because it functions as a gate wiring. Tungsten is preferably used for the conductive layer 365. For example, a two-layer structure of titanium nitride and tungsten may be used.

[0265] [Substrate] Substrates for forming transistors can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include semiconductor substrates having an insulating region within the semiconductor substrate, such as SOI (Silicon-On-Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride and a metal oxide. Examples of substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0266] This embodiment mode can be combined as appropriate with the descriptions of other embodiment modes or examples.

[0267] Embodiment 3 In this embodiment, an example of a package and a camera module that house an image sensor chip will be described. The image sensor chip can have the same structure as the imaging device of one embodiment of the present invention.

[0268] 15A is a perspective view of the appearance of a package containing an image sensor chip. The package is a CSP (Chip Size Package) and includes an image sensor bare chip 850, a cover glass 840, and an adhesive 830 that bonds the two together.

[0269] An electrode pad 825 provided outside the pixel array 855 is electrically connected to the rear electrode 815 via a through electrode 820. The electrode pad 825 is electrically connected to a circuit constituting the image sensor by electrical wiring or wires. Note that the bare chip 850 may be a laminated chip in which circuits having various functions are laminated.

[0270] 15A illustrates a BGA (Ball Grid Array) configuration in which bumps 810 are formed with solder balls on rear surface electrodes 815. The configuration is not limited to a BGA, and may be an LGA (Land Grid Array) or a PGA (Pin Grid Array). Alternatively, a package in which bare chip 850 is mounted on a QFN (Quad Flat No-Lead Package) or a QFP (Quad Flat Package) may be used.

[0271] 15B is a perspective view of the top surface of a camera module that combines an image sensor chip and a lens. The camera module includes a lens cover 860 and multiple lenses 870 in addition to the configuration shown in FIG. 15A. An optical filter 880 that absorbs light of a specific wavelength is provided between the lens 870 and the cover glass 840 as needed. For example, in the case of an image sensor that primarily captures visible light, an infrared cut filter or the like can be used as the optical filter 880.

[0272] By housing the image sensor chip in a package of the above-described type, it becomes easy to mount the image sensor chip on a printed circuit board or the like, and the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0273] This embodiment mode can be combined as appropriate with the descriptions of other embodiment modes or examples.

[0274] (Embodiment 4) Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with a recording medium, mobile phones, game consoles including portable devices, portable data terminals, e-book terminals, cameras such as video cameras and digital still cameras, goggle displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio player, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines (ATMs), vending machines, and the like. By using the imaging device according to one embodiment of the present invention in these electronic devices, high-resolution images can be obtained. Furthermore, the electronic devices can be operated at high speed. Furthermore, the electronic devices can be miniaturized. Specific examples of these electronic devices are shown in FIGS. 16A to 16F .

[0275] 16A illustrates an example of a mobile phone, which includes a housing 981, a display portion 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The mobile phone includes a touch sensor in the display portion 982. Any operation, such as making a call or inputting characters, can be performed by touching the display portion 982 with a finger or a stylus. The imaging device of one embodiment of the present invention can be applied to the mobile phone.

[0276] 16B shows a portable data terminal including a housing 911, a display portion 912, a speaker 913, a camera 919, and the like. Information can be input and output using a touch panel function of the display portion 912. Characters and the like can be recognized from an image acquired by the camera 919 and output as voice through the speaker 913. The imaging device of one embodiment of the present invention can be applied to the portable data terminal.

[0277] 16C illustrates a digital camera including a housing 961, a shutter button 962, a microphone 963, a light-emitting portion 967, a lens 965, and the like. The imaging device of one embodiment of the present invention can be applied to the digital camera.

[0278] 16D shows a wristwatch-type information terminal including a display portion 932, a housing / wristband 933, a camera 939, and the like. The display portion 932 includes a touch panel for operating the information terminal. The display portion 932 and the housing / wristband 933 are flexible and therefore easily worn on the body. The imaging device of one embodiment of the present invention can be applied to this information terminal.

[0279] 16E shows a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, and the like. The camera unit 952 is provided with a rotation mechanism and is installed on the ceiling, enabling imaging of the entire periphery. The imaging device of one embodiment of the present invention can be applied to an element for acquiring an image in the camera unit. Note that the term "surveillance camera" is a common name and is not intended to limit the application. For example, a device having a function as a surveillance camera is also called a camera or a video camera.

[0280] 16F shows a drive recorder including a frame 941, a camera 942, an operation button 943, and an attachment part 944. By installing the drive recorder on the front window of a vehicle or the like via the attachment part 944, the view ahead while the vehicle is traveling can be recorded. Note that a display panel that displays recorded images is provided on the back surface (not shown). The imaging device of one embodiment of the present invention can be applied to the camera 942.

[0281] 17A illustrates a drone, which is an example of a moving object, including a frame 921, an arm 922, a rotor 923, blades 924, a camera 925, a battery 926, and the like, and has a function of autonomously flying, a function of remaining stationary in the air, etc. The imaging device of one embodiment of the present invention can be applied to the camera 925.

[0282] 17B illustrates an external view of a car as an example of a moving object. The car 890 includes multiple cameras 891 and can acquire information about the front, rear, left, right, and above the car 890. The imaging device of one embodiment of the present invention can be applied to the camera 891. The car 890 also includes various sensors (not shown), such as infrared radar, millimeter-wave radar, and laser radar. The car 890 analyzes images acquired by the cameras 891 in multiple imaging directions 892, determines surrounding traffic conditions such as the presence or absence of guardrails or pedestrians, and can perform autonomous driving. The car 890 can also be used in systems that provide road guidance, hazard prediction, and the like.

[0283] In an imaging device according to one embodiment of the present invention, the obtained image data is subjected to arithmetic processing such as a neural network, thereby enabling processing such as increasing the image resolution, reducing image noise, face recognition (for crime prevention purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reduction of reflected glare.

[0284] In the above description, the automobile may be any of an automobile having an internal combustion engine, an electric automobile, a hydrogen automobile, etc. Furthermore, the moving object is not limited to an automobile. For example, the moving object may be a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle, airplane, rocket), etc., and a system using artificial intelligence can be provided by applying a computer according to one embodiment of the present invention to these moving objects.

[0285] This embodiment mode can be combined as appropriate with the descriptions of other embodiment modes or examples.

[0286] FD: node, SN: node, 10: pixel, 20: pixel array, 30: driver circuit, 40: readout circuit, 103: transistor, 104: transistor, 105: transistor, 106: transistor, 108: capacitor, 110: transistor, 111: capacitor, 115: conductive layer, 121: wiring, 122: wiring, 123: wiring, 126: wiring, 127: wiring, 128: wiring, 129: wiring, 130: wiring, 150: photodiode, 208: layer, 210: layer, 220a: layer, 220b: layer, 230: layer, 240: layer, 250: layer, 310: insulator layer, 320A: conductive layer, 320a: conductive layer, 320B: conductive layer, 320b: conductive layer, 320: conductive layer, 330: oxide semiconductor layer, 335: insulating layer, 340A: conductive layer, 340a: conductive layer, 340b: conductive layer, 340: conductive layer, 350: insulating layer, 355: conductive layer, 356: conductive layer, 357: conductive layer, 365A: conductive layer, 365B: conductive layer, 365: conductive layer, 380a: insulating layer, 380b: insulating layer, 380: insulating layer, 390: opening, 400: CDS circuit, 401: transistor, 402: capacitor, 403: transistor, 404: transistor, 405 : capacitor, 410: A / D converter, 451: transistor, 452: transistor, 453: transistor, 454: transistor, 511: layer, 512: insulating layer, 513: insulating layer, 514: insulating layer, 515: insulating layer, 516: insulating layer, 517: insulating layer, 518: insulating layer, 529a: insulating layer, 529b: insulating layer, 531a: conductive layer, 531b: conductive layer, 532a: conductive layer, 532b: conductive layer, 541: insulating layer, 542: insulating layer, 543: p-type region, 544: n-type region, 545: insulating layer, 546: insulating layer, 550B: color filter, 550G: color filter IR: infrared filter, 550R: color filter, 550UV: ultraviolet filter, 550: optical conversion layer, 551: light-shielding layer, 555: microlens array, 610: transistor, 620: transistor, 631: wiring, 632: wiring, 641: wiring, 642: wiring, 650: memory cell, 660: capacitor, 661: conductive layer, 662: conductive layer, 663: insulating layer, 810: bump, 815: rear electrode, 820: through electrode, 825: electrode pad, 830: adhesive, 840: cover glass, 850: bare chip, 855: pixel array,860: lens cover, 870: lens, 880: optical filter, 890: automobile, 891: camera, 892: imaging direction, 911: housing, 912: display unit, 913: speaker, 919: camera, 921: frame, 922: arm, 923: rotor, 924: blade, 925: camera, 926: battery, 932: display unit, 933: housing / wristband, 939: camera, 941 : Frame, 942: Camera, 943: Operation button, 944: Mounting part, 951: Support stand, 952: Camera unit, 953: Protective cover, 961: Housing, 962: Shutter button, 963: Microphone, 965: Lens, 967: Light emitting part, 981: Housing, 982: Display part, 983: Operation button, 984: External connection port, 985: Speaker, 986: Microphone, 987: Camera,

Claims

A first layer, a second layer, and a third layer, the second layer is provided between the first layer and the third layer, the first layer having a first transistor and a second transistor; the second layer includes a third transistor and a capacitor; the third layer includes a fourth transistor and a photodiode; each of the first to third transistors has a channel formation region in a metal oxide formed along a side surface of an opening provided in an insulator; the capacitor is of the trench type; the fourth transistor has a channel formation region in a single crystal silicon substrate; The photodiode is an imaging device having a photoelectric conversion region in the single crystal silicon substrate. 　 In claim 1, The first transistor and the third transistor have regions where they overlap each other, and the second transistor and the capacitor have regions where they overlap each other. 　 In claim 1, The first transistor and the capacitor have regions where they overlap each other, and the second transistor and the third transistor have regions where they overlap each other. 　 In claim 1, a cathode of the photodiode is electrically connected to one of a source and a drain of the fourth transistor; the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor, one of the source and the drain of the third transistor, and one electrode of the capacitor; One of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the second transistor. 　 In claim 1, The imaging device includes a pixel circuit formed by the first to fourth transistors, the capacitor, and the photodiode. 　 In claim 5, A fourth layer, the fourth layer has the first layer between the second layer, The fourth layer is an imaging device having a drive circuit and a readout circuit for the pixel circuits. 　 In claim 1, A fifth layer, the fifth layer is provided between the first layer and the second layer, the fifth layer includes a memory element; the memory element includes a fifth transistor and a sixth transistor; the fifth transistor and the sixth transistor have overlapping regions; one of a source and a drain of the fifth transistor is electrically connected to a gate of the sixth transistor; The imaging device, wherein the fifth transistor and the sixth transistor each have a channel formation region in a metal oxide formed along a side surface of an opening provided in an insulator. 　 In claim 7, A sixth layer, the sixth layer has the first layer between the second layer, The sixth layer is an imaging device having a readout circuit for the memory element. 　 In claim 1, The metal oxide comprises In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

9. An electronic device comprising: the imaging device according to claim 1; and a display unit.

Images