Phase adjustment circuit

Abstract

A phase adjustment circuit (10) according to the present invention is provided with: a clock generation circuit (11) that generates a sine wave signal; a first multiplication unit (124) that multiplies the amplitude of the signal by a first variable; a delay unit (123) that delays the signal; a second multiplication unit (125) that multiplies the amplitude of the signal by a second variable; an addition unit (126) that adds the output signals of the first multiplication unit and the second multiplication unit; a phase extraction circuit (131) that detects the phase difference between the sine wave signal and the output signal of the addition unit; a first low-pass filter (132) that flattens this output and outputs the result to the first multiplication unit; an amplitude extraction circuit (141) that detects the amplitude of the output signal of the addition unit; a differential amplification unit (142) that subtracts the amplitude from a target amplitude and amplifies the result; and a second low-pass filter (143) that flattens this output and outputs the result to the second multiplication unit. The transfer functions of the first low-pass filter and the second low-pass filter are stable.　Thus, the present invention can provide a phase adjustment circuit capable of controlling phase and amplitude.

Description

Phase Adjustment Circuit

[0001] The present invention relates to a sine wave phase adjustment circuit.

[0002] In communications, sine waves are used to generate carrier waves and as clocks, and clocks are used as timing references to determine data in communications.

[0003] When a clock is used as a timing reference for data determination, a mechanism is required to adjust the clock phase and perform data determination at the appropriate timing. One example of a clock data recovery method is a configuration using a phase comparator and a phase interpolator. In this configuration, the phase is compared using some means, and the desired phase is generated based on the comparison result. A phase interpolator is often used to generate the desired phase.

[0004] As this phase interpolator, a configuration has been disclosed in which an intermediate phase is generated by adding a reference sine wave and a sine wave having a fixed phase difference of π / 2 relative to the reference (Non-Patent Document 1). In this configuration, as shown in Fig. 21A, a Quadrature-VCO 41 or the like is used to generate sine waves having a fixed phase difference of π / 2, i.e., sine waves and cosine waves.

[0005] Another known method for generating a sine wave with a fixed phase difference of π / 2 from a sine wave is to use a 90° hybrid circuit. In this method, as shown in Fig. 21B, a sine wave is generated by an LC-VCO 42, and a sine wave and a cosine wave are generated from this sine wave by a 90° hybrid circuit 43.

[0006] Arun Goyal et al., "A High-Resolution Digital Phase Interpolator based CDR with a Half-Rate Hybrid Phase Detector", 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 26-29 May 2019, <URL: https: / / ieeexplore.ieee.org / document / <8702262>

[0007] However, in the configuration (FIG. 21A) disclosed in Non-Patent Document 1, the Quadrature-VCO 41 was difficult to use in the limit region of the device because of its low oscillation frequency due to its structure.

[0008] Also, in the configuration shown in FIG. 21B, the operating frequency is the frequency at which the 90° hybrid circuit 43 operates, and since the operating frequency of the 90° hybrid circuit 43 is determined by the physical length, there was a problem that the operating frequency was narrow.

[0009] In order to solve the above-mentioned problems, a phase adjustment circuit according to the present invention includes a clock generation circuit that generates a first sine wave signal, a first multiplication unit that multiplies the amplitude of the first sine wave signal by a first variable, a delay unit that delays the first sine wave signal, a second multiplication unit that multiplies the amplitude of a second sine wave signal output from the delay unit by a second variable, an addition unit that adds the signal output from the first multiplication unit and the signal output from the second multiplication unit, a phase extraction circuit that detects a phase difference between the first sine wave signal and the output signal of the addition unit, and The input signal is a first low-pass filter that flattens an output result and outputs a control signal that determines the first variable to the first multiplier; an amplitude extraction circuit that detects the amplitude of the output signal of the adder; a differential amplifier that subtracts the amplitude detected by the amplitude extraction circuit from a target amplitude and amplifies the amplitude obtained as a result of the subtraction; and a second low-pass filter that flattens the output result of the differential amplifier and outputs a control signal that determines the second variable to the second multiplier, and the transfer functions of the first low-pass filter and the second low-pass filter are stable.

[0010] According to the present invention, a phase adjustment circuit can be provided that operates over a wide frequency range.

[0011] FIG. 1 is a block diagram showing the configuration of a phase adjustment circuit according to a first embodiment of the present invention. FIG. 2 is a diagram illustrating the operation of the phase adjustment circuit according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating the operation of the phase adjustment circuit according to the first embodiment of the present invention. FIG. 4 is a block diagram showing an example of the configuration of a phase adjustment circuit according to the first embodiment of the present invention. FIG. 5 is a block diagram showing the configuration of a phase adjustment circuit according to a first example of the present invention. FIG. 6 is a block diagram showing an example of the configuration of a phase adjustment circuit according to the first example of the present invention. FIG. 7 is a circuit diagram showing the configuration of a multiplier unit in a phase adjustment circuit according to a second example of the present invention. FIG. 8 is a circuit diagram showing the configuration of an adder unit in a phase adjustment circuit according to a third example of the present invention. FIG. 9 is a circuit diagram showing an example of a configuration combining a multiplier unit and an adder unit in the phase adjustment circuits according to the second and third examples of the present invention. FIG. 10 is a circuit diagram showing the configuration of an amplitude extraction circuit in a phase adjustment circuit according to a fourth example of the present invention. FIG. 11 is a circuit diagram showing the configuration of a differential amplifier unit in a phase adjustment circuit according to a fifth example of the present invention. FIG. 12 is a circuit diagram showing an example of the configuration of a low-pass filter circuit in a phase adjustment circuit according to the embodiments and examples of the present invention. FIG. 13 is a circuit diagram showing an example of the configuration of an amplitude extraction circuit in a phase adjustment circuit according to an embodiment and an example of the present invention. FIG. 14 is a circuit diagram showing an example of the configuration of an amplitude extraction circuit in a phase adjustment circuit according to an embodiment and an example of the present invention. FIG. 15 is a block diagram showing the configuration of a phase adjustment circuit according to a second embodiment of the present invention. FIG. 16 is a circuit diagram showing an example of the configuration of an amplitude limiting circuit in a phase adjustment circuit according to the second embodiment of the present invention. FIG. 17 is a diagram for explaining the effect of the amplitude limiting circuit in a phase adjustment circuit according to the second embodiment of the present invention. FIG. 18 is a diagram for explaining the effect of the amplitude limiting circuit in a phase adjustment circuit according to the second embodiment of the present invention. FIG. 19 is a diagram for explaining the effect of the amplitude limiting circuit in a phase adjustment circuit according to the second embodiment of the present invention. FIG. 20 is a diagram for explaining the effect of the amplitude limiting circuit in a phase adjustment circuit according to the second embodiment of the present invention. FIG. 21A is a diagram for explaining a conventional phase adjustment circuit.FIG. 21B is a diagram for explaining a conventional phase adjustment circuit.

[0012] First Embodiment A phase adjustment circuit according to a first embodiment of the present invention will be described with reference to FIGS.

[0013] <Configuration of Phase Adjustment Circuit> As shown in FIG. 1 , the phase adjustment circuit 10 according to this embodiment includes a clock generation circuit 11 that generates a sinusoidal clock signal, a phase interpolation unit 12, a phase extraction circuit 131, a first low-pass filter (first LPF) 132, an amplitude extraction circuit 141, a differential amplification unit 142, and a second low-pass filter (second LPF) 143.

[0014] The phase interpolation unit 12 includes buffer units 121 and 122 that receive as input the signal (first sine wave signal) output from the clock generation circuit 11, a delay unit 123 that delays the signal output from the buffer unit 122, a multiplication unit 124 that outputs a signal obtained by multiplying the amplitude of the signal output from the buffer unit 121 by A (first variable), a multiplication unit 125 that outputs a signal obtained by multiplying the amplitude of the signal (second sine wave signal) output from the delay unit 123 by B (second variable), and an addition unit 126 that adds the signal output from the multiplication unit 124 and the signal output from the multiplication unit 125.

[0015] The path for phase extraction includes a phase extraction unit to which the signal output from the clock generation circuit 11 and whose amplitude is made constant by an AGC (Automatic Gain Control) unit 15 and the output signal of the adder 126 are input, and a first low-pass filter (first low-pass filter or first LPF) 132 that smoothes the amount of error in the phase difference detected by the phase extraction unit and outputs the smoothed amount to the multiplier 124. The signal output from the first LPF 132 is supplied to the multiplier 124 as a control signal (first control signal) that determines a first variable (A).

[0016] The path for amplitude extraction includes an amplitude extraction circuit 141 that detects the amplitude of the output signal of the adder 126, a differential amplifier 142 that subtracts the amplitude detected by the amplitude extraction circuit 141 from the target amplitude Vref2 and amplifies the result, and a second low-pass filter (second low-pass filter or second LPF) 143 that flattens the output result of the differential amplifier 142 and outputs the flattened result to the multiplier 125. The signal output from the second LPF 143 is supplied to the multiplier 125 as a control signal (second control signal) that determines a second variable (B).

[0017] <Operation of Phase Adjustment Circuit> The operation of the phase adjustment circuit 10 according to this embodiment will be described.

[0018] First, a sine wave is input from the clock generation circuit 11 to the phase interpolation unit 12 .

[0019] Next, the phase interpolation unit 12 performs phase interpolation by adding the input sine wave and the delayed sine wave.

[0020] Next, the signal output from the phase interpolator 12 is fed back to the phase interpolator 12 via two paths. One path passes through a phase extraction circuit 131, and the other path passes through an amplitude extraction circuit 141.

[0021] In one path, a phase extraction circuit 131 outputs a signal proportional to the amount of error based on the target phase difference. A first low-pass filter (first LPF) 132 smooths this error amount and supplies it to a multiplication unit 124 as a control signal for determining a first variable (A). In this way, feedback reduces the phase error, making it possible to obtain the target phase difference (90°).

[0022] In the other path, the amplitude value error detected by comparing the amplitude extracted by the amplitude extraction circuit 141 with the reference potential Vref2 is smoothed by the second LPF 143 and supplied to the multiplication unit 125 as a control signal for determining the second variable (B). In this way, by performing feedback, it is possible to reduce the amplitude error and obtain the target output amplitude.

[0023] The operation of the phase adjustment circuit 10 will be described in detail below.

[0024] First, the operation of one path (path passing through phase extraction circuit 131 ) will be described on the assumption that the operation of amplitude extraction circuit 141 is sufficiently slower than that of phase extraction circuit 131 .

[0025] The phase extraction circuit 131 can be configured with a multiplier such as a Gilbert cell. When the phase extraction circuit 131 is configured with a multiplier, two sine waves, A1 sin(ωt) and A2 sin(ωt + τ), are multiplied by the multiplier. A1 and A2 are the amplitudes of the respective sine waves. τ is the phase difference between the two sine waves input to the phase extraction circuit 131.

[0026] One sine wave A 1 sin(ωt) is a signal that is output from the clock generation circuit 11 , has its amplitude made constant by the AGC unit 15 , and is then input to the phase extraction circuit 131 .

[0027] The other sine wave A2 sin(ωt+τ) is a signal that is input to the phase extraction circuit 131 after the input sine wave is added to the sine wave to which the phase difference φ has been added in the delay unit by the phase interpolation unit 12.

[0028] Since the two sine waves contain a phase error during propagation along their respective paths, the phase difference between the two sine waves input to the phase extraction circuit 131 becomes τ according to the phase difference φ imparted by the delay section.

[0029] The phase comparison result by the phase extraction circuit 131 (multiplier) is expressed by equation (1).

[0030]

[0031] From equation (1), by removing the second harmonic (corresponding to the first term in equation (1)) using the first LPF 132 after multiplication, it is possible to obtain τ (corresponding to the second term in equation (1)), which is a value corresponding to the phase difference φ imparted by the delay section, and to obtain the amount of error based on 90°.

[0032] Since the sine waves output from the phase interpolator 12 are A sin(ωt) and B sin(ωt+τ), the phase difference ρ in the output sine waves from the phase interpolator 12 is a function of A and B and is expressed by equation (2). The phase difference ρ is the difference between the phase of the input sine wave and the phase of the output sine wave in the phase interpolator 12, with the phase of the input sine wave as the reference.

[0033]

[0034] From equation (2), equation (3) is obtained.

[0035]

[0036] From equation (3), the phase difference ρ is expressed by equation (4).

[0037]

[0038] Here, A is the first variable, B is the second variable, and φ is the phase difference given by the delay unit.

[0039] In this way, the phase difference ρ of the sine wave output from the phase interpolation unit 12 can be controlled by the phase difference φ imparted by the delay unit.

[0040] In the phase adjustment circuit 10, by detecting the amount of phase error from the phase difference τ between the two sine waves input to the phase extraction circuit 131 in one path (path passing through the phase extraction circuit 131) and feeding it back, it is possible to control the phase so that the phase difference ρ of the sine wave signal output from the adder 126 (phase interpolator 12) approaches the target value of 90°.

[0041] Next, the other path (path passing through amplitude extraction circuit 141) will be described.

[0042] In the other path, the amplitude detected by the amplitude extraction circuit 141 is subtracted from the target amplitude Vref2 by a differential amplifier 142, the amplitude obtained as a result of the subtraction is amplified, flattened by a second low-pass filter (second LPF) 143, and output to a multiplication unit 125 as a control signal for determining a second variable (B).

[0043] The operation of the other path (path passing through the amplitude extraction circuit 141) is slower than the operation of one path (path passing through the phase extraction circuit 131). For example, when the amplitude of the sine wave is higher than the target value (Vref2), the value of the amplitude B of the sine wave in the phase interpolator 12 decreases more slowly via the second LPF 143 than via one path. As a result, while the amplitude B of the sine wave changes in the other circuit, the phase of the sine wave changes to the target value in one circuit. In other words, the phase can always be kept approximately at the target value during the process of bringing the amplitude closer to the target value. This allows the phase adjustment circuit 10, which has a dual loop circuit, to operate stably.

[0044] "The operation of the other path is slower than the operation of one path" roughly corresponds to the second LPF 143 having a lower cutoff frequency than the first LPF 132. In other words, the bandwidth of the second LPF 143 is narrower (the cutoff frequency is lower) than the bandwidth of the first LPF 132.

[0045] In this embodiment, it is desirable that the operation of the other path is about 10 times slower than the operation of one path.

[0046] Below, we will explain the fact that ``the operation of the other path is slower than the operation of one path,'' i.e., the fact that the path including the second LPF 143 is slower than the path including the LPF 132, from the perspective of the stability of the transfer function in the phase adjustment circuit 10.

[0047] Based on equations (2) and (3), equations (5) and (6) are obtained.

[0048]

[0049]

[0050] Equations (5) and (6) show that when A and B are input, the amplitude and phase are determined.

[0051] FIG. 2 shows a diagram in which the block diagram (FIG. 1) to be analyzed is replaced with a model.

[0052] In order to simplify the discussion of the stability of the nonlinear phase interpolation unit, a linear expansion is performed with an arbitrary point as the center to discuss the stability. Specifically, the stable point (A, B) = (A ０, B ０ ) is used as the steady state. As a result, the phase interpolation unit is expressed by equations (7) and (8).

[0053]

[0054]

[0055] Here, R ０ is the amplitude in the steady state and is equal to Vref2. Ａ , k Ｂ , l Ａ , l Ｂ is the coefficient from the Taylor expansion.

[0056] A similar linear expansion is performed on the multiplier (phase extraction circuit) 131. Since the inputs to the multiplier 131 are ρ−π / 2 and r, the output m of the multiplier 131 is expressed by equation (9).

[0057]

[0058] Stable point (A, B) = (A ０ , B ０ ) in which ρ(A ０ , B ０ ) = π / 2, and r(A ０ , B ０ ) = R ０ and m(A ０ , B ０ ) = 0, and perform the Taylor expansion in the same manner as above.

[0059]

[0060] where ρ ｄ is expressed by equation (11).

[0061]

[0062] Figure 3 shows a block diagram redrawn based on the results of the linear expansion. ρ denotes the transfer function of the first LPF 132, and H ｒ denotes the transfer function of the second LPF 143. Ａ , k Ｂ , l Ａ , l Ｂ , hＡ , h Ｂ is a coefficient by Taylor expansion as shown in equations (7), (8), and (10). For example, the coefficient (k Ａ A multiplier of 1.0x or more may be considered.

[0063] For stability reasons, n ρ and ｒ In order to simplify the analysis, two noise sources are added. ρ The characteristic of the LPF is multiplied by the amplitude value of the signal that serves as the phase reference. That is, the reference amplitude is also multiplied in addition to the characteristic of the LPF.

[0064] These noise n ρ , n ｒ are input randomly, and the target is a linear system. Therefore, if we calculate assuming one of the noises is 0 and then add it to the other, we get the same result.

[0065] From the above, equations (12) to (15) are obtained.

[0066]

[0067]

[0068]

[0069]

[0070] These are four linear equations obtained for four unknowns ρ, r, A, and B, so n ρ or n ｒ The transfer function is obtained in a form that includes

[0071] n ρ When r = 0, ρ０ =T ρ０ｒ (n ｒ ), ρ ρ０ =T ρ０ρ (n ｒ )

[0072] n ｒ When r = 0, ｒ０ =T ｒ０ｒ (n ｒ ), ρ ｒ０=T ｒ０ρ (n ｒ )

[0073] Any n ρ and ｒ For ρ０ , ρ ρ０ , r ｒ０ , ρ ｒ０ Therefore, in order to operate the phase adjustment circuit 10 stably, the transfer function T ρ０ｒ , T ρ０ρ , T ｒ０ｒ , T ｒ０ρ is required to be stable.

[0074] In designing the phase adjustment circuit 10, ０ and B ０ The value of is calculated using equations (7) and (8) and R(A ０ , B ０ ) = R ０ = Vref2, ρ(A ０ , B ０ )=π / 2.

[0075] Furthermore, as shown in equations (12) to (15), the characteristics of the first LPF 132 and the second LPF 143 (LPF2) also include the gain of the amplifier. In particular, the characteristics of the first LPF 132 are also multiplied by the amplitude of the reference signal according to equation (15). Therefore, the first LPF 132 and the second LPF 143 can be designed based on the above analysis results.

[0076] As described above, the phase adjustment circuit according to this embodiment can operate stably by satisfying the conditions shown in equations (12) to (15).

[0077] In the phase adjustment circuit 10, the sign of the signal input to the multiplier depends on the phase delay amount imparted by the delay unit of the phase compensation unit. Therefore, in order to adjust the sign of the signal input to the multiplier, a set value for the phase delay amount or the like may be set according to the sign that can be determined at the time of design. Also, a circuit that inverts the sign may be placed in the stage preceding the multiplier, or a function that monitors the operation of the phase adjustment circuit and dynamically adjusts it may be placed.

[0078] In this embodiment, as shown in FIG. 4, the connections of one path (path passing through phase extraction circuit 131) and the other path (path passing through amplitude extraction circuit 141) may be interchanged.

[0079] In this embodiment, in order to reduce errors when the phase difference converges to 90°, an amplifier circuit may be disposed at least either before or after the first LPF 132 and the second LPF 143.

[0080] Although the present embodiment shows an example in which an AGC is provided, the present invention is not limited to this. An AGC need not be provided. Alternatively, instead of an AGC, an amplifier may be provided, or a VGA whose gain can be adjusted externally may be provided.

[0081] Furthermore, if it is not necessary to make the amplitudes of the sine wave and the cosine wave match, it is not necessary to provide the AGC or the circuit that replaces the AGC.

[0082] <Effects> A possible configuration for expanding the operating frequency range of a conventional phase adjustment circuit is to use a phase adjustment circuit that creates an arbitrary phase difference by adding two sine waves with an arbitrary phase difference at an arbitrary ratio. For example, there is a circuit that inputs a sine wave generated using an LC-VCO to the phase adjustment circuit and generates a sine wave with a phase difference of 90 degrees from the sine wave.

[0083] This configuration can operate at high speed because it creates a set of sine waves with a phase difference of 90° based on the sine wave output from the LC-VCO, which transmits at high speed. However, when the phase is adjusted to 90°, the amplitude also fluctuates at the same time, making it difficult to control both the phase and the amplitude.

[0084] As described above, the phase adjustment circuit according to this embodiment can control the phase and amplitude and can operate over a wide frequency range.

[0085] Furthermore, the phase adjustment circuit according to this embodiment can operate stably by making the operation of the other path (path passing through the amplitude extraction circuit) slower than the operation of one path (path passing through the phase extraction circuit).

[0086] First Embodiment A phase adjustment circuit according to a first embodiment of the present invention will be described with reference to FIGS.

[0087] As shown in FIG. 5 , in the phase adjustment circuit 20 according to the present embodiment, a circuit in which an ADC (Analog to Digital Converter) 232, a DSP (Digital Signal Processor) 233, and a DAC (Digital to Analog Converter) 234 are connected in order is arranged in place of the first LPF 132 in one path of the phase adjustment circuit 20 according to the first embodiment, and a circuit in which an ADC 242, a DSP 243, and a DAC 244 are connected in order is arranged in place of the amplifier and second LPF 143 in the other path.

[0088] In the phase adjustment circuit 20, digitization is performed by ADCs 232 and 242 after the phase extraction circuit 131 and amplitude extraction circuit 141, respectively, and digital processing is performed by DSPs 233 and 243. The signals digitally processed by the DSPs 233 and 243 are converted back to analog signals by DACs 234 and 244, and become control signals.

[0089] In this embodiment, as shown in FIG. 6, a DSP 261 and a DAC 262 may be arranged to receive the output of the ADC 232 subsequent to the phase extraction circuit 131 and the output of the ADC 242 subsequent to the amplitude extraction circuit 141.

[0090] In this configuration, the ADC outputs of the phase extraction circuit 131 and the amplitude extraction circuit 141 are processed collectively by the DSP 261, thereby improving the convergence.

[0091] Second Embodiment A phase adjustment circuit according to a second embodiment of the present invention will be described with reference to FIG.

[0092] In this embodiment, an example will be described in which a Gilbert cell, which is a variable amplifier, is used as the multiplier in the phase adjustment circuit according to the first embodiment.

[0093] 7, the multiplication unit 124 includes an NPN bipolar transistor Q1 having a base to which a control signal IN1n (first control signal) is input from one path (path via the phase extraction circuit 131) and which outputs a positive phase side output signal OUT1p from its collector, an NPN bipolar transistor Q2 having a base to which a control signal IN1p (second control signal) is input and which outputs a negative phase side output signal OUT1n from its collector, an NPN bipolar transistor Q3 having a base to which the control signal IN1n is input and which outputs a negative phase side output signal OUT1n from its collector, an NPN bipolar transistor Q4 having a base to which the control signal IN1p is input and which outputs a positive phase side output signal OUT1p from its collector, and an NPN bipolar transistor Q5 having a base to which a positive phase side signal IN2p of the differential signal output from the buffer unit 121 is input and which has a collector connected to the emitters of the transistors Q1 and Q2. The circuit is composed of a transistor Q5, an NPN bipolar transistor Q6 having a base to which the negative-phase signal IN2n of the differential signal output from the buffer unit 121 is input and a collector connected to the emitters of the transistors Q3 and Q4, an NPN bipolar transistor Q7 having a base to which a bias voltage Vb is applied, a resistor R1 having one end connected to the power supply voltage VCC and the other end connected to the collectors of the transistors Q1 and Q4, a resistor R2 having one end connected to the power supply voltage VCC and the other end connected to the collectors of the transistors Q2 and Q3, a resistor R3 having one end connected to the emitter of the transistor Q5 and the other end connected to the collector of the transistor Q7, a resistor R4 having one end connected to the emitter of the transistor Q6 and the other end connected to the collector of the transistor Q7, and a resistor R5 having one end connected to the emitter of the transistor Q7 and the other end connected to the ground.

[0094] The amplification factor (the amplitude A) of the multiplication unit 124 can be controlled by the voltage difference between the control signals IN1p and IN1n.

[0095] In the above-described operation, an example is shown in which the differential signal output from the buffer unit is input, but the differential signal output from the buffer unit may be input to transistors Q1 to Q4, and a control signal may be input to transistors Q5 and Q6.

[0096] The configuration of the multiplication unit 125 is similar to that of the multiplication unit 124. In the multiplication unit 125, a control signal IN1n (third control signal) or a control signal IN1p (fourth control signal) is input to the transistors Q1 to Q4 from the other path (path passing through the amplitude extraction circuit 141), and differential signals IN2p and IN2n output from the delay unit 123 are input to the transistors Q5 and Q6. Alternatively, the differential signal output from the delay unit 123 may be input to the transistors Q1 to Q4, and a control signal may be input to the transistors Q5 and Q6. The amplification factor of the multiplication unit 125 (the above-mentioned amplitude B) can be controlled by the voltage difference between the control signals IN1p and IN1n.

[0097] In the configuration of this embodiment, the multiplication units 124 and 125 are configured as differential input / differential output types. To accommodate this configuration, the buffer units 121 and 122 may be configured as differential output type buffer units. Furthermore, the delay unit 123 may be configured as a differential transmission line consisting of two transmission lines, or may be configured as a cascade connection of differential input / differential output type amplifiers.

[0098] Third Embodiment A phase adjustment circuit according to a third embodiment of the present invention will be described with reference to FIG.

[0099] In this embodiment, an example will be described in which a current addition-based CML (Current Mode Logic) block is used as the amplitude addition unit in the phase adjustment circuit according to the first embodiment.

[0100] 8, the adder 126 includes an NPN bipolar transistor Q8 having a base to which the negative phase signal IN5n of the differential signals output from the multiplier 124 is input and which outputs a positive phase output signal OUT2p from its collector; an NPN bipolar transistor Q9 having a base to which the positive phase signal IN5p of the differential signals output from the multiplier 124 is input and which outputs a negative phase output signal OUT2n from its collector; an NPN bipolar transistor Q10 having a base to which the positive phase signal IN6p of the differential signals output from the multiplier 125 is input and which outputs a negative phase output signal OUT2n from its collector; an NPN bipolar transistor Q11 having a base to which the negative phase signal IN6n of the differential signals output from the multiplier 125 is input and which outputs a positive phase output signal OUT2p from its collector; NPN bipolar transistors Q12 and Q13 having bases to which a bias voltage Vb is applied; C and the other end connected to the collectors of transistors Q8 and Q11; a resistor R7 connected to the power supply voltage VCC and the other end connected to the collectors of transistors Q9 and Q10; a resistor R8 connected to the emitter of transistor Q8 and the other end connected to the collector of transistor Q12; a resistor R9 connected to the emitter of transistor Q9 and the other end connected to the collector of transistor Q12; a resistor R10 connected to the emitter of transistor Q10 and the other end connected to the collector of transistor Q13; a resistor R11 connected to the emitter of transistor Q11 and the other end connected to the collector of transistor Q13; a resistor R12 connected to the emitter of transistor Q12 and the other end connected to ground; and a resistor R13 connected to the emitter of transistor Q13 and the other end connected to the ground.

[0101] In this embodiment, the adder 126 has a differential input / differential output configuration. To accommodate this configuration, the multipliers 124 and 125 in the second embodiment may be configured as differential output types.

[0102] <Fourth Embodiment> A phase adjustment circuit according to a fourth embodiment of the present invention will be described with reference to FIG.

[0103] In this embodiment, as shown in FIG. 9, the multiplier circuit in the second embodiment and the adder circuit in the third embodiment may be used in combination.

[0104] As shown in FIG. 9, the configuration of this embodiment includes an NPN bipolar transistor Q1_1 having a base to which a control signal IN1n (first control signal) is input and which outputs a positive phase side output signal OUT2p from its collector, an NPN bipolar transistor Q1_2 having a base to which a control signal IN1p (second control signal) is input and which outputs a negative phase side output signal OUT2n from its collector, an NPN bipolar transistor Q1_3 having a base to which a control signal IN1n is input and which outputs a negative phase side output signal OUT2n from its collector, and an NPN bipolar transistor Q1_4 having a base to which a control signal IN1n (second control signal) is input and which outputs a negative phase side output signal OUT2n from its collector. an NPN bipolar transistor Q1_4 to which a signal IN1p is input and which outputs a positive-phase output signal OUT2p from its collector; an NPN bipolar transistor Q1_5 to which a positive-phase signal IN2p of the differential signal output from the buffer unit 121 is input to its base and which has its collector connected to the emitters of the transistors Q1_1 and Q1_2; and an NPN bipolar transistor Q1_5 to which a negative-phase signal IN2n of the differential signal output from the buffer unit 121 is input to its base and which has its collector connected to the emitters of the transistors Q1_3 and Q1_4. an NPN bipolar transistor Q1_6, an NPN bipolar transistor Q1_7 having a base to which a first bias voltage Vb1 is applied, an NPN bipolar transistor Q2_1 having a base to which a control signal IN3n (third control signal) is input and which outputs a positive phase output signal OUT2p from its collector, an NPN bipolar transistor Q2_2 having a base to which a control signal IN3p (fourth control signal) is input and which outputs a negative phase output signal OUT2n from its collector, and an NPN bipolar transistor Q2_2 having a base to which a control signal IN3n is input and which outputs a negative phase output signal OUT2n from its collector. an NPN bipolar transistor Q2_3 that receives a control signal IN3p at its base and outputs a positive-phase output signal OUT2p from its collector; an NPN bipolar transistor Q2_4 that receives a positive-phase signal IN4p of the differential signal output from the delay unit 123 at its base and has its collector connected to the emitters of the transistors Q2_1 and Q2_2; an NPN bipolar transistor Q2_5 that receives a negative-phase signal IN4n of the differential signal output from the delay unit 123 at its base and has its collector connected to the emitters of the transistors Q2_3 and Q2_2;an NPN bipolar transistor Q2_6 connected to the emitter of the transistor Q1_5 and the collector of the transistor Q2_4; an NPN bipolar transistor Q2_7 having a base to which a second bias voltage Vb2 is applied; a resistor R1_1 having one end connected to the power supply voltage VCC and the other end connected to the collectors of the transistors Q1_1, Q1_4, Q2_1, and Q2_4; a resistor R1_2 having one end connected to the power supply voltage VCC and the other end connected to the collectors of the transistors Q1_2, Q1_3, Q2_2, and Q2_3; a resistor R1_3 having one end connected to the emitter of the transistor Q1_5 and the other end connected to the collector of the transistor Q1_7; It is composed of a resistor R1_4 connected to the emitter of the transistor Q1_6 and the other end connected to the collector of the transistor Q1_7, a resistor R1_5 connected to the emitter of the transistor Q1_7 and the other end connected to ground, a resistor R2_3 connected to the emitter of the transistor Q2_5 and the other end connected to the collector of the transistor Q2_7, a resistor R2_4 connected to the emitter of the transistor Q2_6 and the other end connected to the collector of the transistor Q2_7, and a resistor R2_5 connected to the emitter of the transistor Q2_7 and the other end connected to ground.

[0105] The first bias voltage Vb1 and the second bias voltage Vb2 may be different values ​​or may be the same value.

[0106] The gain (A) of the multiplication unit 124 can be controlled by the voltage difference between the control signals IN1p and IN1n, and the gain (B) of the multiplication unit 125 can be controlled by the voltage difference between the control signals IN3p and IN3n. Also, as described in Fig. 9, the differential signal output from the buffer unit 121 may be assigned to IN1p and IN1n, the differential signal output from the delay unit 123 may be assigned to IN3p and IN3n, and IN2p, IN2n, IN4p, and IN4n may be used as control signals.

[0107] Fifth Embodiment A phase adjustment circuit according to a fifth embodiment of the present invention will be described with reference to FIG.

[0108] In this embodiment, an example will be described in which a circuit based on a Gilbert cell is used as the amplitude extraction circuit 141 in the phase adjustment circuit according to the first embodiment.

[0109] As shown in FIG. 10, the amplitude extraction circuit 141 includes an NPN bipolar transistor Q14 having a base input with a negative phase signal IN7n of the differential signal output from the adder 126, an NPN bipolar transistor Q15 having a base input with a positive phase signal IN7p of the differential signal output from the adder 126, an NPN bipolar transistor Q16 having a base and a collector connected together, an NPN bipolar transistor Q17 having a base and a collector connected together, and an NPN bipolar transistor Q18 having a base to which a first bias voltage Vb1 is applied and a collector connected to the emitter of the transistor Q16. an NPN bipolar transistor Q18 having a base connected to the emitter of the transistor Q17; an NPN bipolar transistor Q19 having a base to which a first bias voltage Vb1 is applied and a collector connected to the emitter of the transistor Q17; an NPN bipolar transistor Q20 having a base to which a signal IN7n on the negative phase side of the differential signal output from the adder 126 is input; an NPN bipolar transistor Q21 having a base to which a signal IN7p on the positive phase side of the differential signal output from the adder 126 is input; an NPN bipolar transistor Q22, an NPN bipolar transistor Q23 having a base to which the positive phase signal IN7p of the differential signal output from the adder 126 is input; an NPN bipolar transistor Q24 having a base connected to the base and collector of the transistor Q16 and a collector connected to the emitters of the transistors Q20 and Q21; an NPN bipolar transistor Q25 having a base connected to the base and collector of the transistor Q17 and a collector connected to the emitters of the transistors Q22 and Q23; and an NPN bipolar transistor Q26 having a base to which a second bias voltage Vb2 is applied. a bipolar transistor Q26, a resistor R14 having one end connected to the power supply voltage VCC and the other end connected to the collector of the transistor Q14, a resistor R15 having one end connected to the power supply voltage VCC and the other end connected to the collector of the transistor Q15, a resistor R16 having one end connected to the emitter of the transistor Q14 and the other end connected to the base and collector of the transistor Q16, a resistor R17 having one end connected to the emitter of the transistor Q15 and the other end connected to the base and collector of the transistor Q17, and a resistor R17 having one end connected to the emitter of the transistor Q18,a resistor R18 having one end connected to the emitter of transistor Q19 and the other end connected to ground; a resistor R19 having one end connected to the emitter of transistor Q19 and the other end connected to ground; a resistor R20 having one end connected to the power supply voltage VCC and the other end connected to the collectors of transistors Q20 and Q23; a resistor R21 having one end connected to the power supply voltage VCC and the other end connected to the collectors of transistors Q21 and Q22; a resistor R22 having one end connected to the emitter of transistor Q24 and the other end connected to the collector of transistor Q26; a resistor R23 having one end connected to the emitter of transistor Q25 and the other end connected to the collector of transistor Q26; a resistor R24 ​​connected to the collector of the transistors Q20 and Q23, a resistor R25 having one end connected to the collectors of the transistors Q20 and Q23 and outputting a positive phase output signal OUT3p from the other end, a resistor R26 having one end connected to the collectors of the transistors Q21 and Q22 and outputting a negative phase output signal OUT3n from the other end, a capacitor C1 having one end connected to the collectors of the transistors Q20 and Q23 and the other end connected to ground, a capacitor C2 having one end connected to the collectors of the transistors Q21 and Q22 and the other end connected to ground, a capacitor C3 having one end connected to the other end of the resistor R25 and the other end connected to ground, and a capacitor C4 having one end connected to the other end of the resistor R26 and the other end connected to ground.

[0110] The first bias voltage Vb1 and the second bias voltage Vb2 may be different values ​​or may be the same value.

[0111] In this circuit, the amplitude of the output from adder 126 is squared by a squarer consisting of transistors Q14 to Q26 and resistors R14 to R24, and the squared amplitude is then flattened by a low-pass filter (third low-pass filter or third LPF) consisting of resistors R25 and R26 and capacitors C1 to C4. To achieve this squaring of the amplitude using a Gilbert cell, it is necessary to absorb the difference in the in-phase signal level between the signals input to transistors Q20 to Q23 and the signals input to transistors Q24 and Q25. Therefore, an emitter follower consisting of transistors Q14 to Q19 and resistors R14 to R19 is inserted in the first stage to adjust the in-phase level of the input signals. Note that diode-connected transistors Q16 and Q17 can also be replaced with resistors or diodes.

[0112] In the configuration of this embodiment, the amplitude extraction circuit 141 has a differential input / differential output configuration. To accommodate the configuration of this embodiment, the adder 126 in the third embodiment may be configured as a differential output type.

[0113] Sixth Embodiment A phase adjustment circuit according to a sixth embodiment of the present invention will be described with reference to FIG.

[0114] In this embodiment, an example of the differential amplifier 142 used in the other path (path passing through the amplitude extraction circuit 141) in the first embodiment will be described.

[0115] As shown in FIG. 11, the differential amplifier 142 has a configuration similar to that of the adder shown in the third embodiment, subtracts the amplitude detected by the amplitude extraction circuit 141 from the target amplitude Vref2, and amplifies the amplitude obtained as a result of the subtraction.

[0116] In the differential amplifier 142, the positive-phase signal of the differential signal output from the amplitude extraction circuit 141 is input to the base of the NPN bipolar transistor Q8, the negative-phase signal of the differential signal output from the amplitude extraction circuit 141 is input to the base of the NPN bipolar transistor Q9, the positive-phase signal of the differential signal indicating the target amplitude Vref2 is input to the base or gate of the NPN bipolar transistor Q10, and the negative-phase signal of the differential signal indicating the target amplitude Vref2 is input to the base of the NPN bipolar transistor Q11.

[0117] In the embodiments and examples of the present invention, a filter circuit shown in Fig. 12 may be used as a low-pass filter (LPF) circuit. In addition, an inductor may be used instead of a resistor, or both may be used.

[0118] Although a passive filter has been used in the example, an active filter may also be used. The filter may be either analog or digital. That is, the signal may be AD converted, the filter may operate in the digital domain, and the signal may be converted back to an analog signal by DA conversion.

[0119] In the embodiment and examples of the present invention, an example has been shown in which the amplitude extraction circuit 141 is configured with a squaring device and an LPF, but it may also be configured with a peak extraction circuit as shown in FIG. 13 or a combination of an asynchronous detection circuit and an LPF circuit as shown in FIG. 14.

[0120] Second Embodiment A phase adjustment circuit 30 according to a second embodiment of the present invention will be described with reference to FIGS.

[0121] <Configuration of Phase Adjustment Circuit> As shown in FIG. 15 , the phase adjustment circuit 30 according to this embodiment includes a clock generation circuit 11, a phase interpolation unit 12, a phase extraction circuit 131, a first low-pass filter (first LPF) 132, an amplitude extraction circuit 141, a differential amplification unit 142, a second low-pass filter (second LPF) 143, and an amplitude limiting circuit 31.

[0122] The phase interpolation unit 12 and the path for phase extraction have the same configuration as in the first embodiment.

[0123] The path for amplitude extraction includes an amplitude extraction circuit 141 that detects the amplitude of the output signal of the adder 126, a differential amplifier 142 that subtracts the amplitude detected by the amplitude extraction circuit 141 from the target amplitude Vref2 and amplifies the result, a second low-pass filter (second LPF) 143 that smoothes the output result of the differential amplifier 142 and outputs the smoothed result to the multiplier 125, and an amplitude limiting circuit 31. As described above, in the path for amplitude extraction in the first embodiment, the amplitude limiting circuit 31 is connected downstream of the second low-pass filter (second LPF) 143.

[0124] 16, the amplitude limiting circuit 31 includes an NPN bipolar transistor Q27 having a base to which the control signal IN8n output from the second LPF 143 in the other path is input and from which the negative phase output signal OUT1n is output from the collector, an NPN bipolar transistor Q28 having a base to which the control signal IN8p output from the second LPF 143 is input and from which the positive phase output signal OUT1p is output from the collector, an NPN bipolar transistor Q29 having a base to which a bias voltage (first bias voltage) Vb1 is applied and a collector to which the transistor Q27 is connected, an NPN bipolar transistor Q30 having a base to which a bias voltage (first bias voltage) Vb1 is applied and a collector to which the transistor Q28 is connected, and an NPN bipolar transistor Q31 having a base to which a bias voltage (second bias voltage) Vb1 is applied and a resistor R27 having one end connected to the power supply voltage VCC and the other end connected to the collector of the transistor Q27; a resistor R28 having one end connected to the power supply voltage VCC and the other end connected to the collector of the transistor Q28; a resistor R29 having one end connected to the emitter of the transistor Q29 and the other end connected to ground; a resistor R30 having one end connected to the emitter of the transistor Q30 and the other end connected to ground; a resistor R31 connected to the emitters of the transistor Q27 and the transistor Q28; a resistor R32 having one end connected to the collector of the transistor Q27 and the other end connected to the collector of the transistor Q31; and a resistor R33 having one end connected to the emitter of the transistor Q31 and the other end connected to ground.

[0125] The bias voltage (first bias voltage) Vb1 and the bias voltage (second bias voltage) Vb2 may be different values ​​or may be the same value.

[0126] <Operation> In the phase adjustment circuits according to the first embodiment and the first to sixth examples, during the convergence process in which the phase difference approaches the target value of 90° and stabilizes, the sign of the feedback value of the other path (the path passing through the amplitude extraction circuit 141) may change, possibly resulting in a deterioration in convergence.

[0127] The phase adjustment circuit 30 according to this embodiment includes an amplitude limiting circuit 31. In the amplitude limiting circuit 31, a path formed by an NPN transistor Q31, resistors R32, and resistors R33 functions as a path for extracting current. This provides an offset to the differential output signal, making it possible to make the output value equal to or greater than 0 (zero) V. Details are described below.

[0128] 17 shows the calculation results of the input / output voltage characteristics of the amplitude limiting circuit 31 to explain the effect of the amplitude limiting circuit 31 in the phase adjustment circuit 30. In the figure, the input voltage is the voltage difference between the positive-phase and negative-phase differential signals (IN8p and IN8n) input to the NPN transistors Q27 and Q28. The output voltage is the voltage difference between the positive-phase and negative-phase differential signals (OUT4p and OUT4n) output from the NPN transistors Q27 and Q28.

[0129] The calculation was performed using the electronic circuit simulator "SPICE." The size of the NPN transistor Q27 and the size of the NPN transistor Q28 were assumed to be different. The size of the transistor is determined by the multiplication factor or emitter length of the transistor.

[0130] For comparison, FIG. 18 shows the calculation results of the input / output characteristics when no path for extracting current is provided.

[0131] If no path for drawing out the current is provided, the differential output signal varies between −0.7 V and 0.7 V, as shown in FIG.

[0132] On the other hand, in the amplitude limiting circuit 31 in which a path for drawing out current is arranged, the differential output signal varies between 0 V and 1.4 V, as shown in Figure 17. In this way, the NPN transistor Q31 in the amplitude limiting circuit 31 draws current from the node at one end, thereby lowering the voltage to a predetermined level. As a result, it is possible to output a voltage of 0 (zero) V or higher for any input.

[0133] More specifically, a predetermined amount of current is extracted from the negative-phase output signal OUT4n by the NPN bipolar transistor Q27. As a result, an offset Voffset is applied to the output differential value (Vp-Vn) between the output signals OUT4p and OUT4n, and Vp-(Vn-Voffset)=Vp-Vn+Voffset is output. For example, in this embodiment, by configuring a path for extracting current so that an offset Voffset of about 0.7 V is applied, it is possible to output a voltage of 0 (zero) V or higher.

[0134] Similar calculations were also performed for a configuration in which the size of NPN transistor Q27 and the size of NPN transistor Q28 were the same. Figures 19 and 20 show the calculation results for the cases in which a path for extracting current is provided and not provided, respectively.

[0135] When a path for drawing out current is not provided, the differential output signal varies between −0.7 V and 0.7 V, as shown in Fig. 20. On the other hand, when a path for drawing out current is provided, the differential output signal varies between 0 V and 1.4 V, as shown in Fig. 19.

[0136] In this way, regardless of the size of the NPN transistor Q27 and the size of the NPN transistor Q28, a voltage equal to or greater than zero can be output by using a path that draws out current.

[0137] In the amplitude limiting circuit 31 of this embodiment, the offset amount may be adjusted by changing the size of the transistor Q31 and the sizes of the transistors Q27 and Q28. The amount of current drawn may also be adjusted by changing the resistor R33 on the emitter side of the transistor Q31. The amount of current drawn may also be adjusted by changing the bias voltage Vb2. The bias voltage Vb2 may be the same as or different from the bias voltage Vb1.

[0138] In the present embodiment, an example has been shown in which the resistor R31 for degeneration is provided to adjust the gain, but the resistor R31 does not necessarily have to be provided.

[0139] According to the phase adjustment circuit of this embodiment, during the convergence process in which the phase difference approaches the target value of 90° and stabilizes, the feedback value of the other path (the path via the amplitude extraction circuit 141) can be maintained at a value greater than or equal to zero without changing its positive or negative sign, thereby improving the convergence of the phase difference.

[0140] Although the embodiment of the present invention shows an example in which a bipolar transistor is used, a MOS transistor may also be used. In the case of using a MOS transistor, the base may be replaced with a gate, the collector with a drain, and the emitter with a source in the above description.

[0141] In the embodiments of the present invention, examples of the structure, dimensions, materials, etc. of each component in the configuration of the phase adjustment circuit etc. are shown, but the present invention is not limited to these. Anything that can demonstrate the function and effect of the phase adjustment circuit can be used.

[0142] It should be noted that the present invention is not limited to the above-described embodiments, and it is clear that many modifications and combinations can be made by a person skilled in the art within the technical spirit of the present invention. For example, the second embodiment may be combined with the first to sixth examples.

[0143] A part or all of the above-described embodiment or an example thereof can be described as, but is not limited to, the following supplementary notes.

[0144] (Supplementary Note 1) A clock generation circuit that generates a first sine wave signal, a first multiplier that multiplies the amplitude of the first sine wave signal by a first variable, a delay unit that delays the first sine wave signal, a second multiplier that multiplies the amplitude of a second sine wave signal output from the delay unit by a second variable, an adder that adds a signal output from the first multiplier and a signal output from the second multiplier, a phase extraction circuit that detects a phase difference between the first sine wave signal and an output signal from the adder, and a phase detector that flattens an output result of the phase extraction circuit and multiplies the amplitude by the first variable. an amplitude extraction circuit that detects the amplitude of the output signal of the addition unit; a differential amplification unit that subtracts the amplitude detected by the amplitude extraction circuit from a target amplitude and amplifies the amplitude obtained as a result of the subtraction; and a second low-pass filter that flattens the output result of the differential amplification unit and outputs a control signal that determines the second variable to the second multiplication unit, wherein transfer functions of the first low-pass filter and the second low-pass filter are stable.

[0145] (Supplementary Note 2) The phase adjustment circuit according to Supplementary Note 1, which adjusts the phase difference of the sine wave signals output from the adding unit so that it approaches 90°.

[0146] (Supplementary Note 3) The phase adjustment circuit according to Supplementary Note 1 or Supplementary Note 2, wherein the phase difference ρ of the sine wave signals output from the adding unit is expressed by equation (A).

[0147] Here, A is the first variable, B is the second variable, and φ is the phase difference given by the delay unit.

[0148] (Supplementary Note 4) The first multiplication unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor, a first control signal or a signal having a negative phase of the first sine wave signal is input to a base or a gate of the first transistor, a positive phase signal is output from a collector or a drain of the first transistor, and a second control signal or a signal having a negative phase of the first sine wave signal is input to a base or a gate of the second transistor. the positive-phase signal of the first sine wave signal is input to the base or gate of the third transistor, and the negative-phase signal is output from the collector or drain of the third transistor; the positive-phase signal of the second control signal or the positive-phase signal of the first sine wave signal is input to the base or gate of the fourth transistor, and the positive-phase signal of the fourth transistor is output from the collector or drain of the fourth transistor; a positive-phase signal of the first sine wave signal or the second control signal is input to a base or gate of the fifth transistor, a collector or drain of the fifth transistor is connected to an emitter or source of the first and second transistors, a negative-phase signal of the first sine wave signal or the first control signal is input to a base or gate of the sixth transistor, a collector or drain of the fifth transistor is connected to an emitter or source of the third and fourth transistors, a bias voltage is applied to a base or gate of the seventh transistor, one end of the first resistor is connected to a power supply voltage, the other end of the first resistor is connected to the collectors or drains of the first and fourth transistors, one end of the second resistor is connected to the power supply voltage, the other end of the second resistor is connected to the collectors or drains of the second and third transistors, one end of the third resistor is connected to the emitter or source of the fifth transistor, and the other end of the third resistor is connected to the collector or drain of the seventh transistor;One end of the fourth resistor is connected to the emitter or source of the sixth transistor, the other end of the fourth resistor is connected to the collector or drain of the seventh transistor, one end of the fifth resistor is connected to the emitter or source of the seventh transistor, and the other end of the fifth resistor is connected to ground, and the second multiplication unit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, the sixth resistor, the seventh resistor, and the eighth transistor. a resistor, a ninth resistor, and a tenth resistor, wherein a third control signal or a signal on the negative phase side of the second sine wave signal in a differential format is input to the base or gate of the eighth transistor, a signal on the positive phase side is output from the collector or drain of the eighth transistor, a fourth control signal or a signal on the positive phase side of the second sine wave signal is input to the base or gate of the ninth transistor, a signal on the negative phase side is output from the collector or drain of the ninth transistor, and the third control signal or The negative-phase signal of the second sine wave signal is input to the base or gate of the tenth transistor, the negative-phase signal is output from the collector or drain of the tenth transistor, the fourth control signal or the positive-phase signal of the second sine wave signal is input to the base or gate of the eleventh transistor, the positive-phase signal is output from the collector or drain of the eleventh transistor, the positive-phase signal of the second sine wave signal or the fourth control signal is input to the base or gate of the twelfth transistor, and the collector or drain of the twelfth transistor is connected to the collector or drain of the eighth and ninth transistors. a collector or drain of the thirteenth transistor connected to the emitters or sources of the tenth and eleventh transistors, a signal having a reverse phase of the second sine wave signal or the third control signal is input to the base or gate of the thirteenth transistor, a collector or drain of the thirteenth transistor connected to the emitters or sources of the tenth and eleventh transistors, a bias voltage is applied to the base or gate of the fourteenth transistor, one end of the sixth resistor is connected to the power supply voltage, and the other end of the sixth resistor is connected to the collectors or drains of the eighth and eleventh transistors,The phase adjustment circuit according to any one of Supplementary Note 1 to Supplementary Note 3, wherein one end of the seventh resistor is connected to the power supply voltage, the other end of the seventh resistor is connected to the collector or drain of the ninth and tenth transistors, one end of the eighth resistor is connected to the emitter or source of the twelfth transistor, the other end of the eighth resistor is connected to the collector or drain of the fourteenth transistor, one end of the ninth resistor is connected to the emitter or source of the thirteenth transistor, the other end of the ninth resistor is connected to the collector or drain of the fourteenth transistor, one end of the tenth resistor is connected to the emitter or source of the fourteenth transistor, and the other end of the tenth resistor is connected to ground.

[0149] (Supplementary Note 5) The adder unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor, wherein a negative phase signal of the differential signal output from the first multiplier unit is input to a base or gate of the first transistor, a positive phase signal is output from a collector or drain of the first transistor, and a negative phase signal of the differential signal is output from a base or gate of the second transistor. a positive-phase signal of the differential signal output from the first multiplier unit is input to the first transistor, a negative-phase signal is output from the collector or drain of the second transistor, a positive-phase signal of the differential signal output from the second multiplier unit is input to the base or gate of the third transistor, a negative-phase signal is output from the collector or drain of the third transistor, a negative-phase signal of the differential signal output from the second multiplier unit is input to the base or gate of the fourth transistor, and a positive-phase signal is output from the collector or drain of the fourth transistor. a bias voltage is applied to the bases or gates of the fifth and sixth transistors, one end of the first resistor is connected to a power supply voltage, the other end of the first resistor is connected to the collectors or drains of the first and fourth transistors, one end of the second resistor is connected to the power supply voltage, the other end of the second resistor is connected to the collectors or drains of the second and third transistors, one end of the third resistor is connected to the emitter or source of the first transistor, and the other end of the third resistor is connected to the collector or drain of the fifth transistor one end of the fourth resistor is connected to the emitter or source of the second transistor, the other end of the fourth resistor is connected to the collector or drain of the fifth transistor, one end of the fifth resistor is connected to the emitter or source of the third transistor, the other end of the fifth resistor is connected to the collector or drain of the sixth transistor, one end of the sixth resistor is connected to the emitter or source of the fourth transistor, and the other end of the sixth resistor is connected to the collector or drain of the sixth transistor;The phase adjustment circuit according to any one of Supplementary Note 1 to Supplementary Note 4, wherein one end of the seventh resistor is connected to the emitter or source of the fifth transistor, the other end of the seventh resistor is connected to ground, one end of the eighth resistor is connected to the emitter or source of the sixth transistor, and the other end of the eighth resistor is connected to ground.

[0150] (Supplementary Note 6) The phase adjustment circuit according to any one of Supplementary Notes 1 to 5, wherein the amplitude extraction circuit includes a squarer configured to square the output amplitude of the adder, and a third low-pass filter that flattens the amplitude squared by the squarer.

[0151] (Supplementary Note 7) The phase adjustment circuit according to any one of Supplementary Notes 1 to 6 or Supplementary Note 9, further comprising an amplitude limiting circuit between the second low-pass filter and the second multiplication unit, wherein the amplitude limiting circuit extracts a predetermined current from an input current and outputs a voltage equal to or greater than zero.

[0152] (Supplementary Note 8) The amplitude limiting circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor, a third control signal output from the second low-pass filter is input to the base of the first transistor, an output signal on the negative phase side is output from the collector of the first transistor, a fourth control signal output from the second low-pass filter is input to the base of the first transistor, an output signal on the positive phase side is output from the collector of the first transistor, a first bias voltage is applied to the base of the third transistor, the collector of the third transistor is connected to the emitter of the first transistor, the first bias voltage is applied to the base of the fourth transistor, the collector of the fourth transistor is connected to the emitter of the second transistor, and the base of the fifth transistor is connected to the emitter of the a second bias voltage is applied to the source, one end of the first resistor is connected to a power supply voltage, the other end of the first resistor is connected to a collector of the first transistor, one end of the second resistor is connected to the power supply voltage, the other end of the second resistor is connected to the collector of the second transistor, one end of the third resistor is connected to an emitter of the third transistor, the other end of the third resistor is connected to ground, one end of the fourth resistor is connected to an emitter of the fourth transistor, the other end of the fourth resistor is connected to ground, one end of the fifth resistor is connected to the emitter of the first transistor, the other end of the fifth resistor is connected to the emitter of the second transistor, one end of the sixth resistor is connected to the collector of the first transistor, the other end of the sixth resistor is connected to the collector of the fifth transistor, one end of the seventh resistor is connected to the emitter of the fifth transistor, and the other end of the seventh resistor is connected to ground.

[0153] (Supplementary Note 9) The squarer includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and an eleventh resistor, a negative-phase signal of the differential signal output from the adder is input to the base of the first transistor, a positive-phase signal of the differential signal output from the adder is input to the base of the second transistor, the base and collector of the third transistor are connected, the base and collector of the fourth transistor are connected, a bias voltage is applied to the base of the fifth transistor, the collector of the fifth transistor is connected to the emitter of the third transistor, a bias voltage is applied to the base of the sixth transistor, the collector of the sixth transistor is connected to the emitter of the fourth transistor, the negative-phase signal of the differential signal output from the adder is input to the base of the seventh transistor, the positive-phase signal of the differential signal output from the adder is input to the base of the eighth transistor, the negative-phase signal of the differential signal output from the adder is input to the base of the ninth transistor, the positive-phase signal of the differential signal output from the adder is input to the base of the tenth transistor, and the base of the eleventh transistor is connected to the base and collector of the third transistor. a collector of the eleventh transistor is connected to the emitters of the seventh and eighth transistors, a base of the twelfth transistor is connected to the base and collector of the fourth transistor, a collector of the twelfth transistor is connected to the emitters of the ninth and tenth transistors, a bias voltage is applied to the base of the thirteenth transistor, one end of the first resistor is connected to a power supply voltage, the other end of the first resistor is connected to the collector of the first transistor, and one end of the second resistor is connected to the power supply voltage;The other end of the second resistor is connected to the collector of the second transistor, one end of the third resistor is connected to the emitter of the first transistor, the other end of the third resistor is connected to the base and collector of the third transistor, one end of the fourth resistor is connected to the emitter of the second transistor, the other end of the fourth resistor is connected to the base and collector of the fourth transistor, one end of the fifth resistor is connected to the emitter of the fifth transistor, the other end of the fifth resistor is connected to ground, and one end of the sixth resistor is the other end of the sixth resistor is connected to the emitter of the sixth transistor, the other end of the sixth resistor is connected to ground, one end of the seventh resistor is connected to the power supply voltage, the other end of the seventh resistor is connected to the collectors of the seventh and tenth transistors, one end of the eighth resistor is connected to the power supply voltage, the other end of the eighth resistor is connected to the collectors of the eighth and ninth transistors, one end of the ninth resistor is connected to the emitter of the eleventh transistor, the other end of the ninth resistor is connected to the collector of the thirteenth transistor, one end of the tenth resistor is connected to the emitter of the twelfth transistor, the other end of the tenth resistor is connected to the collector of the thirteenth transistor, one end of the eleventh resistor is connected to the emitter of the thirteenth transistor, and the other end of the eleventh resistor is connected to ground; the third low-pass filter includes a twelfth resistor, a thirteenth resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; one end of the twelfth resistor is connected to the collectors of the seventh and tenth transistors; a first end of the thirteenth resistor connected to the collectors of the eighth and ninth transistors and a second end of the thirteenth resistor connected to the collectors of the seventh and tenth transistors and a third end of the third capacitor connected to the ground; one end of the third capacitor connected to the other end of the twelfth resistor and a fourth end of the third capacitor connected to the ground;7. The phase adjustment circuit according to claim 6, wherein one end of the fourth capacitor is connected to the other end of the thirteenth resistor, and the other end of the fourth capacitor is connected to ground.

[0154] (Supplementary Note 10) The amplitude detection unit includes a first diode, a second diode, a third diode, a fourth diode, a fourth low-pass filter, and a fifth low-pass filter, and the positive-phase signal of the differential signal output from the adder is input to the cathode of the first diode, the positive-phase signal of the differential signal output from the adder is input to the anode of the second diode, the negative-phase signal of the differential signal output from the adder is input to the cathode of the third diode, and the anode of the third diode is connected to the first low-pass filter. the anode of the fourth diode is connected to the anode of the third diode, a signal of a reverse phase side of the differential signal output from the adder is input to the anode of the fourth diode, the cathode of the fourth diode is connected to the cathode of the second diode, the fourth low-pass filter flattens the signal at the connection point of the anode of the first diode and the anode of the third diode, and the fifth low-pass filter flattens the signal at the connection point of the cathode of the second diode and the cathode of the fourth diode.

[0155] (Supplementary Note 11) The differential amplifier unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor, wherein a negative phase signal of the differential signal output from the amplitude extraction circuit is input to a base or a gate of the first transistor, a positive phase signal is output from a collector or a drain of the first transistor, and a negative phase signal of the differential signal is output from a collector or a drain of the second transistor. Alternatively, the positive-phase signal of the differential signal output from the amplitude extraction circuit is input to the gate of the second transistor, the negative-phase signal is output from the collector or drain of the second transistor, the positive-phase signal of the differential signal indicating the target amplitude is input to the base or gate of the third transistor, the negative-phase signal is output from the collector or drain of the third transistor, the negative-phase signal of the differential signal indicating the target amplitude is input to the base or gate of the fourth transistor, the positive-phase signal is output from the collector or drain of the fourth transistor, A bias voltage is applied to the bases or gates of the fifth and sixth transistors, one end of the first resistor is connected to a power supply voltage, the other end of the first resistor is connected to the collectors or drains of the first and fourth transistors, one end of the second resistor is connected to the power supply voltage, the other end of the second resistor is connected to the collectors or drains of the second and third transistors, one end of the third resistor is connected to the emitter or source of the first transistor, and the other end of the third resistor is connected to the collector or drain of the fifth transistor. one end of the fourth resistor is connected to the emitter or source of the second transistor, the other end of the fourth resistor is connected to the collector or drain of the fifth transistor, one end of the fifth resistor is connected to the emitter or source of the third transistor, the other end of the fifth resistor is connected to the collector or drain of the sixth transistor, one end of the sixth resistor is connected to the emitter or source of the fourth transistor, and the other end of the sixth resistor is connected to the collector or drain of the sixth transistor;The phase adjustment circuit according to any one of Supplementary Note 1 to Supplementary Note 10, wherein one end of the seventh resistor is connected to the emitter or source of the fifth transistor, the other end of the seventh resistor is connected to ground, one end of the eighth resistor is connected to the emitter or source of the sixth transistor, and the other end of the eighth resistor is connected to ground.

[0156] (Supplementary Note 12) The first and second multiplication units and the addition unit include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor. a first control signal or a negative-phase signal of the first sine wave signal in a differential format is input to the base or gate of the first transistor, a positive-phase signal is output from the collector or drain of the first transistor, a second control signal or a positive-phase signal of the first sine wave signal is input to the base or gate of the second transistor, a negative-phase signal is output from the collector or drain of the second transistor, and the first control signal or the negative-phase signal of the first sine wave signal is input to the base or gate of the third transistor, a negative-phase signal is output from the collector or drain of the third transistor; the second control signal or the positive-phase signal of the first sine wave signal is input to the base or gate of the fourth transistor; a positive-phase signal is output from the collector or drain of the fourth transistor; the positive-phase signal of the first sine wave signal or the second control signal is input to the base or gate of the fifth transistor; the collector or drain of the fifth transistor is connected to the emitters or sources of the first and second transistors; the negative-phase signal of the first sine wave signal or the first control signal is input to the base or gate of the sixth transistor; the collector or drain of the sixth transistor is connected to the emitters or sources of the third and fourth transistors; a bias voltage is applied to the base or gate of the seventh transistor; the third control signal or the negative-phase signal of the second sine wave signal in a differential format is input to the base or gate of the eighth transistor; and a positive-phase signal is output from the collector or drain of the eighth transistor;The fourth control signal or the positive-phase signal of the second sine wave signal is input to the base or gate of the ninth transistor, and the negative-phase signal is output from the collector or drain of the ninth transistor. The third control signal or the negative-phase signal of the second sine wave signal is input to the base or gate of the tenth transistor, and the negative-phase signal is output from the collector or drain of the tenth transistor. The fourth control signal or the positive-phase signal of the second sine wave signal is input to the base or gate of the eleventh transistor, and the positive-phase signal is output from the collector or drain of the eleventh transistor. The positive-phase signal of the second sine wave signal or the fourth control signal is input to the base or gate of the twelfth transistor. The collector or drain of the twelfth transistor is connected to the emitters or sources of the eighth and ninth transistors. The negative-phase signal of the second sine wave signal or the third control signal is input to the base or gate of the thirteenth transistor, and the collector or drain of the thirteenth transistor is connected to the emitters or sources of the eighth and ninth transistors. a bias voltage is applied to the base or gate of the fourteenth transistor; one end of the first resistor is connected to a power supply voltage; the other end of the first resistor is connected to the collectors or drains of the first, fourth, eighth and eleventh transistors; one end of the second resistor is connected to the power supply voltage; the other end of the second resistor is connected to the collectors or drains of the second, third, ninth and tenth transistors; and one end of the third resistor is connected to the fifth the other end of the third resistor is connected to the collector or drain of the seventh transistor, one end of the fourth resistor is connected to the emitter or source of the sixth transistor, the other end of the fourth resistor is connected to the collector or drain of the seventh transistor, one end of the fifth resistor is connected to the emitter or source of the seventh transistor, the other end of the fifth resistor is connected to ground, and one end of the sixth resistor is connected to the emitter or source of the twelfth transistor,The phase adjustment circuit according to any one of Supplementary Note 1 to Supplementary Note 11, wherein the other end of the sixth resistor is connected to the collector or drain of the fourteenth transistor, one end of the seventh resistor is connected to the emitter or source of the thirteenth transistor, the other end of the seventh resistor is connected to the collector or drain of the fourteenth transistor, one end of the eighth resistor is connected to the emitter or source of the fourteenth transistor, and the other end of the eighth resistor is connected to ground.

[0157] (Supplementary Note 13) The phase adjustment circuit according to any one of Supplementary Note 1 to Supplementary Note 12, wherein the cutoff frequency of the second low-pass filter is lower than the cutoff frequency of the first low-pass filter.

[0158] The present invention relates to a phase adjustment circuit for a sine wave signal, and can be applied to communication devices and communication systems.

[0159] REFERENCE SIGNS LIST 10 Phase adjustment circuit 11 Clock generation circuit 124 First multiplication unit 123 Delay unit 125 Second multiplication unit 126 Addition unit 131 Phase extraction circuit 132 First low-pass filter 141 Amplitude extraction circuit 142 Differential amplification unit 143 Second low-pass filter

Claims

1. A clock generation circuit that generates a first sine wave signal, a first multiplication unit that multiplies the amplitude of the first sine wave signal by a first variable, a delay unit that delays the first sine wave signal, a second multiplication unit that multiplies the amplitude of a second sine wave signal output from the delay unit by a second variable, an addition unit that adds a signal output from the first multiplication unit and a signal output from the second multiplication unit, a phase extraction circuit that detects a phase difference between the first sine wave signal and an output signal of the addition unit, a first low-pass filter that smoothes an output result of the phase extraction circuit and outputs a control signal that determines the first variable to the first multiplication unit, an amplitude extraction circuit that detects the amplitude of the output signal of the addition unit, a differential amplification unit that subtracts the amplitude detected by the amplitude extraction circuit from a target amplitude and amplifies the amplitude obtained as a result of the subtraction, and a second low-pass filter that smoothes an output result of the differential amplification unit and outputs a control signal that determines the second variable to the second multiplication unit, A phase adjustment circuit, wherein the transfer functions of the first low-pass filter and the second low-pass filter are stable.

2. The phase adjustment circuit according to claim 1, which adjusts the phase difference of the sine wave signals output from said adder section so as to approach 90°.

3. A phase adjustment circuit according to claim 1 or 2, wherein the phase difference ρ of the sine wave signal output from the adder is expressed by equation (A). Here, A is the first variable, B is the second variable, and φ is the phase difference provided by the delay unit.

4. The first multiplication unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor, wherein a first control signal or a negative phase signal of the first sine wave signal is input to a base or gate of the first transistor, and a positive phase signal is output from a collector or drain of the first transistor, a second control signal or a positive phase signal of the first sine wave signal is input to a base or gate of the second transistor, and a negative phase signal is output from a collector or drain of the second transistor, the first control signal or the negative phase signal of the first sine wave signal is input to a base or gate of the third transistor, and a negative phase signal is output from the collector or drain of the third transistor, the second control signal or the positive phase signal of the first sine wave signal is input to a base or gate of the fourth transistor, and the positive phase signal is output from a collector or drain of the fourth transistor; the positive phase signal of the first sine wave signal or the second control signal is input to a base or gate of the fifth transistor, and the collector or drain of the fifth transistor is connected to the emitters or sources of the first and second transistors; the negative phase signal of the first sine wave signal or the first control signal is input to a base or gate of the sixth transistor, and the collector or drain of the fifth transistor is connected to the emitters or sources of the third and fourth transistors; a bias voltage is applied to the base or gate of the seventh transistor; one end of the first resistor is connected to a power supply voltage, and the other end of the first resistor is connected to the collectors or drains of the first and fourth transistors; one end of the second resistor is connected to the power supply voltage, and the other end of the second resistor is connected to the collectors or drains of the second and third transistors;one end of the third resistor is connected to the emitter or source of the fifth transistor, and the other end of the third resistor is connected to the collector or drain of the seventh transistor, one end of the fourth resistor is connected to the emitter or source of the sixth transistor, and the other end of the fourth resistor is connected to the collector or drain of the seventh transistor, one end of the fifth resistor is connected to the emitter or source of the seventh transistor, and the other end of the fifth resistor is connected to ground, the second multiplication unit comprises an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor, a third control signal or a negative phase signal of the second sine wave signal in a differential format is input to a base or gate of the eighth transistor, and a positive phase signal is output from a collector or drain of the eighth transistor; a fourth control signal or a positive phase signal of the second sine wave signal is input to a base or gate of the ninth transistor, and a negative phase signal is output from a collector or drain of the ninth transistor; a third control signal or a negative phase signal of the second sine wave signal is input to a base or gate of the tenth transistor, and a negative phase signal is output from a collector or drain of the tenth transistor; a fourth control signal or a positive phase signal of the second sine wave signal is input to a base or gate of the eleventh transistor, and a positive phase signal is output from a collector or drain of the eleventh transistor; a positive phase signal of the second sine wave signal or the fourth control signal is input to a base or a gate of the twelfth transistor, and a collector or a drain of the twelfth transistor is connected to the emitters or sources of the eighth and ninth transistors,a signal having an inverse phase of the second sine wave signal or the third control signal is input to a base or gate of the thirteenth transistor, and a collector or drain of the thirteenth transistor is connected to the emitters or sources of the tenth and eleventh transistors; a bias voltage is applied to a base or gate of the fourteenth transistor; one end of the sixth resistor is connected to the power supply voltage, and the other end of the sixth resistor is connected to the collectors or drains of the eighth and eleventh transistors; one end of the seventh resistor is connected to the power supply voltage, and the other end of the seventh resistor is connected to the collectors or drains of the ninth and tenth transistors; one end of the eighth resistor is connected to the emitter or source of the twelfth transistor, and the other end of the eighth resistor is connected to the collector or drain of the fourteenth transistor; one end of the ninth resistor is connected to the emitter or source of the thirteenth transistor, and the other end of the ninth resistor is connected to the collector or drain of the fourteenth transistor; 3. The phase adjustment circuit according to claim 1, wherein one end of the tenth resistor is connected to the emitter or source of the fourteenth transistor, and the other end of the tenth resistor is connected to ground.

5. The adder unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor, wherein a negative phase signal of the differential signal output from the first multiplier unit is input to a base or gate of the first transistor, and a positive phase signal is output from a collector or drain of the first transistor, a positive phase signal of the differential signal output from the first multiplier unit is input to a base or gate of the second transistor, and a negative phase signal is output from a collector or drain of the second transistor, a positive phase signal of the differential signal output from the second multiplier unit is input to a base or gate of the third transistor, and a negative phase signal is output from a collector or drain of the third transistor, a negative phase signal of the differential signal output from the second multiplier unit is input to a base or gate of the fourth transistor, and a positive phase signal is output from a collector or drain of the fourth transistor; a bias voltage is applied to the bases or gates of the fifth and sixth transistors; one end of the first resistor is connected to a power supply voltage, and the other end of the first resistor is connected to the collectors or drains of the first and fourth transistors; one end of the second resistor is connected to the power supply voltage, and the other end of the second resistor is connected to the collectors or drains of the second and third transistors; one end of the third resistor is connected to the emitter or source of the first transistor, and the other end of the third resistor is connected to the collector or drain of the fifth transistor; one end of the fourth resistor is connected to the emitter or source of the second transistor, and the other end of the fourth resistor is connected to the collector or drain of the fifth transistor; one end of the fifth resistor is connected to the emitter or the source of the third transistor, and the other end of the fifth resistor is connected to the collector or the drain of the sixth transistor;3. The phase adjustment circuit according to claim 1, wherein one end of the sixth resistor is connected to the emitter or source of the fourth transistor and the other end of the sixth resistor is connected to the collector or drain of the sixth transistor, one end of the seventh resistor is connected to the emitter or source of the fifth transistor and the other end of the seventh resistor is connected to ground, and one end of the eighth resistor is connected to the emitter or source of the sixth transistor and the other end of the eighth resistor is connected to ground.

6. A phase adjustment circuit as claimed in claim 1 or 2, wherein the amplitude extraction circuit comprises: a squarer configured to square the output amplitude of the addition unit; and a third low-pass filter that flattens the amplitude squared by the squarer.

7. A phase adjustment circuit as claimed in claim 1 or 2, further comprising an amplitude limiting circuit between said second low-pass filter and said second multiplication section, said amplitude limiting circuit extracting a predetermined current from an input current and outputting a voltage equal to or greater than zero.

8. The amplitude limiting circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; a third control signal output from the second low-pass filter is input to a base of the first transistor, and an output signal on the negative phase side is output from the collector of the first transistor; a fourth control signal output from the second low-pass filter is input to a base of the first transistor, and an output signal on the positive phase side is output from the collector of the first transistor; a first bias voltage is applied to the base of the third transistor, and the collector of the third transistor is connected to the emitter of the first transistor; the first bias voltage is applied to the base of the fourth transistor, and the collector of the fourth transistor is connected to the emitter of the second transistor; a second bias voltage is applied to the base of the fifth transistor; one end of the first resistor is connected to a power supply voltage and the other end of the first resistor is connected to the collector of the first transistor; one end of the second resistor is connected to the power supply voltage and the other end of the second resistor is connected to the collector of the second transistor; one end of the third resistor is connected to the emitter of the third transistor and the other end of the third resistor is connected to ground; one end of the fourth resistor is connected to the emitter of the fourth transistor and the other end of the fourth resistor is connected to ground; one end of the fifth resistor is connected to the emitter of the first transistor and the other end of the fifth resistor is connected to the emitter of the second transistor; one end of the sixth resistor is connected to the collector of the first transistor and the other end of the sixth resistor is connected to the collector of the fifth transistor; 8. The phase adjustment circuit according to claim 7, wherein one end of the seventh resistor is connected to the emitter of the fifth transistor, and the other end of the seventh resistor is connected to ground.

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