Voltage selection circuit for power supply circuit

Abstract

Disclosed in the present invention is a voltage selection circuit for a power supply circuit. The voltage selection circuit comprises: a voltage comparison module, a first level shift module, and a second level shift module. The voltage comparison module comprises a high-voltage turn-on module, a low-voltage mirror module, and an inverter signal output module. The first level shift module comprises a first level shift branch and a second level shift branch. The second level shift module comprises a third level shift branch and a fourth level shift branch. A first supply voltage V1 and a second supply voltage V2 are inputted into the voltage comparison module, and the voltage comparison module outputs a first control signal V1H and a second control signal V2H; the first control signal V1H is used for controlling the first level shift module so as to control the output of the first supply voltage V1 to a voltage output end of the voltage selection circuit, and the second control signal V2H is used for controlling the second level shift module so as to control the output of the second supply voltage V2 to the voltage output end of the voltage selection circuit.

Description

Voltage selection circuit for power supply circuit Technical Field

[0001] The present invention relates to the technical field of power supply technology, and in particular to a voltage selection circuit for a power supply circuit. Background Art

[0002] In the design of power supply circuits in the prior art, multiple supply voltages often power the power supply circuit. In order to ensure reliable and stable operation of the power supply circuit, for example, when some supply voltages have been powered on while others have not yet been established (for example, the supply voltages are generated by a BOOST circuit), it is necessary to select a higher voltage supply voltage to power the power supply circuit.

[0003] However, the currently disclosed power supply circuits have the problem of a narrow supply voltage application range and cannot be applied to both high and low voltage domains. Alternatively, when the supply voltage switches between different voltage domains, the power supply circuit may suffer from leakage.

[0004] In view of this, the technical purpose of the present invention is to design a new voltage selection circuit for a power supply circuit, which can operate in a high voltage domain (such as 40V) and can effectively avoid leakage through parasitic body diodes between different voltage domains.

[0005] Summary of the Invention

[0006] The technical purpose to be achieved by the present invention is to provide a voltage selection circuit for a power supply circuit, so that it can automatically select and output a high power supply voltage under high voltage application conditions to power the entire circuit; and there is no leakage problem between different voltage domains, thereby improving circuit reliability.

[0007] The present invention provides a voltage selection circuit for a power supply circuit, the voltage selection circuit comprising: a voltage comparison module 1, a first level shift module 2, and a second level shift module 3; the voltage comparison module 1 comprises a high-voltage conduction module 11, a low-voltage mirror module 12, and an inverter signal output module 13; the first level shift module 2 comprises a first level shift branch 21 and a second level shift branch 22; the second level shift module 3 comprises a third level shift branch 31 and a fourth level shift branch 32;

[0008] The first supply voltage V1 and the second supply voltage V2 are input into the voltage comparison module 1, and the voltage comparison module 1 outputs a first control signal V 1H and the second control signal V 2H , the first control signal V 1H When the first power supply voltage V1 is high, it indicates that the first power supply voltage V1 is higher than the second power supply voltage V2, and the second control signal V2H When it is at a high level, it indicates that the first supply voltage V1 is lower than the second supply voltage V2;

[0009] The first control signal V 1H is used to control the first level shift module 2 to control the first supply voltage V1 to be output to the voltage output terminal of the voltage selection circuit; the second control signal V 2H It is used to control the second level shift module 3 to control the second supply voltage V2 to be output to the voltage output terminal of the voltage selection circuit.

[0010] In one embodiment, the high-voltage conduction module 11 includes a first high-voltage PMOS transistor PH1, a second high-voltage PMOS transistor PH2, a first high-voltage NMOS transistor NH1, and a second high-voltage NMOS transistor NH2, wherein the source of the first high-voltage PMOS transistor PH1 is connected to the first power supply voltage V1, the gate of the first high-voltage PMOS transistor PH1 is connected to its own drain, the source of the second high-voltage PMOS transistor PH2 is connected to the second power supply voltage V2, and the gate of the second high-voltage PMOS transistor PH2 is connected to the gate of the first high-voltage PMOS transistor PH1; the drain of the first high-voltage NMOS transistor NH1 is connected to the drain of the first high-voltage PMOS transistor PH1, and the gate of the first high-voltage NMOS transistor NH1 is connected to the external low-voltage power supply voltage V L The drain of the second high-voltage NMOS transistor NH2 is connected to the drain of the second high-voltage PMOS transistor PH2, and the gate of the second high-voltage NMOS transistor NH2 is also connected to the external low-voltage power supply voltage V L .

[0011] In one embodiment, the low-voltage mirror module 12 includes a first low-voltage NMOS transistor NM1, a second low-voltage NMOS transistor NM2, and a third low-voltage NMOS transistor NM3; the drain of the first low-voltage NMOS transistor NM1 is connected to the external bias current I B The source of the first low-voltage NMOS transistor NM1 is grounded, and the drain of the first low-voltage NMOS transistor NM1 is connected to its own gate; the drain of the second low-voltage NMOS transistor NM2 is connected to the source of the first high-voltage NMOS transistor NH1, and the source of the second low-voltage NMOS transistor NM2 is grounded. At the same time, the gate of the second low-voltage NMOS transistor NM2 is connected to the external bias current I B The drain of the third low-voltage NMOS tube NM3 is connected to the source of the second high-voltage NMOS tube NH2, the source of the third low-voltage NMOS tube NM3 is grounded, and the gate of the third low-voltage NMOS tube NM3 is connected to the external bias current I B connected.

[0012] In one embodiment, the inverter signal output module 13 includes a first inverter INV1, a second inverter INV2 and a third inverter INV3, the input end of the first inverter INV1 is connected to the source of the second high-voltage NMOS tube NH2, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is connected to the input end of the third inverter INV3.

[0013] In one embodiment, the first level shift branch 21 includes a third high-voltage PMOS transistor PH3, a first resistor R1, a third high-voltage NMOS transistor NH3, and a fourth low-voltage NMOS transistor NM4; wherein the source of the third high-voltage PMOS transistor PH3 is connected to the first power supply voltage V1, and the first resistor R1 is connected between the source and the gate of the third high-voltage PMOS transistor PH3; the gate of the third high-voltage NMOS transistor NH3 is connected to the first control signal V 1H The drain of the third high-voltage NMOS transistor NH3 is connected to the gate of the third high-voltage PMOS transistor PH3; the drain of the fourth low-voltage NMOS transistor NM4 is connected to the source of the third high-voltage NMOS transistor NH3, the source of the fourth low-voltage NMOS transistor NM4 is grounded, and the gate of the fourth low-voltage NMOS transistor NM4 is connected to the external bias current I B connected.

[0014] In one embodiment, the second level shift branch 22 includes a fourth high-voltage PMOS transistor PH4, a second resistor R2, a fourth high-voltage NMOS transistor NH4, and a fifth low-voltage NMOS transistor NM5; wherein the drain of the fourth high-voltage PMOS transistor PH4 is connected to the drain of the third high-voltage PMOS transistor PH3, the source of the fourth high-voltage PMOS transistor PH4 is connected to one end of the second resistor R2, the gate of the fourth high-voltage PMOS transistor PH4 is connected to the other end of the second resistor R2, and the drain of the fourth high-voltage NMOS transistor NH4 is connected to the other end of the second resistor R2, and the gate of the fourth high-voltage NMOS transistor NH4 is connected to the first control signal V 1H The drain of the fifth low-voltage NMOS transistor NM5 is connected to the source of the fourth high-voltage NMOS transistor NH4, the source of the fifth low-voltage NMOS transistor NM5 is grounded, and the gate of the fifth low-voltage NMOS transistor NM5 is connected to the external bias current I B connected.

[0015] In one embodiment, the third level shift branch 31 includes a fifth high-voltage PMOS transistor PH5, a third resistor R3, a fifth high-voltage NMOS transistor NH5, and a sixth low-voltage NMOS transistor NM6; wherein the source of the fifth high-voltage PMOS transistor PH5 is connected to the second power supply voltage V2, and the third resistor R3 is connected between the source and the gate of the fifth high-voltage PMOS transistor PH5; the gate of the fifth high-voltage NMOS transistor NH5 is connected to the second control signal V 2H The drain of the fifth high-voltage NMOS transistor NH5 is connected to the gate of the fifth high-voltage PMOS transistor PH5; the drain of the sixth low-voltage NMOS transistor NM6 is connected to the source of the fifth high-voltage NMOS transistor NH5, the source of the sixth low-voltage NMOS transistor NM6 is grounded, and the gate of the sixth low-voltage NMOS transistor NM6 is connected to the external bias current I B connected.

[0016] In one embodiment, the fourth level shift branch 32 includes a sixth high-voltage PMOS transistor PH6, a fourth resistor R4, a sixth high-voltage NMOS transistor NH6, and a seventh low-voltage NMOS transistor NM7; wherein the drain of the sixth high-voltage PMOS transistor PH6 is connected to the drain of the fifth high-voltage PMOS transistor PH5, the source of the sixth high-voltage PMOS transistor PH6 is connected to one end of the fourth resistor R4, the gate of the sixth high-voltage PMOS transistor PH6 is connected to the other end of the fourth resistor R4, and the drain of the sixth high-voltage NMOS transistor NH6 is connected to the other end of the fourth resistor R4, and the gate of the sixth high-voltage NMOS transistor NH6 is connected to the second control signal V 2H The drain of the seventh low-voltage NMOS transistor NM7 is connected to the source of the sixth high-voltage NMOS transistor NH6, the source of the seventh low-voltage NMOS transistor NM7 is grounded, and the gate of the seventh low-voltage NMOS transistor NM7 is connected to the external bias current I B connected.

[0017] Compared with the prior art, one or more embodiments of the present invention may have the following inventive features and advantages:

[0018] 1. The present invention uses the isolation of high-voltage NMOS tubes and the level shift circuit to enable the entire circuit to operate in a high-voltage domain, thereby realizing the judgment of the power supply voltage in the high-voltage domain;

[0019] 2. The present invention can effectively cut off the leakage path between different voltage domains by adopting a back-gate high-voltage PMOS transistor and its gate control circuit;

[0020] 3. The grid of the high-voltage tube of the present invention will not bear high voltage, and has low requirements and dependence on the process.

[0021] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0023] FIG1 is a schematic structural diagram of a voltage selection circuit for a power supply circuit of the present invention;

[0024] FIG2 is a circuit structure diagram of a voltage selection circuit for a power supply circuit according to the present invention;

[0025] FIG3 is a circuit waveform diagram of a voltage selection circuit for a power supply circuit according to the present invention. DETAILED DESCRIPTION

[0026] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings.

[0027] Before proceeding with the detailed description below, it may be necessary to set forth the definitions of certain words and phrases used throughout the present invention. The terms "coupled," "connected," and their derivatives refer to any direct or indirect communication or connection between two or more elements, regardless of whether those elements are in physical contact with each other. The terms "transmit," "receive," and "communicate," and their derivatives, encompass both direct and indirect communication. The terms "include," "comprise," and their derivatives, mean including, but not limited to. The term "or" is inclusive, meaning and / or. The phrase "associated with..." and its derivatives mean including, included within, interconnected, containing, contained within, connected or connected with, coupled or coupled with, communicate with, cooperate with, intertwine, juxtapose, approach, bound or bound with, have, have attributes, have a relationship, or have a relationship with, etc. The term "controller" refers to any device, system, or part thereof that controls at least one operation. Such a controller may be implemented using hardware, or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, whether local or remote. The phrase "at least one of," when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one of the items in the list may be needed. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A, B, and C.

[0028] The description of the first and second ends of a resistor, capacitor, or inductor in this disclosure is intended solely to distinguish the two connection ends of the device, facilitating description of the device's connection relationship with other devices. It does not specifically designate a particular end of the resistor, capacitor, or inductor in actual practice. Those skilled in the art will appreciate that, in actual circuit construction, any end of a resistor, capacitor, or inductor in an actual device can be defined as the first end. When the first end is defined, the other end of the device is automatically designated as the second end.

[0029] When describing various components or elements in this disclosure, the terms "first," "second," "third," and so on are used solely to distinguish the components and to express the distinct relationships between them. These terms themselves do not imply any relationships between the components. For example, the mere mention of "first" and "third" does not imply the existence of a "second" between them. The "first" and "third" terms simply indicate the existence of two distinct, independent components.

[0030] Definitions of other specific words and phrases are provided throughout this disclosure. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior and future uses of such defined words and phrases.

[0031] In the present invention, the application combination of modules and the division level of sub-modules are only used for illustration, and the application combination of modules and the division level of sub-modules may be in different ways without departing from the scope of the present disclosure.

[0032] Example 1

[0033] As shown in Figure 1, the voltage selection circuit for a power supply circuit of this embodiment includes a voltage comparison module 1, a first level shift module 2, and a second level shift module 3. The voltage comparison module 1 includes a high-voltage conduction module 11, a low-voltage mirror module 12, and an inverter signal output module 13. The first level shift module 2 includes a first level shift branch 21 and a second level shift branch 22. The second level shift module 3 includes a third level shift branch 31 and a fourth level shift branch 32.

[0034] In this embodiment, the first supply voltage V1 and the second supply voltage V2 are input to the voltage comparison module 1, and the voltage comparison module 1 outputs a first control signal V 1H and the second control signal V 2H , the first control signal V 1H When the first power supply voltage V1 is high, it indicates that the first power supply voltage V1 is higher than the second power supply voltage V2, and the second control signal V 2H When it is at a high level, it indicates that the first supply voltage V1 is lower than the second supply voltage V2.

[0035] The first control signal V 1H is used to control the first level shift module 2 to control the first supply voltage V1 to be output to the voltage output terminal of the voltage selection circuit; the second control signal V 2H It is used to control the second level shift module 3 to control the second supply voltage V2 to be output to the voltage output terminal of the voltage selection circuit.

[0036] As shown in FIG2 , in this embodiment, the high-voltage conduction module 11 includes a first high-voltage PMOS transistor PH1, a second high-voltage PMOS transistor PH2, a first high-voltage NMOS transistor NH1, and a second high-voltage NMOS transistor NH2, wherein the source of the first high-voltage PMOS transistor PH1 is connected to a first power supply voltage V1, the gate of the first high-voltage PMOS transistor PH1 is connected to its own drain, the source of the second high-voltage PMOS transistor PH2 is connected to a second power supply voltage V2, the gate of the second high-voltage PMOS transistor PH2 is connected to the gate of the first high-voltage PMOS transistor PH1, the drain of the first high-voltage NMOS transistor NH1 is connected to the drain of the first high-voltage PMOS transistor PH1, and the gate of the first high-voltage NMOS transistor NH1 is connected to an external low-voltage power supply voltage V L The drain of the second high-voltage NMOS transistor NH2 is connected to the drain of the second high-voltage PMOS transistor PH2, and the gate of the second high-voltage NMOS transistor NH2 is also connected to the external low-voltage power supply voltage V L .

[0037] In this embodiment, the low voltage mirror module 12 includes a first low voltage NMOS transistor NM1, a second low voltage NMOS transistor NM2 and a third low voltage NMOS transistor NM3. The drain of the first low voltage NMOS transistor NM1 is connected to the external bias current I B The source of the first low-voltage NMOS transistor NM1 is grounded, and the drain of the first low-voltage NMOS transistor NM1 is connected to its own gate. The drain of the second low-voltage NMOS transistor NM2 is connected to the source of the first high-voltage NMOS transistor NH1, and the source of the second low-voltage NMOS transistor NM2 is grounded. At the same time, the gate of the second low-voltage NMOS transistor NM2 is connected to the external bias current I B The drain of the third low-voltage NMOS transistor NM3 is connected to the source of the second high-voltage NMOS transistor NH2, the source of the third low-voltage NMOS transistor NM3 is grounded, and the gate of the third low-voltage NMOS transistor NM3 is connected to the external bias current I B connected.

[0038] In this embodiment, the inverter signal output module 13 includes a first inverter INV1, a second inverter INV2 and a third inverter INV3. The input end of the first inverter INV1 is connected to the source of the second high-voltage NMOS tube NH2, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is connected to the input end of the third inverter INV3.

[0039] In this embodiment, in the low-voltage mirror circuit, the first low-voltage NMOS transistor NM1, the second low-voltage NMOS transistor NM2, and the third low-voltage NMOS transistor NM3 form a current mirror, that is, when the second low-voltage NMOS transistor NM2 and the third low-voltage NMOS transistor NM3 are in the on state, the current flowing through the second low-voltage NMOS transistor NM2 and the third low-voltage NMOS transistor NM3 is the same. If the first power supply voltage V1 is higher than the second power supply voltage V2, the gate-source voltage V GS The gate-source voltage V GS , which causes the source of the second high-voltage NMOS transistor NH2 to output a low-level signal. Furthermore, the second control signal V 2H The output is a low level signal, and the output end of the third inverter INV3 outputs the first control signal V 1H The output is a high level signal. When the first supply voltage V1 is lower than the second supply voltage V2, the first control signal V 1H is low level, the second control signal V 2H is high level.

[0040] As shown in FIG2 , in this embodiment, the first level shift branch 21 includes a third high-voltage PMOS transistor PH3, a first resistor R1, a third high-voltage NMOS transistor NH3, and a fourth low-voltage NMOS transistor NM4. The source of the third high-voltage PMOS transistor PH3 is connected to the first supply voltage V1, and the first resistor R1 is connected between the source and gate of the third high-voltage PMOS transistor PH3. The gate of the third high-voltage NMOS transistor NH3 is connected to the first control signal V 1H The drain of the third high-voltage NMOS transistor NH3 is connected to the gate of the third high-voltage PMOS transistor PH3. The drain of the fourth low-voltage NMOS transistor NM4 is connected to the source of the third high-voltage NMOS transistor NH3, the source of the fourth low-voltage NMOS transistor NM4 is grounded, and the gate of the fourth low-voltage NMOS transistor NM4 is connected to the external bias current I B connected.

[0041] The second level shift branch 22 includes a fourth high-voltage PMOS transistor PH4, a second resistor R2, a fourth high-voltage NMOS transistor NH4, and a fifth low-voltage NMOS transistor NM5. The drain of the fourth high-voltage PMOS transistor PH4 is connected to the drain of the third high-voltage PMOS transistor PH3, the source of the fourth high-voltage PMOS transistor PH4 is connected to one end of the second resistor R2, the gate of the fourth high-voltage PMOS transistor PH4 is connected to the other end of the second resistor R2, and the drain of the fourth high-voltage NMOS transistor NH4 is connected to the other end of the second resistor R2, and the gate of the fourth high-voltage NMOS transistor NH4 is connected to the first control signal V 1H The drain of the fifth low-voltage NMOS transistor NM5 is connected to the source of the fourth high-voltage NMOS transistor NH4, the source of the fifth low-voltage NMOS transistor NM5 is grounded, and the gate of the fifth low-voltage NMOS transistor NM5 is connected to the external bias current I B connected.

[0042] The third level shift branch 31 includes a fifth high-voltage PMOS transistor PH5, a third resistor R3, a fifth high-voltage NMOS transistor NH5, and a sixth low-voltage NMOS transistor NM6. The source of the fifth high-voltage PMOS transistor PH5 is connected to the second power supply voltage V2, and the third resistor R3 is connected between the source and gate of the fifth high-voltage PMOS transistor PH5. The gate of the fifth high-voltage NMOS transistor NH5 is connected to the second control signal V 2H The drain of the fifth high-voltage NMOS transistor NH5 is connected to the gate of the fifth high-voltage PMOS transistor PH5. The drain of the sixth low-voltage NMOS transistor NM6 is connected to the source of the fifth high-voltage NMOS transistor NH5. The source of the sixth low-voltage NMOS transistor NM6 is grounded. At the same time, the gate of the sixth low-voltage NMOS transistor NM6 is connected to the external bias current I B connected.

[0043] The fourth level shift branch 32 includes a sixth high-voltage PMOS transistor PH6, a fourth resistor R4, a sixth high-voltage NMOS transistor NH6, and a seventh low-voltage NMOS transistor NM7. The drain of the sixth high-voltage PMOS transistor PH6 is connected to the drain of the fifth high-voltage PMOS transistor PH5, the source of the sixth high-voltage PMOS transistor PH6 is connected to one end of the fourth resistor R4, the gate of the sixth high-voltage PMOS transistor PH6 is connected to the other end of the fourth resistor R4, and the drain of the sixth high-voltage NMOS transistor NH6 is connected to the other end of the fourth resistor R4, and the gate of the sixth high-voltage NMOS transistor NH6 is connected to the second control signal V 2HThe drain of the seventh low-voltage NMOS transistor NM7 is connected to the source of the sixth high-voltage NMOS transistor NH6, the source of the seventh low-voltage NMOS transistor NM7 is grounded, and the gate of the seventh low-voltage NMOS transistor NM7 is connected to the external bias current I B connected.

[0044] The source of the fourth high-voltage PMOS transistor PH4 is connected to the source of the sixth high-voltage PMOS transistor PH6 and serves as the voltage output terminal V of the voltage selection circuit. MAX .

[0045] In this embodiment, the first low-voltage NMOS transistor NM1 to the seventh low-voltage NMOS transistor NM7 form a current mirror circuit composed of low-voltage NMOS transistors, and the first high-voltage NMOS transistor NH1 to the sixth high-voltage NMOS transistor NH6 are high-voltage NMOS transistors used to isolate the high-voltage domain from the low-voltage domain so that devices in the low-voltage domain are not affected by the high voltage.

[0046] For the first level shift branch 21, when the first power supply voltage V1 is higher than the second power supply voltage V2, the first control signal V 1H When the gate of the third high-voltage NMOS transistor NH3 is high, the gate of the third high-voltage NMOS transistor NH3 is turned on, and the fourth high-voltage NMOS transistor NM4 generates a current I1 that flows through the first resistor R1. By selecting appropriate I1 and R1, the value of I1*R1 is greater than the conduction threshold of the third high-voltage PMOS transistor PH3 and less than the gate withstand voltage of the third high-voltage PMOS transistor PH3 (for example, 5V). At this time, the gate voltage V G1 =V1-I1*R1, so that the third high-voltage PMOS tube PH3 is turned on; when the voltage of V1 is lower than V2, the first control signal V 1H is low, the third high-voltage NMOS tube NH3 is turned off, and no current flows through the first resistor R1. At this time, V G1 =V1, PH3 is turned off.

[0047] For the second level shift branch 22, NM5, NH4 and R2 form a level shift circuit that controls the on or off of PH4, generating a gate voltage V G2 If there is no fourth high-voltage PMOS tube PH4, when the output voltage V MAX When the diode conduction voltage is greater than V1, there will be a leakage current from V1 through the parasitic diode of PH3. MAX Flows to V1, and the presence of PH4 and its control circuit cuts off the leakage path, improving the reliability of the circuit. When the voltage of V1 is higher than V2, V 1H=High, NH4 is turned on, NM5 generates current I2 flowing through R2, by selecting appropriate I2 and R2 so that the value of I2*R2 is greater than the conduction threshold of PH4 and less than the gate withstand voltage of PH4 (such as 5V), then V G2 =V MAX -I2*R2, PH4 is turned on; when the voltage of V1 is lower than V2, V 1H is low, NH4 is turned off, no current flows through R2, and V G2 =V MAX , PH4 is turned off.

[0048] The first level shift branch 21 and the second level shift branch 22 are both controlled by V 1H Control, so the on and off of PH3 and PH4 are synchronized. When PH3 and PH4 are turned on, the voltage of V1 is transmitted to V MAX , whereas V1 and V MAX It is in the circuit breaker state.

[0049] NM6, NH5 and R3 form a level shift circuit that controls the on / off of PH5, generating the gate voltage V G3 When the voltage of V2 is higher than that of V1, V 2H =High, NH5 is turned on, NM6 generates current I3 flowing through R3, by selecting appropriate I3 and R3 so that the value of I3*R3 is greater than the conduction threshold of PH5 and less than the gate withstand voltage of PH5 (for example, 5V). At this time, V G3 =V2-I3*R3, PH5 is turned on; when V2 voltage is lower than V1, V 2H is low, NH5 is turned off, no current flows through R3, and V G3 =V2, PH5 is turned off.

[0050] NM7, NH6 and R4 form a level shift circuit that controls the on / off of PH6, generating the gate voltage V G4 When the voltage of V2 is higher than that of V1, V 2H is high, NH6 is turned on, and NM7 generates a current I4 flowing through R4. By selecting appropriate I4 and R4, the value of I4*R4 is greater than the conduction threshold of PH6 and less than the gate withstand voltage of PH6 (for example, 5V). At this time, V G4 =V MAX -I4*R4, PH6 is turned on; when the voltage of V2 is lower than V1, V 2H is low, NH6 is turned off, no current flows through R4, and V G4 =V MAX , PH6 is turned off.

[0051] The third level shift branch 31 and the fourth level shift branch 32 are both affected by V2H Control, so the on and off of PH5 and PH6 are synchronized. When PH5 and PH6 are turned on, the voltage of V2 is transmitted to V MAX , on the contrary V2 and V MAX It is in the circuit breaker state.

[0052] In summary, when the first power supply voltage V1 is greater than the second power supply voltage V2, the third high-voltage PMOS transistor PH3 and the fourth high-voltage PMOS transistor PH4 are turned on, and the fifth high-voltage PMOS transistor PH5 and the sixth high-voltage PMOS transistor PH6 are turned off. At this time, the voltage output terminal V MAX The output voltage is the first power supply voltage V1; conversely, when the first power supply voltage V1 is less than the second power supply voltage V2, the third high-voltage PMOS transistor PH3 and the fourth high-voltage PMOS transistor PH4 are turned off, and the fifth high-voltage PMOS transistor PH5 and the sixth high-voltage PMOS transistor PH6 are turned on. At this time, the voltage output terminal V MAX The output voltage is the second power supply voltage V2. MAX Automatically selects the high power supply voltage function.

[0053] As shown in FIG3 , the voltage waveform diagram of the voltage selection circuit for the power supply circuit of the present invention, when the first power supply voltage V1 outputs 20V and the second power supply voltage V2 gradually rises from 0V to 40V; the voltage output terminal V MAX The output voltage first outputs the first supply voltage V1 20V, and when the first supply voltage V1 is lower than the second supply voltage V2, it starts to output the second supply voltage V2.

[0054] The above description is merely a preferred embodiment of the present disclosure and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present disclosure is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but should also encompass other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the inventive concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in the embodiments of the present disclosure.

Claims

1. A voltage selection circuit for a power supply circuit, characterized in that: The voltage selection circuit includes: a voltage comparison module, a first level shift module and a second level shift module; the voltage comparison module includes a high voltage conduction module, a low voltage mirror module and an inverter signal output module; the first level shift module includes a first level shift branch and a second level shift branch; the second level shift module includes a third level shift branch and a fourth level shift branch; The first supply voltage V1 and the second supply voltage V2 are input into the voltage comparison module, and the voltage comparison module outputs a first control signal V 1H and the second control signal V 2H , the first control signal V 1H When the first power supply voltage V1 is high, it indicates that the first power supply voltage V1 is higher than the second power supply voltage V2, and the second control signal V 2H When it is at a high level, it indicates that the first supply voltage V1 is lower than the second supply voltage V2; The first control signal V 1H is used to control the first level shift module to control the first supply voltage V1 to be output to the voltage output terminal of the voltage selection circuit; the second control signal V 2H Used to control the second level shift module to control the second supply voltage V2 to be output to the voltage output terminal of the voltage selection circuit.

2. The voltage selection circuit for a power supply circuit according to claim 1, characterized in that: The high-voltage conduction module includes a first high-voltage PMOS tube PH1, a second high-voltage PMOS tube PH2, a first high-voltage NMOS tube NH1 and a second high-voltage NMOS tube NH2, wherein the source of the first high-voltage PMOS tube PH1 is connected to a first power supply voltage V1, the gate of the first high-voltage PMOS tube PH1 is connected to its own drain, the source of the second high-voltage PMOS tube PH2 is connected to a second power supply voltage V2, and the gate of the second high-voltage PMOS tube PH2 is connected to the gate of the first high-voltage PMOS tube PH1; the drain of the first high-voltage NMOS tube NH1 is connected to the drain of the first high-voltage PMOS tube PH1, and the gate of the first high-voltage NMOS tube NH1 is connected to an external low-voltage power supply voltage V L The drain of the second high-voltage NMOS tube NH2 is connected to the drain of the second high-voltage PMOS tube PH2, and the gate of the second high-voltage NMOS tube NH2 is also connected to the external low-voltage power supply voltage V L .

3. The voltage selection circuit for a power supply circuit according to claim 2, characterized in that: The low-voltage mirror module 12 includes a first low-voltage NMOS transistor NM1, a second low-voltage NMOS transistor NM2 and a third low-voltage NMOS transistor NM3; the drain of the first low-voltage NMOS transistor NM1 is connected to the external bias current I B , the source of the first low-voltage NMOS tube NM1 is grounded, and the drain of the first low-voltage NMOS tube NM1 is connected to its own gate; the drain of the second low-voltage NMOS tube NM2 is connected to the source of the first high-voltage NMOS tube NH1, and the source of the second low-voltage NMOS tube NM2 is grounded, and the gate of the second low-voltage NMOS tube NM2 is connected to the external bias current I B The drain of the third low-voltage NMOS tube NM3 is connected to the source of the second high-voltage NMOS tube NH2, the source of the third low-voltage NMOS tube NM3 is grounded, and the gate of the third low-voltage NMOS tube NM3 is connected to the external bias current I B connected.

4. The voltage selection circuit for a power supply circuit according to claim 3, characterized in that: The inverter signal output module includes a first inverter INV1, a second inverter INV2 and a third inverter INV3, the input end of the first inverter INV1 is connected to the source of the second high-voltage NMOS tube NH2, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is connected to the input end of the third inverter INV3.

5. The voltage selection circuit for a power supply circuit according to claim 4, characterized in that: The first level shift branch includes a third high-voltage PMOS transistor PH3, a first resistor R1, a third high-voltage NMOS transistor NH3 and a fourth low-voltage NMOS transistor NM4; wherein the source of the third high-voltage PMOS transistor PH3 is connected to the first power supply voltage V1, and the first resistor R1 is connected between the source and the gate of the third high-voltage PMOS transistor PH3; the gate of the third high-voltage NMOS transistor NH3 is connected to the first control signal V 1H The drain of the third high-voltage NMOS tube NH3 is connected to the gate of the third high-voltage PMOS tube PH3; the drain of the fourth low-voltage NMOS tube NM4 is connected to the source of the third high-voltage NMOS tube NH3, the source of the fourth low-voltage NMOS tube NM4 is grounded, and the gate of the fourth low-voltage NMOS tube NM4 is connected to the external bias current I B connected.

6. The voltage selection circuit for a power supply circuit according to claim 5, characterized in that: The second level shift branch includes a fourth high-voltage PMOS tube PH4, a second resistor R2, a fourth high-voltage NMOS tube NH4 and a fifth low-voltage NMOS tube NM5; wherein the drain of the fourth high-voltage PMOS tube PH4 is connected to the drain of the third high-voltage PMOS tube PH3, the source of the fourth high-voltage PMOS tube PH4 is connected to one end of the second resistor R2, the gate of the fourth high-voltage PMOS tube PH4 is connected to the other end of the second resistor R2, and the drain of the fourth high-voltage NMOS tube NH4 is connected to the other end of the second resistor R2, and the gate of the fourth high-voltage NMOS tube NH4 is connected to the first control signal V 1H The drain of the fifth low-voltage NMOS tube NM5 is connected to the source of the fourth high-voltage NMOS tube NH4, the source of the fifth low-voltage NMOS tube NM5 is grounded, and the gate of the fifth low-voltage NMOS tube NM5 is connected to the external bias current I B connected.

7. The voltage selection circuit for a power supply circuit according to claim 6, characterized in that: The third level shift branch includes a fifth high-voltage PMOS transistor PH5, a third resistor R3, a fifth high-voltage NMOS transistor NH5 and a sixth low-voltage NMOS transistor NM6; wherein the source of the fifth high-voltage PMOS transistor PH5 is connected to the second power supply voltage V2, and the third resistor R3 is connected between the source and the gate of the fifth high-voltage PMOS transistor PH5; the gate of the fifth high-voltage NMOS transistor NH5 is connected to the second control signal V 2H The drain of the fifth high-voltage NMOS tube NH5 is connected to the gate of the fifth high-voltage PMOS tube PH5; the drain of the sixth low-voltage NMOS tube NM6 is connected to the source of the fifth high-voltage NMOS tube NH5, the source of the sixth low-voltage NMOS tube NM6 is grounded, and the gate of the sixth low-voltage NMOS tube NM6 is connected to the external bias current I B connected.

8. The voltage selection circuit for a power supply circuit according to claim 7, characterized in that: The fourth level shift branch includes a sixth high-voltage PMOS tube PH6, a fourth resistor R4, a sixth high-voltage NMOS tube NH6 and a seventh low-voltage NMOS tube NM7; wherein the drain of the sixth high-voltage PMOS tube PH6 is connected to the drain of the fifth high-voltage PMOS tube PH5, the source of the sixth high-voltage PMOS tube PH6 is connected to one end of the fourth resistor R4, the gate of the sixth high-voltage PMOS tube PH6 is connected to the other end of the fourth resistor R4, and the drain of the sixth high-voltage NMOS tube NH6 is connected to the other end of the fourth resistor R4, and the gate of the sixth high-voltage NMOS tube NH6 is connected to the second control signal V 2H The drain of the seventh low-voltage NMOS tube NM7 is connected to the source of the sixth high-voltage NMOS tube NH6, the source of the seventh low-voltage NMOS tube NM7 is grounded, and the gate of the seventh low-voltage NMOS tube NM7 is connected to the external bias current I B connected.

9. The voltage selection circuit for a power supply circuit according to claim 8, characterized in that: The source of the fourth high-voltage PMOS transistor PH4 is connected to the source of the sixth high-voltage PMOS transistor PH6 and serves as a voltage output terminal of the voltage selection circuit.

10. An integrated circuit chip, comprising the voltage selection circuit according to any one of claims 1 to 9.

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