Interrupt request balance method and apparatus, and computing device

Abstract

An interrupt request (IRQ) balance method and apparatus, and a computing device. There are a plurality of processors in the computing device, and the running states of the plurality of processors are acquired. The computing device may configure processors, which are in a non-idle state and in an operating frequency that is within a preset frequency range, and have a load rate that is below a set load rate, from among the plurality of processors to process IRQs other than specified IRQs, and configure processors which are in another state to process the specified IRQs. The computing device does not allow processors in an idle state to receive the IRQs other than the specified IRQs, such that the computing device is prevented from power consumption deterioration and performance degradation caused by problems such as processors in the idle state being woken up, the latency in processing IRQs by processors having a high load rate being increased, and power consumption of processors in a high frequency being increased.

Description

Interrupt request balancing method, device and computing equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on August 7, 2023, with application number 202310985953.7 and application name “A method, device and computing device for balancing interrupt requests”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of artificial intelligence technology, and in particular to a method, device and computing equipment for balancing interrupt requests. Background Art

[0003] Interrupt balancing refers to the rational allocation and management of interrupt requests (IRQs) in a computer system to achieve a balance between system performance and reliability. Mainstream operating systems are equipped with interrupt balancing algorithms that evenly distribute and process IRQs across different central processing units (CPUs), achieving high parallelism in the operating system. However, some of the multiple CPUs managed by the operating system may be idle. If the operating system uses interrupt balancing algorithms to allocate IRQs, problems such as waking up idle processors, increased latency in processing IRQs for highly loaded processors, and increased power consumption for high-frequency processors can occur, leading to reduced power consumption and performance.

[0004] Summary of the Invention

[0005] To address the aforementioned issues, an embodiment of the present application provides an interrupt request balancing method. By detecting the operating status of multiple processors in a computing device and treating the processors in normal working order as a collection node, IRQs can be evenly distributed to the processors within the collection node, avoiding issues such as waking up idle processors, increasing the delay in processing IRQs by highly loaded processors, and increasing power consumption by high-frequency processors, which can lead to degraded power consumption and performance of the computing device. Furthermore, the present application also provides an interrupt request balancing device and a computing device corresponding to the interrupt request balancing method.

[0006] To this end, the following technical solutions are adopted in the embodiments of the present application:

[0007] In the first aspect, an embodiment of the present application provides a method for balancing interrupt requests IRQ, and the method for balancing interrupt requests IRQ is characterized in that the method is executed by a computing device, and the computing device includes multiple processors, and the method includes: obtaining the operating status of the multiple processors; when the processor is not in a set state, setting the processor to process a specified IRQ; the set state includes one or more of a non-idle state, an operating frequency within a preset frequency range, and a load rate less than a set load rate; when the processor is in the set state, setting the processor to process IRQs other than the specified IRQ.

[0008] In this embodiment, a computing device typically contains multiple processors. Among the multiple processors, a processor that is in a non-idle state, operating at a frequency within a preset frequency range, and with a load rate less than a preset load rate can be configured to handle IRQs other than designated IRQs, while processors in other states can also be configured to handle designated IRQs. The computing device will not allow an idle processor to receive IRQs other than designated IRQs, thereby avoiding issues such as waking up an idle processor, increasing the latency of a highly loaded processor in handling IRQs, and increasing the power consumption of a high-frequency processor, which can lead to reduced power consumption and performance of the computing device.

[0009] In one embodiment, the method further includes: based on an interrupt balancing algorithm, evenly distributing the IRQs other than the designated IRQ to the processors in the set state.

[0010] In this embodiment, when the computing device runs the interrupt balancing algorithm, the received IRQs can be evenly distributed to the processors in the set state, so that the processors in the set state can process the IRQs evenly. This not only keeps the load rate, power consumption, operating frequency and other performance of each processor in the set state the same, but also avoids problems such as waking up the processor in the idle state, lengthening the delay in processing IRQs by the processor with a high load rate, and increasing the power consumption of the processor with a high frequency, which leads to deterioration of the power consumption and performance of the computing device.

[0011] In one embodiment, the further embodiment includes: when the operating state of the processor is switched from the set state to not being in the set state, setting the processor to process a specified IRQ.

[0012] In this embodiment, when the computing device determines that the operating state of the processor has switched from a set state to a non-set state, the type of IRQ handled by the processor can be changed to allow the processor to handle the specified IRQ, and avoid problems such as waking up the processor in the idle state, longer delays in handling IRQs by processors with high load rates, and increased power consumption of high-frequency processors, which lead to deterioration of power consumption and performance of the computing device.

[0013] In one embodiment, when the operating state of the processor is switched from not being in the set state to being in the set state, the processor is set to process the IRQ other than the designated IRQ.

[0014] In this embodiment, when the computing device determines that the operating state of the processor has switched from not being in the set state to being in the set state, the type of IRQ processed by the processor can be changed, allowing more processors to process IRQs other than the specified IRQ, thereby reducing the load rate, power consumption, latency, etc. of each processor in the running state.

[0015] In one embodiment, the method further includes: in response to the number of IRQs received by the processor in the set state exceeding a set threshold, setting some of the processors not in the set state to process the IRQs other than the designated IRQ.

[0016] In this embodiment, when the computing device detects a large number of IRQs and a small number of processors in a specific state, each processor needs to handle a large number of IRQs, resulting in a longer latency for the processors to handle the IRQs. Therefore, the computing device can convert some processors that are not in the specified state into processors in the specified state, allowing more processors to handle IRQs other than the specified IRQs, thereby reducing the latency of each processor in the running state.

[0017] In one embodiment, the method further includes: detecting an application scenario of the computing device; and adjusting the number of processors currently in the set state based on a pre-stored relationship between the number of processors in the set state corresponding to various application scenarios of the computing device.

[0018] In this embodiment, the computing device can be used in various application scenarios, such as communications, application usage, mobile office work, and web browsing. Different application scenarios generate different numbers of IRQs, requiring different numbers of processors in specific states to handle them. Therefore, designers can pre-train and store the relationship between different application scenarios and the number of processors in specific states. After detecting the current application scenario, the computing device can adjust the number of processors in specific states for the current application scenario to ensure that the power consumption, load rate, latency, and other performance of the processors in the specific state are always optimized.

[0019] In the second aspect, an embodiment of the present application provides an interrupt request IRQ balancing device, including: a transceiver unit, used to obtain the operating status of the multiple processors; a processing unit, used to set the processor to process a specified IRQ when the processor is not in a set state; the set state includes one or more of a non-idle state, an operating frequency within a preset frequency range, and a load rate less than a set load rate; when the processor is in the set state, the processor is set to process IRQs other than the specified IRQ.

[0020] In one embodiment, the processing unit is further configured to distribute the IRQs other than the designated IRQ to the processors in the set state in a balanced manner based on an interrupt balancing algorithm.

[0021] In one embodiment, the processing unit is further configured to set the processor to process a specified IRQ when the operating state of the processor is switched from the set state to not being in the set state.

[0022] In one embodiment, the processing unit is further configured to set the processor to process the IRQ other than the designated IRQ when the operating state of the processor is switched from not being in the set state to being in the set state.

[0023] In one embodiment, the processing unit is further configured to set some of the processors not in the set state to process IRQs other than the specified IRQ in response to the number of IRQs received by the processor in the set state exceeding a set threshold.

[0024] In one embodiment, the processing unit is further used to detect the application scenario of the computing device; and adjust the number of processors currently in the set state based on the pre-stored relationship between the number of processors in the set state corresponding to various application scenarios of the computing device.

[0025] In a third aspect, an embodiment of the present application provides a computing device comprising: at least one memory, a plurality of processors, the plurality of processors including a main processor, the main processor being used to execute instructions stored in the at least one memory, so that the computing device can be implemented as any of the possible embodiments of the first aspect.

[0026] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed in a computer, the computer is caused to execute various possible implementation embodiments of the first aspect.

[0027] In a fifth aspect, an embodiment of the present application provides a computer program product, characterized in that the computer program product stores instructions, and when the instructions are executed by a computer, the computer implements each possible implementation embodiment of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The following is a brief introduction to the drawings required for describing the embodiments or prior art.

[0029] FIG1( a ) is a schematic diagram of a solution for allocating IRQs by an operating system in the related art;

[0030] FIG1( b ) is a schematic diagram of another method for allocating IRQs by an operating system in the related art;

[0031] FIG1( c ) is a schematic diagram of another operating system allocation IRQ scheme in the related art;

[0032] FIG2 is a schematic diagram of a solution for allocating IRQs by an operating system provided in an embodiment of the present application;

[0033] FIG3 is a schematic diagram of the architecture of a computing device provided in an embodiment of the present application;

[0034] FIG4 is a schematic diagram of the architecture of an operating system provided in an embodiment of the present application;

[0035] FIG5 is a control flow chart of each module of the operating system provided in an embodiment of the present application;

[0036] FIG6 is a schematic diagram showing a flow chart of an IRQ equalization method provided in an embodiment of the present application;

[0037] FIG7( a ) is a data diagram of a simulation experiment showing the number of core interrupts for different IRQ allocation schemes provided in an embodiment of the present application;

[0038] FIG7( b ) is a data diagram of a simulation experiment showing the time delay of the core processing IRQs under different IRQ allocation schemes provided in an embodiment of the present application;

[0039] FIG7( c ) is a data diagram of a simulation experiment of the time for migrating an IRQ and the time for migrating a core provided in an embodiment of the present application;

[0040] FIG8 is a schematic structural diagram of an IRQ equalization device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0042] The term "and / or" as used herein describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. The symbol " / " as used herein indicates that the related objects are in an "or" relationship, for example, A / B means either A or B.

[0043] The terms "first" and "second" in this specification and claims are used to distinguish different objects rather than to describe a specific order of objects. For example, "first response message" and "second response message" are used to distinguish different response messages rather than to describe a specific order of response messages.

[0044] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0045] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more, for example, multiple processing units means two or more processing units, etc.; multiple elements means two or more elements, etc.

[0046] An IRQ is a signal sent by hardware to the operating system to abort or cancel the current operation or request. Generally, when an external device needs to send an interrupt signal, it modifies the voltage level of the terminal pin connected to the generic interrupt controller (GIC) or advanced programmable interrupt controller (APIC). When the GIC or APIC recognizes a change in the voltage level of the interrupt signal line, it sends an interrupt signal to the CPU. Upon receiving the interrupt signal, the CPU immediately stops the current execution flow and jumps to the interrupt handler. Therefore, the interrupt signal sent by an external device to the GIC or APIC, and vice versa, can be called an IPQ.

[0047] As shown in Figure 1(a), the operating system can run on four CPUs: CPU-0, CPU-1, CPU-2, and CPU-3. The operating system receives four IRQs: IRQ-0, IRQ-1, IRQ-2, and IRQ-3. Normally, the operating system is in performance mode. The operating system can run an interrupt balancing algorithm to evenly distribute multiple IRQs to different CPUs, allowing the operating system to achieve high parallelism. That is, the operating system assigns IRQ-0 to CPU-0, IRQ-1 to CPU-1, IRQ-2 to CPU-2, and IRQ-3 to CPU-3.

[0048] However, the operating system's IRQ allocation process requires periodic counting of the number of IRQs, the load rate of each CPU, calculation of the interrupt affinity of each CPU, and interrupt migration. This results in a relatively high cost for each reallocation of the operating system. Furthermore, when the operating system evenly allocates IRQs, it may cause problems such as waking up idle processors, increasing the latency of IRQ processing for highly loaded processors, and increasing the power consumption of high-frequency processors, leading to reduced power consumption and performance of the computing device.

[0049] As shown in Figure 1(b), the operating system can run four CPUs: CPU-0, CPU-1, CPU-2, and CPU-3. The operating system receives four IRQs: IRQ-0, IRQ-1, IRQ-2, and IRQ-3. When the operating system is in power save mode, it can start a background daemon thread to centrally distribute multiple IRQs to one or a small number of CPUs, thus avoiding waking up idle CPUs. That is, the operating system can distribute IRQ-1 from CPU-1 to CPU-0, IRQ-2 from CPU-2 to CPU-0, and IRQ-3 from CPU-3 to CPU-0.

[0050] However, the operating system's IRQ allocation process incurs a high cost for each reassignment. Furthermore, the operating system assigns multiple IRQs to CPU-0, placing it under high load. Because CPU-0 must handle a large number of IRQs, the latency associated with processing them is long, preventing the operating system from dynamically adjusting in real time.

[0051] As shown in Figure 1(c), the operating system can run four CPUs, namely CPU-0, CPU-1, CPU-2, and CPU-3. The operating system receives four IRQs, namely IRQ-0, IRQ-1, IRQ-2, and IRQ-3. Assume that CPU-0, CPU-1, and CPU-3 are in online mode, and CPU-2 is in offline mode. Offline mode means that CPU-2 may be in sleep mode or unplugged. When CPU-2 switches from online mode to offline mode, the operating system can migrate the IRQs bound to CPU-2 one by one to the CPU in working state. When CPU-2 switches from offline mode to online mode, the operating system can migrate the IRQs bound to other CPUs to CPU-2 one by one.

[0052] However, each time a CPU switches between offline and online modes, it must migrate its bound IRQs to other CPUs, or vice versa. If a large number of IRQs are migrated, the CPU cannot quickly switch from offline mode to online mode, or vice versa, causing operating system lag.

[0053] In order to address the defects in the related art, an embodiment of the present application provides an IRQ balancing method and a computing device. There are generally multiple processors inside the computing device to obtain the operating status of multiple processors. When the processor is in a set state, the computing device sets the processor to process IRQs other than the specified IRQ, and when the processor is in the running state, sets the processor to process the specified IRQ. The set state includes one or more of a non-idle state, an operating frequency within a preset frequency range, and a load rate less than a set load rate.

[0054] In an embodiment of the present application, a computing device can construct processors in a set state into a participating node. The computing device can run an interrupt balancing algorithm to evenly distribute received IRQs to the processors in the participating node, ensuring that each processor within the participating node has equal authority and can equally receive and process IRQs. After receiving an IRQ, the computing device defaults to assigning the IRQ to a processor within the participating node for processing. This can avoid resource competition among single-core processors outside the participating node, which can result in longer IRQ processing delays. This can also avoid problems such as waking up processors in an idle state, increasing IRQ processing delays for highly loaded processors, and increasing power consumption for high-frequency processors, which can lead to power consumption degradation and performance degradation of the computing device. Multiple processors within the participating node can evenly process IRQs, maintaining the same performance, such as load rate, power consumption, and operating frequency, for each processor in the set state. This can also avoid problems such as waking up processors in an idle state, increasing IRQ processing delays for highly loaded processors, and increasing power consumption for high-frequency processors, which can lead to power consumption degradation and performance degradation of the computing device.

[0055] Additionally, a lightweight interrupt request balancer (IRQ balancer) can be designed within the collection node. This balancer monitors performance parameters such as the idle state, load rate, and operating frequency of each processor, as well as system parameters such as the computing device's application scenario and the number of processors. It dynamically adjusts the processors within the collection node, migrating them in and out of the collection node in a lightweight manner. The collection node optimizes its internal processors for better IRQ handling.

[0056] A collection node is a software-defined node that is partitioned based on the characteristics and functionality of the processors that process IRQs other than the specified IRQ. In this embodiment of the present application, a processor within a collection node indicates that it can process IRQs other than the specified IRQ. A processor outside a collection node indicates that it can process the specified IRQ or does not process the IRQ.

[0057] The processors inside a collection node are those in a set state, and the processors outside a collection node are those not in a set state. "Migrating out of a collection node" means switching the operating state of a processor from a specific state to a state not in a specific state. "Migrating into a collection node" means switching the operating state of a processor from a state not in a specific state to a specific state. Therefore, the technical solution of this application will be described below using the "collection node" to help readers better understand the technical solution of this application.

[0058] As shown in Figure 2, the operating system can run on four CPUs: CPU-0, CPU-1, CPU-2, and CPU-3. The operating system receives six IRQs: IRQ-0, IRQ-1, IRQ-2, IRQ-3, IRQ-4, and IRQ-5. CPU-0, CPU-1, and CPU-2 are inside the collection node. CPU-3 is outside the collection node. Assume that IRQ-0, IRQ-1, IRQ-2, and IRQ-3 are assigned to the collection node, while IRQ-4 and IRQ-5 are assigned to the collection node. The lightweight interrupt request balancer inside the collection node can easily migrate CPU-2 to or from the collection node.

[0059] In one scenario, when the operating system is in performance mode, the lightweight interrupt request balancer detects that CPU-2 is idle and can migrate CPU-2 out of the collection node. In this case, IRQs within the collection node are not routed to CPU-2 for processing. This prevents problems such as waking up an idle CPU, increasing IRQ processing latency on a highly loaded CPU, and increasing power consumption on a high-frequency CPU, which can lead to reduced power consumption and performance of the computing device.

[0060] In another scenario, when the operating system is in low-power mode, the lightweight interrupt request balancer can sense the processor's state and allow CPU-2 to enter the collection node. The collection node can then run an interrupt balancing algorithm to allocate some IRQs to CPU-2, reducing the number of IRQs that the original CPU within the collection node needs to handle, thereby avoiding the long latency of the original CPU within the collection node in processing IRQs, which prevents the operating system from being able to adjust dynamically in real time.

[0061] In another case, when the operating system is in a dormant state that can be awakened or hot-plugged, the lightweight interrupt request balancer can lightweightly migrate the dormant or unplugged CPU-2 out of the collection node, or migrate the dormant or plugged-in CPU-2 into the collection node. When the operating system determines that CPU-2 has migrated out of the collection node, the operating system allocates IRQs to other CPUs in the collection node without allocating IRQs to CPU-2. Compared with the related art, the operating system migrates multiple IRQs bound to a CPU to other CPUs one by one. In this application, only CPU-2 needs to be migrated out of the collection node, so that CPU-2 can quickly switch from online mode to offline mode.

[0062] Similarly, when the operating system determines that CPU-2 has been migrated to the collection node, it rechecks the CPUs within the collection node during IRQ allocation and distributes the IRQs evenly to each CPU within the collection node. Compared to related technologies, where the operating system needs to migrate multiple IRQs bound to other CPUs to CPU-2 one by one, this application only requires migrating CPU-2 to the collection node, enabling CPU-2 to quickly switch from offline mode to online mode.

[0063] FIG3 is a schematic diagram of the architecture of a computing device provided in an embodiment of the present application. As shown in FIG3 , a computing device 300 includes an application 310 , an operating system 320 , a basic input and output system (BIOS) 330 , and hardware components 340 .

[0064] Application 310 is a computer program that performs one or more specific tasks. Installed in operating system 320, application 310 interacts with the user, creating and executing tasks upon receiving user commands. Each application 310 runs in an independent process and has its own address space.

[0065] The operating system 320 is a set of interrelated system software programs that manage and control computer operations, run hardware and software resources, and provide common services to organize user interactions. The operating system 320 schedules various resource components of the computing device 300, including hardware and software devices, data, and information. Using a computer operating system can reduce the workload of manual resource allocation, minimize user intervention in computer operations, and significantly improve the computer's intelligent operating efficiency. The operating system 320 can be, for example, a Linux real-time operating system.

[0066] BIOS 330 is an industry-standard firmware interface. It is a set of programs hardwired into a read-only memory (ROM) chip on the computer's motherboard. It stores the computer's most important basic input and output routines, the post-boot self-test program, and the system startup routine. The primary function of BIOS 330 is to provide the lowest-level, most direct hardware configuration and control for the computer. BIOS 330 does not directly control hardware components 340, but rather provides an abstraction layer and directly controls them.

[0067] The hardware component 340 includes various hardware components of the computing device 300 , such as a CPU, a hard disk, a network card, an interrupt controller, etc. The hardware component 340 is used to support the normal operation of the computing device 300 .

[0068] The operating system 320 can divide its operating memory space into two parts: kernel space and user space. User space refers to the space where user program code runs. Kernel space refers to the space where kernel code runs. When a process runs in user space, it is in "user mode." A process in user mode 321 is also called a user mode process. When a process runs in kernel space, it is in "kernel mode." A process in kernel mode 322 is also called a kernel mode process.

[0069] In the design of operating system 320, User State 321 refers to an unprivileged execution state. The kernel prohibits code in this state from performing potentially dangerous operations, such as writing system configuration files, killing other user processes, or restarting the system. Kernel State 322 refers to a privileged execution state. The kernel can perform any operation on code in this state.

[0070] As shown in FIG4 , the operating system 320 is divided into an interrupt initialization module 3221, an interrupt routing management module 3222, a behavior perception module 3223, and a collection node management module 3224 in the kernel state 322, and an interrupt processing module 3211 in the user state 321, based on the functions being executed. The interrupt initialization module 3221, the interrupt routing management module 3222, the behavior perception module 3223, the collection node management module 3224, and the interrupt processing module 3211 can all be implemented through software, hardware, or a combination of software and hardware.

[0071] The technical solution of the present application is described below with reference to the various execution modules of the operating system 320 and the control flow chart shown in FIG5 .

[0072] The hardware component 340 includes an interrupt controller 341. The interrupt controller 341 can be hardware such as GIC and APIC. GIC is an interrupt controller based on the advanced RISC machine (ARM) architecture. In a multi-core processor system, GIC can coordinate the interrupt signal processing between multiple processor cores and provide a consistent interrupt management and distribution mechanism to ensure that the system can run efficiently and reliably respond to external events and devices. APIC is an interrupt controller based on the extended 86 architecture. APIC is used to process and distribute interrupt signals to ensure that the interrupt signals are correctly routed to the corresponding processor core or device.

[0073] The interrupt initialization module 3221 is used to initialize the interrupt controller 234 to ensure that the operating system 320 can accurately and reliably capture and process interrupt events. In addition, the interrupt initialization module 3221 can also sniff the routing mode of the interrupt routing management module 3222, detect which type of routing mode the hardware indicates, and adjust the software policy accordingly.

[0074] After receiving an IRQ, the interrupt routing management module 3222 can select an IRO routing method based on the user-configured interrupt configuration information. IRO routing methods can be categorized as single-core processing routing and multi-core balanced processing routing. Single-core processing routing assigns the IRQ to a specific processor for processing. Multi-core balanced processing routing assigns the IRQ to a row of processors within the collection node for processing.

[0075] In an embodiment of the present application, when the operating system 320 performs interrupt registration, the interrupt handler is associated with a specific interrupt signal. The operating system 320 can divide the processor into a specific processor and a general processor according to the properties of the IRQ processed by the processor. A specific processor is a processor that processes special IRQs such as high-priority IRQs and emergency IRQs. A general processor is a processor that processes IRQs other than special IRQs. The operating system 320 can build the general processors into a collection node so that the general processors can receive and process IRQs equally. The operating system 320 can receive the user's interrupt configuration information for IRQ, divide the IRQ routing mode into a single-core processing routing mode and a multi-core balanced processing routing mode, and select a suitable routing mode for IRQ transmission.

[0076] In one case, when the interrupt routing management module 3222 determines that the IRQ is a special IRQ, it can migrate the IRQ to a specific processor through a single-core processing routing method, allowing the specific processor to specifically handle the special IRQ. Since the special IRQ can only be handled by the specific processor, the specific processor will receive and process the special IRQ regardless of its state.

[0077] In another case, when the interrupt routing management module 3222 determines that the IRQ is not a special IRQ, it defaults to migrating the IRQ to the collection node through multi-core balanced processing routing. The collection node runs an interrupt balancing algorithm to evenly distribute the received IRQ to the processors within the collection node.

[0078] The behavior sensing module 3223 can use the light IRQ balancer to periodically detect parameters of target devices such as the processor, hard disk, clock or timer, external device, and external controller to determine whether the processor is in a sleep state, awakened, or hot-swapped state, whether the processor is in an idle state, whether the processor's operating frequency is within a preset frequency range, whether the processor's load rate is less than a set load rate, whether the processor is processing a high-priority IRQ, whether the processor is processing an emergency IRQ, and the application scenario of the computing device 300. Application scenarios may include communication, application usage, mobile office, web browsing, and the like.

[0079] The collection node management module 3224 typically runs an interrupt balancing algorithm to evenly distribute multiple received IRQs to the various processors within the collection node. This allows each processor within the collection node to process IRQs equally, ensuring consistent operating states for each processor and preventing abnormal states such as high load or high frequency on individual processors. The collection node management module 3224 detects whether the processor states have changed and can optimize the processors within the collection node to better handle IRQs. For example, if a processor within the collection node is in an idle state, the collection node management module 3224 can migrate the idle processors out of the collection node. This can avoid problems such as waking up the idle processors, increasing the latency of high-load processors in processing IRQs, and increasing the power consumption of high-frequency processors, which can lead to reduced power consumption and performance of the computing device. For another example, if a processor within the collection node is in a high load rate, the collection node management module 3224 can migrate a specified number of processors outside the collection node into the collection node to reduce the load rate within the collection node. For another example, when the operating frequency of a processor inside the collection node exceeds the preset frequency range, the collection node management module 3224 can migrate the processor whose operating frequency is not within the set range out of the collection node to avoid large differences in the operating frequencies of the processors inside the collection node, which leads to degradation of the power consumption of the operating system.

[0080] The interrupt processing module 3211 can import the IRQ from the kernel state 322 to the user state 321 according to the routing status of the IRQ, so that the processor called by the user state 321 can process the IRQ.

[0081] In an embodiment of the present application, the operating system 320 can construct some processors into a collection node based on the user's configuration items. The collection node can run an interrupt balancing algorithm to evenly distribute the received IRQs to the processors of the collection node, so that each processor within the collection node has equal authority and can equally receive and process IRQs. The collection node can receive information about devices involved in processing IRQs, dynamically adjust the processors within the collection node, and allow processors to migrate out of or into the collection node in a lightweight manner. The collection node optimizes the internal processors to better handle IRQs.

[0082] The above is an introduction to the computing device 300 provided in the embodiment of the present application. Next, based on the above content, the IRQ equalization method provided in the embodiment of the present application is introduced.

[0083] FIG6 shows a flow chart of an IRQ balancing method provided in an embodiment of the present application. The method may be executed by the operating system 320. As shown in FIG6 , the IRQ balancing method may include the following steps:

[0084] S601 , the operating system 320 obtains the operating status of multiple processors of the computing device 300 .

[0085] Computing device 300 can be a terminal device such as a server, desktop computer, or portable notebook computer. Computing device 300 typically includes multiple processors, each of which performs the key tasks of performing calculations and controlling computer operations. The processors can be devices with computing capabilities, such as a CPU, a graphics processing unit (GPU), or an extensible processing unit (XPU).

[0086] In one case, when there is only one device with computing function inside the computing device 300, the computing device 300 can divide the resources of the device with computing function into multiple computing units according to the computing function. In this case, the processor can be the computing unit.

[0087] In another case, when the computing device 300 is a computing cluster composed of multiple servers, one server can be used as a processor.

[0088] S602: When the processor is in a setting state, the operating system 320 sets the processor to process IRQs other than the designated IRQ.

[0089] S603: When the processor is in the running state, the operating system 320 sets the processor to process the specified IRQ.

[0090] The operating system 320 can use a light IRQ balancer to detect performance parameters such as the idle state, load rate, and operating frequency of each processor, as well as system parameters such as the computing device's application scenario and the number of processors. Based on the processor performance parameters, the operating system 320 can group processors that are in a non-idle state, have an operating frequency within a preset frequency range, and have a load rate less than a set load rate into a collection node. Processors in other states are located outside the collection node. The collection node can run an interrupt balancing algorithm to evenly distribute received IRQs to processors within the collection node. The processors within the collection node have equal authority and can receive and process IRQs equally.

[0091] Optionally, the operating system 320 can divide the processors into specific processors and general processors based on the properties of the IRQs handled by the processors. Specific processors are used to handle special IRQs such as high-priority IRQs and emergency IRQs. General processors are used to handle IRQs other than special IRQs. The operating system 320 can construct general processors into a collection node and transmit non-special IRQs to the collection node by default. The operating system 320 can set the specific processors outside the collection node, allowing the specific processors to act as single-core processors and specifically receive and process special IRQs.

[0092] In an embodiment of the present application, the operating system 320 can detect the status of each processor during the process of constructing a collection node, filter out processors that are in idle state, in high load rate, processing special IRQ, in sleep state or hot-plug state, etc., and construct other processors into a collection node, so that the processors inside the collection node can process IRQ at will.

[0093] A collection node can be configured with a lightweight interface, allowing processors inside the collection node to exit the collection node and processors outside the collection node to enter the collection node. Lightweight interfaces are designed to be simple, flexible, practical, and efficient, providing a concise and effective communication and interaction method. Lightweight interfaces offer low latency, allowing processors to quickly traverse them and rapidly change processors within the collection node.

[0094] In an embodiment of the present application, after receiving an IRQ, the operating system 320 selects an appropriate routing method for the IRQ based on the interrupt configuration information, and migrates the IRQ to the corresponding processor for processing through the appropriate routing method. The routing method of the IRQ can be divided into a single-core processing routing method and a multi-core balanced processing routing method. The single-core processing routing method indicates that the IRQ is assigned to a specific processor for processing. The multi-core balanced processing routing method indicates that the IRQ is assigned to the processor row within the collection node for processing.

[0095] Interrupt configuration information is pre-stored by the user and generally includes information such as the importance of the IRQ and the consistency of input / output (I / O) data storage. In one embodiment, upon receiving an IRQ, the operating system 320 detects that the importance of the IRQ matches the importance of the interrupt configuration information and may select single-core processing routing to migrate the IRQ to a specific processor. Conversely, the operating system 320 selects multi-core balanced processing routing to migrate the IRQ to a collection node.

[0096] The operating system 320 can use the light IRQ balancer to periodically detect parameters of target devices such as the processor, hard disk, clock or timer, external device, external controller, etc. to determine whether the processor is in a sleep state or hot-plug state, whether the processor is in an idle state, whether the processor's operating frequency is within a preset frequency range, whether the processor's load rate is less than the set load rate, whether the processor handles high-priority IRQ, whether the processor handles emergency IRQ, the application scenario of the computing device 300, etc.

[0097] The operating system 320 modifies the processors within the collection node based on whether the processor states have changed, allowing the collection node to better handle IRQs. In one scenario, if the operating system 320 determines that a processor within the collection node is in an idle state, it can migrate the idle processor out of the collection node via a lightweight interface. This avoids issues such as waking up the idle processor, increasing the latency of IRQ processing for highly loaded processors, and increasing the power consumption of high-frequency processors, which could lead to reduced power consumption and performance of the computing device.

[0098] Optionally, when the operating system 320 detects that a processor that has exited the collection node has switched from an idle state to an active state, the operating system 320 can migrate the processor into the collection node via a lightweight interface. By allowing the processor that exited the collection node to reenter the collection node, the operating system 320 can reduce the load on the processor within the collection node and avoid long delays in the processor processing IRQs, which could prevent the operating system 320 from making real-time dynamic adjustments.

[0099] In another case, when the operating system 320 determines that a processor in the collection node is in a dormant and awakenable state or hot-pluggable state, the processor in the dormant and awakenable state or hot-pluggable state may go offline or online at any time, causing the working state of other processors in the collection node to be unstable. The operating system 320 detects the status of the processor and can migrate the dormant or unplugged processor out of the collection node through a lightweight interface, or migrate the dormant or plugged-in processor into the collection node through a lightweight interface, so as to prevent the dormant and awakenable or hot-pluggable processor from affecting the working state of other processors in the collection node.

[0100] In addition, when a processor is suddenly inserted into the computing device 300 or awakened from a dormant state, the computing device 300 needs to allocate the IRQ to the inserted processor as quickly as possible to improve the response speed of the processor. Similarly, when a processor is suddenly unplugged from the computing device or enters an idle state, the computing device 300 needs to allocate the IRQ bound to the offline processor to other processors as quickly as possible to avoid the computing device from suddenly going offline and causing the processor to crash. In an embodiment of the present application, when the operating system 320 determines that a processor inside a collection node has migrated out of a collection node or a processor has migrated into a collection node, the IRQ allocation scheme can be modified. The operating system 320 detects the processors inside the collection node and evenly distributes the IRQs to the various processors inside the current collection node. Compared with related technologies, the operating system 320 converts the operation of migrating IRQs into the operation of migrating processors, so that a processor in a dormant state can be awakened or hot-plugged and can quickly switch from offline mode to online mode, or from online mode to offline mode.

[0101] In another case, when the operating system 320 detects that the processors within the collection node are under high load, it can migrate the processors outside the collection node into the collection node through a lightweight interface. The operating system 320 increases the number of processors within the collection node to reduce the number of IRQs handled by each processor, thereby switching the processors within the collection node from a high load rate to a normal state or a low load rate.

[0102] In another scenario, when the operating system 320 detects that the operating frequency of a processor within a collection node exceeds a preset frequency range, it can migrate the processor in a high-frequency or low-frequency state out of the collection node via a lightweight interface, or shut down the processor in a high-frequency or low-frequency state, thereby adjusting the frequency of multiple processors in the collection node. By shutting down the processor in the collection node with an excessively high or low frequency, the operating system 320 keeps the processors in the collection node within the preset range, allowing the multiple processors in the collection node to process IRQs in parallel and improving the uniformity of the operating frequency distribution of the processors in the collection node.

[0103] In another case, when the operating system 320 detects that a processor inside the collection node is specifically used to process special IRQs such as high-priority IRQs and emergency IRQs, the processor can be migrated out of the collection node through a lightweight interface to prevent the processor from continuing to receive other IRQs in the collection node, thereby affecting the processing progress of the special IRQ.

[0104] In another case, when the operating system 320 detects the application scenario in which the computing device 300 is located, it can migrate a set number of processors outside the collection node into the collection node through a lightweight interface, or migrate a set number of processors inside the collection node out of the collection node through a lightweight interface based on the pre-set number of processors of the collection node corresponding to each scenario, so as to ensure that the number of processors inside the collection node remains at the number of processors corresponding to the scenario in which the computing device 300 is located.

[0105] Computing devices can be used in various application scenarios, such as communications, application usage, mobile office work, and web browsing. Different application scenarios generate different numbers of IRQs, requiring different numbers of processors in specific states to handle them. Therefore, designers can pre-train and store the relationship between different application scenarios and the number of processors in specific states. After detecting the current application scenario, the computing device can adjust the number of processors in a specific state to ensure that the power consumption, load rate, latency, and other performance of the processors in that specific state are always optimized.

[0106] In an embodiment of the present application, the operating system forms a collection node with some of the multiple processors of the computing device. The collection node can run an interrupt balancing algorithm to allow the processors inside the collection node to process IRQs in a balanced manner. The processors outside the collection node can not process IRQs or process special IRQs. After receiving the IRQ, the operating system can assign the IRQ to the processor inside the collection node by default, which can avoid competition for resources among the processors outside the collection node, resulting in a long delay in the processor inside the collection node processing the IRQ. The multiple processors inside the collection node can process IRQs in a balanced manner, avoiding a single processor from processing IRQs with a high load, thereby improving the performance of the operating system and reducing the power consumption of the operating system.

[0107] In addition, the operating system detects whether the status of the processor has changed, and migrates the processors out of the collection node in special circumstances such as being in idle state, operating frequency not within the preset frequency range, load rate not less than the set load rate, processing special IRQs, etc., and migrates some processors to the collection node when the processors inside the collection node are at a high load rate. This can optimize the processors inside the collection node and allow the processors inside the collection node to better handle IRQs.

[0108] Figures 7(a) to 7(c) are data diagrams of experiments conducted on computing devices using the protection scheme of this application.

[0109] As shown in Figure 7(a), a computing device can run four cores: core 0, core 1, core 2, and core 3. The first row of data indicates that core 0 is idle, while cores 1, 2, and 3 are active. When the computing device runs the "Honor of Kings" application, core 0 (also known as CPU 0) is interrupted 11,051 times while in idle state. The weighted average frequency distribution of the four cores is 1391.542 MHz.

[0110] The second row of data indicates that cores 0, 1, 2, and 3 are in idle state. When the computing device runs Honor of Kings, core 0 (also known as cpu0) will be interrupted 6353 times when it is in idle state, core 1 (also known as cpu1) will be interrupted 3342 times when it is in idle state, core 2 (also known as cpu2) will be interrupted 3463 times when it is in idle state, and core 3 (also known as cpu3) will be interrupted 4305 times when it is in idle state. The weighted average of the frequency distribution of cores 0, 1, 2, and 3 is 1520.9MHz. It can be seen from this that although the number of interruptions of a single core in idle state has decreased, the operating frequency fluctuations of the four cores have increased.

[0111] The third line of data indicates that there are cores 0, 1, 2, and 3 inside the collection node, and the cores inside the collection node are in an idle state and can be migrated out of the collection node. When the computing device runs Honor of Kings, the generated IRQ is handled by the core inside the collection node. Core 0 (also known as cpu0) will be interrupted 7559 times when it is in an idle state. The weighted average frequency distribution of the cores inside the collection node is 1300.9MHz. It can be seen from this that the number of interruptions to the cores inside the collection node when they are in an idle state is reduced, and the operating frequency fluctuations of multiple cores inside the collection node are reduced.

[0112] As shown in Figure 7(b), the computing device can run four cores, namely 0 core, 1 core, 2 cores, and 3 cores. The first row of data indicates that there is only 0 core inside the collection node, and the collection node will not migrate out or migrate into the core. When the computing device runs the "JD.com" application, the latency of 0 core processing IRQ inside the collection node is 3ms116us. When the computing device runs the "Honor of Kings" application, the latency of 0 core processing IRQ inside the collection node is 7ms20us. When the computing device plays "TikTok", the latency of 0 core processing IRQ inside the collection node is 89us on average (the extreme values ​​are between 19-1069us).

[0113] The second row of data indicates that there are 0 cores, 1 core, 2 cores, and 3 cores inside the collection node, and the collection node migrates out of or into the core. When the computing device runs the "JD.com" application, the latency of the 0 core processing IRQ inside the collection node is 1ms459us. When the computing device runs the "Honor of Kings" application, the latency of the 0 core processing IRQ inside the collection node is 1ms238us. When the computing device plays "Tik Tok", the latency of the 0 core processing IRQ inside the collection node is an average of 89us (the extreme value is between 20-421us). It can be seen that the latency of the 0 core processing IRQ inside the collection node has been greatly reduced.

[0114] As shown in Figure 7(c), the first row shows that when a core switches from active to sleep mode, it takes 11,000 ns to migrate 100 IRQs bound to that core to other cores. The second row shows that it takes 0.5 ns for a core to migrate out of a collection node. This shows that migrating a single core significantly reduces the time required to migrate 100 IRQs.

[0115] FIG8 is a schematic diagram of the structure of an IRQ equalization device provided in an embodiment of the present application. As shown in FIG8 , the IRQ equalization device 800 can be divided into a transceiver unit 810 and a processing unit 820 according to the execution function. The specific implementation process of the IRQ equalization device 800 is as follows:

[0116] The transceiver unit 810 is configured to obtain the operating status of multiple processors. The processing unit 820 is configured to configure the processor to process a specified IRQ when the processor is not in a set state. The set state includes one or more of a non-idle state, an operating frequency within a preset frequency range, and a load rate less than a set load rate. The processing unit 820 is further configured to configure the processor to process an IRQ other than the specified IRQ when the processor is in the set state.

[0117] In one embodiment, the processing unit 820 is further configured to distribute IRQs other than the designated IRQs to the processors in the set state in a balanced manner based on an interrupt balancing algorithm.

[0118] In one embodiment, the processing unit 820 is further configured to configure the processor to process a specified IRQ when the operating state of the processor is switched from a configured state to a non-configured state.

[0119] In one embodiment, the processing unit 820 is further configured to configure the processor to process IRQs other than the designated IRQ when the operating state of the processor is switched from a non-configured state to a configured state.

[0120] In one embodiment, the processing unit 820 is further configured to set some processors that are not in the set state to process IRQs other than the specified IRQs in response to the number of IRQs received by the processors in the set state exceeding a set threshold.

[0121] In one embodiment, the processing unit 820 is further configured to detect an application scenario of the computing device; and adjust the number of processors currently in the set state based on a pre-stored relationship between the number of processors in the set state corresponding to various application scenarios of the computing device.

[0122] A computing device is also provided in an embodiment of the present application. The computing device includes at least one memory and multiple processors, the multiple processors including a main processor, and the main processor can execute the technical solutions shown in Figures 2-7(c) and the above-mentioned corresponding protections, so that the computing device has the technical effects of the above-mentioned technical solutions.

[0123] In an embodiment of the present application, a computer-readable storage medium is also provided, on which a computer program is stored. When the computer program is executed in a computer, the computer is caused to execute the IRQ equalization method described in any one of Figures 2 to 7 (c) and the corresponding description content.

[0124] A computer program product is also provided in an embodiment of the present application. The computer program product stores instructions, and when the instructions are executed by a computer, the computer implements the IRQ equalization method described in any one of Figures 2 to 7 (c) and the corresponding description content.

[0125] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of this application.

[0126] In addition, various aspects or features of the embodiments of the present application can be implemented as methods, devices or products using standard programming and / or engineering techniques. The term "product" used in this application covers computer programs that can be accessed from any computer-readable device, carrier or medium. For example, computer-readable media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks or tapes, etc.), optical disks (e.g., compact discs (CDs), digital versatile discs (DVDs), etc.), smart cards and flash memory devices (e.g., erasable programmable read-only memories (EPROMs), cards, sticks or key drives, etc.). In addition, the various storage media described herein may represent one or more devices and / or other machine-readable media for storing information. The term "machine-readable medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing and / or carrying instructions and / or data.

[0127] In the above embodiment, the IRQ equalization device 800 in FIG8 can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated therein. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a high-density digital video disc (DVD)), or a semiconductor medium (eg, a solid state disk (SSD)).

[0128] It should be understood that in various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0129] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0130] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0131] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0132] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or an access network device, etc.) to execute all or part of the steps of the method described in each embodiment of the embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0133] The above is only a specific implementation of the embodiment of the present application, but the protection scope of the embodiment of the present application is not limited to this. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in the embodiment of the present application, and they should all be covered by the protection scope of the embodiment of the present application.

Claims

1. A method for balancing interrupt requests IRQ, characterized in that: The method is executed by a computing device, wherein the computing device includes a plurality of processors, and the method includes: Obtaining the operating status of the multiple processors; When the processor is not in a set state, the processor is set to process a specified IRQ; the set state includes one or more of a non-idle state, an operating frequency within a preset frequency range, and a load rate less than a set load rate; When the processor is in the setting state, the processor is set to process an IRQ other than the designated IRQ.

2. The method according to claim 1, characterized in that The method further comprises: Based on an interrupt balancing algorithm, the IRQs other than the designated IRQs are evenly distributed to the processors in the set state.

3. The method according to claim 1 or 2, characterized in that: Also includes: When the operation state of the processor is switched from being in the set state to being not in the set state, the processor is set to process a designated IRQ.

4. The method according to any one of claims 1 to 3, characterized in that: Also includes: When the operation state of the processor is switched from not being in the set state to being in the set state, the processor is set to process the IRQ other than the designated IRQ.

5. The method according to any one of claims 1 to 4, characterized in that: Also includes: In response to the number of IRQs received by the processor in the setting state exceeding a set threshold, some of the processors not in the setting state are set to process the IRQs other than the designated IRQ.

6. The method according to any one of claims 1 to 5, characterized in that: Also includes: Detecting an application scenario of the computing device; Based on the pre-stored relationship between the number of processors in the set state corresponding to various application scenarios of the computing device, the number of processors currently in the set state is adjusted.

7. An interrupt request IRQ equalization device, characterized in that: include: A transceiver unit, configured to obtain the operating status of the plurality of processors; A processing unit, configured to set the processor to process a specified IRQ when the processor is not in a set state; the set state includes one or more of a non-idle state, an operating frequency within a preset frequency range, and a load rate less than a set load rate; When the processor is in the setting state, the processor is set to process an IRQ other than the designated IRQ.

8. The device according to claim 7, characterized in that The processing unit is further configured to distribute the IRQs other than the designated IRQs to the processors in the set state in a balanced manner based on an interrupt balancing algorithm.

9. The device according to claim 7 or 8, characterized in that The processing unit is further configured to set the processor to process a specified IRQ when the operating state of the processor is switched from being in the set state to not being in the set state.

10. The device according to any one of claims 7 to 9, characterized in that: The processing unit is further configured to, when the operating state of the processor is switched from not being in the set state to being in the set state, set the processor to process the IRQ other than the designated IRQ.

11. The device according to any one of claims 7 to 10, characterized in that: The processing unit is further configured to, in response to the number of IRQs received by the processor in the set state exceeding a set threshold, set some of the processors not in the set state to process the IRQs other than the designated IRQs.

12. The device according to any one of claims 7 to 11, characterized in that: The processing unit is further used to detect an application scenario of the computing device; Based on the pre-stored relationship between the number of processors in the set state corresponding to various application scenarios of the computing device, the number of processors currently in the set state is adjusted.

13. A computing device, characterized in that: include: at least one memory, A plurality of processors, wherein the plurality of processors include a main processor, wherein the main processor is configured to execute instructions stored in the at least one memory so that the computing device performs the method according to any one of claims 1 to 6.

14. A computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to execute the method according to any one of claims 1 to 6.

15. A computer program product, characterized in that The computer program product stores instructions, and when the instructions are executed by a computer, the computer is caused to implement the method according to any one of claims 1 to 6.

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