Multiply-accumulate circuit, processor comprising multiply-accumulate circuit, and computing apparatus

Abstract

Provided in the present application are a multiply-accumulate circuit (100), a processor comprising the multiply-accumulate circuit, and a computing apparatus. The multiply-accumulate circuit comprises at least one multiply-accumulate unit (110) and a summing unit (120). The multiply-accumulate unit (110) comprises: a multiplication sub-circuit (111), configured to receive multipliers and calculate the products thereof; an accumulation sub-circuit (112), an input end thereof being coupled to an output end of the multiplication sub-circuit (111), and the accumulation sub-circuit (112) being configured to receive and accumulate outputs of the multiplication sub-circuit (111); and a control sub-circuit (113), an input end thereof being coupled to an output end of the accumulation sub-circuit (112), an output end thereof providing an output end of the multiply-accumulate unit (110), and the control sub-circuit (113) being configured to receive a control signal and outputs of the accumulation sub-circuit (112) and, on the basis of the control signal, control whether to provide the outputs of the accumulation sub-circuit (112) at the output end of the control sub-circuit (113). An input end of the summing unit (120) is coupled to the output end of the at least one multiply-accumulate unit (110), and the summing unit (120) is configured to receive and sum outputs of the at least one multiply-accumulate unit (110). The present application allows for low-power multiply-accumulate circuits.

Description

Multiplication-accumulation circuit, processor and computing device including the multiplication-accumulation circuit

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the application with CN application number 202310990483.3 and application date August 8, 2023, and claims its priority. The disclosed content of the CN application is hereby introduced as a whole into this application. Technical Field

[0003] The present disclosure relates to the technical field of data processing, and more particularly, to a multiplication-accumulation circuit, a processor including the multiplication-accumulation circuit, and a computing device. Background Art

[0004] The multiply and accumulate (MAC) circuit is used to perform multiply and accumulate operations such as vector multiplication, matrix multiplication, and vector-matrix multiplication. It is an extremely important operation subsystem in processors such as coprocessors, digital signal processors, central processing units, special instruction processors, and neural network processors. In particular, the rapid development of artificial intelligence has highlighted the important role of neural network processors, making neural network processors gradually become the cornerstone of intelligent computing technology. The convolution calculation unit is the core unit of the neural network processor, and its implementation is inseparable from the multiplication and accumulation circuit of the activation data and weight data. Since the convolution calculation unit is also the power consumption center of the neural network processor, the design of a low-power multiplication and accumulation circuit is crucial for the convolution calculation unit and is also the key to the large-scale application of the neural network processor containing it.

[0005] Summary of the Invention

[0006] According to a first aspect of the present disclosure, a multiplication-accumulation circuit is provided, comprising at least one multiplication-accumulation unit and a summation unit. The multiplication-accumulation unit comprises a multiplication subcircuit, an accumulation subcircuit, and a control subcircuit. The multiplication subcircuit is configured to receive a multiplier and calculate a product thereof. The input of the accumulation subcircuit is coupled to the output of the multiplication subcircuit. The accumulation subcircuit is configured to receive the output of the multiplication subcircuit and accumulate it. The input of the control subcircuit is coupled to the output of the accumulation subcircuit. The output of the control subcircuit provides the output of the multiplication-accumulation unit. The control subcircuit is configured to receive a control signal and the output of the accumulation subcircuit and control whether to provide the output of the accumulation subcircuit at the output of the control subcircuit based on the control signal. The input of the summation unit is coupled to the output of the at least one multiplication-accumulation unit. The summation unit is configured to receive the output of the at least one multiplication-accumulation unit and sum it.

[0007] In some embodiments, the multiplication subcircuit includes one or more multipliers, each of the one or more multipliers being configured to receive a corresponding pair of multipliers and to calculate a product of the corresponding pair of multipliers. In some examples, the multipliers of the multiplication subcircuit have a single output terminal. In some examples, the multipliers of the multiplication subcircuit have a dual output terminal.

[0008] In some embodiments, the accumulation subcircuit includes a compression tree and multiple register groups, each output terminal of the compression tree is coupled to the input terminal of a corresponding one of the multiple register groups, the output terminal of the multiplication subcircuit and the output terminal of each of the multiple register groups are respectively coupled to the corresponding input terminal of the compression tree, wherein the output terminal of each of the multiple register groups is respectively coupled to the corresponding input terminal of the control subcircuit, and the control subcircuit is configured to control whether the output of each of the multiple register groups is respectively provided at the corresponding output terminal of the control subcircuit according to the control signal.

[0009] In some embodiments, the control subcircuit includes a plurality of control elements, a first input terminal of each of the plurality of control elements is coupled to an output terminal of a corresponding one of the plurality of register groups, a second input terminal of each of the plurality of control elements is configured to receive a control signal, an output terminal of each of the plurality of control elements provides a corresponding one of the output terminals of the multiplication and accumulation unit, and each of the plurality of control elements is configured to control whether the output of the corresponding one of the register groups is provided at the output terminal of the control element according to the received control signal.

[0010] In some embodiments, the accumulation subcircuit includes a full adder module having one or more stages of full adders, a first register group, and a second register group. The first output of the full adder module is coupled to the input of the first register group, and the second output of the full adder module is coupled to the input of the second register group. The output of the multiplication subcircuit, the output of the first register group, and the output of the second register group are respectively coupled to the corresponding inputs of the full adder module. The output of the first register group and the output of the second register group are respectively coupled to the corresponding inputs of the control subcircuit, and the control subcircuit is configured to control whether the output of the first register group and the output of the second register group are respectively provided at the corresponding outputs of the control subcircuit according to the control signal.

[0011] In some embodiments, the control subcircuit includes: a first control element, wherein a first input terminal of the first control element is coupled to an output terminal of the first register group, a second input terminal of the first control element is configured to receive a control signal, an output terminal of the first control element provides a first output terminal of the multiplication and accumulation unit, and the first control element is configured to control whether the output of the first register group is provided at the output terminal of the first control element according to the received control signal; and a second control element, wherein a first input terminal of the second control element is coupled to an output terminal of the second register group, a second input terminal of the second control element is configured to receive a control signal, an output terminal of the second control element provides a second output terminal of the multiplication and accumulation unit, and the second control element is configured to control whether the output of the second register group is provided at the output terminal of the second control element according to the received control signal.

[0012] In some embodiments, the control subcircuit includes at least one of the following: an AND gate, a NAND gate, a multiplexer, and an inverting multiplexer.

[0013] In some embodiments, the control signal is configured so that the control subcircuit does not provide the output of the accumulation subcircuit at the output end of the control subcircuit before the accumulation subcircuit completes each round of accumulation, and is configured to provide the output of the accumulation subcircuit at the output end of the control subcircuit after the accumulation subcircuit completes each round of accumulation and before starting the next round of accumulation.

[0014] In some embodiments, the summing unit comprises an adder.

[0015] In some embodiments, the at least one multiplication-accumulation unit includes two or more multiplication-accumulation units, the summation unit includes an n-level compression tree and an adder, the output end of each of the two or more multiplication-accumulation units is coupled to the corresponding input end of the 1st-level compression tree in the n-level compression tree, the output end of the i-th-level compression tree in the n-level compression tree is coupled to the corresponding input end of the (i+1)th-level compression tree in the n-level compression tree, and the output end of the n-th-level compression tree in the n-level compression tree is coupled to the corresponding input end of the adder, wherein n is a positive integer, i=1, 2, ..., n-1.

[0016] In some embodiments, the summing unit further includes an additional register group, an input of the additional register group is coupled to the output of the adder, and an output of the additional register group is coupled to a corresponding input of the first-level compression tree in the n-level compression tree.

[0017] According to a second aspect of the present disclosure, a processor is provided, comprising the multiplication-accumulation circuit according to the first aspect of the present disclosure.

[0018] According to a third aspect of the present disclosure, a computing device is provided, comprising the processor according to the second aspect of the present disclosure.

[0019] Other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0021] The present disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0022] FIG1 shows a circuit diagram of a multiplication-accumulation circuit according to some comparative examples of the present disclosure;

[0023] FIG2 shows a schematic block diagram of a multiplication-accumulation circuit according to some embodiments of the present disclosure;

[0024] 3 to 7 respectively illustrate example circuit diagrams for implementing the multiplication-accumulation circuit of FIG. 2 according to some embodiments of the present disclosure;

[0025] FIG8 shows a schematic block diagram of a multiplication-accumulation circuit according to some embodiments of the present disclosure;

[0026] 9 to 11 respectively illustrate example circuit diagrams for implementing the multiplication-accumulation circuit of FIG. 8 according to some embodiments of the present disclosure.

[0027] Note that in the embodiments described below, the same reference numerals are sometimes used in common across different drawings to denote the same parts or parts having the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0028] To facilitate understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like may not always represent actual positions, sizes, and ranges. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges disclosed in the drawings and the like. Furthermore, the drawings are not necessarily drawn to scale, and some features may be exaggerated to illustrate details of specific components. DETAILED DESCRIPTION

[0029] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure.

[0030] The following description of at least one exemplary embodiment is merely illustrative and is not intended to limit the present disclosure, its application, or use. In other words, the structures and methods herein are presented in an exemplary manner to illustrate various embodiments of the structures and methods of the present disclosure. However, those skilled in the art will appreciate that these are merely exemplary of the disclosure that may be implemented, and are not exhaustive. Furthermore, the drawings are not necessarily drawn to scale, and some features may be exaggerated to illustrate details of specific components.

[0031] In addition, technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0032] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0033] FIG1 shows a multiplication-accumulation circuit 10, which includes a multiplier 11, an adder 12, and a register 13. Assume that the multiplication-accumulation circuit 10 is to calculate the multiplication-accumulation of the logarithm of x (a1·b1+a2·b2+......a x b x , x is a positive integer), then in each cycle of x periods, the corresponding pair of numbers a in the x logarithms is k 、b k (k=1, 2, ..., x) is fed as a multiplier to the multiplier 11 to calculate the product a of the pair k b k , then a k b k It is accumulated through adder 12 and register 13. For example, if the x logarithms are fed sequentially from 1 to x, then at the end of the first cycle the result stored in register 13 is a1·b1, at the end of the second cycle the result stored in register 13 is a1·b1+a2·b2, and so on until the end of the xth cycle the result stored in register 13 is a1·b1+a2·b2+...a x b x The multiplication and accumulation circuit 10 calculates a1·b1+a2·b2+......a x b xDuring the entire operation, multiplier 11 performs a multiplication operation in each cycle, adder 12 performs an addition operation in each cycle, and register 13 updates the result in each cycle. This causes the entire multiplication-accumulation circuit 10 to be constantly flipping (flipping means the circuit signal changes from 0 to 1 or from 1 to 0). This results in high dynamic power consumption of the multiplication-accumulation circuit 10. In particular, adder 12 is a significant source of circuit power consumption.

[0034] To this end, the present disclosure provides a multiply-accumulate circuit that is divided into a dynamic region and a static region, wherein the flipping frequency of the circuit portion of the static region is much lower than the flipping frequency of the circuit portion of the dynamic region. The static region has low power consumption due to its low flipping frequency, thereby realizing a multiply-accumulate circuit with reduced power consumption. The multiply-accumulate circuit according to various embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be understood that the actual multiply-accumulate circuit may also include additional components, and in order to avoid obscuring the key points of the present disclosure, these additional components are not shown in the drawings and are not discussed in the present disclosure.

[0035] FIG2 shows a multiply-accumulate circuit 100 according to some embodiments of the present disclosure. The multiply-accumulate circuit 100 includes a multiply-accumulate unit 110 and a summing unit 120. An input of the summing unit 120 is coupled to an output of the multiply-accumulate unit 110. The input of the multiply-accumulate unit 110 may provide an input IN of the multiply-accumulate circuit 100, while an output of the summing unit 120 may provide an output OUT of the multiply-accumulate circuit 100.

[0036] The multiplication and accumulation unit 110 includes a multiplication sub-circuit 111, an accumulation sub-circuit 112, and a control sub-circuit 113. The multiplication sub-circuit 111 is configured to receive a multiplier and calculate a product thereof. An input terminal of the multiplication sub-circuit 111 can provide an input terminal of the multiplication and accumulation unit 110. An input terminal of the accumulation sub-circuit 112 is coupled to an output terminal of the multiplication sub-circuit 111. The accumulation sub-circuit 112 is configured to receive an output of the multiplication sub-circuit 111 and accumulate it. An input terminal of the control sub-circuit 113 is coupled to an output terminal of the accumulation sub-circuit 112. An output terminal of the control sub-circuit 113 can provide an output terminal of the multiplication and accumulation unit 110. The control sub-circuit 113 is configured to receive a control signal S c The output of the summation sub-circuit 112 is then added according to the control signal S cThe control subcircuit 113 controls whether to provide the output of the accumulation subcircuit 112 at the output terminal of the control subcircuit 113. For example, the control signal can be configured to prevent the control subcircuit 113 from providing the output of the accumulation subcircuit 112 at the output terminal of the control subcircuit 113 before the accumulation subcircuit 112 completes each round of accumulation, and to provide the output of the accumulation subcircuit 112 at the output terminal of the control subcircuit 113 after the accumulation subcircuit 112 completes each round of accumulation and before starting the next round of accumulation. Note that, as can be understood with reference to FIG1 , “each round of accumulation” here refers to the accumulation performed from each time the register is cleared of the result stored therein to prepare for accumulation to the next time the register is cleared of the result stored therein to prepare for accumulation. In FIG1 , the result of the register 13 ranges from 0 to (a1·b1+a2·b2+...a x b x ) means completing a round of accumulation, rather than updating the result stored in the register each time.

[0037] The summing unit 120 is configured to receive and sum the outputs of the multiplication and accumulation unit 110. Under the control of the control subcircuit 113, the summing unit 120 does not receive the output of the accumulation subcircuit 112 until the accumulation subcircuit 112 completes its current round of accumulation, and thus does not perform a summing operation. In other words, under the control of the control subcircuit 113, the output of the multiplication and accumulation unit 110 received by the summing unit 120 before the accumulation subcircuit 112 completes its current round of accumulation is always zero. Only after the accumulation subcircuit 112 completes its current round of accumulation does the summing unit 120, under the control of the control subcircuit 113, receive and sum the outputs of the accumulation subcircuit 112. That is, throughout the entire operation of the multiplication and accumulation unit 110, the multiplication and accumulation unit 110 continuously flips, but the summing unit 120 does not flip. Only after the multiplication and accumulation unit 110 completes its operation does the summing unit 120 flip for one cycle for summing. The multiplication and accumulation unit 110 can be regarded as the active region of the multiplication and accumulation circuit 100, while the summing unit 120 can be regarded as the quiet region of the multiplication and accumulation circuit 100. By dividing the active region and the quiet region, the multiplication and accumulation circuit 100 achieves reduced power consumption.

[0038] In some embodiments, the multiplication subcircuit 111 may include one or more multipliers, each of which is configured to receive a corresponding pair of multipliers and calculate the product of the corresponding pair of multipliers. The multipliers in the multiplication subcircuit 111 may have a single output terminal or a dual output terminal, which can be configured according to specific needs. When the multiplication subcircuit 111 includes multiple multipliers, parallel computing can be implemented.

[0039] In some embodiments, accumulation subcircuit 112 may include a compression tree and multiple register banks. Each output of the compression tree is coupled to an input of a corresponding one of the multiple register banks. The output of multiplication subcircuit 111 and the output of each of the multiple register banks are respectively coupled to corresponding inputs of the compression tree. The output of each of the multiple register banks is respectively coupled to a corresponding input of control subcircuit 113. Control subcircuit 113 is configured to control whether the output of each of the multiple register banks is provided at a corresponding output of control subcircuit 113 based on a control signal. Common compression trees include those with two outputs, such as 4:2 compression trees and 3:2 compression trees, as well as those with three outputs, such as 5:3 compression trees, 6:3 compression trees, and 7:3 compression trees. The compression tree used in accumulation subcircuit 112 may be any existing or later-developed compression tree with any number of inputs and outputs, as long as it can compress the output result of multiplication subcircuit 111. When the sum of the number of output terminals of the multiplication subcircuit 111 and the number of output terminals of the register banks is greater than the number of input terminals of the compression tree employed, a combination of multiple compression trees may also be employed (e.g., a cascade of multiple stages of compression trees, where each stage of compression trees may include one compression tree or multiple compression trees in parallel). In some embodiments, the control subcircuit 113 may include multiple control elements, wherein a first input terminal of each of the multiple control elements is coupled to an output terminal of a corresponding one of the multiple register banks, a second input terminal of each of the multiple control elements is configured to receive a control signal, an output terminal of each of the multiple control elements is provided to a corresponding one of the output terminals of the multiplication-accumulation unit 110, and each of the multiple control elements is configured to control whether the output of the corresponding one of the register banks is provided at the output terminal of the control element according to the received control signal.

[0040] In other embodiments, the compression tree may alternatively be implemented as a full adder or a combination of a full adder and a half adder. For example, in some embodiments, the accumulation subcircuit 112 may include a full adder module having one or more full adder stages, a first register group, and a second register group. The first output of the full adder module is coupled to the input of the first register group, and the second output of the full adder module is coupled to the input of the second register group. The output of the multiplication subcircuit 111, the output of the first register group, and the output of the second register group are respectively coupled to the corresponding inputs of the full adder module. The output of the first register group and the output of the second register group are respectively coupled to the corresponding inputs of the control subcircuit 113. The control subcircuit 113 is configured to control whether the output of the first register group and the output of the second register group are provided at the corresponding outputs of the control subcircuit 113 based on a control signal. In some embodiments, the control subcircuit 113 includes a first control element and a second control element. The first input of the first control element is coupled to the output of the first register group, the second input of the first control element is configured to receive the control signal, and the output of the first control element provides the first output of the multiplication and accumulation unit 110. The first control element is configured to control whether the output of the first register group is provided at its output terminal according to a received control signal. A first input terminal of the second control element is coupled to the output terminal of the second register group, a second input terminal of the second control element is configured to receive a control signal, and an output terminal of the second control element provides a second output terminal of the multiplication-accumulation unit 110. The second control element is configured to control whether the output of the second register group is provided at its output terminal according to a received control signal.

[0041] The accumulation subcircuit 112 does not include an adder, so that even if the accumulation subcircuit 112 keeps flipping during the entire operation process, it will not generate excessive power consumption. The number of registers included in the register group may depend on the bit width of the register and the bit width of the input data.

[0042] In some embodiments, the control sub-circuit 113 may include at least one of the following: an AND gate, a NAND gate, a multiplexer, and an inverting multiplexer.

[0043] In some embodiments, the summing unit 120 may include an adder. When the multiplication and accumulation unit 110 has only two output terminals, the summing unit 120 may only include an adder. When the multiplication and accumulation unit 110 includes more than two output terminals, the summing unit 120 may include an n-level compression tree and an adder, the output terminal of the multiplication and accumulation unit 110 is coupled to the corresponding input terminal of the first-level compression tree in the n-level compression tree, the output terminal of the i-th level compression tree in the n-level compression tree is coupled to the corresponding input terminal of the (i+1)-th level compression tree in the n-level compression tree, and the output terminal of the n-level compression tree in the n-level compression tree is coupled to the corresponding input terminal of the adder, where n is a positive integer, i=1, 2, ..., n-1. Each level of compression tree may include one compression tree or multiple compression trees in parallel. Similar to the above, the compression tree here can also be alternatively implemented as a full adder or a combination of a full adder and a half adder. In addition, in some embodiments, the summing unit 120 may further include an additional register group, the input end of the additional register group being coupled to the output end of the adder, and the output end of the additional register group being coupled to the corresponding input end of the first-level compression tree in the n-level compression tree. Due to the introduction of the additional register group, the summing unit 120 also has an accumulation function, which eliminates the need for the accumulation sub-circuit 112 to perform full accumulation, thereby reducing the bit width requirement for the register group of the accumulation sub-circuit 112, allowing the registers in the register group of the accumulation sub-circuit 112 to have a smaller number of bits, thereby reducing area and power consumption.

[0044] For non-limiting illustrative purposes, FIG. 3 to FIG. 7 respectively illustrate example circuit diagrams for implementing the multiplication-accumulation circuit 100 of FIG. 2 according to some embodiments of the present disclosure.

[0045] As shown in FIG3 , the multiplication and accumulation circuit 100A includes a multiplication and accumulation unit 110 and a summation unit 120. The multiplication and accumulation unit 110 includes a multiplication subcircuit 111, an accumulation subcircuit 112, and a control subcircuit 113. In the example of FIG3 , the multiplication subcircuit 111 includes a multiplier 1110 with a single output terminal. Assume that the multiplication and accumulation circuit 100A is to calculate the multiplication and accumulation of the logarithm of x (a1·b1+a2·b2+...a x b x , x is a positive integer), then in each cycle of x periods, the corresponding pair of numbers a in the x logarithms can be k 、b k (k=1, 2, ..., x) is fed into the multiplier 1110 as a multiplier to calculate the product a of the pair k b k , then a k b k is accumulated via the accumulation sub-circuit 112 .

[0046] Accumulation subcircuit 112 includes a compression tree 1120, which is a 3:2 compression tree, and a first register bank 1121 and a second register bank 1122. A first output of compression tree 1120 is coupled to an input of first register bank 1121, and a second output of compression tree 1120 is coupled to an input of second register bank 1122. An output of multiplier 1110, an output of first register bank 1121, and an output of second register bank 1122 are coupled to corresponding inputs of compression tree 1120.

[0047] The control subcircuit 113 includes a first control element 1131 and a second control element 1132. A first input terminal of the first control element 1131 is coupled to an output terminal of the first register group 1121, and a second input terminal of the first control element 1131 is configured to receive a control signal S c , and the output terminal of the first control element 1131 can provide the first output terminal of the multiplication and accumulation unit 110. The first control element 1131 is configured to receive the control signal S c The first input terminal of the second control element 1132 is coupled to the output terminal of the second register group 1122, and the second input terminal of the second control element 1132 is configured to receive the control signal S c , and the output terminal of the second control element 1132 can provide the second output terminal of the multiplication and accumulation unit 110. The second control element 1132 is configured to receive the control signal S c And controls whether to provide the output of the second register group 1122 at the output terminal of the second control element 1132. Each of the first control element 1131 and the second control element 1132 may include at least one of the following: an AND gate, a NAND gate, a multiplexer, an inverting multiplexer. For example, each of the first control element 1131 and the second control element 1132 may include an AND gate group or a NAND gate group or a multiplexer group or an inverting multiplexer group. The number of elements in the AND gate group or the NAND gate group or the multiplexer group or the inverting multiplexer group may depend on the data bit width. For example, when each of the first control element 1131 and the second control element 1132 includes an AND gate group, when the control signal S c = 0, the output of the corresponding register group is not provided at its output (instead, 0 can be output at its output) and the control signal S c =1, the output of the corresponding register group is provided at its output terminal. When each of the first control element 1131 and the second control element 1132 includes a multiplexer group, the control signal S c can serve as a selection signal, 0 can serve as the first input, and the output of the corresponding register group can serve as the second input, so that the multiplexer group can control the signal S c= 0, the first input is provided as 0 at its output (ie, the second input as the output of the corresponding register group is not provided at its output) and the control signal S c = 1, the second input of the output of the corresponding register group is provided at its output terminal. The case when each of the first control element 1131 and the second control element 1132 includes a NAND gate group and the case when each of the first control element 1131 and the second control element 1132 includes an inverting multiplexer group are similar to the case when each of the first control element 1131 and the second control element 1132 includes an AND gate group and the case when each of the first control element 1131 and the second control element 1132 includes a multiplexer group, respectively, but an inverted output is provided, which can be corrected within the summing unit 120 by adjusting the configuration of the summing unit 120 (for example, adding a NOT gate or an inverter, etc.).

[0048] The summing unit 120 includes an adder 1200. Assuming that the logarithms of x to be calculated by the multiplication-accumulation circuit 100A are fed sequentially from 1 to x to the multiplier 1110, then at the end of the first cycle, the result stored in the first register group 1121 is the first part of a1·b1 and the result stored in the second register group 1122 is the second part of a1·b1. At the end of the second cycle, the result stored in the first register group 1121 is the first part of (a1·b1+a2·b2) and the result stored in the second register group 1122 is the second part of (a1·b1+a2·b2). This continues until the end of the xth cycle, when the result stored in the first register group 1121 is (a1·b1+a2·b2+ ... x b x ) and the result stored in the second register group 1122 is (a1·b1+a2·b2+....…a x b x ). In these x cycles, the control signal S c Under the control of , adder 1200 does not receive any output from the first register group 1121 and the second register group 1122, so it has not been flipped. In the x+1th cycle, the switching control signal S c The result stored in the first register group 1121 (a1·b1+a2·b2+......a x b x ) and the result (a1·b1+a2·b2+......a1) stored in the first part of the second register group 1122. x b x ) is provided to the adder 1200, and the adder 1200 sums up to obtain (a1·b1+a2·b2+......ax b x ). Therefore, adder 1200 flips over for only one cycle.

[0049] Compared to the multiplication-accumulation circuit 10 of FIG1 , the multiplication-accumulation circuit 100A of FIG3 replaces the single-stage accumulation circuit with a two-stage accumulation circuit, which is then placed in a dynamic region and a static region. The first-stage accumulation circuit in the dynamic region consists of simple circuit components and does not include an adder. Therefore, even with a high switching frequency, it does not consume much power. The second-stage accumulation circuit in the static region, although including an adder, has a very low switching frequency and therefore does not consume much power. Therefore, the multiplication-accumulation circuit 100A has reduced power consumption overall.

[0050] Figure 4 shows a multiply-accumulate circuit 100B. Compared to the multiply-accumulate circuit 100A of Figure 3 , the difference lies in that multiplier 1110 has a dual output terminal instead of a single output terminal, and accordingly, compression tree 1120 has been changed from a 3:2 compression tree to a 4:2 compression tree. A multiplier typically consists of three parts: a partial product generation part, a partial accumulation and addition part, and a final addition part. Compared to a multiplier with a single output terminal, a multiplier with a dual output terminal can reduce the final addition part, meaning that one adder can be eliminated. Because multiplier 1110 is constantly flipping during the entire operation, using a multiplier with a dual output terminal can further reduce power consumption compared to a multiplier with a single output terminal.

[0051] It can be understood that although the multiplier with a single output terminal in the multiplication and accumulation circuit 100A of Figure 3 includes an adder, this adder has a smaller bit width than the adder 1200 or the adder 12 used in the multiplication and accumulation circuit 10. Therefore, even if the adder of the multiplier with a single output terminal flips frequently, it will not bring such high dynamic power consumption.

[0052] FIG5 shows a multiplication-accumulation circuit 100C, which differs from the multiplication-accumulation circuit 100B of FIG4 in that the multiplication subcircuit 111 includes m parallel multipliers 11101, 11102, ..., 1110. m (m is a positive integer greater than 1). Accordingly, compression tree 1120 changes from a 4:2 compression tree to a (2m+2):2 compression tree. As previously mentioned, when a (2m+2):2 compression tree is inconvenient to design, a combination of existing compression trees can be used to achieve compression from (2m+2) inputs to two outputs. Through the parallel design of multipliers, multiplication-accumulation circuit 100C can perform m logarithmic multiplications and accumulations in each cycle. Compared to the (x+1) cycles required by multiplication-accumulation circuit 100B in FIG4 , multiplication-accumulation circuit 100C only requires (x / m+1) cycles, thereby improving computational efficiency. The number m of parallel multipliers can be flexibly configured according to actual needs.

[0053] FIG6 shows a multiply-accumulate circuit 100D, which differs from the multiply-accumulate circuit 100C of FIG5 in that the compression tree 1120 is replaced by a full adder module 1120 ′ having multiple stages of full adders (FA).

[0054] FIG7 shows a multiplication-accumulation circuit 100E, which differs from the multiplication-accumulation circuit 100C of FIG5 in that the accumulation subcircuit 112 includes m parallel compression trees 11201, . . . 1120 m At the output ends of these compression trees, first register groups 11211, ... 1121 are correspondingly provided. m , first control element 11311, ... 1131 m , second register group 11221, ... 1122 m , second control element 11321, ... 1132 m . Although each compression tree is illustrated as corresponding to a multiplier in FIG7 , it is understandable that there may be multiple multipliers in parallel in front of each compression tree. The compression tree of the multiplication-accumulation circuit 100E may have a simpler design than the compression tree of the multiplication-accumulation circuit 100C. From another perspective, when the multiplication-accumulation circuit 100E and the multiplication-accumulation circuit 100C use the same compression tree, the former can accommodate a larger multiplier scale, thereby further improving the circuit processing performance. Moreover, the accumulation sub-circuit 112 of the multiplication-accumulation circuit 100E is divided into multiple parts for separate accumulation compared to the accumulation sub-circuit 112 of the multiplication-accumulation circuit 100C, thereby avoiding the difficulty of timing convergence caused by the excessive circuit scale in one accumulation part.

[0055] FIG8 shows a multiplication-accumulation circuit 200 according to some embodiments of the present disclosure. The multiplication-accumulation circuit 200 includes a plurality of multiplication-accumulation units 1101, 1102, ... 110 j (j is a positive integer greater than 1) and summing unit 120. Multiplication and accumulation units 1101, 1102, ... 110 j The output terminal of each multiplication and accumulation unit in is coupled to the corresponding input terminal of the summing unit 120. j An input terminal of each multiplication-accumulation unit in the multiplication-accumulation circuit 200 may provide an input terminal IN of the multiplication-accumulation circuit 200 , and an output terminal of the summing unit 120 may provide an output terminal OUT of the multiplication-accumulation circuit 200 .

[0056] Multiplication and accumulation units 1101, 1102, ... 110 j Each includes a multiplication subcircuit 1111, 1112, ... 111 j, accumulation sub-circuits 1121, 1122, ... 112 j , control sub-circuits 1131, 1132, ... 113 j Control subcircuits 1131, 1132, ... 113 j Each receives a control signal S c1 、S c2 、......、S cj For example, the control signal S c1 、S c2 、......、S cj Each of the control sub-circuits 1131, 1132, ... 113 j A corresponding control subcircuit in the accumulation subcircuit 1121, 1122, ... 112 j The output of the corresponding accumulation sub-circuit is not provided at the output terminal of the corresponding control sub-circuit before the corresponding accumulation sub-circuit completes each round of accumulation, and is configured to provide the output of the corresponding accumulation sub-circuit at the output terminal of the corresponding control sub-circuit after the corresponding accumulation sub-circuit completes each round of accumulation and before starting the next round of accumulation.

[0057] The summing unit 120 is configured to receive a plurality of multiplication and accumulation units 1101, 1102, ... 110 j The output of the control sub-circuit 1131, 1132, ... 113 is summed. j Under the control of the summing unit 120, the summing sub-circuits 1121, 1122, ... 112 j The accumulation sub-circuits 1121, 1122, ... 112 will not be received before the current accumulation is completed. j The output of , therefore, no summing operation is performed. j After completing this round of accumulation, the summing unit 120 will control the sub-circuits 1131, 1132, ..., 113 j Under the control of the accumulation sub-circuit 1121, 1122, ... 112 j That is, in the multiplication and accumulation units 1101, 1102, ... 110 j During the entire operation process, the multiplication and accumulation units 1101, 1102, ... 110 j The summing unit 120 will not flip. jAfter the operation is completed, the summing unit 120 will flip over a cycle for summing. j The summing unit 120 can be regarded as the active region of the multiplication-accumulation circuit 200, while the summing unit 120 can be regarded as the quiet region of the multiplication-accumulation circuit 200. By dividing the active region and the quiet region, the multiplication-accumulation circuit 200 achieves reduced power consumption.

[0058] Multiplication and accumulation units 1101, 1102, ... 110 j Each of the multiplication and accumulation units in the circuit is similar to the multiplication and accumulation unit 110 of the aforementioned multiplication and accumulation circuit 100, so the above description of the multiplication and accumulation unit 110 and its various embodiments are also applicable here, and will not be repeated here. It can be understood that the multiplication and accumulation units 1101, 1102, ... 110 j They may have the same design or different designs.

[0059] Compared to the multiplication-accumulation circuit 100 having only one multiplication-accumulation unit 110, the multiplication-accumulation circuit 200 has a plurality of parallel multiplication-accumulation units 1101, 1102, ..., 110. j Each multiplication and accumulation unit takes on part of the accumulation function, so that each multiplication and accumulation unit can be kept at an appropriate scale, avoiding the difficulty of timing convergence caused by the circuit scale of a single multiplication and accumulation unit being too large, and facilitating the reduction of glitch power consumption and optimization of circuit speed.

[0060] In particular, due to the multiple multiplication and accumulation units 1101, 1102, ... 110 j Typically, there are more than two output terminals. Therefore, in such an embodiment, the summing unit 120 may include an n-level compression tree and adders, multiplication and accumulation units 1101, 1102, ... 110 jThe output end of each multiplication and accumulation unit is coupled to the corresponding input end of the first-level compression tree in the n-level compression tree, the output end of the i-th level compression tree in the n-level compression tree is coupled to the corresponding input end of the (i+1)-th level compression tree in the n-level compression tree, and the output end of the n-level compression tree in the n-level compression tree is coupled to the corresponding input end of the adder, wherein n is a positive integer, i=1, 2, ..., n-1. Each level of compression tree may include one compression tree or multiple compression trees in parallel. Similar to the above, the compression tree here can also be implemented as a full adder or a combination of a full adder and a half adder. In addition, in some embodiments, the summing unit 120 may also include an additional register group, the input end of the additional register group is coupled to the output end of the adder, and the output end of the additional register group is coupled to the corresponding input end of the first-level compression tree in the n-level compression tree. Due to the introduction of the additional register group, the summing unit 120 also has an accumulation function, which makes the multiplication and accumulation units 1101, 1102, ... 110 j The accumulation subcircuit of each multiplication-accumulation unit does not need to fully accumulate, which reduces the bit width requirement of the register group of the accumulation subcircuit, so that the registers in the register group of the accumulation subcircuit can have a smaller number of bits and thus have lower area and power consumption.

[0061] For non-limiting illustrative purposes, FIG9 to FIG11 respectively illustrate example circuit diagrams for implementing the multiplication-accumulation circuit 200 of FIG8 according to some embodiments of the present disclosure.

[0062] FIG9 shows a multiplication-accumulation circuit 200A. Compared with the multiplication-accumulation circuit 100C of FIG5 , the difference is that the number of multiplication-accumulation units is increased from 1 to j. Accordingly, the summing unit 120 adds a first-level compression tree before the adder 1200, i.e., the first-level compression tree 1210, so as to compress the data from the j multiplication-accumulation units 1101, ..., 110 j Output. By designing the multiplication and accumulation units in parallel, each multiplication and accumulation unit in the multiplication and accumulation circuit 200A can perform m logarithmic multiplication and accumulation in each cycle. Compared to the (x / m+1) cycles required by the multiplication and accumulation circuit 100C in FIG5 , the multiplication and accumulation circuit 200A only requires (x / jm+1) cycles, thereby improving computational efficiency. The number j of parallel multiplication and accumulation units can be flexibly configured according to actual needs.

[0063] Referring to FIG10 , it shows that the summing unit 120 adds two levels of compression trees before the adder 1200, wherein the first level compression tree includes two parallel compression trees 12101 and 12102, the second level compression tree includes a compression tree 1220, and the multiplication and accumulation units 1101, ... 110 jThe output end of is coupled to the corresponding input end of the first-level compression tree 12101 and 12102, and the output end of the first-level compression tree 12101 and 12102 is coupled to the corresponding input end of the second-level compression tree 1220. The output end of the second-level compression tree 1220 is coupled to the adder 1200. The output end of the adder 1200 provides the output end of the summing unit 120 and also provides the output end of the multiplication and accumulation circuit. Figure 10 is equivalent to implementing an 8:2 compression tree by combining three 4:2 compression trees. The compression tree of the summing unit 120 of Figure 10 can have a simpler design than the compression tree of the summing unit 120 of Figure 9. From another perspective, when the summing unit 120 of Figure 10 and the summing unit 120 of Figure 9 use the same compression tree, the former can accommodate a larger multiplication and accumulation unit scale, thereby further improving the circuit processing performance.

[0064] FIG11 shows a multiplication-accumulation circuit 200B. Compared with the multiplication-accumulation circuit 200A of FIG9 , the difference is that the summing unit 120 further includes an additional register group 1201. The input end of the additional register group 1201 is coupled to the output end of the adder 1200, and the output end of the additional register group 1201 is coupled to the corresponding input end of the first-level compression tree 1210. The introduction of the additional register group 1201 enables the summing unit 120 to also have an accumulation function, which makes the multiplication-accumulation units 1101, 110... j The accumulation subcircuit of each multiplication-accumulation unit does not need to fully accumulate, which reduces the bit width requirement of the register group of the accumulation subcircuit, so that the registers in the register group of the accumulation subcircuit can have a smaller number of bits and thus have lower area and power consumption.

[0065] For example, assume that the multiplication and accumulation circuit 200B is to implement 1024 logarithmic multiplication and accumulation (a1·b1+a2·b2+...a 1024 b 1024 ), the multiplication-accumulation circuit 200B includes 4 multiplication-accumulation units (j=4), and the multiplication subcircuit of each multiplication-accumulation unit includes 4 multipliers (m=4). Then the typical multiplication-accumulation operation process can be carried out as follows: 16 multipliers calculate in parallel to output 16 multiplication operation results in each cycle; 4 accumulation subcircuits accumulate in parallel, and the register group in each accumulation subcircuit is configured to output the stored results and clear them every 8 cycles (meaning that one round of accumulation includes 8 cycles). Therefore, under the control of the corresponding control subcircuit, the output provided to the summation unit each time by each accumulation subcircuit includes 32 logarithmic multiplication-accumulation results, that is, the summation unit will receive 128 logarithmic multiplication-accumulation results every 8 cycles; in order to complete the multiplication-accumulation of 1024 logarithms, the compression tree, adder and additional register group in the summation unit need to be flipped 8 times.

[0066] In contrast, if the multiplication-accumulation circuit 10 of FIG1 is used to implement the multiplication-accumulation of 1024 logarithms, the adder needs to flip 1024 times. Thus, although the multiplication-accumulation circuit 200B introduces the accumulation function into the summing unit 120, the flipping frequency of the summing unit 120 is still effectively suppressed, thereby reducing the power consumption of the multiplication-accumulation circuit 200B.

[0067] Furthermore, if multiply-accumulate circuit 200A is used to implement 1024-logarithm multiplication and accumulation, and multiply-accumulate circuit 200A also includes four multiply-accumulate units (j=4), and the multiplication sub-circuit of each multiply-accumulate unit also includes four multipliers (m=4), then, as previously described, summing unit 120 only needs to flip once. Although the flipping frequency of summing unit 120 in multiply-accumulate circuit 200B is higher than that of summing unit 120 in multiply-accumulate circuit 200A, their power consumption is significantly lower than that of multiply-accumulate circuit 10. In practical applications, a power reduction of one order of magnitude may be significant. Putting aside the dynamic power consumption caused by flipping, multiply-accumulate circuit 200B reduces the bit width requirement for the register bank of the accumulation sub-circuit compared to multiply-accumulate circuit 200A, allowing the registers in the register bank of the accumulation sub-circuit to have a smaller number of bits, thereby reducing area and power consumption. Therefore, multiply-accumulate circuit 200B further reduces power consumption and improves performance in other aspects.

[0068] In another aspect, the present disclosure provides a processor that may include the multiplication-accumulation circuit described in any of the aforementioned embodiments. For example, such a processor may be a coprocessor, a digital signal processor, a central processing unit, a dedicated instruction processor, a neural network processor, or other processors. If such a processor is a neural network processor, its convolution calculation unit may include the multiplication-accumulation circuit described in any of the aforementioned embodiments.

[0069] The present disclosure further provides, on another aspect, a computing device, which may include the processor according to any of the foregoing embodiments. Examples of computing devices may include, but are not limited to, consumer electronic products, components of consumer electronic products, electronic test equipment, cellular communication infrastructure such as base stations, and the like. Examples of computing devices may include, but are not limited to, mobile phones such as smartphones, wearable computing devices such as smart watches or headphones, phones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal digital assistants (PDAs), microwave ovens, refrigerators, in-vehicle electronic systems such as automotive electronic systems, stereo systems, DVD players, CD players, digital music players such as MP3 players, radios, portable cameras, cameras such as digital cameras, portable memory chips, washing machines, dryers, washer / dryers, peripheral devices, clocks, and the like. In addition, computing devices may include incomplete products.

[0070] The terms "left," "right," "front," "back," "top," "bottom," "upper," "lower," "higher," "lower," and the like, if used in the specification and claims, are used for descriptive purposes and are not necessarily intended to describe invariant relative positions. It should be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the present disclosure described herein, for example, are capable of operation in other orientations than those illustrated or otherwise described herein. For example, features previously described as "above" other features could be described as "below" the other features when the apparatus in the drawings is turned over. The apparatus can also be otherwise oriented (rotated 90 degrees or at other orientations) and relative spatial relationships will be interpreted accordingly.

[0071] In the specification and claims, when an element is referred to as being "on," "attached," "connected," "coupled," or "contacting," etc., another element, the element may be directly on, directly attached, directly connected, directly coupled, or directly contacting the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being "directly" on, "directly attached," "directly connected," "directly coupled," or "directly contacting" another element, there may be no intervening elements. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that the feature has a portion that overlaps with the adjacent feature or a portion that is located above or below the adjacent feature.

[0072] As used herein, the word "exemplary" means "serving as an example, instance, or illustration" rather than as a "model" to be precisely copied. Any implementation described as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, this disclosure is not to be bound by any expressed or implied theory presented in the technical field, background, summary, or detailed description.

[0073] As used herein, the word "substantially" is intended to encompass any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The word "substantially" also allows for deviations from a perfect or ideal condition due to parasitic effects, noise, and other practical considerations that may be present in actual implementations.

[0074] Additionally, terms such as "first," "second," and the like may also be used herein for reference purposes only and are not intended to be limiting. For example, the terms "first," "second," and other numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly indicates otherwise.

[0075] It should also be understood that when the term "include / comprises" is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0076] In addition, when used in this application, the words "herein," "above," "below," "hereunder," "supra," and words of similar meaning shall refer to this application as a whole and not to any particular portions of this application. Furthermore, unless expressly stated otherwise or otherwise understood in the context of use, conditional language used herein, such as "may," "might," "for example," "such as," and the like, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements, and / or states. Thus, such conditional language is generally not intended to imply that one or more embodiments in any way require features, elements, and / or states, or whether such features, elements, and / or states are included or performed in any particular embodiment.

[0077] In this disclosure, the term "provide" is used in a broad sense to cover all ways of obtaining an object, and thus "providing an object" includes but is not limited to "purchasing", "preparing / manufacturing", "arranging / setting up", "installing / assembling", and / or "ordering" an object, etc.

[0078] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0079] Those skilled in the art will appreciate that the boundaries between the above-described operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Furthermore, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are also possible. Aspects and elements of all of the embodiments disclosed above may be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be regarded as illustrative, not restrictive. In fact, the novel devices, methods, and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions, and changes may be made to the form of the methods and systems described herein without departing from the spirit of the present disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in a variety of different ways.

[0080] The various embodiments of the present disclosure may be described in a progressive manner, and the same or similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments. In the present disclosure, descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present disclosure, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in an appropriate manner in any one or more embodiments or examples.

[0081] Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art will appreciate that the above examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. Those skilled in the art will also appreciate that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A multiplication-accumulation circuit, comprising: At least one multiply-accumulate unit, the multiply-accumulate unit comprising: a multiplication subcircuit configured to receive a multiplier and calculate a product thereof, an accumulation subcircuit, the input terminal of the accumulation subcircuit being coupled to the output terminal of the multiplication subcircuit, the accumulation subcircuit being configured to receive and accumulate the output of the multiplication subcircuit, and a control subcircuit, wherein an input terminal of the control subcircuit is coupled to an output terminal of the accumulation subcircuit, an output terminal of the control subcircuit provides an output terminal of the multiplication-accumulation unit, and the control subcircuit is configured to receive a control signal and an output of the accumulation subcircuit and control whether to provide the output of the accumulation subcircuit at the output terminal of the control subcircuit according to the control signal; and A summing unit, wherein an input terminal of the summing unit is coupled to an output terminal of the at least one multiplication-accumulation unit, and the summing unit is configured to receive and sum the output of the at least one multiplication-accumulation unit.

2. The multiplication-accumulation circuit according to claim 1, wherein: The multiplication subcircuit includes one or more multipliers, each of the one or more multipliers being configured to receive a corresponding pair of multipliers and to product the corresponding pair of multipliers.

3. The multiplication-accumulation circuit according to claim 2, wherein: The multiplier of the multiplication subcircuit has a single output terminal.

4. The multiplication-accumulation circuit according to claim 2, wherein: The multiplier of the multiplication subcircuit has dual output terminals.

5. The multiplication-accumulation circuit according to claim 1, wherein: The accumulation subcircuit comprises a compression tree and a plurality of register groups, each output end of the compression tree is coupled to an input end of a corresponding one of the plurality of register groups, and an output end of the multiplication subcircuit and an output end of each of the plurality of register groups are respectively coupled to a corresponding input end of the compression tree. The output end of each of the multiple register groups is respectively coupled to the corresponding input end of the control subcircuit, and the control subcircuit is configured to control whether the output of each of the multiple register groups is respectively provided at the corresponding output end of the control subcircuit according to the control signal.

6. The multiplication-accumulation circuit according to claim 5, wherein: The control subcircuit comprises: A plurality of control elements, wherein a first input terminal of each of the plurality of control elements is coupled to a corresponding one of the plurality of register groups. The output end of each of the plurality of control elements is configured to receive an output end of a register group, the second input end of each of the plurality of control elements is configured to receive a control signal, the output end of each of the plurality of control elements provides a corresponding output end of the multiplication and accumulation unit, and each of the plurality of control elements is configured to control whether to provide the output of the corresponding register group at the output end of the control element according to the received control signal.

7. The multiplication-accumulation circuit according to claim 1, wherein: The accumulation subcircuit comprises a full adder module having one or more stages of full adders, a first register group and a second register group, wherein a first output end of the full adder module is coupled to an input end of the first register group, a second output end of the full adder module is coupled to an input end of the second register group, an output end of the multiplication subcircuit, an output end of the first register group and an output end of the second register group are respectively coupled to corresponding input ends of the full adder module, The output end of the first register group and the output end of the second register group are respectively coupled to the corresponding input end of the control subcircuit, and the control subcircuit is configured to control whether to provide the output of the first register group and the output of the second register group at the corresponding output end of the control subcircuit according to the control signal.

8. The multiplication-accumulation circuit according to claim 7, wherein: The control subcircuit comprises: a first control element, wherein a first input terminal of the first control element is coupled to an output terminal of the first register group, a second input terminal of the first control element is configured to receive a control signal, an output terminal of the first control element provides a first output terminal of the multiplication-accumulation unit, and the first control element is configured to control whether to provide an output of the first register group at the output terminal of the first control element according to the received control signal; and a second control element, wherein a first input terminal of the second control element is coupled to an output terminal of the second register group, a second input terminal of the second control element is configured to receive a control signal, an output terminal of the second control element provides a second output terminal of the multiplication-accumulation unit, and the second control element is configured to control whether to provide an output of the second register group at the output terminal of the second control element according to the received control signal.

9. The multiplication-accumulation circuit according to claim 1, wherein: The control subcircuit includes at least one of the following: an AND gate, a NAND gate, a multiplexer, and an inverting multiplexer.

10. The multiplication-accumulation circuit according to claim 1, wherein: The control signal is configured so that the control subcircuit does not provide the output of the accumulation subcircuit at the output terminal of the control subcircuit before the accumulation subcircuit completes each round of accumulation, and is configured to provide the output of the accumulation subcircuit at the output terminal of the control subcircuit after the accumulation subcircuit completes each round of accumulation and before starting the next round of accumulation.

11. The multiplication-accumulation circuit according to any one of claims 1 to 10, wherein: The summing unit includes an adder.

12. The multiplication-accumulation circuit according to any one of claims 1 to 10, wherein: The at least one multiplication-accumulation unit includes two or more multiplication-accumulation units, the summation unit includes an n-level compression tree and an adder, an output end of each of the two or more multiplication-accumulation units is coupled to a corresponding input end of a first-level compression tree among the n-level compression trees, an output end of an i-th-level compression tree among the n-level compression trees is coupled to a corresponding input end of an (i+1)-th-level compression tree among the n-level compression trees, and an output end of an n-th-level compression tree among the n-level compression trees is coupled to a corresponding input end of the adder, Wherein, n is a positive integer, i=1, 2, ..., n-1.

13. The multiplication-accumulation circuit according to claim 12, wherein: The summing unit further includes an additional register group, an input terminal of the additional register group is coupled to an output terminal of the adder, and an output terminal of the additional register group is coupled to a corresponding input terminal of a first-stage compression tree in the n-stage compression tree.

14. A processor comprising the multiplication-accumulation circuit according to any one of claims 1 to 13.

15. A computing device comprising a processor according to claim 14.

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