Shift register, gate drive circuit, display panel, and display device

Abstract

The present disclosure relates to the technical field of display, and provides a shift register, a gate drive circuit, a display panel, and a display device. In the shift register, a first display input circuit is configured to write a signal of a first signal end into a first pull-up node under the control of a signal of a first display input end; a first display shift circuit is configured to write a signal of a first shift signal end into a first shift output end under the control of a signal of the first pull-up node; a black frame insertion input circuit is configured to write a signal of a second voltage end into the first pull-up node under the control of signals of a first black frame insertion input end, a first control end, and a second control end; a first black frame insertion shift circuit is configured to write a signal of a second shift signal end into a second shift output end under the control of the signal of the first pull-up node; and a first output circuit is configured to write the signal of the first signal end into a first output end under the control of the signal of the first pull-up node.

Description

Shift register, gate drive circuit, display panel and display device

[0001] This application claims priority to the Chinese patent application filed with the Patent Office of China on August 8, 2023, with application number 202310993841.6, and with the invention name “Shift register, gate drive circuit, display panel and display device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit, a display panel, and a display device. Background Art

[0003] In the display field, especially in organic light-emitting diode (OLED) displays, the switching process of dynamic display images is prone to dynamic image smearing. This phenomenon occurs when switching from the previous display frame to the next. To overcome this dynamic image smearing, related technologies have added a blackout process during the pixel's light-emitting period. This process reduces the normal display time of the pixel, effectively improving the dynamic image smearing phenomenon.

[0004] Summary of the Invention

[0005] Embodiments of the present disclosure provide a shift register, a gate driving circuit, a display panel, and a display device, which improve the ghosting phenomenon of dynamic images.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] In one aspect, a shift register is provided, comprising a first scanning unit, wherein the first scanning unit comprises a first display input circuit, a first display shift circuit, a black insertion input circuit, a first black insertion shift circuit, and a first output circuit;

[0008] The first display input circuit is electrically connected to the first display input terminal, the first voltage terminal and the first pull-up node, and the first display input circuit is configured to write the signal of the first signal terminal into the first pull-up node under the control of the signal of the first display input terminal;

[0009] The first display shift circuit is electrically connected to the first pull-up node, the first shift signal terminal, and the first shift output terminal, and the first display shift circuit is configured to write the signal of the first shift signal terminal to the first shift output terminal under the control of the signal of the first pull-up node;

[0010] The black insertion input circuit is electrically connected to the first black insertion input terminal, the first control terminal, the second control terminal, the second voltage terminal, and the first pull-up node. The black insertion input circuit is configured to write the signal of the second voltage terminal into the first pull-up node under the control of the signals of the first black insertion input terminal, the first control terminal, and the second control terminal;

[0011] The first black insertion shift circuit is electrically connected to the first pull-up node, the second shift signal terminal, and the second shift output terminal. The first black insertion shift circuit is configured to write the signal of the second shift signal terminal to the second shift output terminal under the control of the signal of the first pull-up node;

[0012] The first output circuit is electrically connected to the first pull-up node, the first signal terminal and the first output terminal. The first output circuit is configured to write the signal of the first signal terminal into the first output terminal under the control of the signal of the first pull-up node.

[0013] In some embodiments, the shift register further includes a second scanning unit, the second scanning unit including a second display input circuit, a second display shift circuit, and a second output circuit;

[0014] The second display input circuit is electrically connected to the first shift output terminal, the first voltage terminal and the second pull-up node, and the second display input circuit is configured to write the signal of the first voltage terminal into the second pull-up node under the control of the signal of the first shift output terminal;

[0015] The second display shift circuit is electrically connected to the second pull-up node, the third shift signal terminal and the third shift output terminal, and the second display shift circuit is configured to write the signal of the third shift signal terminal to the third shift output terminal under the control of the signal of the second pull-up node;

[0016] The second output circuit is electrically connected to the second pull-up node, the second signal terminal and the second output terminal, and the second output circuit is configured to write the signal of the second signal terminal into the second output terminal under the control of the signal of the second pull-up node;

[0017] The black insertion input circuit is electrically connected to the first pull-up node and the second pull-up node at the same time, and is further configured to write a signal to the second pull-up node.

[0018] In some embodiments, the black insertion input circuit includes a first black insertion input circuit and a second black insertion input circuit; the first black insertion input circuit is electrically connected to the first pull-up node, and the first black insertion input circuit is configured to write a signal to the first node; the second black insertion input circuit is electrically connected to the second pull-up node, and the second black insertion input circuit is configured to write a signal to the second pull-up node.

[0019] In some embodiments, at the same time, the signal written by the first black insertion input circuit to the first pull-up node is the same as the signal written by the second black insertion input circuit to the second pull-up node.

[0020] In some embodiments,

[0021] The first black insertion input circuit is electrically connected to the first black insertion input terminal, the first control terminal, the second control terminal, the second voltage terminal, and the first pull-up node. The first black insertion input circuit is configured to write a signal from the second voltage terminal into the first pull-up node under the control of signals from the first black insertion input terminal, the first control terminal, and the second control terminal.

[0022] The second black insertion input circuit is electrically connected to the first black insertion input terminal, the first control terminal, the second control terminal, the second voltage terminal, and the second pull-up node. The second black insertion input circuit is configured to write a signal from the second voltage terminal into the second pull-up node under the control of signals from the first black insertion input terminal, the first control terminal, and the second control terminal.

[0023] In some embodiments, the first black insertion input circuit includes a first subcircuit and a second subcircuit;

[0024] The first sub-circuit is electrically connected to the first black insertion input terminal, the first control terminal, the second voltage terminal, and a first node, and is configured to write a signal from the second voltage terminal into the first node under the control of signals from the first black insertion input terminal and the first control terminal;

[0025] The second sub-circuit is electrically connected to the second control terminal, the first node, and the first pull-up node, and the second sub-circuit is configured to write the signal of the first node into the first pull-up node under the control of the signal of the second control terminal;

[0026] The second black insertion input circuit is electrically connected to the first node, the second control terminal and the second pull-up node, and is configured to write the signal of the first node into the second pull-up node under the control of the signal of the second control terminal.

[0027] In some embodiments, the second black insertion input circuit includes a first subcircuit and a second subcircuit;

[0028] The first sub-circuit is electrically connected to the first black insertion input terminal, the first control terminal, the second voltage terminal, and a second node, and is configured to write a signal from the second voltage terminal into the second node under the control of signals from the first black insertion input terminal and the first control terminal;

[0029] The second sub-circuit is electrically connected to the second control terminal, the first node, and the second pull-up node, and the second sub-circuit is configured to write the signal of the first node into the second pull-up node under the control of the signal of the second control terminal;

[0030] The first black insertion input circuit is electrically connected to the first node, the second control terminal, and the first pull-up node. The second black insertion input circuit is configured to write the signal of the first node into the first pull-up node under the control of a signal of the second control terminal.

[0031] In some embodiments, the first black insertion input circuit is electrically connected to the first black insertion input terminal, the first control terminal, the second control terminal, the second voltage terminal, and the first pull-up node, and the first black insertion input circuit is configured to write a signal from the second voltage terminal to the first pull-up node under the control of signals from the first black insertion input terminal, the first control terminal, and the second control terminal;

[0032] The second black insertion input circuit is electrically connected to the second black insertion input terminal, the first control terminal, the second control terminal, the second voltage terminal, and the second pull-up node. The second black insertion input circuit is configured to write a signal from the second voltage terminal to the second pull-up node under the control of signals from the second black insertion input terminal, the first control terminal, and the second control terminal.

[0033] The second scanning unit further includes a second black insertion shift circuit, which is electrically connected to the second pull-up node, the fourth shift signal terminal and the fourth shift output terminal, and the second black insertion shift circuit is configured to write the signal of the fourth shift signal terminal to the fourth shift output terminal under the control of the signal of the second pull-up node.

[0034] In some embodiments, the second voltage terminal and the second control terminal are electrically connected, or the second voltage terminal and the second control terminal are disconnected.

[0035] In some embodiments, the first sub-circuit includes a third sub-circuit and a fourth sub-circuit;

[0036] The third sub-circuit is electrically connected to the first black insertion input terminal, the first control terminal, and the second node, and is configured to write the signal of the first black insertion input terminal into the second node under the control of the signal of the first control terminal;

[0037] The fourth sub-circuit is electrically connected to the second node, the second voltage terminal, the second control terminal and the first pull-up node, and the fourth sub-circuit is configured to write the signal of the second voltage terminal into the first pull-up node under the control of the signal of the second node and the second control terminal.

[0038] In some embodiments, the first scanning unit further includes a first black insertion reset circuit, the first black insertion reset circuit being electrically connected to the first pull-up node, the second node, the black insertion reset control terminal, and the first reset voltage terminal, and the first black insertion reset circuit being configured to write a signal from the first reset voltage terminal into the pull-up node under control of signals from the second node and the black insertion reset control terminal.

[0039] In some embodiments, the first scanning unit further includes a first pull-down circuit and a first noise reduction circuit;

[0040] The first pull-down circuit is electrically connected to the first pull-up node, the first reset voltage terminal, and the first pull-down node, and the first pull-down circuit is configured to write the signal of the first reset voltage terminal into the first pull-down node under the control of the signal of the first pull-up node;

[0041] The first noise reduction circuit is electrically connected to the first pull-down node, the first reset voltage terminal and the second shift output terminal. The first noise reduction circuit is configured to write the signal of the first reset voltage terminal to the second shift output terminal under the control of the signal of the first pull-down node.

[0042] In some embodiments, the shift register also includes a fifth reset circuit, which is electrically connected to the second control terminal, the second node, the first reset voltage terminal and the first pull-down node, and the fifth reset circuit is configured to write the signal of the first reset voltage terminal into the first pull-down node under the control of the signal of the second node and the second control terminal.

[0043] On the other hand, a gate driving circuit is provided, comprising a plurality of the shift registers described above, wherein the plurality of shift registers are cascaded.

[0044] In some embodiments, the plurality of shift registers include a cascaded first shift register and a second shift register, the shift registers including a first display shift circuit, a second display shift circuit, and a first black insertion shift circuit, the second shift output terminal of the first shift register is electrically connected to the first black insertion input terminal of the second shift register, and the third shift output terminal of the first shift register is electrically connected to the first display input terminal of the second shift register.

[0045] In some embodiments, the plurality of shift registers include a cascaded first shift register and a second shift register, and when the shift register includes a first display shift circuit, a second display shift circuit, a first black insertion shift circuit, and a second black insertion shift circuit, the third shift output terminal of the first shift register is electrically connected to the first display input terminal of the second shift register, the second shift output terminal of the first shift register is electrically connected to the first black insertion input terminal of the second shift register, and the fourth shift output terminal of the first shift register is electrically connected to the second black insertion input terminal of the second shift register.

[0046] In some embodiments, the gate drive circuit includes multiple gate lines, the first scanning unit includes multiple first output circuits, and the first output ends of the multiple first output circuits are electrically connected to different gate lines respectively; and / or the second scanning unit includes multiple second output circuits, the second output ends of the multiple second output circuits are electrically connected to different gate lines respectively, and the first output end and the second output end are electrically connected to different gate lines.

[0047] In some embodiments, the first scanning unit includes four first output circuits, and the second scanning unit includes four second output circuits.

[0048] On the other hand, a display panel is provided, comprising the gate driving circuit.

[0049] In yet another aspect, a display device is provided, comprising the display panel.

[0050] The shift register, gate drive circuit, display panel, and display device of the disclosed embodiments are also provided with a first black insertion input circuit, a first black insertion shift circuit, a first display input circuit, a first display shift circuit, and a first output circuit. The first output circuit is electrically connected to the pixel drive circuit P1 to control the pixel drive circuit P1 to write the picture data signal and the black data signal. The first black insertion input circuit, the first output circuit, and the first black insertion shift circuit constitute a black insertion drive module to implement black insertion drive, and the first display input circuit, the first output circuit, and the first display shift circuit constitute a display drive module to implement display drive. The first black insertion shift circuit can be used to implement cascading of different black insertion drive modules, and the first display shift circuit can be used to implement cascading of different display drive modules, that is, a separate first black insertion shift circuit is provided to implement cascading between different black insertion drive modules. Compared with the related art that implements cascading of black insertion drive modules by multiplexing the display shift circuit and / or the display output circuit, the first black insertion shift circuit in the disclosed embodiments crosses fewer shift registers when cascading, and the wiring difficulty is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0052] FIG1 exemplarily shows a front view structure of a display device;

[0053] FIG2 exemplarily shows a structural diagram of a display panel;

[0054] FIG3 exemplarily shows a circuit diagram of a pixel driving circuit;

[0055] FIG4 exemplarily shows a structural diagram of another display panel;

[0056] FIG5 exemplarily shows a signal timing diagram of the pixel driving circuit shown in FIG3 ;

[0057] FIG6 exemplarily shows a circuit block diagram of a shift register;

[0058] FIG7 exemplarily shows a circuit diagram of a first scanning unit;

[0059] FIG8 exemplarily shows a structural block diagram of another shift register;

[0060] FIG9 exemplarily shows a structural block diagram of another shift register;

[0061] FIG10 exemplarily shows a circuit diagram of a shift register;

[0062] FIG11 exemplarily shows a circuit diagram of a first black insertion input circuit;

[0063] FIG12 exemplarily shows a circuit diagram of a second black insertion input circuit;

[0064] FIG13 exemplarily shows a circuit diagram of a shift register;

[0065] FIG14 exemplarily shows a circuit diagram of a first black insertion input circuit;

[0066] FIG15 exemplarily shows a block diagram of a gate driving circuit;

[0067] FIG16 exemplarily shows a timing diagram of a gate driving circuit;

[0068] FIG17 exemplarily shows a circuit diagram of a shift register;

[0069] FIG18 exemplarily shows a circuit diagram of another shift register. Specific embodiments

[0070] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0071] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0072] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, a scanning unit and its driving method, a gate driving circuit and a display device provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0073] The terms "first", "second" and similar terms used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms "include" or "comprise" and similar terms mean that the elements or objects preceding the term include the elements or objects listed after the term and their equivalents, without excluding other elements or objects. The terms "coupled" or "connected" and similar terms are not limited to physical or mechanical coupling, but may include electrical coupling, whether direct or indirect.

[0074] The transistors used in the embodiments of the present disclosure may be thin film transistors (TFTs) or field effect transistors (FETs) or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present disclosure, in order to distinguish the source and drain of the transistor, one of the electrodes is referred to as the first electrode, the other electrode is referred to as the second electrode, and the gate is referred to as the control electrode. In addition, transistors can be divided into N-type and P-type according to the characteristics of the transistor. The following embodiments are described using N-type transistors. When an N-type transistor is used, the first electrode is the source of the N-type transistor, and the second electrode is the drain of the N-type transistor. When the gate input is high, the source and drain are turned on, and the P-type is the opposite. It can be imagined that the use of P-type transistors is something that a person skilled in the art can easily think of without creative work, and therefore it is also within the scope of protection of the embodiments of the present disclosure.

[0075] In the embodiments of the present disclosure, a "signal at an active level" refers to a signal that, when input to the control electrode of a transistor, can turn the transistor on, and a "signal at an inactive level" refers to a signal that, when input to the control electrode of a transistor, can turn the transistor off. For an N-type transistor, a high-level signal is a signal at an active level, while a low-level signal is a signal at an inactive level. For a P-type transistor, a low-level signal is a signal at an active level, while a high-level signal is a signal at an inactive level.

[0076] FIG1 exemplarily illustrates a front view of a display device. As shown in FIG1 , some embodiments of the present disclosure provide a display device, which can be any device that displays either moving (e.g., video) or fixed (e.g., still images) and whether text or images. More specifically, it is expected that the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, camera view displays (e.g., displays for rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays for images of a piece of jewelry), etc. FIG1 illustrates the display device as a television.

[0077] The display device includes a display panel. For example, the display device includes a housing and a display panel, with the display panel connected to the housing. In practical applications, the display device may also include a circuit board, a display driver IC (Integrated Circuit), and other electronic components disposed within the housing.

[0078] The display panel may be a liquid crystal display panel (LCD); the display panel may also be an electroluminescent display panel or a photoluminescent display panel. In the case where the display panel is an electroluminescent display panel, the electroluminescent display panel may be an organic light-emitting diode (OLED) display panel or a quantum dot light-emitting diode (QLED) display panel. In the case where the display panel is a photoluminescent display panel, the photoluminescent display device may be a quantum dot photoluminescent display panel. Some embodiments of the present disclosure are described by taking the display panel as an organic light-emitting diode (OLED) display panel as an example.

[0079] Fig. 2 exemplarily shows a structural diagram of a display panel. As shown in Fig. 2 , the display panel includes a substrate, a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL arranged on one side of the substrate.

[0080] The substrate can be a rigid substrate or a flexible substrate, and can be selected according to actual needs.

[0081] Exemplarily, the substrate is a rigid substrate, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0082] Exemplarily, the substrate may be a flexible substrate, such as a PET (Polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate twoformic acid glycol ester) substrate, or a PI (Polyimide) substrate.

[0083] The display panel may include a display area A and a non-display area B electrically connected to the display area A. The non-display area B may be located on one, two, or three sides of the display area A, or the non-display area B may be disposed around the display area A. A plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL may be located within the display area A.

[0084] For example, the plurality of sub-pixels PX may be arranged in an array. For example, the plurality of sub-pixels PX may be arranged in an array to form a plurality of sub-pixel rows and a plurality of sub-pixel columns, wherein the plurality of sub-pixels PX in a sub-pixel row are arranged along a first direction X, and the plurality of sub-pixels PX in a sub-pixel column are arranged along a second direction Y.

[0085] The first direction X and the second direction Y intersect each other. The angle between the first direction X and the second direction Y can be set according to actual needs. For example, the angle between the first direction X and the second direction Y can be 85°, 88°, 90°, 92°, or 95°.

[0086] The sub-pixel PX may include a pixel driving circuit P1 and a light emitting device P2 electrically connected to the pixel driving circuit P1. When the display panel is in operation, the light emitting device P2 may emit light under the drive of the pixel driving circuit P1.

[0087] For example, one gate line GL may be electrically connected to a plurality of pixel driving circuits P1 in a sub-pixel row, and one data line DL may be electrically connected to a plurality of pixel driving circuits P1 in a sub-pixel column.

[0088] The pixel driving circuit P1 has various structures that can be selected based on actual needs. For example, the pixel driving circuit P1 may have a "3T1C," "6T1C," "7T1C," "6T2C," or "7T2C" structure. "T" represents a transistor, and the number preceding "T" represents the number of transistors. "C" represents a storage capacitor, and the number preceding "C" represents the number of storage capacitors.

[0089] During use of the display device, the stability of the transistors in the pixel driving circuit P1 and the light-emitting device OLED may decrease (for example, the threshold voltage of the driving transistor drifts), affecting the display effect of the display device. In this case, compensation of the sub-pixel PX is required.

[0090] There are multiple ways to compensate sub-pixels PX, which can be selected based on actual needs. For example, a pixel compensation circuit can be provided in the sub-pixel PX to perform internal compensation on the sub-pixel P using the pixel compensation circuit. In another example, a transistor within the sub-pixel PX can sense a driving transistor or a light-emitting device, and the sensed data can be transmitted to an external sensing circuit, which can then calculate the driving voltage value to be compensated and provide feedback, thereby achieving external compensation for the sub-pixel PX.

[0091] This disclosure takes the external compensation method (sensing the driving transistor) and the pixel driving circuit adopting the "3T1C" structure as an example to schematically illustrate the structure and working process of the sub-pixel PX.

[0092] Fig. 3 exemplarily shows a circuit diagram of a pixel driving circuit. Exemplarily, as shown in Fig. 3 , the pixel driving circuit P1 may include a switching transistor T1, a driving transistor T2, a sensing transistor T3, and a storage capacitor Cst.

[0093] The control electrode of the switching transistor T1 is electrically connected to the first gate signal terminal G1, the first electrode of the switching transistor T1 is electrically connected to the data signal terminal Data, and the second electrode of the switching transistor T1 is electrically connected to the node G. The switching transistor T1 is configured to transmit the data signal of the data signal terminal Data to the node G under the control of the first scan signal of the first gate signal terminal G1.

[0094] Here, the data signal includes, for example, a detection data signal and a display data signal. The detection data signal is used during the blanking period, and the display data signal is used during the display period. For details about the display period and the blanking period, please refer to the description in the following embodiments and will not be repeated here.

[0095] The control electrode of the driving transistor T2 is electrically connected to the node G, the first electrode of the driving transistor T2 is electrically connected to the sixth voltage signal terminal ELVDD, and the second electrode of the driving transistor T2 is electrically connected to the node S. The driving transistor T2 is configured to be turned on under the control of the signal at the node G and to write a driving signal related to the node G and the sixth voltage signal terminal ELVDD to the node S.

[0096] A first end of the storage capacitor Cst is electrically connected to the node G, and a second end of the storage capacitor Cst is electrically connected to the node S. In the process of charging the node G, the switch transistor T1 simultaneously charges the storage capacitor Cst.

[0097] The anode of the light emitting device P2 is electrically connected to the node S, and the cathode of the light emitting device P2 is electrically connected to the seventh voltage signal terminal ELVSS. The light emitting device P2 is configured to emit light under the driving of the driving signal.

[0098] The control electrode of the sensing transistor T3 is electrically connected to the second gate signal terminal G2, the first electrode of the sensing transistor T3 is electrically connected to the node S, and the second electrode of the sensing transistor T3 is electrically connected to the sensing signal terminal Sense. The sensing transistor T3 is configured to detect an electrical characteristic of the driving transistor T2 under the control of the second scan signal at the second gate signal terminal G2 to implement external compensation. The electrical characteristic may include, for example, a threshold voltage and / or carrier mobility of the driving transistor T2.

[0099] Here, the sensing signal terminal Sense can provide a reset signal or obtain a sensing signal, wherein the reset signal is used to reset the node S during the display period, and the sensing signal is used to obtain the threshold voltage and / or carrier mobility of the driving transistor T2 during the blanking period.

[0100] When the structure of the pixel driving circuit P1 adopts the structure shown in FIG3 , the multiple pixel driving circuits P1 in a sub-pixel row can be electrically connected to the two gate lines GL. For example, the multiple gate lines include a first gate line and a second gate line, the first gate line is electrically connected to the multiple first gate signal terminals G1 in the sub-pixel row, so that each first gate signal terminal G1 can receive a first scanning signal through the first gate line, and the second gate line is electrically connected to the multiple second gate signal terminals G2 in the sub-pixel row, so that each second gate signal terminal G2 can receive a second scanning signal through the second gate line.

[0101] Of course, multiple pixel driving circuits P1 in a sub-pixel row can also be electrically connected to a gate line GL. Figure 4 exemplarily shows a structural diagram of another display panel. As shown in Figure 4, the first gate signal terminal G1 and the second gate signal terminal G2 in a sub-pixel row are both electrically connected to the same gate line GL.

[0102] Continuing with FIG2 , a gate drive circuit is also provided on one side of the substrate. The gate drive circuit is located on the same side of the substrate as the multiple sub-pixels PX, gate lines GL, and data lines DL. The gate drive circuit includes multiple cascaded shift registers, each of which includes an output terminal electrically connected to the gate line GL. When the gate drive circuit is in operation, the multiple cascaded shift registers sequentially output a first scanning signal and a second scanning signal to the pixel drive circuit P1 via the output terminals.

[0103] It should be noted that, during the display phase of a frame, the first scanning signal transmitted by the first gate signal terminal G1 and the second scanning signal transmitted by the second gate signal terminal G2 are both provided by the gate driver circuit. That is, each shift register in the gate driver circuit can be electrically connected to the first gate signal terminal G1 via a first gate line to transmit the first scanning signal to the first gate signal terminal G1 via the first gate line, and can be electrically connected to the second gate signal terminal G2 via a second gate line to transmit the second scanning signal to the second scanning signal terminal G2 via the second gate line.

[0104] FIG4 exemplarily illustrates a structural diagram of another display panel. As shown in FIG4 , the first gate signal terminal G1 and the second gate signal terminal G2 of multiple pixel drive circuits P1 in a sub-pixel row can also be electrically connected to the same gate line GL. In this case, the first scan signal and the second scan signal are the same. Each shift register in the gate drive circuit can be electrically connected to the first gate signal terminal G1 and the second gate signal terminal G2 via the corresponding gate line GL, and transmit the scan signal to the first gate signal terminal G1 and the second gate signal terminal G2 via the gate line GL.

[0105] In the related art, dynamic image drag will appear in the sub-pixel PX during operation, that is, when the display device switches from one frame to another, the user will feel the drag of the previous frame. In order to improve the problem of image drag, a black data write process and a black data hold process can be set in the light-emitting process of the sub-pixel PX. Figure 5 exemplarily shows a signal timing diagram of the pixel driving circuit shown in Figure 3. As shown in Figure 5, the black data write process and the black data hold process are sequentially added to the original light-emitting process, that is, a black screen insertion process is set. This reduces the light-emitting time and enhances the moving picture response time (MPRT). The larger the MPRT, the lighter the drag phenomenon.

[0106] Controlling the pixel driver circuit P1 to write data and emit light is called display driving, while controlling the pixel driver circuit P1 to write black data and maintain black data is called black insertion driving. The gate driver circuit can simultaneously perform both display driving and black insertion driving functions. That is, each shift register within the gate driver circuit can be used for both display driving and black insertion driving. As shown in Figure 5, the timing of display driving and black insertion driving are not synchronized. Therefore, the circuit structure within the gate driver circuit used for display driving can have a different cascade relationship than the circuit structure used for black insertion driving.

[0107] The operation process of the gate drive circuit may include an alternating display drive phase and a black insertion drive phase. In the display drive phase, several stages of shift registers within the gate drive circuit sequentially output display drive signals (e.g., pulse 1 in FIG. 5 ) for display drive through their output terminals. In the black insertion drive phase, several stages of shift registers within the gate drive circuit sequentially output black insertion drive signals (e.g., pulse 2 in FIG. 5 ) for black insertion through their output terminals.

[0108] Figure 6 exemplarily shows a circuit block diagram of a shift register. As shown in Figure 6 , the shift register includes a first scanning unit MD1, which includes a first display input circuit 11, a first display shift circuit 12, a black insertion input circuit 13, a first black insertion shift circuit 14, and a first output circuit 15.

[0109] The first display input circuit 11 is connected to the first voltage terminal GVDD1 and the first display input terminal CR <k-1>The first output circuit 15 is electrically connected to the first pull-up node Q1, the first signal terminal CLKE1 and the first output terminal Gout1. The first display shift circuit 12 is electrically connected to the first pull-up node Q1, the first shift signal terminal CLKD3 and the first shift output terminal CR <k>Electrical connection.

[0110] In the display driving stage, the first display input circuit 11 is configured to be <k-1>Under the control of the signal of the first pull-up node Q1, the signal of the first voltage terminal GVDD1 is written into the first pull-up node Q1. The first output circuit 15 is configured to write the signal of the first signal terminal into the first output terminal Gout1 under the control of the signal of the first pull-up node Q1. The first display shift circuit 12 is configured to write the signal of the first shift signal terminal CLKD3 into the first shift output terminal CR under the control of the signal of the first pull-up node Q1. <k>.

[0111] The first voltage terminal GVDD1 can be fed with a signal of a constant level. For example, the first voltage terminal GVDD1 can be fed with a signal of a constant high level. Exemplarily, the display panel includes a first voltage line, the first voltage line being fed with a constant high level signal, and the first voltage line being electrically connected to the first voltage terminal GVDD1.

[0112] The first pull-up node Q1 does not represent an actual component, but rather represents the junction of related electrical connections in the circuit diagram. In other words, the first pull-up node Q1 is equivalent to the junction of related electrical connections in the circuit diagram. Similarly, the second pull-up node Q2, the first pull-down node QB1, the second pull-down node QB2, the node G, the node S, the first node P, and the second node M in the embodiments of the present disclosure are all equivalent to the junction of related electrical connections in the circuit diagram.

[0113] The first display input terminal CR <k-1>It can be electrically connected to the start signal line STV to receive the start signal in the start signal line STV. For example, when the shift register is the first shift register in the gate drive circuit, the first display input terminal CR in the shift register <k-1>The first display input terminal CR is electrically connected to the start signal line STV. <k-1>It can also be electrically connected to the previous shift register to receive the first shift signal output by the previous shift register. For example, the shift register is the nth shift register (n>1), and the first display input terminal CR of the nth shift register is <k-1>Electrically connected to the (n-1)th shift register.

[0114] The first output terminal Gout1 may be electrically connected to the gate line GL to provide a scan signal to the first gate signal terminal G1 and / or the second gate signal terminal G2 through the gate line GL.

[0115] The first signal terminal may be electrically connected to a clock signal line. For example, the gate driving circuit includes a plurality of display clock signal lines CE, and the first signal terminal is electrically connected to the display clock signal lines CE.

[0116] The first shift signal terminal CLKD3 may be electrically connected to a clock signal line. For example, the gate driving circuit includes a plurality of black-insertion clock signal lines CD, and the first shift signal terminal CLKD3 is electrically connected to the black-insertion clock signal lines CD.

[0117] For example, the first display input terminal CR <k-1>When receiving a high-level signal output from the previous shift register or the start signal line STV, the path between the first voltage terminal GVDD1 and the first pull-up node Q1 is connected, and the high-level signal of the first voltage terminal GVDD1 is written into the first pull-up node Q1, making the signal of the first pull-up node Q1 a high-level signal. Under the control of the high-level signal of the first pull-up node Q1, the first output circuit 15 connects the path between the first signal terminal and the first output terminal Gout1, and the high-level signal of the first signal terminal is written into the first output terminal Gout1, that is, the first output terminal Gout1 of the shift register provides a high-level signal to the first gate signal terminal G1 and the second gate signal terminal G2 through the gate line GL, so that the pixel driving circuit P1 writes the picture data signal. Under the control of the high-level signal of the first pull-up node Q1, the first display shift circuit 12 connects the first shift signal terminal CLKD3 and the first shift output terminal CR <k>The path between the first shift signal terminal CLKD3 is turned on, and the high level signal of the first shift signal terminal CLKD3 is written into the first shift output terminal CR <k>.

[0118] That is, the first display input circuit 11, the first output circuit 15 and the first display shift circuit 12 constitute a display driving module to realize display driving. For example, the gate driving circuit may include multiple display driving modules, and the first shift output terminal CR of the previous display driving module <k>and the first display input terminal CR of the next display driving module <k-1>Electrically connected to achieve cascading of multiple display driver modules.

[0119] The black insertion input circuit 13 and the first black insertion input terminal CR2 <k-2>The first black insertion shift circuit 14 is electrically connected to the first pull-up node Q1, the second shift signal terminal CLKD2 and the second shift output terminal CR2. <k>Electrical connection.

[0120] In the black insertion driving stage, the black insertion input circuit 13 is configured to be <k-2>The first output circuit 15 is further configured to write the signal of the first signal terminal to the first output terminal Gout1 under the control of the signal of the first pull-up node Q1. The first black insertion shift circuit 14 is configured to write the signal of the second signal terminal to the second shift output terminal CR2 under the control of the signal of the first pull-up node Q1. <k>.

[0121] The first control terminal BCK1 and the second control terminal BCK2 may be electrically connected to a clock signal line. For example, the gate driving circuit includes a plurality of control signal lines BC, and the first control terminal BCK1 and the second control terminal BCK2 may be electrically connected to different control signal lines BC.

[0122] The second voltage terminal V2 can be fed with the same signal as the second control terminal BCK2, for example, the second voltage terminal V2 is electrically connected to the second control terminal BCK2. The second voltage terminal V2 can also be fed with a signal at a constant level. For example, the display panel includes a fourth voltage line GVDD4 that is fed with a constant high-level signal, and the second voltage terminal V2 is electrically connected to the fourth voltage line GVDD4.

[0123] For example, the first black insertion input terminal CR2 <k-2>, the first control terminal BCK1 and the second control terminal BCK2 all receive high-level signals, so that the path between the second voltage terminal V2 and the first pull-up node Q1 is conductive, and the high-level signal of the second voltage terminal V2 is written into the first pull-up node Q1. Under the control of the high-level signal of the first pull-up node Q1, the first output circuit 15 connects the path between the first signal terminal and the first output terminal Gout1, and the high-level signal of the first signal terminal is written into the first output terminal Gout1, that is, the first output terminal Gout1 of the shift register provides a high-level signal to the first gate signal terminal G1 and the second gate signal terminal G2 through the gate line GL, so that the pixel driving circuit P1 writes the black data signal. Under the control of the high-level signal of the first pull-up node Q1, the first black insertion shift circuit 14 connects the second shift signal terminal CLKD2 and the second shift output terminal CR2. <k>The path between the two terminals is turned on, and the high level signal of the second shift signal terminal CLKD2 is written into the second shift output terminal CR2. <k>.

[0124] That is, the black insertion input circuit 13, the first output circuit 15, and the first black insertion shift circuit 14 constitute a black insertion driving module to implement black insertion driving. The gate driving circuit may include multiple black insertion driving modules, and the previous black insertion driving module and the next black insertion driving module may be cascaded through the first black insertion shift circuit 14.

[0125] The shift register of the disclosed embodiment is provided with a black insertion input circuit 13, a first black insertion shift circuit 14, a first display input circuit 11, a first display shift circuit 12, and a first output circuit 15. The first output circuit 15 is electrically connected to the pixel driving circuit P1 to control the pixel driving circuit P1 to write the picture data signal and the black data signal. The black insertion input circuit 13, the first output circuit 15, and the first black insertion shift circuit 14 constitute a black insertion driving module to implement black insertion driving, and the first display input circuit 11, the first output circuit 15, and the first display shift circuit 12 constitute a display driving module to implement display driving. The first black insertion shift circuit 14 can be used to implement cascading of different black insertion driving modules, and the first display shift circuit 12 can be used to implement cascading of different display driving modules, that is, the first black insertion shift circuit 14 is separately provided to implement cascading between different black insertion driving modules. Compared with the related art in which the black insertion driving modules are cascaded by multiplexing the display shift circuit and / or the display output circuit, the first black insertion shift circuit 14 in the embodiment of the present disclosure has fewer shift registers when cascaded and has lower wiring difficulty.

[0126] The first scanning unit MD1 can include multiple first output circuits 15, each electrically connected to a different gate line GL. This allows the first scanning unit MD1 to simultaneously drive multiple rows of sub-pixels PX, reducing the number of first scanning units MD1. The more first output circuits 15 included in the first scanning unit MD1, the fewer first scanning units MD1 are required, but the more display clock signal lines electrically connected to the first output circuits 15 are required. Therefore, the first scanning unit MD1 can include four first output circuits 15, reducing the number of first scanning units MD1 without excessively increasing the number of display clock signal lines.

[0127] Exemplarily, the display clock signal lines include a first display clock signal line CE1, a second display clock signal line CE2, a third display clock signal line CE3, and a fourth display clock signal line CE4. The four display clock signal lines are electrically connected to four first output circuits 15, respectively. The first output circuit 15 electrically connected to the first display clock signal line CE1 is electrically connected to the Nth row of sub-pixels PX, the first output circuit 15 electrically connected to the second display clock signal line CE2 is electrically connected to the N+1th row of sub-pixels PX, the first output circuit 15 electrically connected to the third display clock signal line CE3 is electrically connected to the N+2th row of sub-pixels PX, and the first output circuit 15 electrically connected to the fourth display clock signal line CE4 is electrically connected to the N+3th row of sub-pixels PX.

[0128] Of course, the embodiment of the present disclosure does not limit the number of the first output circuits 15 in the first scanning unit MD1, and the number can be one, two, three, five, etc.

[0129] The shift register may include only the first scanning unit MD1. In this case, multiple shift registers in the gate drive circuit are cascaded, that is, multiple first scanning units MD1 are cascaded. For example, the multiple shift registers may include a cascaded first shift register and a second shift register, and the first shift output terminal CR of the first shift register is <k>and the first display input terminal CR of the second shift register <k-1>Electrically connected to the second shift output terminal CR2 of the first shift register <k>The first black insertion input terminal CR2 of the second shift register <k-2>Electrical connection.

[0130] Exemplarily, the gate drive circuit includes a first control signal line BC1, a second control signal line BC2, a third control signal line BC3, and a fourth control signal line BC4, as well as a second black insertion clock signal line CD2, a third black insertion clock signal line CD3, a sixth black insertion clock signal line CD6, and a seventh black insertion clock signal line CD7, and also includes a first display clock signal line CE1, a second display clock signal line CE2, a third display clock signal line CE3, a fourth display clock signal line CE4, a fifth display clock signal line CE5, a sixth display clock signal line CE6, a seventh display clock signal line CE7, and an eighth display clock signal line CE8. The first control signal line BC1 is electrically connected to the first control terminal BCK1 of the first shift register, the second control signal line BC2 is electrically connected to the second control terminal BCK2 of the first shift register and the second voltage terminal V2, the third control signal line BC3 is electrically connected to the first control terminal BCK1 of the second shift register, and the fourth control signal line BC4 is electrically connected to the second control terminal BCK2 of the second shift register and the second voltage terminal V2. The second black insertion clock signal line CD2 is electrically connected to the second shift signal terminal CLKD2 of the first shift register, and the third black insertion clock signal line CD3 is electrically connected to the first shift signal terminal CLKD3 of the first shift register. The seventh black insertion clock signal line CD7 is electrically connected to the first shift signal terminal CLKD3 of the second shift register, and the sixth black insertion clock signal line CD6 is electrically connected to the second shift signal terminal CLKD2 of the second shift register. The four first output circuits 15 of the first shift register are electrically connected to the first display clock signal line CE1, the second display clock signal line CE2, the third display clock signal line CE3, and the fourth display clock signal line CE4, respectively. The four first output circuits 15 of the second shift register are electrically connected to the fifth display clock signal line CE5, the sixth display clock signal line CE6, the seventh display clock signal line CE7, and the eighth display clock signal line CE8, respectively.

[0131] Figure 7 exemplarily shows a circuit diagram of a first scanning unit. As shown in Figure 7 , the first scanning unit MD1 may further include a first pull-down circuit 17, a first pull-down control circuit 16, a first noise reduction circuit 18, a first reset circuit 20, a second reset circuit 26, a third reset circuit 22, a fourth reset circuit 23, and a first blanking circuit 24.

[0132] The first pull-down control circuit 16 is electrically connected to the third voltage terminal and the first pull-down node QB1 . The first pull-down control circuit 16 is configured to write a signal from the third voltage terminal into the first pull-down node QB1 .

[0133] Exemplarily, the first pull-down control circuit 16 includes a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17. The fourteenth transistor M14 and the fifteenth transistor M15 are connected in series, and the control electrodes of the fourteenth transistor M14 and the fifteenth transistor M15 are both electrically connected to the second voltage line GVDD2. The second electrode of the fifteenth transistor M15 is electrically connected to the control electrode of the sixteenth transistor M16. The first electrode of the sixteenth transistor M16 is electrically connected to the second voltage line GVDD2. The second electrode of the sixteenth transistor M16 is electrically connected to the first pull-down node QB1. The control electrode of the seventeenth transistor M17 is electrically connected to the first pull-up node Q1. The second electrode of the seventeenth transistor M17 is electrically connected to the second electrode of the fifteenth transistor M15. The first electrode of the seventeenth transistor M17 is electrically connected to the first pull-down node QB1.

[0134] The first pull-down circuit 17 is electrically connected to the first pull-up node Q1 , the first reset voltage terminal VGL1 and the first pull-down node QB1 . The first pull-down circuit 17 is configured to write the signal of the first reset voltage terminal VGL1 into the first pull-down node QB1 under the control of the signal of the first pull-up node Q1 .

[0135] Exemplarily, the first pull-down circuit 17 includes an eighteenth transistor M18, a control electrode of the eighteenth transistor M18 is electrically connected to the first pull-up node Q1, a first electrode of the eighteenth transistor M18 is electrically connected to the first reset voltage terminal VGL1, and a second electrode of the eighteenth transistor M18 is electrically connected to the first pull-down node QB1.

[0136] The first noise reduction circuit 18 is connected to the first pull-down node QB1, the first pull-up node Q1, the first reset voltage terminal VGL1, and the first shift output terminal CR <k>and the second shift output terminal CR2 <k>The first noise reduction circuit 18 is configured to write the signal of the first reset voltage terminal VGL1 into the first pull-up node Q1 and the first shift output terminal CR under the control of the signal of the first pull-down node QB1. <k>and the second shift output terminal CR2 <k>.

[0137] Exemplarily, the first noise reduction circuit 18 includes a nineteenth transistor M19, a twentieth transistor M20, a twenty-second transistor M22, a twenty-fourth transistor M24, a twenty-sixth transistor M26, a twenty-eighth transistor M28, a thirtieth transistor M30, and a thirty-fifth transistor M35. The nineteenth transistor M19 and the twenty-second transistor M20 are connected in series, and the control electrodes of the nineteenth transistor M19 and the twenty-second transistor M20 are electrically connected to the first pull-down node QB1, the first electrode of the twentieth transistor M20 is electrically connected to the first reset voltage terminal VGL1, and the second electrode of the nineteenth transistor M19 is electrically connected to the first pull-up node Q1. The control electrodes of the twenty-second transistor M22, the twenty-fourth transistor M24, the twenty-sixth transistor M26, the twenty-eighth transistor M28, the thirtieth transistor M30, and the thirty-fifth transistor M35 are electrically connected to the first pull-down node QB1, the first electrodes of the twenty-second transistor M22 and the thirty-fifth transistor M35 are electrically connected to the first reset voltage terminal VGL1, and the second electrode of the twenty-second transistor M22 is electrically connected to the second shift output terminal CR2. <k>The second electrode of the thirty-fifth transistor M35 is electrically connected to the first shift output terminal CR <k>The second electrodes of the 24th transistor M24, the 26th transistor M26, the 28th transistor M28, and the 30th transistor M30 are electrically connected to the first output terminal Gout1, and the first electrodes are electrically connected to the second reset voltage terminal VGL2. The second reset voltage terminal VGL2 can be fed with a constant low-level signal.

[0138] The first reset circuit 20 is electrically connected to the reset signal terminal TRST, the first pull-up node Q1 and the first reset voltage terminal VGL1. The first reset circuit 20 is configured to write the signal of the first reset voltage terminal VGL1 into the first pull-up node Q1 under the control of the reset signal terminal TRST.

[0139] Exemplarily, the first reset circuit 20 includes a ninth transistor M9 and a tenth transistor M10, wherein the control electrodes of the ninth transistor M9 and the tenth transistor M10 are electrically connected to the reset control terminal, the first electrode of the tenth transistor M10 is electrically connected to the first reset voltage terminal VGL1, and the second electrode of the ninth transistor M9 is electrically connected to the first pull-up node Q1.

[0140] The second reset circuit 26 is electrically connected to the reset input terminal, the first pull-up node Q1 and the first reset voltage terminal VGL1. The second reset circuit 26 is configured to write the signal of the first reset voltage terminal VGL1 into the first pull-up node Q1 under the control of the signal of the reset input terminal. The reset input terminal can be connected to the first shift output terminal CR of the next stage scanning unit.<K+1> Electrical connection.

[0141] Illustratively, the second reset circuit 26 includes a twelfth transistor M12 and a thirteenth transistor M13, the twelfth transistor M12 and the thirteenth transistor M13 are connected in series, and the control electrodes of the twelfth transistor M12 and the thirteenth transistor M13 are electrically connected to the reset input terminal, the second electrode of the twelfth transistor M12 is electrically connected to the first pull-up node Q1, and the first electrode of the thirteenth transistor M13 is electrically connected to the first reset voltage terminal VGL1.

[0142] The third reset circuit 22 is connected to the first pull-down node QB1, the first reset voltage terminal VGL1 and the first display input terminal CR <k-1>The third reset circuit 22 is configured to be electrically connected to the first display input terminal CR <k-1>The signal of the first reset voltage terminal VGL1 is written into the first pull-down node QB1 under the control of the signal.

[0143] Exemplarily, the third reset circuit 22 includes a thirty-third transistor M33, the control electrode of the thirty-third transistor M33 is connected to the first display input terminal CR <k-1>A first electrode of the thirty-third transistor M33 is electrically connected to the first reset voltage terminal VGL1 , and a second electrode of the thirty-third transistor M33 is electrically connected to the first pull-down node QB1 .

[0144] The first blanking circuit 24 is connected to the fifth control terminal OE and the first display input terminal CR <k-1>, the fourth voltage terminal CLKA and the first pull-up node Q1 are electrically connected, and the first blanking circuit 24 is configured to be connected to the fifth control terminal, the first display input terminal CR <k-1>Under the control of the signal of , the signal of the fourth voltage terminal CLKA is written into the first pull-up node Q1.

[0145] For example, when the first display input terminal CR <k-1>The signals at the fifth control terminal OE, the fifth control terminal OE, and the fourth voltage terminal CLKA are all high-level signals. The high-level signal at the fourth voltage terminal CLKA is written to the first pull-up node Q1. Under the control of the high-level signal at the first pull-up node Q1, the first output circuit 15 writes the high-level signal at the first signal terminal to the first output terminal Gout1. The first output terminal Gout1 provides a high-level signal to the second gate signal terminal G1 via the gate line GL, resetting the node S or driving the sub-pixel PX to display a black screen. This method, combined with the electrical signal on the sensing signal line on the display substrate, achieves the effect of eliminating smear in the displayed image.

[0146] Exemplarily, the first blanking circuit 24 includes a first capacitor C1, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5. The first transistor M1 and the second transistor M2 are connected in series, and the control electrodes of the first transistor M1 and the second transistor M2 are electrically connected to the fifth control terminal OE. The second electrode of the first transistor M1 is electrically connected to the first display input terminal CR. <k-1>The first electrode of the third transistor M3 is electrically connected to the node H, the second electrode of the third transistor M3 is connected between the first transistor M1 and the second transistor M2, the first electrode of the third transistor M3 is connected to the first voltage line point, one plate of the first capacitor C1 is electrically connected to the node H, and the other plate is electrically connected to the first reset voltage terminal VGL1, the control electrode of the fourth transistor M4 is electrically connected to the node H, the second electrode of the fourth transistor M4 is electrically connected to the fourth voltage terminal CLKA, the first electrode of the fourth transistor M4 is electrically connected to the node N, the fifth transistor M5 and the sixth transistor M6 are connected in series, and the control electrodes of the fifth transistor M5 and the sixth transistor M6 are electrically connected to the fourth voltage terminal CLKA, the second electrode of the fifth transistor M5 is electrically connected to the node N, and the first electrode of the sixth transistor M6 is electrically connected to the first pull-up node Q1.

[0147] The fourth reset circuit 23 is electrically connected to the first pull-down node QB1, the first reset voltage terminal VGL1, the fourth voltage terminal CLKA and the node H. The fourth reset circuit 23 is configured to write the signal of the first reset voltage terminal VGL1 into the first pull-down node QB1 under the control of the signal of the node H and the fourth voltage terminal CLKA.

[0148] Illustratively, the fourth reset circuit 23 includes a thirty-first transistor M31 and a thirty-second transistor M32, the control electrode of the thirty-first transistor M31 is electrically connected to the fourth voltage terminal CLKA, the control electrode of the thirty-second transistor M32 is electrically connected to the node H, the second electrode of the thirty-first transistor M31 is electrically connected to the first pull-down node QB1, and the first electrode of the thirty-second transistor M32 is electrically connected to the first reset voltage terminal VGL1.

[0149] FIG8 exemplarily shows a structural block diagram of another shift register. As shown in FIG8 , the shift register may further include a second scanning unit MD2 , which includes a second display input circuit 16 , a second display shift circuit 17 and a second output circuit 18 .

[0150] The second display input circuit 16 and the first shift output terminal CR <k>, the first voltage terminal GVDD1 and the second pull-up node Q2 are electrically connected, the second display shift circuit 17 is electrically connected to the second pull-up node Q2, the third shift signal terminal CLKD7 and the third shift output terminal CR<K+1> The second output circuit 18 is electrically connected to the second pull-up node Q2, the second signal terminal and the second output terminal Gout2.

[0151] In the display driving stage, the second display input circuit 16 is configured to output the first shift output terminal CR <k>The second display shift circuit 17 is configured to write the signal of the third shift signal terminal CLKD7 into the third shift output terminal CR under the control of the signal of the second pull-up node Q2.<K+1> The second output circuit 18 is configured to write the signal of the second signal terminal into the second output terminal Gout2 under the control of the signal of the second pull-up node Q2.

[0152] The third shift signal terminal CLKD7 may be electrically connected to a clock signal line. For example, the gate driving circuit includes a plurality of black insertion clock signal lines CD, and the third shift signal terminal CLKD7 is electrically connected to the black insertion clock signal line CD.

[0153] The third shift output terminal CR<K+1> The first display input terminal CR of the next stage shift register <k-1>Electrical connection.

[0154] For example, the second display input terminal receives the first shift output terminal CR <k>When a high-level signal is output, the path between the first voltage terminal GVDD1 and the second pull-up node Q2 is conductive, and the high-level signal of the first voltage terminal GVDD1 is written into the second pull-up node Q2, making the signal of the second pull-up node Q2 a high-level signal. Under the control of the high-level signal of the second pull-up node Q2, the second output circuit 18 makes the path between the second signal terminal and the second output terminal Gout2 conductive, and the high-level signal of the second signal terminal is written into the second output terminal Gout2, that is, the second output terminal Gout2 of the shift register provides a high-level signal to the first gate signal terminal G1 and the second gate signal terminal G2 through the gate line GL, so that the pixel driving circuit P1 writes the picture data signal. Under the control of the high-level signal of the second pull-up node Q2, the second display shift circuit 17 makes the second shift signal terminal CLKD2 and the second shift output terminal CR2 <k>The path between the two terminals is turned on, and the high level signal of the second shift signal terminal CLKD2 is written into the second shift output terminal CR2. <k>.

[0155] The second scanning unit MD2 may also include a second pull-down circuit, a second pull-down control circuit, a second noise reduction circuit, a first reset circuit, a second reset circuit, a third reset circuit, a fourth reset circuit, a fifth reset circuit, and a second blanking circuit. The circuit structures and connection relationships of the second pull-down circuit, the second pull-down control circuit, the second noise reduction circuit, the first reset circuit, the second reset circuit, the third reset circuit, the fourth reset circuit, the fifth reset circuit, and the second blanking circuit can refer to the first scanning unit MD1 and will not be described in detail here. That is, the first scanning unit MD1 and the second scanning unit MD2 may have the same or similar structures except for the black insertion input circuit 13 and the first black insertion shift circuit 14. The following is an example in which the structures of the first scanning unit MD1 and the second scanning unit MD2 are the same except for the black insertion input circuit 13 and the first black insertion shift circuit 14.

[0156] The black insertion input circuit 13 is also electrically connected to the second pull-up node Q2 and configured to write a signal to the second pull-up node Q2. The black insertion input circuit 13 controls the sub-pixels PX electrically connected to the first scanning unit MD1 and the second scanning unit MD2 to implement black insertion.

[0157] Figure 9 illustrates a block diagram of another shift register structure. As shown in Figure 9 , the black insertion input circuit 13 may include a first black insertion input circuit 13a and a second black insertion input circuit 13b. The first black insertion input circuit 13a is electrically connected to the first pull-up node Q1 and is configured to write a signal to the first node. The second black insertion input circuit 13b is electrically connected to the second pull-up node Q2 and is configured to write a signal to the second pull-up node Q2. Specifically, the first black insertion input circuit 13a drives the subpixel PX electrically connected to the first scanning unit MD1 to implement black insertion, while the second black insertion input circuit 13b drives the subpixel PX electrically connected to the second scanning unit MD2 to implement black insertion.

[0158] At the same time, the signal written by the first black insertion input circuit 13a to the first pull-up node Q1 and the signal written by the second black insertion input circuit 13b to the second pull-up node Q2 can be the same. The same signals mean that the signal written by the first black insertion input circuit 13a to the first pull-up node Q1 can drive the first output circuit 15 to conduct the first signal terminal and the first output terminal Gout1, and the signal written by the second black insertion input circuit 13b to the second pull-up node Q2 can drive the second output circuit 18 to conduct the second signal terminal and the second output terminal Gout2. The two signals do not necessarily have to have strictly identical levels.

[0159] When the signal written by the first black insertion input circuit 13a at the first pull-up node Q1 and the signal written by the second black insertion input circuit 13b at the second pull-up node Q2 are the same, the sub-pixel PX electrically connected to the first black insertion input circuit 13a and the sub-pixel PX electrically connected to the second black insertion input circuit 13b can be driven to simultaneously implement black insertion, thereby reducing the black insertion time.

[0160] FIG10 exemplarily shows a circuit diagram of a shift register. As shown in FIG9 and FIG10:

[0161] The first black insertion input circuit 13a can be connected to the first black insertion input terminal CR2 <k-2>, the first control terminal BCK1, the second control terminal BCK2, the second voltage terminal V2 and the first pull-up node Q1 are electrically connected, and the first black insertion input circuit 13a is configured to be at the first black insertion input terminal CR2 <k-2>Under the control of the signals of the first control terminal BCK1 and the second control terminal BCK2, the signal of the second voltage terminal V2 is written into the first pull-up node Q1.

[0162] The second black insertion input circuit 13b can also be connected to the first black insertion input terminal CR2 <k-2>, the first control terminal BCK1, the second control terminal BCK2, the second voltage terminal V2 and the second pull-up node Q2 are electrically connected, and the second black insertion input circuit 13b is configured to be connected to the first black insertion input terminal CR2 <k-2>Under the control of the signals of the first control terminal BCK1 and the second control terminal BCK2, the signal of the second voltage terminal V2 is written into the second pull-up node Q2.

[0163] Because the first black insertion input circuit 13a and the second black insertion input circuit 13b are both electrically connected to the first insertion input terminal, the first control terminal BCK1, the second control terminal BCK2, and the second voltage terminal V2, the signal written by the first black insertion input circuit 13a to the first pull-up node Q1 is the same as the signal written by the second black insertion input circuit 13b to the second pull-up node Q2, and the number of signal lines electrically connected to the black insertion input circuit 13 is reduced.

[0164] FIG11 exemplarily shows a circuit diagram of a first black insertion input circuit. As shown in FIG11 , the first black insertion input circuit 13 a includes a first sub-circuit 1 and a second sub-circuit 2 .

[0165] The first sub-circuit 1 and the first black insertion input terminal CR2 <k-2>, the first control terminal BCK1, the second voltage terminal V2 and the first node are electrically connected, and the first sub-circuit 1 is configured to be connected to the first black insertion input terminal CR2 <k-2>, the signal of the second voltage terminal V2 is written into the first node P under the control of the signal of the first control terminal BCK1.

[0166] The second sub-circuit 2 is electrically connected to the second control terminal BCK2 , the first node P and the first pull-up node Q1 . The second sub-circuit 2 is configured to write the signal of the first node P into the first pull-up node Q1 under the control of the signal of the second control terminal BCK2 .

[0167] Exemplarily, the first sub-circuit 1 includes a thirty-sixth transistor M36, a thirty-seventh transistor M37, a thirty-eighth transistor M38, an eighth capacitor C8, and a thirty-ninth transistor M39. The thirty-sixth transistor M36 and the thirty-seventh transistor M37 are connected in series, and the gates of the thirty-sixth transistor M36 and the thirty-seventh transistor M37 are electrically connected to the first control terminal BCK1, and the second electrode of the thirty-sixth transistor M36 is electrically connected to the first black insertion input terminal CR2. <k-2>The first electrode of the thirty-seventh transistor M37 is electrically connected to the second node M. The second electrode of the thirty-eighth transistor M38 is electrically connected between the thirty-sixth transistor M36 and the thirty-seventh transistor M37, and the first electrode of the thirty-eighth transistor M38 is electrically connected to the first voltage line GVDD1. One plate of the eighth transistor M8 is electrically connected to the node M, and the second plate is electrically connected to the first reset voltage terminal VGL1. The second electrode of the thirty-ninth transistor M39 is electrically connected to the second control terminal BCK2, the control electrode of the thirty-ninth transistor M39 is electrically connected to the node M, and the first electrode of the thirty-ninth transistor M39 is electrically connected to the first node P.

[0168] Illustratively, the second sub-circuit 2 includes a 40th transistor M40 and a 41st transistor M41, the 40th transistor M40 and the 41st transistor M41 are connected in series, and the control electrodes of the 40th transistor M40 and the 41st transistor M41 are electrically connected to the second control terminal BCK2, the first electrode of the 41st transistor M41 is electrically connected to the first pull-up node Q1, and the second electrode of the 40th transistor M40 is electrically connected to the first node P.

[0169] Of course, the second sub-circuit 2 may also only include the 40th transistor M40, the control electrode of the 40th transistor M40 is electrically connected to the second control terminal BCK2, the first electrode of the 40th transistor M40 is electrically connected to the first pull-up node Q1, and the second electrode of the 40th transistor M40 is electrically connected to the first node P.

[0170] Figure 12 exemplifies a circuit diagram of a second black insertion input circuit. As shown in Figure 12 , the second black insertion input circuit 13b is electrically connected to the first node, the second control terminal BCK2, and the second pull-up node Q2. The second black insertion input circuit 13b is configured to write the signal from the first node to the second pull-up node Q2 under the control of a signal from the second control terminal BCK2.

[0171] Exemplarily, the second black insertion input circuit 13 b includes a 40th transistor M40 and a 41st transistor M41 , which are connected in series, and the control electrodes of the 40th transistor M40 and the 41st transistor M41 are connected to the second control terminal BCK2 .

[0172] Figure 13 illustrates a circuit diagram of a shift register. As shown in Figures 12 and 13 , the second black insertion input circuit 13b uses the signal at the first node P in the first black insertion input circuit 13a as its input signal. This is equivalent to the second scanning unit MD2 sharing the first sub-circuit 1 in the first scanning unit MD1, reducing the circuit complexity of the shift register.

[0173] Of course, the second black insertion input circuit 13b may also include the first sub-circuit 1 and the second sub-circuit 2. In this case, the first scanning unit MD1 shares the first sub-circuit 1 in the second scanning unit MD2.

[0174] For example, the first sub-circuit 1 and the first black insertion input terminal CR2 <k-2>, the first control terminal BCK1, the second voltage terminal V2 and the second node are electrically connected, and the first sub-circuit 1 is configured to be connected to the first black insertion input terminal CR2 <k-2>The first sub-circuit 2 is electrically connected to the second control terminal BCK2, the first node, and the second pull-up node Q2. The second sub-circuit 2 is configured to write the signal of the first node to the second pull-up node Q2 under the control of the signal of the second control terminal BCK2. The first black insertion input circuit 13a is electrically connected to the first node, the second control terminal BCK2, and the first pull-up node Q1. The second black insertion input circuit 13b is configured to write the signal of the first node to the first pull-up node Q1 under the control of the signal of the second control terminal BCK2.

[0175] In addition, when the first scanning unit MD1 includes the first blanking circuit 24, the second scanning unit MD2 may also include a second blanking circuit, and the second blanking circuit may share a portion of the structure of the first blanking circuit 24. As shown in FIG13 , the second blanking circuit is electrically connected to the node N, the fourth voltage terminal CLKA, and the second pull-up node Q2. The second blanking circuit is configured to write the signal at the node N to the second pull-up node Q2 under the control of the signal of the fourth voltage terminal CLKA.

[0176] Fig. 14 exemplarily shows a circuit diagram of a first black insertion input circuit. As shown in Fig. 14 , the first sub-circuit 1 may include a third sub-circuit 1a and a fourth sub-circuit 1b.

[0177] The third sub-circuit 1a and the first black insertion input terminal CR2 <k-2>, the first control terminal BCK1, and the second node are electrically connected, and the third sub-circuit 1a is configured to switch the first black insertion input terminal CR2 under the signal control of the first control terminal BCK1. <k-2>The signal is written to the second node.

[0178] The fourth sub-circuit 1b is electrically connected to the second node, the second voltage terminal V2, the second control terminal BCK2 and the first pull-up node Q1. The fourth sub-circuit 1b is configured to write the signal of the second voltage terminal V2 into the first pull-up node Q1 under the control of the signal of the second node and the second control terminal BCK2.

[0179] 7 , the first scanning unit MD1 may further include a first black insertion reset circuit 19. The first black insertion reset circuit 19 is electrically connected to the first pull-up node Q1, the node M, the black insertion reset control terminal BTRST, and the first reset voltage terminal VGL1. The first black insertion reset circuit 19 is configured to write a signal from the first reset voltage terminal VGL1 into the first pull-up node Q1 under the control of signals from the node M and the black insertion reset control terminal BTRST.

[0180] Illustratively, the first black insertion reset circuit 19 includes a 44th transistor M44, a 45th transistor M45, and a 46th transistor M46. The 44th transistor M44, the 45th transistor M45, and the 46th transistor M46 are connected in series in sequence. The control electrode of the 44th transistor M44 is electrically connected to the node M, and the control electrodes of the 45th transistor M45 and the 46th transistor M46 are electrically connected to the black insertion reset control terminal BTRST.

[0181] The first scanning unit MD1 may further include a fifth reset circuit 21, which is electrically connected to the second control terminal BCK2, the node M, the first pull-down node QB1 and the first reset voltage terminal VGL1. The fifth reset circuit 21 is configured to write the signal of the first reset voltage terminal VGL1 into the first pull-down node QB1 under the control of the signal of the second control terminal BCK2 and the node M.

[0182] Exemplarily, the fifth reset circuit 21 includes a forty-second transistor M42 and a forty-third transistor M43, which are connected in series, a gate of the forty-second transistor M42 is electrically connected to the second control terminal BCK2, and a gate of the forty-third transistor M43 is electrically connected to the node M.

[0183] The first scanning unit MD1 may further include an anti-leakage circuit 25, which is electrically connected to the first voltage terminal GVDD1, the first pull-up node Q1, and the first black insertion input circuit 13, the first blanking circuit 24, the first black insertion reset circuit 19, the first reset circuit 20, and the first noise reduction circuit 18. The anti-leakage circuit is configured to write the signal of the first voltage terminal GVDD1 into the first black insertion input circuit 13, the first blanking circuit 24, the first black insertion reset circuit 19, the first reset circuit 20, and the first noise reduction circuit 18 under the control of the signal of the first pull-up node Q1.

[0184] Exemplarily, the anti-leakage circuit 25 includes an eleventh transistor M11, the control electrode of the eleventh transistor is electrically connected to the first pull-up node Q1, and the first electrode of the eleventh transistor is connected between the thirty-sixth transistor M36 and the thirty-seventh transistor M37, between the fifth transistor M5 and the sixth transistor M6, between the ninth transistor M9 and the tenth transistor M10, between the forty-fifth transistor M45 and the forty-sixth transistor M46, between the twelfth transistor M12 and the thirteenth transistor M13, and between the nineteenth transistor M19 and the twentieth transistor M20.

[0185] The multiple shift registers in the gate drive circuit may include multiple first shift registers and multiple second shift registers, and the first shift registers and the second shift registers are alternately arranged and cascaded. The connection relationship of each shift register is described below using the connection relationship of the connected cascaded first shift register and the second shift register as an example.

[0186] Figure 15 exemplarily shows a block diagram of a gate drive circuit. In Figure 15, A represents the first shift register, B represents the second shift register, A<1-8> refers to the first shift register electrically connected to the first row of sub-pixels PX to the eighth row of sub-pixels PX, B<9-16> refers to the second shift register electrically connected to the ninth row of sub-pixels PX to the sixteenth row of sub-pixels PX, and so on. The first output terminal and the second output terminal of the first shift register A and the second shift register B are both represented by G1. CD1-CD8 refer to black insertion clock signal lines with serial numbers between CD1 and CD8, for example, including the second black insertion clock signal line CD2, the third black insertion clock signal line CD3, the sixth black insertion clock signal line CD6, and the seventh black insertion clock signal line CD7. And so on, other reference numerals are not explained here.

[0187] For example, as shown in FIG15 , the gate drive circuit includes a first control signal line BC1, a second control signal line BC2, a third control signal line BC3, and a fourth control signal line BC4, and also includes a second black insertion clock signal line CD2, a third black insertion clock signal line CD3, a sixth black insertion clock signal line CD6, a seventh black insertion clock signal line CD7, a tenth black insertion clock signal line CD10, an eleventh black insertion clock signal line CD11, and a fifteenth black insertion clock signal line CD15, and also includes a first display clock signal line CE1, a second display clock signal line CE2, a third display clock signal line CE3, a fourth display clock signal line CE4, a fifth display clock signal line CE5, a sixth display clock signal line CE6, a seventh display clock signal line CE7, an eighth display clock signal line CE8, a ninth display clock signal line CE9, a tenth display clock signal line CE10, an eleventh display clock signal line CE11, a twelfth display clock signal line CE12, a thirteenth display clock signal line CE13, a fourteenth display clock signal line CE14, a fifteenth display clock signal line CE15, and a sixteenth display clock signal line CE16. A first control signal line BC1 is electrically connected to a first control terminal BCK1 of a first shift register, a second control signal line BC2 is electrically connected to a second control terminal BCK2 of the first shift register and a second voltage terminal V2, a third control signal line BC3 is electrically connected to the first control terminal BCK1 of a second shift register, and a fourth control signal line BC4 is electrically connected to a second control terminal BCK2 of the second shift register and a second voltage terminal V2. The second black insertion clock signal line CD2 is electrically connected to the second shift signal terminal CLKD2 of the first shift register, the third black insertion clock signal line CD3 is electrically connected to the first shift signal terminal CLKD3 of the first shift register, and the seventh black insertion clock signal line CD7 is electrically connected to the third shift signal terminal CLKD7 of the first shift register. The tenth black insertion clock signal line CD10 is electrically connected to the second shift signal terminal CLKD2 of the second shift register, the eleventh black insertion clock signal line CD11 is electrically connected to the first shift signal terminal CLKD3 of the second shift register, and the fifteenth black insertion clock signal line CD15 is electrically connected to the third shift signal terminal CLKD7 of the second shift register. The four first output circuits 15 of the first shift register are electrically connected to the first display clock signal line CE1, the second display clock signal line CE2, the third display clock signal line CE3, and the fourth display clock signal line CE4, respectively. The four first output circuits 15 of the second shift register are electrically connected to the fifth display clock signal line CE5, the sixth display clock signal line CE6, the seventh display clock signal line CE7, and the eighth display clock signal line CE8, respectively.

[0188] Figure 16 exemplarily shows a timing diagram of a gate driving circuit. As shown in Figure 16 , the black insertion driving phase of the gate driving circuit includes a first phase T1, a second phase T2, a third phase T3 and a fourth phase T4.

[0189] In the first phase T1, BSTV (first black input terminal CR2 <k-2>) and the first control terminal BCK1 are both high-level signals, and the black insertion input circuit 13 writes a high-level signal into the node M.

[0190] In the second phase T2, the second control terminal BCK2 is a high level signal, and the black insertion input circuit 13 writes the high level signal of the second voltage terminal V2 (the second control terminal BCK2) into the first pull-up node Q1 and the second pull-up node Q2 under the control of the signal at the node M.

[0191] In the third stage T3, the first output circuit 15 is turned on under the control of the high-level signal of the first pull-up node Q1, and the second output circuit 18 is turned on under the control of the high-level signal of the second pull-up node Q2. All first signal terminals (CLKE1, CLKE2, CLKE3, CLKE4, CLKE5, CLKE6, CLKE7, CLKE8) are high-level signals, so that both the first output terminal and the second output terminal output high-level signals, controlling the pixel driving circuit P1 to write the black data signal.

[0192] In the fourth stage T4, the first black insertion reset control terminal BTRST is a high-level signal. The first black insertion reset circuit 19 is turned on under the control of the high-level signal of the first black insertion reset control terminal BTRST, so that the signal of the first reset voltage terminal VGL1 is written into the first pull-up node Q1 and the second pull-up node Q2, thereby completing the resetting of the first pull-up node Q1 and the second pull-up node Q2.

[0193] FIG17 exemplarily shows a circuit diagram of a shift register. As shown in FIG17 , the first black insertion input circuit 13a and the first black insertion input terminal CR2 <k-2>, the first control terminal BCK1, the second control terminal BCK2, the second voltage terminal V2 and the first pull-up node Q1 are electrically connected, and the first black insertion input circuit 13a is configured to be at the first black insertion input terminal CR2 <k-2>Under the control of the signals of the first control terminal BCK1 and the second control terminal BCK2, the signal of the second voltage terminal V2 is written into the first pull-up node Q1.

[0194] The second black insertion input circuit 13 b is electrically connected to the second black insertion input terminal, the first control terminal BCK1, the second control terminal BCK2, the second voltage terminal V2, and the second pull-up node Q2. The second black insertion input circuit 13 b is configured to write the signal of the second voltage terminal V2 into the second pull-up node Q2 under the control of the signals of the second black insertion input terminal, the first control terminal BCK1, and the second control terminal BCK2.

[0195] The second scanning unit MD2 also includes a second black insertion shift circuit, which is electrically connected to the second pull-up node Q2, the fourth shift signal terminal and the fourth shift output terminal. The second black insertion shift circuit is configured to write the signal of the fourth shift signal terminal to the fourth shift output terminal under the control of the signal of the second pull-up node Q2.

[0196] The multiple shift registers in the gate drive circuit may include multiple first shift registers and multiple second shift registers, and the first shift registers and the second shift registers are alternately arranged and cascaded. The connection relationship of each shift register is described below using the connection relationship of the connected cascaded first shift register and the second shift register as an example.

[0197] The second shift output terminal CR2 of the first shift register <k>The first black insertion input terminal CR2 of the second shift register <k-2>The fourth shift output terminal of the first shift register is electrically connected to the second black insertion input terminal of the second shift register. This makes the number of scanning units crossed when the black insertion driving module is cascaded smaller and the wiring is simpler.

[0198] FIG18 exemplarily shows a circuit diagram of another shift register. As shown in FIG18 , the first display input circuit 11 may include a seventh transistor M7, an eighth transistor M8, a forty-seventh transistor M47, and a forty-eighth transistor M48. The seventh transistor M7 and the eighth transistor M8 are connected in series, and the control electrodes of the seventh transistor M7 and the eighth transistor M8 are connected to the first display input terminal CR. <k-1>The first electrode of the forty-eighth transistor M48 is electrically connected to the first pull-up node Q1, the second electrode of the seventh transistor M7 is electrically connected to the first voltage terminal GVDD1, and the first electrode of the eighth transistor M8 is electrically connected to the first pull-up node Q1. The forty-seventh transistor M47 and the forty-eighth transistor M48 are connected in series, and the control electrodes of the forty-seventh transistor M47 and the forty-eighth transistor M48 and the second electrode of the forty-seventh transistor are electrically connected to the voltage line GVDD3, a constant high-level signal is input to GVDD3, and the first electrode of the forty-eighth transistor M48 is connected between the seventh transistor M7 and the eighth transistor M8.

[0199] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims. < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k>

Claims

1. A shift register, characterized in that: It comprises a first scanning unit, wherein the first scanning unit comprises a first display input circuit, a first display shift circuit, a black insertion input circuit, a first black insertion shift circuit and a first output circuit; The first display input circuit is electrically connected to the first display input terminal, the first voltage terminal and the first pull-up node, and the first display input circuit is configured to write the signal of the first signal terminal into the first pull-up node under the control of the signal of the first display input terminal; The first display shift circuit is electrically connected to the first pull-up node, the first shift signal terminal and the first shift output terminal, and the first display shift circuit is configured to write the signal of the first shift signal terminal to the first shift output terminal under the control of the signal of the first pull-up node; The black insertion input circuit is electrically connected to the first black insertion input terminal, the first control terminal, the second control terminal, the second voltage terminal and the first pull-up node, and the black insertion input circuit is configured to write the signal of the second voltage terminal into the first pull-up node under the control of the signals of the first black insertion input terminal, the first control terminal and the second control terminal; The first black insertion shift circuit is electrically connected to the first pull-up node, the second shift signal terminal and the second shift output terminal, and the first black insertion shift circuit is configured to write the signal of the second shift signal terminal to the second shift output terminal under the control of the signal of the first pull-up node; The first output circuit is electrically connected to the first pull-up node, the first signal terminal and the first output terminal, and is configured to write the signal of the first signal terminal into the first output terminal under the control of the signal of the first pull-up node.

2. The shift register according to claim 1, wherein: The shift register further includes a second scanning unit, which includes a second display input circuit, a second display shift circuit and a second output circuit; The second display input circuit is electrically connected to the first shift output terminal, the first voltage terminal and the second pull-up node, and the second display input circuit is configured to write the signal of the first voltage terminal into the second pull-up node under the control of the signal of the first shift output terminal; The second display shift circuit is electrically connected to the second pull-up node, the third shift signal terminal and the third shift output terminal, and the second display shift circuit is configured to write the signal of the third shift signal terminal to the third shift output terminal under the control of the signal of the second pull-up node; The second output circuit is electrically connected to the second pull-up node, the second signal terminal and the second output terminal. The second output circuit is configured to write the signal of the second signal terminal into the second output terminal under the control of the signal of the second pull-up node; The black insertion input circuit is electrically connected to the first pull-up node and the second pull-up node at the same time, and the black insertion input circuit is further configured to write a signal to the second pull-up node.

3. The shift register according to claim 2, wherein: The black insertion input circuit includes a first black insertion input circuit and a second black insertion input circuit; the first black insertion input circuit is electrically connected to the first pull-up node, and the first black insertion input circuit is configured to write a signal at the first node; the second black insertion input circuit is electrically connected to the second pull-up node, and the second black insertion input circuit is configured to write a signal at the second pull-up node.

4. The shift register according to claim 3, wherein: At the same time, the signal written by the first black insertion input circuit at the first pull-up node is the same as the signal written by the second black insertion input circuit at the second pull-up node.

5. The shift register according to claim 4, wherein: The first black insertion input circuit is electrically connected to the first black insertion input terminal, the first control terminal, the second control terminal, the second voltage terminal and the first pull-up node, and the first black insertion input circuit is configured to write the signal of the second voltage terminal into the first pull-up node under the control of the signals of the first black insertion input terminal, the first control terminal and the second control terminal; The second black insertion input circuit is electrically connected to the first black insertion input terminal, the first control terminal, the second control terminal, the second voltage terminal and the second pull-up node, and the second black insertion input circuit is configured to write the signal of the second voltage terminal into the second pull-up node under the control of the signals of the first black insertion input terminal, the first control terminal and the second control terminal.

6. The shift register according to claim 4, wherein: The first black insertion input circuit includes a first subcircuit and a second subcircuit; The first sub-circuit is electrically connected to the first black insertion input terminal, the first control terminal, the second voltage terminal and a first node, and the first sub-circuit is configured to write a signal of the second voltage terminal into the first node under the control of signals of the first black insertion input terminal and the first control terminal; The second sub-circuit is electrically connected to the second control terminal, the first node and the first pull-up node, and the second sub-circuit is configured to write the signal of the first node into the first pull-up node under the control of the signal of the second control terminal; The second black insertion input circuit is connected to the first node, the second control terminal and the second The second black insertion input circuit is configured to write the signal of the first node into the second pull-up node under the control of the signal of the second control end.

7. The shift register according to claim 4, wherein: The second black insertion input circuit includes a first subcircuit and a second subcircuit; The first sub-circuit is electrically connected to the first black insertion input terminal, the first control terminal, the second voltage terminal and a second node, and the first sub-circuit is configured to write a signal of the second voltage terminal into the second node under the control of a signal of the first black insertion input terminal and the first control terminal; The second sub-circuit is electrically connected to the second control terminal, the first node and the second pull-up node, and the second sub-circuit is configured to write the signal of the first node into the second pull-up node under the control of the signal of the second control terminal; The first black insertion input circuit is electrically connected to the first node, the second control terminal and the first pull-up node, and the second black insertion input circuit is configured to write the signal of the first node into the first pull-up node under the control of the signal of the second control terminal.

8. The shift register according to claim 3, wherein: The first black insertion input circuit is electrically connected to the first black insertion input terminal, the first control terminal, the second control terminal, the second voltage terminal and the first pull-up node, and the first black insertion input circuit is configured to write the signal of the second voltage terminal into the first pull-up node under the control of the signals of the first black insertion input terminal, the first control terminal and the second control terminal; The second black insertion input circuit is electrically connected to the second black insertion input terminal, the first control terminal, the second control terminal, the second voltage terminal and the second pull-up node, and the second black insertion input circuit is configured to write the signal of the second voltage terminal into the second pull-up node under the control of the signal of the second black insertion input terminal, the first control terminal and the second control terminal; The second scanning unit also includes a second black insertion shift circuit, which is electrically connected to the second pull-up node, the fourth shift signal terminal and the fourth shift output terminal, and the second black insertion shift circuit is configured to write the signal of the fourth shift signal terminal to the fourth shift output terminal under the control of the signal of the second pull-up node.

9. The shift register according to claim 4, wherein: The second voltage terminal is electrically connected to the second control terminal, or the second voltage terminal is disconnected from the second control terminal.

10. The shift register according to claim 6, wherein: The first sub-circuit includes a third sub-circuit and a fourth sub-circuit; The third subcircuit is electrically connected to the first black insertion input terminal, the first control terminal, and the second node, and the third subcircuit is configured to write the signal of the first black insertion input terminal into the second node under the control of the signal of the first control terminal; The fourth sub-circuit is electrically connected to the second node, the second voltage terminal, the second control terminal and the first pull-up node, and the fourth sub-circuit is configured to write the signal of the second voltage terminal into the first pull-up node under the control of the signal of the second node and the second control terminal.

11. The shift register according to claim 10, wherein: The first scanning unit further includes a first black insertion reset circuit, which is electrically connected to the first pull-up node, the second node, the black insertion reset control terminal and the first reset voltage terminal, and the first black insertion reset circuit is configured to write the signal of the first reset voltage terminal into the pull-up node under the control of the signal of the second node and the black insertion reset control terminal.

12. The shift register according to claim 10, wherein: The first scanning unit further includes a first pull-down circuit and a first noise reduction circuit; The first pull-down circuit is electrically connected to the first pull-up node, the first reset voltage terminal and the first pull-down node, and the first pull-down circuit is configured to write the signal of the first reset voltage terminal into the first pull-down node under the control of the signal of the first pull-up node; The first noise reduction circuit is electrically connected to the first pull-down node, the first reset voltage terminal and the second shift output terminal, and the first noise reduction circuit is configured to write the signal of the first reset voltage terminal to the second shift output terminal under the control of the signal of the first pull-down node.

13. The shift register according to claim 12, wherein: The shift register also includes a fifth reset circuit, which is electrically connected to the second control terminal, the second node, the first reset voltage terminal and the first pull-down node, and the fifth reset circuit is configured to write the signal of the first reset voltage terminal into the first pull-down node under the control of the signal of the second node and the second control terminal.

14. A gate drive circuit, characterized in that: The invention comprises a plurality of shift registers according to any one of claims 1 to 13, wherein the plurality of shift registers are cascaded.

15. The gate driving circuit according to claim 14, wherein: The multiple shift registers include a cascaded first shift register and a second shift register, the shift registers include a first display shift circuit, a second display shift circuit and a first black insertion shift circuit, the second shift output terminal of the first shift register is electrically connected to the first black insertion input terminal of the second shift register, and the third shift output terminal of the first shift register is electrically connected to the first display input terminal of the second shift register.

16. The gate driving circuit according to claim 14, wherein: The multiple shift registers include a cascaded first shift register and a second shift register, and when the shift registers include a first display shift circuit, a second display shift circuit, a first black insertion shift circuit, and a second black insertion shift circuit, the third shift output terminal of the first shift register is electrically connected to the first display input terminal of the second shift register, the second shift output terminal of the first shift register is electrically connected to the first black insertion input terminal of the second shift register, and the fourth shift output terminal of the first shift register is electrically connected to the second black insertion input terminal of the second shift register.

17. The gate drive circuit according to any one of claims 14 to 16, wherein: The gate drive circuit includes multiple gate lines, the first scanning unit includes multiple first output circuits, and the first output ends of the multiple first output circuits are electrically connected to different gate lines respectively; and / or the second scanning unit includes multiple second output circuits, and the second output ends of the multiple second output circuits are electrically connected to different gate lines respectively, and the first output end and the second output end are electrically connected to different gate lines.

18. The gate driving circuit according to claim 17, wherein: The first scanning unit includes four first output circuits, and the second scanning unit includes four second output circuits.

19. A display panel, characterized in that: Comprising the gate drive circuit as claimed in any one of claims 14 to 18.

20. A display device, characterized in that: Comprising the display panel as claimed in claim 19.

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