Signal processing apparatus, and communication apparatus for vehicle comprising same

Abstract

A signal processing apparatus according to an embodiment of the present disclosure comprises a storage device and a processor that: executes a peripheral component interconnect express driver; executes a host channel adapter (HCA) driver on the peripheral component interconnect express driver; and executes a remote direct memory access (RMDA) driver on the host channel adapter driver. Accordingly, it is possible to provide high-performance scalable data sharing.

Description

Signal processing device and vehicle communication device having the same

[0001] The present disclosure relates to a signal processing device and a vehicle communication device having the same, and more particularly, to a signal processing device capable of providing high-performance, scalable data sharing and a vehicle communication device having the same.

[0002] A vehicle is a device that allows the user to move in the desired direction. A representative example is an automobile.

[0003] Meanwhile, for the convenience of vehicle users, a vehicle signal processing device is installed inside the vehicle.

[0004] The signal processing device inside the vehicle receives and processes sensor data from various sensor devices inside the vehicle.

[0005] Meanwhile, the types and number of sensors installed in vehicles are exploding due to advanced driver assistance systems (ADAS) and autonomous driving, and the amount of data generated from vehicles is also exploding.

[0006] Meanwhile, to store this data and process it in conjunction with cloud servers, etc., high-performance, high-capacity storage devices are required.

[0007] Meanwhile, in a situation where multiple processors or multiple signal processing devices are used in a vehicle, if each processor or each signal processing device independently operates memory and storage devices, data sharing between each processor or each signal processing device becomes difficult, and there is a disadvantage in that the flexibility and expandability of the system configuration are reduced.

[0008] Furthermore, when using optical cable-based data communication between each signal processing device, problems such as space constraints or design constraints of each signal processing device arise due to refractive index constraints of the optical cable.

[0009] The problem that the present disclosure seeks to solve is to provide a flexible, high-bandwidth data communication method between computing nodes in a high-performance vehicle signal processing device using a plurality of computing nodes.

[0010] Another challenge that the present disclosure seeks to address is to construct an efficient and scalable data storage device between nodes based on a high-bandwidth data communication method between computing nodes, and to provide a function capable of responding to safety requirements required as a vehicle device.

[0011] Another challenge that the present disclosure seeks to address is to provide a communication method that is expandable between controllers and has high bandwidth when designing a vehicle electrical system by extending the above two functions to other vehicle controllers.

[0012] Another problem that the present disclosure seeks to solve is to provide a signal processing device capable of providing high-performance, scalable data sharing and a vehicle communication device having the same.

[0013] Another problem that the present disclosure seeks to solve is to provide a signal processing device capable of improving efficient management and expandability of a data storage device and a vehicle communication device having the same.

[0014] A signal processing device according to one embodiment of the present disclosure includes a storage device, a processor that executes a Peripheral Component Interconnect Express (PCI) driver, executes a Host Channel Adapter (HCA) driver on the PCI driver, and executes a Remote Direct Memory Access (RMDA) driver on the Host Channel Adapter driver.

[0015] Meanwhile, the processor can execute a non-volatile memory express driver on top of the remote direct memory access driver.

[0016] Meanwhile, the processor can exchange data with a storage device through a non-volatile memory express driver.

[0017] Meanwhile, a signal processing device according to one embodiment of the present disclosure further includes an external component high-speed connection switch that receives data input through an external flexible cable, and the processor can control the storage device to store the data.

[0018] Meanwhile, a signal processing device according to one embodiment of the present disclosure may further include a second processor that exchanges data based on a high-speed connection between a processor or a storage device and an external component.

[0019] Meanwhile, the processor operates as a host, the second processor operates as a client, and the processor can control the storage device according to a request to write data to or read data from the storage device from the second processor.

[0020] Meanwhile, the second processor may execute an external component high-speed link root complex (RC) for access to a storage device, and execute a second external component high-speed link driver on the external component high-speed link root complex.

[0021] Meanwhile, the second processor may execute a second host channel adapter driver on the second external component high-speed connection driver and a second remote direct memory access driver on the second host channel adapter driver.

[0022] Meanwhile, the processor may execute an external component high-speed connection endpoint (EP) for access to the storage device of the second processor, and execute a host channel adapter driver on the external component high-speed connection endpoint.

[0023] Meanwhile, the processor can further execute a Non-Transparent Bridge (NTB) transport between the external component high-speed link driver and the host channel adapter driver.

[0024] Meanwhile, the opaque bridge transport can create and manage a Que-Pair list.

[0025] Meanwhile, the opaque bridge transport can be processed by distinguishing between the opaque bridge-based application programming interface (API) of the host channel adapter channel and the opaque bridge NetDev-based application programming interface.

[0026] Meanwhile, the processor can divide the storage device into multiple areas and control each area to be mapped to each queue pair.

[0027] Meanwhile, the processor divides the storage device into multiple areas, and maps them to each of the multiple processors or each of the multiple signal processing units, and may exchange or replace some of the multiple areas based on power-off or restart of some of the processors or some of the signal processing units.

[0028] Meanwhile, the processor can perform authentication based on a security key in response to an authentication request from another processor or another signal processing device, and control data exchange with the processor or signal processing device that has completed authentication.

[0029] Meanwhile, the processor can control to encrypt or decrypt data in a secure area within the storage device.

[0030] Meanwhile, a signal processing device according to one embodiment of the present disclosure further includes a second processor, wherein the processor controls data input through an external flexible cable to be stored in a first area of ​​the storage device, and the second processor can control data from the first area of ​​the storage device to be read and a namespace of the first area of ​​the storage device to be changed.

[0031] Meanwhile, a signal processing device according to another embodiment of the present disclosure includes a storage device, a processor that controls to store data input through an external flexible cable in a first area of ​​the storage device, and a second processor that controls to read data from the first area of ​​the storage device and change a namespace of the first area of ​​the storage device.

[0032] A vehicle communication device according to one embodiment of the present disclosure includes a signal processing device and a second signal processing device that exchanges data with the signal processing device, wherein the signal processing device includes a storage device and a processor that executes a Peripheral Component Interconnect Express (PCI) driver, executes a Host Channel Adapter (HCA) driver on the PCI driver, and executes a Remote Direct Memory Access (RMDA) driver on the PCI driver.

[0033] Meanwhile, a vehicle communication device according to one embodiment of the present disclosure may further include a retimer that receives data from a second signal processing device and transmits it to a signal processing device.

[0034] A signal processing device according to one embodiment of the present disclosure includes a storage device, a processor that executes a Peripheral Component Interconnect Express (PCI Express) driver, executes a Host Channel Adapter (HCA) driver on the PCI Express driver, and executes a Remote Direct Memory Access (RMDA) driver on the PCI Express driver. Accordingly, high-bandwidth, flexible data communication between computing nodes can be provided. In addition, high-performance, scalable data sharing can be provided.

[0035] Meanwhile, the processor can execute a non-volatile memory express driver on top of the remote direct memory access driver, thereby providing high-performance, scalable data sharing.

[0036] Meanwhile, the processor can exchange data with storage devices via the non-volatile memory express driver, providing high-performance, scalable data sharing.

[0037] Meanwhile, a signal processing device according to one embodiment of the present disclosure further comprises an external component high-speed connection switch that receives data input via an external flexible cable, and the processor can control the storage device to store the data. Accordingly, while performing data communication based on the flexible cable, it is possible to provide high-performance, scalable data sharing.

[0038] Meanwhile, a signal processing device according to one embodiment of the present disclosure may further include a second processor that exchanges data based on a high-speed connection between the processor or storage device and an external component. This enables high-performance, scalable data sharing.

[0039] Meanwhile, the processor operates as a host, and the second processor operates as a client. The processor can control the storage device in response to data write or read requests from the second processor. This provides high-performance, scalable data sharing.

[0040] Meanwhile, the second processor can execute an external component high-speed connection root complex (RC) for access to the storage device, and execute a second external component high-speed connection driver on the external component high-speed connection root complex. This enables high-performance, scalable data sharing while performing data communication based on a flexible cable.

[0041] Meanwhile, the second processor can execute a second host channel adapter driver on the second external component high-speed connection driver and a second remote direct memory access driver on the second host channel adapter driver. This provides high-performance, scalable data sharing.

[0042] Meanwhile, the processor may execute an external component high-speed connection endpoint (EP) for access to the storage device of the second processor, and execute a host channel adapter driver on the EP. This provides high-performance, scalable data sharing.

[0043] Meanwhile, the processor can further implement a Non-Transparent Bridge (NTB) transport between the external component high-speed connection driver and the host channel adapter driver, thereby providing high-performance, scalable data sharing.

[0044] Meanwhile, the opaque bridge transport can create and manage queue pair lists, providing high-performance, scalable data sharing.

[0045] Meanwhile, the opaque bridge transport can handle the application programming interface (API) based on the opaque bridge of the host channel adapter channel separately from the opaque bridge NetDev-based application programming interface. This enables high-performance, scalable data sharing.

[0046] Meanwhile, the processor can divide the storage device into multiple areas and control the mapping of each area to each queue pair. This improves the efficient management and scalability of the storage device's storage space.

[0047] Meanwhile, the processor divides the storage device into multiple areas, mapping them to each processor or each signal processing unit, and may exchange or replace some of the areas based on the power off or restart of some processors or some signal processing units. This improves the efficient management and expandability of the storage device's storage space.

[0048] Meanwhile, the processor can perform authentication based on a security key in response to an authentication request from another processor or signal processing device, and control data exchange with the authenticated processor or signal processing device. This enhances the security of the storage device.

[0049] Meanwhile, the processor can control the encryption or decryption of data in the secure area within the storage device, thereby enhancing the security of the storage device.

[0050] Meanwhile, a signal processing device according to one embodiment of the present disclosure further includes a second processor, wherein the processor controls data input via an external flexible cable to be stored in a first area of ​​the storage device, and the second processor controls data reading from the first area of ​​the storage device and changing the namespace of the first area of ​​the storage device. Accordingly, while performing data communication based on a flexible cable, it is possible to provide high-performance, scalable data sharing.

[0051] Meanwhile, a signal processing device according to another embodiment of the present disclosure includes a storage device, a processor that controls data input via an external flexible cable to be stored in a first region of the storage device, and a second processor that controls data reading from the first region of the storage device and changing the namespace of the first region of the storage device. Accordingly, while performing data communication based on the flexible cable, it is possible to provide high-bandwidth, flexible data communication between computing nodes. In addition, it is possible to provide high-performance, scalable data sharing.

[0052] A vehicle communication device according to one embodiment of the present disclosure includes a signal processing device and a second signal processing device that exchanges data with the signal processing device, wherein the signal processing device includes a storage device and a processor that executes a Peripheral Component Interconnect Express (PCI Express) driver, executes a Host Channel Adapter (HCA) driver on the PCI Express driver, and executes a Remote Direct Memory Access (RMDA) driver on the Host Channel Adapter driver. Accordingly, high-bandwidth, flexible data communication between computing nodes can be provided. In addition, high-performance, scalable data sharing can be provided. Furthermore, a function capable of responding to safety requirements required as a vehicle device can be provided.

[0053] Meanwhile, a vehicle communication device according to one embodiment of the present disclosure may further include a retimer that receives data from a second signal processing device and transmits it to the signal processing device. Accordingly, high-performance, scalable data sharing can be provided.

[0054] Figure 1 is a drawing showing an example of the exterior and interior of a vehicle.

[0055] Figures 2a to 2c are drawings illustrating various architectures of a vehicle communication gateway.

[0056] Figure 3a is a drawing showing an example of the arrangement of a vehicle display device inside a vehicle.

[0057] Figure 3b is a drawing showing another example of the arrangement of a vehicle display device inside a vehicle.

[0058] Fig. 4 is an example of an internal block diagram of the vehicle display device of Fig. 3b.

[0059] Figures 5a to 5d are drawings showing various examples of vehicle communication devices.

[0060] FIG. 6 is an example of a block diagram of a vehicle communication device according to an embodiment of the present disclosure.

[0061] Figures 7a to 7c are drawings referenced in the operation description of Figure 6.

[0062] Figure 8 is an example of an internal block diagram of a communication device related to the present invention.

[0063] FIG. 9 is an example of an internal block diagram of a signal processing device according to an embodiment of the present disclosure.

[0064] FIG. 10 is an example of an internal block diagram of a signal processing device according to another embodiment of the present disclosure.

[0065] FIG. 11 is an example of an internal block diagram of a vehicle communication device according to an embodiment of the present disclosure.

[0066] Figures 12a to 14 are drawings referenced in the operation descriptions of Figures 9 to 11.

[0067] Hereinafter, the present disclosure will be described in more detail with reference to the drawings.

[0068] The suffixes "module" and "part" used in the following description are given solely for the convenience of writing this specification and do not impart any particularly significant meaning or role to the components themselves. Therefore, the terms "module" and "part" may be used interchangeably.

[0069] Figure 1 is a drawing showing an example of the exterior and interior of a vehicle.

[0070] Referring to the drawing, the vehicle (200) is operated by a plurality of wheels (103FR, 103FL, 103RL, etc.) that rotate by a power source and a steering wheel (150) for controlling the direction of travel of the vehicle (200).

[0071] Meanwhile, the vehicle (200) may further be equipped with a camera (195) for capturing images of the front of the vehicle.

[0072] Meanwhile, the vehicle (200) may be equipped with multiple displays (180a, 180b) for displaying images, information, etc. inside.

[0073] In Fig. 1, a cluster display (180a) and an AVN (Audio Video Navigation) display (180b) are exemplified as multiple displays (180a, 180b). In addition, a HUD (Head Up Display) is also possible.

[0074] Meanwhile, the AVN (Audio Video Navigation) display (180b) may also be named a center information display.

[0075] Meanwhile, the vehicle (200) described in this specification may be a concept that includes all of a vehicle equipped with an engine as a power source, a hybrid vehicle equipped with an engine and an electric motor as a power source, and an electric vehicle equipped with an electric motor as a power source.

[0076] Figures 2a to 2c are drawings illustrating various architectures of a vehicle communication gateway.

[0077] First, FIG. 2a is a drawing illustrating the first architecture of a vehicle communication gateway.

[0078] Referring to the drawing, the first architecture (300a) can correspond to a zone-based architecture.

[0079] Accordingly, sensor devices and processors inside the vehicle may be placed in each of the plurality of zones (Z1 to Z4), and a signal processing device (170a) including a vehicle communication gateway (GWDa) may be placed in the central area of ​​the plurality of zones (Z1 to Z4).

[0080] Meanwhile, the signal processing device (170a) may further include, in addition to the vehicle communication gateway (GWDa), an autonomous driving control module (ACC), a cockpit control module (CPG), etc.

[0081] The vehicle communication gateway (GWDa) within the signal processing device (170a) may be an HPC (High Performance Computing) gateway.

[0082] That is, the signal processing device (170a) of FIG. 2a is an integrated HPC and can exchange data with an external communication module (not shown) or a processor (not shown) within a plurality of zones (Z1 to Z4).

[0083] FIG. 2b is a diagram illustrating a second architecture of a vehicle communication gateway.

[0084] Referring to the drawing, the second architecture (300b) can correspond to a domain-integrated architecture.

[0085] Accordingly, a body chassis control module (BSG), a power control module (PTG), an ADAS control module (ADG), and a cockpit control module (CPG) are connected in parallel to the gateway (GWDb), and multiple processors (ECUs) can be electrically connected to each module (BSG, PTG, ADG, CPG).

[0086] Meanwhile, each processor (ECU) can be integrated and connected to a gateway (GWDb).

[0087] Meanwhile, the signal processing device (170) including the gateway (GWDb) of FIG. 2b operates as a domain-integrated signal processing device.

[0088] Figure 2c is a diagram illustrating the third architecture of a vehicle communication gateway.

[0089] Referring to the drawing, the third architecture (300c) can correspond to a distributed architecture.

[0090] Accordingly, a body chassis control module (BSG), a power control module (PTG), an ADAS control module (ADG), and a cockpit control module (CPG) are connected in parallel to the gateway (GWDc), and in particular, multiple processors (ECUs) within each control module can be connected in parallel to the gateway (GWDb).

[0091] Compared to Fig. 2b, the third architecture differs in that each processor (ECU) is directly connected to the gateway (GWDb) without being connected to other modules.

[0092] Meanwhile, the signal processing device (170) including the gateway (GWDc) of FIG. 2c operates as a distributed signal processing device.

[0093] Figure 3a is a drawing showing an example of the arrangement of a vehicle display device inside a vehicle.

[0094] Referring to the drawing, the interior of the vehicle may be equipped with a cluster display (180a), an AVN (Audio Video Navigation) display (180b), a rear seat entertainment display (180c, 180d), a room mirror display (not shown), etc.

[0095] Figure 3b is a drawing showing another example of the arrangement of a vehicle display device inside a vehicle.

[0096] A vehicle display device (100) according to an embodiment of the present disclosure may include a plurality of displays (180a to 180b), and a signal processing device (170) that performs signal processing for displaying images, information, etc. on the plurality of displays (180a to 180b).

[0097] Among the plurality of displays (180a to 180b), the first display (180a) may be a cluster display (180a) for displaying driving status, operation information, etc., and the second display (180b) may be an AVN (Audio Video Navigation) display (180b) for displaying vehicle driving information, a navigation map, various entertainment information, or images.

[0098] The signal processing device (170) has a processor (175) therein and can execute a first virtual machine to a third virtual machine (not shown) on a hypervisor (not shown) within the processor (175).

[0099] A second virtual machine (not shown) can operate for the first display (180a), and a third virtual machine (not shown) can operate for the second display (180b).

[0100] Meanwhile, the first virtual machine (not shown) within the processor (175) can control the shared memory (508) based on the hypervisor (505) to be set for the same data transmission to the second virtual machine (not shown) and the third virtual machine (not shown). Accordingly, the same information or the same image can be displayed in synchronization on the first display (180a) and the second display (180b) within the vehicle.

[0101] Meanwhile, the first virtual machine (not shown) within the processor (175) shares at least a portion of data with the second virtual machine (not shown) and the third virtual machine (not shown) for data sharing processing. Accordingly, data can be shared and processed among multiple virtual machines for multiple displays within the vehicle.

[0102] Meanwhile, a first virtual machine (not shown) within a processor (175) may receive and process vehicle wheel speed sensor data, and transmit the processed wheel speed sensor data to at least one of a second virtual machine (not shown) or a third virtual machine (not shown). Accordingly, the vehicle wheel speed sensor data may be shared with at least one virtual machine.

[0103] Meanwhile, the vehicle display device (100) according to the embodiment of the present disclosure may further include a rear seat entertainment display (180c) for displaying driving status information, simple navigation information, various entertainment information, or images.

[0104] The signal processing device (170) can control the RSE display (180c) by executing a fourth virtual machine (not shown) in addition to the first virtual machine to the third virtual machine (not shown) on a hypervisor (not shown) within the processor (175).

[0105] Accordingly, it is possible to control various displays (180a to 180c) using one signal processing device (170).

[0106] Meanwhile, some of the multiple displays (180a~180c) may operate under Linux OS, while others may operate under Web OS.

[0107] The signal processing device (170) according to the embodiment of the present disclosure can control the same information or the same image to be displayed in synchronization on displays (180a to 180c) operating under various operating systems (OS).

[0108] Meanwhile, in FIG. 3b, a vehicle speed indicator (212a) and a vehicle interior temperature indicator (213a) are displayed on a first display (180a), a home screen (222) including a plurality of applications and a vehicle speed indicator (212b) and a vehicle interior temperature indicator (213b) are displayed on a second display (180b), and a second home screen (222b) including a plurality of applications and a vehicle interior temperature indicator (213c) are displayed on a third display (180c).

[0109] Fig. 4 is an example of an internal block diagram of the vehicle display device of Fig. 3b.

[0110] Referring to the drawings, a vehicle display device (100) according to an embodiment of the present disclosure may include an input unit (110), a communication unit (120) for communication with an external device, a plurality of communication modules (EMa to EMd) for internal communication, a memory (140), a signal processing unit (170), a plurality of displays (180a to 180c), an audio output unit (185), and a power supply unit (190).

[0111] A plurality of communication modules (EMa to EMd) can be arranged, for example, in a plurality of zones (Z1 to Z4) of FIG. 2a, respectively.

[0112] Meanwhile, the signal processing device (170) may have a communication switch (736b) for data communication with each communication module (EM1 to EM4) inside.

[0113] Each communication module (EM1 to EM4) can perform data communication with multiple sensor devices (SN) or ECUs (770) or area signal processing devices (170Z).

[0114] Meanwhile, the plurality of sensor devices (SN) may include a camera (195), a lidar (196), a radar (197), or a position sensor (198).

[0115] The input unit (110) may be equipped with physical buttons, pads, etc. for button input, touch input, etc.

[0116] Meanwhile, the input unit (110) may be equipped with a microphone (not shown) for user voice input.

[0117] The communication unit (120) can exchange data wirelessly with a mobile terminal (800) or a server (900).

[0118] In particular, the communication unit (120) can wirelessly exchange data with the vehicle driver's mobile terminal. Various data communication methods are possible, such as Bluetooth, WiFi, WiFi Direct, and APiX.

[0119] The communication unit (120) can receive weather information, road traffic information, for example, TPEG (Transport Protocol Expert Group) information, from a mobile terminal (800) or a server (900). To this end, the communication unit (120) may be equipped with a mobile communication module (not shown).

[0120] A plurality of communication modules (EM1 to EM4) can receive sensor data, etc. from an ECU (770), a sensor device (SN), or an area signal processing device (170Z), and transmit the received sensor data to the signal processing device (170).

[0121] Here, the sensor data may include at least one of vehicle direction data, vehicle location data (GPS data), vehicle angle data, vehicle speed data, vehicle acceleration data, vehicle inclination data, vehicle forward / backward data, battery data, fuel data, tire data, vehicle lamp data, vehicle interior temperature data, and vehicle interior humidity data.

[0122] Such sensor data can be obtained from a heading sensor, a yaw sensor, a gyro sensor, a position module, a vehicle forward / backward sensor, a wheel sensor, a vehicle speed sensor, a body tilt detection sensor, a battery sensor, a fuel sensor, a tire sensor, a steering sensor by steering wheel rotation, a vehicle interior temperature sensor, a vehicle interior humidity sensor, etc.

[0123] Meanwhile, the position module may include a GPS module or a position sensor (198) for receiving GPS information.

[0124] Meanwhile, at least one of the plurality of communication modules (EM1 to EM4) can transmit location information data sensed by a GPS module or location sensor (198) to a signal processing device (170).

[0125] Meanwhile, at least one of the plurality of communication modules (EM1 to EM4) can receive vehicle front image data, vehicle side image data, vehicle rear image data, vehicle surrounding obstacle distance information, etc. from a camera (195), lidar (196), radar (197), etc., and transmit the received information to a signal processing device (170).

[0126] The memory (140) can store various data for the overall operation of the vehicle display device (100), such as a program for processing or controlling the signal processing device (170).

[0127] For example, the memory (140) may store data regarding a hypervisor, a first virtual machine, a third virtual machine, or the like, for execution within the processor (175).

[0128] The audio output unit (185) converts an electric signal from the signal processing device (170) into an audio signal and outputs it. For this purpose, a speaker or the like may be provided.

[0129] The power supply unit (190) can supply power required for the operation of each component under the control of the signal processing device (170). In particular, the power supply unit (190) can receive power from a battery or the like inside the vehicle.

[0130] The signal processing device (170) controls the overall operation of each unit within the vehicle display device (100).

[0131] For example, the signal processing device (170) may include a processor (175) that performs signal processing for a vehicle display (180a, 180b).

[0132] The processor (175) can execute a first virtual machine to a third virtual machine (not shown) on a hypervisor (not shown) within the processor (175).

[0133] Among the first virtual machine to the third virtual machine (not shown), the first virtual machine (not shown) may be named a server virtual machine (Server Virtual Maschine), and the second virtual machine to the third virtual machine (not shown) may be named a guest virtual machine (Guest Virtual Maschine).

[0134] For example, a first virtual machine (not shown) within a processor (175) may receive, process, or output sensor data from a plurality of sensor devices, such as vehicle sensor data, location information data, camera image data, audio data, or touch input data.

[0135] In this way, by performing most of the data processing in the first virtual machine (not shown), data sharing in a 1:N manner becomes possible.

[0136] As another example, a first virtual machine (not shown) can directly receive and process CAN data, Ethernet data, audio data, radio data, USB data, and wireless communication data for a second virtual machine or a third virtual machine (not shown).

[0137] And, the first virtual machine (not shown) can transmit processed data to the second virtual machine or the third virtual machine (not shown).

[0138] Accordingly, among the first virtual machine to the third virtual machine (not shown), only the first virtual machine (not shown) receives sensor data, communication data, or external input data from multiple sensor devices and performs signal processing, thereby reducing the signal processing burden on other virtual machines, enabling 1:N data communication, and enabling synchronization when sharing data.

[0139] Meanwhile, the first virtual machine (not shown) can control the second virtual machine (not shown) and the third virtual machine (not shown) to share the same data by writing data to the shared memory (508).

[0140] For example, a first virtual machine (not shown) can record vehicle sensor data, the location information data, the camera image data, or the touch input data in shared memory (508) and control the same data to be shared with a second virtual machine (not shown) and a third virtual machine (not shown). Accordingly, data sharing in a 1:N manner becomes possible.

[0141] Ultimately, by performing most of the data processing on the first virtual machine (not shown), data sharing in a 1:N manner becomes possible.

[0142] Meanwhile, the first virtual machine (not shown) within the processor (175) can control the shared memory (508) based on the hypervisor (505) to be set for the same data transmission to the second virtual machine (not shown) and the third virtual machine (not shown).

[0143] Meanwhile, the signal processing device (170) can process various signals such as audio signals, video signals, and data signals. To this end, the signal processing device (170) can be implemented in the form of a system on chip (SOC).

[0144] Meanwhile, the signal processing device (170) in the display device (100) of FIG. 4 may be the same as the signal processing device (170, 170a1, 170a2) of the vehicle communication device of FIG. 5a or lower.

[0145] Figures 5a to 5d are drawings showing various examples of vehicle communication devices.

[0146] FIG. 5A illustrates an example of a vehicle communication device according to an embodiment of the present disclosure.

[0147] Referring to the drawing, a vehicle communication device (800a) according to an embodiment of the present disclosure includes a signal processing device (170a1, 170a2) and a plurality of area signal processing devices (170Z1 to 170Z4).

[0148] Meanwhile, in the drawing, two signal processing devices (170a1, 170a2) are exemplified, but this is for backup purposes, etc., and one is also possible.

[0149] Meanwhile, the signal processing device (170a1, 170a2) may also be named an HPC (High Performance Computing) signal processing device.

[0150] Multiple area signal processing devices (170Z1 to 170Z4) are arranged in each area (Z1 to Z4) and can transmit sensor data to signal processing devices (170a1, 170a2).

[0151] The signal processing device (170a1, 170a2) receives data via a wire from multiple area signal processing devices (170Z1 to 170Z4) or a communication device (120).

[0152] In the drawing, data is exchanged based on wired communication between a signal processing device (170a1, 170a2) and multiple area signal processing devices (170Z1 to 170Z4), and the signal processing device (170a1, 170a2) and the server (400) exchange data based on wireless communication. However, data may be exchanged based on wireless communication between a communication device (120) and a server (400), and the signal processing device (170a1, 170a2) and the communication device (120) may exchange data based on wired communication.

[0153] Meanwhile, data received by the signal processing device (170a1, 170a2) may include camera data or sensor data.

[0154] For example, sensor data within a vehicle may include at least one of vehicle wheel speed data, vehicle direction data, vehicle location data (GPS data), vehicle angle data, vehicle speed data, vehicle acceleration data, vehicle inclination data, vehicle forward / backward data, battery data, fuel data, tire data, vehicle lamp data, vehicle interior temperature data, vehicle interior humidity data, vehicle exterior radar data, and vehicle exterior lidar data.

[0155] Meanwhile, camera data may include vehicle exterior camera data and vehicle interior camera data.

[0156] Meanwhile, the signal processing device (170a1, 170a2) can execute multiple virtual machines (820, 830, 840) based on safety standards.

[0157] In the drawing, it is illustrated that a processor (175) within a signal processing device (170a) executes a hypervisor (505) and, on the hypervisor (505), executes first to third virtual machines (820 to 840) according to an automotive safety integrity level (Automotive SIL; ASIL).

[0158] The first virtual machine (820) may be a virtual machine corresponding to Quality Management (QM), which is the lowest safety level in the Automotive Safety Integrity Level (ASIL) and is a non-enforceable level.

[0159] The first virtual machine (820) can execute an operating system (822), a container runtime (824) on the operating system (822), and containers (827, 829) on the container runtime (824).

[0160] The second virtual machine (830) may be a virtual machine corresponding to ASIL A or ASIL B, in which the sum of severity, exposure, and controllability is 7 or 8 in the automotive safety integrity level (ASIL).

[0161] The second virtual machine (830) can execute an operating system (832), a container runtime (834) on the operating system (832), and containers (837, 839) on the container runtime (834).

[0162] The third virtual machine (840) may be a virtual machine corresponding to ASIL C or ASIL D, in which the sum of severity, exposure, and controllability is 9 or 10 in the automotive safety integrity level (ASIL).

[0163] Meanwhile, ASIL D can correspond to the grade that requires the highest safety level.

[0164] The third virtual machine (840) can run a safety operating system (842) and an application (845) on the operating system (842).

[0165] Meanwhile, the third virtual machine (840) may also execute a safety operating system (842), a container runtime (844) on the safety operating system (842), and a container (847) on the container runtime (844).

[0166] Meanwhile, unlike the drawing, the third virtual machine (840) can also be executed through a separate core rather than the processor (175). This will be described later with reference to FIG. 5b.

[0167] FIG. 5b illustrates another example of a vehicle communication device according to an embodiment of the present disclosure.

[0168] Referring to the drawing, a vehicle communication device (800b) according to an embodiment of the present disclosure includes a signal processing device (170a1, 170a2) and a plurality of area signal processing devices (170Z1 to 170Z4).

[0169] The vehicle communication device (800b) of FIG. 5b is similar to the vehicle communication device (800a) of FIG. 5a, but the signal processing device (170a1) has some differences from the signal processing device (170a1) of FIG. 5a.

[0170] To describe the difference, the signal processing device (170a1) may include a processor (175) and a second processor (177).

[0171] The processor (175) within the signal processing unit (170a1) executes a hypervisor (505), and executes first and second virtual machines (820 to 830) on the hypervisor (505) according to the automotive safety integrity level (Automotive SIL; ASIL).

[0172] The first virtual machine (820) can execute an operating system (822), a container runtime (824) on the operating system (822), and containers (827, 829) on the container runtime (824).

[0173] The second virtual machine (830) can execute an operating system (832), a container runtime (834) on the operating system (832), and containers (837, 839) on the container runtime (834).

[0174] Meanwhile, the second processor (177) within the signal processing device (170a1) can execute a third virtual machine (840).

[0175] The third virtual machine (840) can execute a safety operating system (842), an auto-execution (845) on the operating system (842), and an application (845) on the auto-execution (845). That is, unlike FIG. 5A, an auto-execution (846) on the operating system (842) can be executed.

[0176] Meanwhile, the third virtual machine (840) may, similarly to FIG. 5a, execute a safety operating system (842), a container runtime (844) on the safety operating system (842), and a container (847) on the container runtime (844).

[0177] Meanwhile, the third virtual machine (840) requiring a high level of security is preferably executed on a second processor (177), which is a different core or different processor, unlike the first and second virtual machines (820 to 830).

[0178] Meanwhile, in the signal processing devices (170a1, 170a2) of FIGS. 5a and 5b, when the first signal processing device (170a) malfunctions, the second signal processing device (170a2), which is a backup device, can operate.

[0179] Alternatively, it is also possible for the signal processing devices (170a1, 170a2) to operate simultaneously, with the first signal processing device (170a) operating as the main device and the second signal processing device (170a2) operating as the sub device. This will be described with reference to FIGS. 5c and 5d.

[0180] FIG. 5c illustrates another example of a vehicle communication device according to an embodiment of the present disclosure.

[0181] Referring to the drawing, a vehicle communication device (800c) according to an embodiment of the present disclosure includes a signal processing device (170a1, 170a2) and a plurality of area signal processing devices (170Z1 to 170Z4).

[0182] Meanwhile, in the drawing, two signal processing devices (170a1, 170a2) are exemplified, but this is for backup purposes, etc., and one is also possible.

[0183] Meanwhile, the signal processing device (170a1, 170a2) may also be named an HPC (High Performance Computing) signal processing device.

[0184] Multiple area signal processing devices (170Z1 to 170Z4) are arranged in each area (Z1 to Z4) and can transmit sensor data to signal processing devices (170a1, 170a2).

[0185] The signal processing device (170a1, 170a2) receives data via a wire from multiple area signal processing devices (170Z1 to 170Z4) or a communication device (120).

[0186] In the drawing, data is exchanged based on wired communication between a signal processing device (170a1, 170a2) and multiple area signal processing devices (170Z1 to 170Z4), and the signal processing device (170a1, 170a2) and the server (400) exchange data based on wireless communication. However, data may be exchanged based on wireless communication between a communication device (120) and a server (400), and the signal processing device (170a1, 170a2) and the communication device (120) may exchange data based on wired communication.

[0187] Meanwhile, data received by the signal processing device (170a1, 170a2) may include camera data or sensor data.

[0188] Meanwhile, among the signal processing devices (170a1, 170a2), the processor (175) in the first signal processing device (170a1) executes a hypervisor (505) and can execute a safety virtualization machine (860) and a non-safety virtualization machine (870) on the hypervisor (505), respectively.

[0189] Meanwhile, among the signal processing devices (170a1, 170a2), the processor (17b5) in the second signal processing device (170a2) executes the hypervisor (505b) and can execute only the safety virtualization machine (880) on the hypervisor (505).

[0190] In this way, since the processing for safety is separated between the first signal processing device (170a1) and the second signal processing device (170a2), it is possible to improve stability and processing speed.

[0191] Meanwhile, high-speed network communication can be performed between the first signal processing device (170a1) and the second signal processing device (170a2).

[0192] FIG. 5d illustrates another example of a vehicle communication device according to an embodiment of the present disclosure.

[0193] Referring to the drawing, a vehicle communication device (800d) according to an embodiment of the present disclosure includes a signal processing device (170a1, 170a2) and a plurality of area signal processing devices (170Z1 to 170Z4).

[0194] The vehicle communication device (800d) of FIG. 5d is similar to the vehicle communication device (800c) of FIG. 5c, but the second signal processing device (170a2) has some differences from the second signal processing device (170a2) of FIG. 5c.

[0195] The processor (17b5) in the second signal processing device (170a2) of FIG. 5d executes a hypervisor (505b) and can execute a safety virtualization machine (880) and a non-safety virtualization machine (890) on the hypervisor (505).

[0196] That is, unlike FIG. 5c, the difference is that the processor (17b5) within the second signal processing device (170a2) further executes a non-safety virtualization machine (890).

[0197] In this way, since the processing for safety and non-safety is separated into the first signal processing device (170a1) and the second signal processing device (170a2), it is possible to improve stability and processing speed.

[0198] FIG. 6 is an example of a block diagram of a vehicle communication device according to an embodiment of the present disclosure.

[0199] Referring to the drawings, a vehicle communication device (900) according to an embodiment of the present disclosure includes a plurality of area signal processing devices (170Z1 to 170Z4) and a signal processing device (170).

[0200] The signal processing device (170) at this time is a high-performance centralized signal processing and control device having multiple CPUs and GPUs, and may be called an HPC (High Performance Computing) signal processing device or a central signal processing device.

[0201] A plurality of area signal processing devices (170Z1 to 170Z4) and a signal processing device (170) are connected by wired cables (CB1 to CB4).

[0202] Meanwhile, multiple area signal processing devices (170Z1 to 170Z4) can be connected to each other with wired cables (CBa to CBd).

[0203] The wired cable (CBa~CBd) at this time may include a CAN communication cable, an Ethernet communication cable, or a PCI Express cable.

[0204] Meanwhile, a signal processing device (170) according to an embodiment of the present disclosure comprises at least one processor (175, 178, 177) and a large-capacity storage device (925).

[0205] For example, at least one processor may be a central processor.

[0206] Meanwhile, the signal processing device (170) according to the embodiment of the present disclosure may further include a graphics processor or a neural processor.

[0207] Meanwhile, sensor data may be transmitted from at least one of the multiple area signal processing devices (170Z1 to 170Z4) to the signal processing device (170). In particular, the sensor data may be stored in a storage device (925) within the signal processing device (170).

[0208] The sensor data at this time may include at least one of camera data, lidar data, radar data, vehicle direction data, vehicle location data (GPS data), vehicle angle data, vehicle speed data, vehicle acceleration data, vehicle inclination data, vehicle forward / backward data, battery data, fuel data, tire data, vehicle lamp data, vehicle interior temperature data, and vehicle interior humidity data.

[0209] In the drawing, it is exemplified that camera data from a camera (195a) and lidar data from a lidar sensor (196) are input to a first area signal processing device (170Z1), and the camera data and lidar data are transmitted to a signal processing device (170) via a second area signal processing device (170Z2), a third area signal processing device (170Z3), etc.

[0210] Meanwhile, since the data read speed or write speed to the storage device (925) is faster than the network speed when sensor data is transmitted from at least one of the plurality of area signal processing devices (170Z1 to 170Z4) to the signal processing device (170), it is preferable that multi-path routing be performed so that a network bottleneck does not occur.

[0211] To this end, the signal processing device (170) according to the embodiment of the present disclosure can perform multi-path routing based on a Software Defined Network (SDN). Accordingly, a stable network environment can be secured when reading or writing data from the storage device (925). Furthermore, since data can be transmitted to the storage device (925) using multiple paths, the network configuration can be dynamically changed to transmit data.

[0212] Data communication between a plurality of area signal processing devices (170Z1 to 170Z4) and a signal processing device (170) in a vehicle communication device (900) according to an embodiment of the present disclosure is preferably Peripheral Component Interconnect Express communication for high-bandwidth, low-latency communication.

[0213] Figures 7a to 7c are drawings referenced in the operation description of Figure 6.

[0214] FIG. 7a illustrates a circuit board (BDz) including a region signal processing device (170Z) and a circuit board (BD) including a signal processing device (170) and a storage device (925) being connected by a flexible cable (CB).

[0215] Referring to the drawing, the circuit board (BDz) including the area signal processing device (170Z) may further include a retimer (RTz) for signal compensation.

[0216] For example, the retimer (RTz) can receive data from the second signal processing device (170Z), perform signal compensation, and transmit the compensated signal to the signal processing device (170).

[0217] A circuit board (BD) including a signal processing device (170) may further include a retimer (RT) for signal compensation.

[0218] For example, the retimer (RT) can receive data from a signal processing device (170), perform signal compensation, and transmit the compensated signal to a second signal processing device (170Z).

[0219] Flexible cable-based data communication is possible between the area signal processing device (170Z) and the signal processing device (170), and the gap between the multiple area signal processing devices (170Z1 to 170Z4) and the signal processing device (170) can be reduced, thereby improving design freedom, etc.

[0220] Figure 7b is a drawing showing an internal block diagram between the two circuit boards of Figure 7a.

[0221] Referring to the drawing, a circuit board (BDz) corresponding to a region signal processing device (170Z) may include a region signal processing device (170Z) and a retimer (RTz) for signal compensation.

[0222] A circuit board (BD) corresponding to a signal processing device (170) may include a signal processing device (170), a storage device (925), and a retimer (RT) for signal compensation.

[0223] Figure 7c is a diagram illustrating the transmission speed of PCI Express (Peripheral Component Interconnect express) communication.

[0224] Referring to the drawing, the storage device (925) is PCI Express (Peripheral Component Interconnect express) Gen 3, and when 16 lanes are used, the transmission speed can be approximately 8*16=128 Gbps, and when 4 lanes are used, the transmission speed can be approximately 8*4=32 Gbps.

[0225] In the case of PCI Express communication, there is a distance limit to which a physical connection (lane) can be used. In this disclosure, it was confirmed that PCI Express communication is possible within a distance of approximately 7 m.

[0226] Accordingly, in the present disclosure, PCI Express communication is performed between a region signal processing device (170Z) and a signal processing device (170).

[0227] Figure 8 is an example of an internal block diagram of a communication device related to the present invention.

[0228] Referring to the drawing, the communication device (100) related to the present invention performs data communication based on an optical cable between two computing nodes.

[0229] The first computing node (CNa) is equipped with a hardware Infiniband card (ICDa), executes an Infiniband driver (IDRa) for the hardware Infiniband card (ICDa), and can execute an Infiniband core on the Infiniband driver (IDRa).

[0230] Meanwhile, the first computing node (CNa) runs a remote direct memory access (RMDA) provider (PRDa) on an InfiniBand core, runs an application programming interface (API) (RAIa) on the RMDA provider (PRDa), and runs an application on the RMDA API (RAIa).

[0231] Meanwhile, an application within the first computing node (CNa) can transfer large amounts of data to the counterpart node, the second computing node (CNb), using a user-level RMDA API (RAIa), such as rcopy.

[0232] The second computing node (CNb) is equipped with a hardware InfiniBand card (ICDb), executes an InfiniBand driver (IDRb) for the hardware InfiniBand card (ICDb), and can execute an InfiniBand core on the InfiniBand driver (IDRb).

[0233] Meanwhile, the second computing node (CNb) runs an RMDA provider (PRDb) on the InfiniBand core, runs an application programming interface (RAIb) on the RMDA provider (PRDb), and runs applications on the RMDA API (RAIb).

[0234] Meanwhile, an application within the second computing node (CNb) can transfer large amounts of data to the counterpart node, the first computing node (CNa), using a user-level RMDA API (RAIb), ​​such as rcopy.

[0235] In this way, the communication device (100) related to the present invention can perform large-capacity data transmission or reception by combining InfiniBand and remote direct memory access.

[0236] However, since the present invention and related communication device (100) must use a non-flexible optical cable, problems such as space constraints or design constraints arise.

[0237] Accordingly, in the present disclosure, a Peripheral Component Interconnect Express method is applied between computing nodes instead of InfiniBand. This is described with reference to FIG. 9 and below.

[0238] FIG. 9 is an example of an internal block diagram of a signal processing device according to an embodiment of the present disclosure.

[0239] Referring to the drawing, a signal processing device (170) according to an embodiment of the present disclosure may include a plurality of computing nodes (CN1, CN2, Cn3).

[0240] At this time, multiple computing nodes (CN1, CN2, Cn3) can correspond to multiple processors (175, 177, 178) of FIG. 6.

[0241] A signal processing device (170) according to one embodiment of the present disclosure includes a storage device (925), a first computing node (CN1) or processor (175) that executes a Peripheral Component Interconnect Express (PCI Express) driver, executes a Host Channel Adapter (HCA) driver (HDVa) on the PCI Express driver, and executes a Remote Direct Memory Access (RMDA) driver (RCPa) on the PCI Express driver. Accordingly, high-performance, scalable data sharing can be provided.

[0242] Meanwhile, the first computing node (CN1) or processor (175) can exchange data with the storage device (925) via the non-volatile memory express driver (NSKa). Accordingly, high-performance, scalable data sharing can be provided.

[0243] In the drawing, a first computing node (CN1) or processor (175) is illustrated executing an external component high-speed connection root complex (PECa), executing an external component high-speed connection switch driver on the external component high-speed connection root complex (PECa), executing an external component high-speed connection network bus (NTB) driver on the external component high-speed connection switch driver, and executing a host channel adapter (HCA) driver (HDVa) on the external component high-speed connection NTB driver.

[0244] Meanwhile, the first computing node (CN1) or processor (175) executes a remote direct memory access (RMDA) driver (RCPa) on a host channel adapter (HCA) driver (HDVa).

[0245] Unlike FIG. 8, the host channel adapter (HCA) driver (HDVa) for operating the InfiniBand card runs on the PCI Express NTB driver, which enables the host channel adapter (HCA) driver (HDVa) to transmit RDMA data packets to the PCI Express Bus.

[0246] Meanwhile, the storage device (925) may include a plurality of non-volatile memory (NVMeoF (Non-Volatile Memory Express; NVMe) devices.

[0247] For access to the storage device (925) from multiple computing nodes (CN1 to CN3) or multiple processors (175, 177, 178), it is desirable to implement a non-volatile memory express driver on a remote direct memory access (RMDA) driver.

[0248] As shown in the drawing, the first computing node (CN1) or processor (175) can execute a non-volatile memory express driver (NSKa) on a remote direct memory access driver (RCPa). This enables high-performance, scalable data sharing.

[0249] The first computing node (CN1) or processor (175) can run Filesys on a non-volatile memory express driver (NSKa) and execute applications on Filesys.

[0250] Meanwhile, the first computing node (CN1) or processor (175), unlike other computing nodes or processors, can further execute a storage device driver (NDR) for driving the storage device (925). Accordingly, the first computing node (CN1) or processor (175) can directly control the storage device (925).

[0251] Meanwhile, a signal processing device (170) according to one embodiment of the present disclosure may further include a second computing node (CN2) or a second processor (177) that exchanges data based on a high-speed connection between a processor (175) or a storage device (925) and an external component.

[0252] Meanwhile, the first computing node (CN1) or processor (175) operates as a host, and the second computing node (CN2) or the second processor (177) operates as a client, and the first computing node (CN1) or processor (175) can control the storage device (925) in response to a data write or data read request from the second computing node (CN2) or the second processor (177) to the storage device (925). Accordingly, high-performance, scalable data sharing can be provided.

[0253] Meanwhile, the second computing node (CN2) or the second processor (177) may execute an external component high-speed connection root complex (PECb) (RC) (PECb) for access to the storage device (925), and execute a second external component high-speed connection driver on the external component high-speed connection root complex (PECb). Accordingly, while performing data communication based on a flexible cable (CB), it is possible to provide high-performance, scalable data sharing.

[0254] Meanwhile, the second computing node (CN2) or second processor (177) may execute a second host channel adapter driver (HDVb) on the second external component high-speed connection driver and execute a second remote direct memory access driver (RCPb) on the second host channel adapter driver (HDVb). This enables high-performance, scalable data sharing to be provided.

[0255] For example, the second computing node (CN2) or the second processor (177) may execute an external component high-speed connection root complex (PECb), execute an external component high-speed connection switch driver on the external component high-speed connection root complex (PECb), execute an external component high-speed connection NTB driver on the external component high-speed connection switch driver, and execute a host channel adapter driver (HDVb) on the external component high-speed connection NTB driver.

[0256] Meanwhile, the second computing node (CN2) or second processor (177) executes a remote direct memory access driver (RCPb) on the host channel adapter driver (HDVb).

[0257] Unlike in Figure 8, the host channel adapter driver (HDVb) for operating the InfiniBand card runs on the PCI Express NTB driver, which enables the host channel adapter driver (HDVb) to transmit RDMA data packets to the PCI Express Bus.

[0258] Meanwhile, the second computing node (CN2) or second processor (177) can execute a non-volatile memory express driver (NSKb) on a remote direct memory access driver (RCPb). This enables high-performance, scalable data sharing.

[0259] Meanwhile, the second computing node (CN2) or the second processor (177) can run Filesys on the non-volatile memory express driver (NSKb) and execute applications on Filesys.

[0260] Meanwhile, a signal processing device (170) according to one embodiment of the present disclosure may further include a third computing node (CN3) or a third processor (178) that exchanges data based on a high-speed connection between a processor (175) or a storage device (925) and an external component.

[0261] Meanwhile, the first computing node (CN1) or processor (175) operates as a host, and the third computing node (CN3) or the third processor (178) operates as a client. The first computing node (CN1) or processor (175) can control the storage device (925) in response to a data write or data read request from the third computing node (CN3) or the third processor (178) to the storage device (925). Accordingly, high-performance, scalable data sharing can be provided.

[0262] Meanwhile, the third computing node (CN3) or the third processor (178) may execute an external component high-speed connection root complex (PECc) (RC) (PECc) for access to the storage device (925) and execute a second external component high-speed connection driver on the external component high-speed connection root complex (PECc). Accordingly, while performing data communication based on a flexible cable (Cc), it is possible to provide high-performance, scalable data sharing.

[0263] Meanwhile, the third computing node (CN3) or third processor (178) may execute a second host channel adapter driver (HDVc) on the second external component high-speed connection driver and execute a second remote direct memory access driver (RCPc) on the second host channel adapter driver (HDVc). This enables high-performance, scalable data sharing.

[0264] For example, the third computing node (CN3) or the third processor (178) may execute an external component high-speed connection root complex (PECc), execute an external component high-speed connection switch driver on the external component high-speed connection root complex (PECc), execute an external component high-speed connection NTB driver on the external component high-speed connection switch driver, and execute a host channel adapter driver (HDVc) on the external component high-speed connection NTB driver.

[0265] Meanwhile, the third computing node (CN3) or third processor (178) executes a remote direct memory access driver (RCPc) on the host channel adapter driver (HDVc).

[0266] Unlike in Figure 8, the host channel adapter driver (HDVc) for operating the InfiniBand card runs on the PCI Express NTB driver, which enables the host channel adapter driver (HDVc) to transmit RDMA data packets to the PCI Express Bus.

[0267] Meanwhile, the third computing node (CN3) or third processor (178) can execute a non-volatile memory express driver (NSKc) on a remote direct memory access driver (RCPc). This enables high-performance, scalable data sharing.

[0268] Meanwhile, the third computing node (CN3) or third processor (178) can run Filesys on a non-volatile memory express driver (NSKc) and execute applications on Filesys.

[0269] Meanwhile, a signal processing device (170) according to one embodiment of the present disclosure further includes an external component high-speed connection (PCI Express) switch (736b) that receives data input through an external flexible cable (CB).

[0270] Meanwhile, the first computing node (CNm1) or processor (175) can control data to be stored in the storage device (925). Accordingly, while performing data communication based on a flexible cable (CB), high-performance, scalable data sharing can be provided.

[0271] Meanwhile, the storage device (925) may be directly connected to the first computing node (CNm1) or processor (175), or may be connected to an external component high-speed connection switch (736b).

[0272] Meanwhile, the external component high-speed connection switch (736b) can perform USP communication or NRB communication.

[0273] FIG. 10 is an example of an internal block diagram of a signal processing device according to another embodiment of the present disclosure.

[0274] Referring to the drawing, a signal processing device (170m) according to another embodiment of the present disclosure includes a first computing node (CNm1) or processor (175), a second computing node (CNm2) or second processor (177), and a storage device (925).

[0275] The first computing node (CNm1) or processor (175) can operate as a host, and the second computing node (CNm2) or second processor (177) can operate as a client.

[0276] To this end, the first computing node (CNm1) or processor (175) may execute an external component high-speed connection end point (EP) (PEE) for access to the storage device (925) of the second computing node (CNm2) or the second processor (177), and may execute a host channel adapter driver (HDVm) on the external component high-speed connection end point (PEE).

[0277] For example, the first computing node (CNm1) or processor (175) may execute an external component high-speed connection endpoint (PEE), execute an external component high-speed connection endpoint function (PEF) on the external component high-speed connection endpoint (PEE), and execute a host channel adapter driver (HDVm) on the external component high-speed connection endpoint function (PEF).

[0278] Meanwhile, the first computing node (CNm1) or processor (175) executes a remote direct memory access driver (RCPa) on the host channel adapter driver (HDVm).

[0279] Meanwhile, the first computing node (CNm1) or processor (175) can execute a non-volatile memory express driver (NSKa) on a remote direct memory access driver (RCPa). This enables high-performance, scalable data sharing.

[0280] Meanwhile, the first computing node (CNm1) or processor (175) can run Filesys on a non-volatile memory express driver (NSKa) and execute applications on Filesys.

[0281] For example, the second computing node (CNm2) or the second processor (177) may execute an external component high-speed link root complex (PECb), execute an external component high-speed link client driver (PCDm) on the external component high-speed link root complex (PECb), and execute a host channel adapter driver (HDVb) on the external component high-speed link client driver (PCDm).

[0282] Meanwhile, the second computing node (CNm2) or second processor (177) executes a remote direct memory access driver (RCPb) on the host channel adapter driver (HDVb).

[0283] Meanwhile, the second computing node (CNm2) or second processor (177) can execute a non-volatile memory express driver (NSKb) on a remote direct memory access driver (RCPb). This enables high-performance, scalable data sharing.

[0284] Meanwhile, the second computing node (CNm2) or the second processor (177) can run Filesys on the non-volatile memory express driver (NSKb) and execute applications on Filesys.

[0285] Unlike FIG. 9, in FIG. 10, the first computing node (CNm1) or processor (175) and the second computing node (CNm2) or second processor (177) are directly connected without an external component high-speed connection switch (736b).

[0286] To this end, the first computing node (CN1) or processor (175) directly connected to the storage device (925) acts as an endpoint and thus executes an external component high-speed connection endpoint (PEE) as shown in the drawing.

[0287] In response, the second computing node (CNm2) or second processor (177) executes an external component high-speed link root complex (PECb).

[0288] Meanwhile, an external component high-speed connection endpoint function (PEF) within a first computing node (CN1) or processor (175) can perform requests and commands from a second computing node (CNm2) or second processor (177) that wishes to access a storage device (925).

[0289] Meanwhile, the external component high-speed connection client driver (PCDm) within the second computing node (CNm2) or the second processor (177) can register (enumerate) the first computing node (CN1) or processor (175) to the PCI Express bus and perform data communication.

[0290] FIG. 11 is an example of an internal block diagram of a vehicle communication device according to an embodiment of the present disclosure.

[0291] Referring to the drawing, a vehicle communication device (900) according to an embodiment of the present disclosure includes a signal processing device (170) and a second signal processing device (170Z) that exchanges data with the signal processing device (170).

[0292] The signal processing device (170) may be the central signal processing device of FIG. 6, and the second signal processing device (170Z) may be the area signal processing device of FIG. 6.

[0293] The signal processing device (170) includes a first computing node (CNm1) or processor (175), a second computing node (CNm2) or second processor (177), and a storage device (925), as shown in FIG. 9.

[0294] The operation of the first computing node (CNm1) or processor (175), the second computing node (CNm2) or second processor (177), and the storage device (925) may be the same as the description of FIG. 9.

[0295] Meanwhile, the signal processing device (170) further includes an external component high-speed connection switch (736b).

[0296] Meanwhile, the external component high-speed connection switch (736b) can perform USP communication or NRB communication.

[0297] Meanwhile, a vehicle communication device (900) according to one embodiment of the present disclosure may further include a retimer (RTz) that receives data from a second signal processing device (170Z) and transmits it to a signal processing device (170), as shown in FIG. 7b.

[0298] The retimer (RTz) may be equipped with a RefClk terminal (PCKz) for a RefClk signal, a PERESET terminal (PSTz) for a PERESET signal, and a lane terminal (RTz) for PCI Express data lines (Tx / Rx).

[0299] Meanwhile, the second signal processing device (170Z) may be equipped with a GPIO terminal (OBNz) for a separate line (Outband) for transmitting a control signal or a simple data signal.

[0300] Meanwhile, between the signal processing device (170) and the second signal processing device (170Z) or between the signal processing device (170) and the retimer (RTz), a line for transmitting RefClk and PERESET or a separate line (Outband) for transmitting a control signal or a simple data signal may be additionally required.

[0301] For this purpose, the external component high-speed connection switch (736b) may be equipped with a GPIO terminal (OBN) for a separate line for transmitting a control signal or a simple data signal, a RefClk terminal (PCK) for a RefClk signal, a PERESET terminal (PST) for a PERESET signal, an NTB / USP terminal, etc.

[0302] Meanwhile, the second signal processing device (170z) can execute an external component high-speed connection root complex (PECz), execute an external component high-speed connection switch driver on the external component high-speed connection root complex (PECz), execute an external component high-speed connection NTB driver on the external component high-speed connection switch driver, and execute a host channel adapter driver (HDVz) on the external component high-speed connection NTB driver.

[0303] Meanwhile, the second signal processing unit (170z) executes a remote direct memory access driver (RCPz) on the host channel adapter driver (HDVz).

[0304] Meanwhile, the second signal processing unit (170z) can execute a non-volatile memory express driver (NSKz) on a remote direct memory access driver (RCPz). This enables high-performance, scalable data sharing.

[0305] Meanwhile, the second signal processing device (170z) can execute Filesys on a non-volatile memory express driver (NSKz) and execute an application on Filesys.

[0306] Meanwhile, the second signal processing device (170z) can execute an authentication requester (ANR) for authentication.

[0307] Meanwhile, the first computing node (CN1) or processor (175) can perform authentication based on a security key in response to an authentication request from an authentication requester (ANR) in another processor (175) or another signal processing device (170Z), and control data exchange with the authenticated processor (175) or signal processing device (170). Accordingly, access to the storage device (925) by an unauthorized processor or signal processing device can be blocked, which ultimately improves the security of the storage device (925).

[0308] Meanwhile, the first computing node (CN1) or processor (175) can control to encrypt or decrypt data in a secure area within the storage device (925). Accordingly, the security of the storage device (925) can be improved.

[0309] Meanwhile, by implementing the same PCI Express-based RDMA in the signal processing device (170) and the second signal processing device (170Z), high-performance, expandable data sharing becomes possible.

[0310] Figures 12a to 14 are drawings referenced in the operation descriptions of Figures 9 to 11.

[0311] Figure 12a is a drawing explaining signal attenuation according to the distance between the signal processing device (170) and the second signal processing device (170Z).

[0312] (a) of Fig. 12a illustrates an eye diagram of a PCI Express bus signal (SGNa) when the signal processing device (170) and the second signal processing device (170Z) are at the first distance.

[0313] Referring to the drawing, when the signal processing device (170) and the second signal processing device (170Z) are at the first distance, a PCI Express bus signal (SGNa) may appear as in (a) of FIG. 12a.

[0314] (b) of Fig. 12a illustrates an eye diagram of a PCI Express bus signal (SGNa) when the signal processing device (170) and the second signal processing device (170Z) are at a second distance.

[0315] Referring to the drawing, when the signal processing device (170) and the second signal processing device (170Z) are at the second distance, a PCI Express bus signal (SGNb) may appear as in (b) of FIG. 12a.

[0316] The farther the distance between the signal processing device (170) and the second signal processing device (170Z) is, the greater the attenuation of the PCI Express bus signal.

[0317] Accordingly, the vehicle communication device (900) according to one embodiment of the present disclosure may further include a retimer (RTz) that receives data from the second signal processing device (170Z) and transmits it to the signal processing device (170), as shown in FIG. 7b. Accordingly, signal attenuation between the signal processing device (170) and the second signal processing device (170Z) can be reduced.

[0318] FIG. 12b is a diagram illustrating the operating speed according to the data size at each distance between the signal processing device (170) and the second signal processing device (170Z).

[0319] Referring to the drawing, GROa exemplifies the operation speed according to the data size when directly connected between the signal processing device (170) and the second signal processing device (170Z), GROd exemplifies the operation speed when a distance of 7 m is between the signal processing device (170) and the second signal processing device (170Z), GROb exemplifies the operation speed when a distance of 1 m is between the signal processing device (170) and the second signal processing device (170Z), and GROc exemplifies the operation speed when a distance of 2 m is between the signal processing device (170) and the second signal processing device (170Z).

[0320] As shown in the drawing, it can be seen that the distance between the signal processing device (170) and the second signal processing device (170Z) is either directly connected, within 7 m, or has no significant difference.

[0321] Accordingly, according to the vehicle communication device (900) of the present disclosure, the distance between the signal processing device (170) and the second signal processing device (170Z) is arranged within 7 m by using a retimer (RTz) or the like.

[0322] Figure 13a is an example of the interior of a computing node or processor.

[0323] Referring to the drawing, a computing node (CNP) or processor (175) may execute an external component high-speed connection root complex (PEC), execute an external component high-speed connection switch driver (PESD) on the external component high-speed connection root complex (PEC), execute an external component high-speed connection network bus (NTB) driver (PEND) on the external component high-speed connection switch driver (PESD), and execute a host channel adapter driver (HDV) on the external component high-speed connection NTB driver (PEND).

[0324] Meanwhile, the computing node (CNP) or processor (175) can further execute a Non-Transparent Bridge (NTB) Transport (NTPT) between the External Component High Speed ​​Connect Driver (PESD or PEND) and the Host Channel Adapter Driver (HDV).

[0325] In the drawing, an NTB transport (NTPT) is executed on an external component high-speed connection NTB driver (PEND), a host channel adapter channel (HNB) for NTB is executed on the NTB transport (NTPT), a channel bus (HNB) is executed on the host channel adapter channel (HNB) for NTB, and a host channel adapter driver (HDV) is executed on the channel bus (HNB).

[0326] Meanwhile, a computing node (CNP) or processor (175) may execute a remote direct memory access driver (RCP) on a host channel adapter driver (HDV).

[0327] Meanwhile, the computing node (CNP) or processor (175) may further execute a network interface controller (NIR).

[0328] Meanwhile, a computing node (CNP) or processor (175) may have a host channel adapter channel (HTP) for TCP running on a network interface controller (NIR), and a channel bus (HNB) running on the host channel adapter channel (HTP) for TCP.

[0329] Meanwhile, the computing node (CNP) or processor (175) can run NTB NetDev (NNDV) on the NTB transport (NTPT).

[0330] Figure 13b is a drawing explaining the NTB transport of Figure 13a.

[0331] Referring to the drawing, the NTB Transport (NTPT) can simultaneously process requests from the Host Channel Adapter Channel (HNB) for NTB and requests from the NTB NetDev (NNDV).

[0332] Meanwhile, requests from the Host Channel Adapter Channel (HNB) for NTB and requests from NTB NetDev (NNDV) must be processed through the External Component High-Speed ​​Connect Switch Driver (PESD) and the External Component High-Speed ​​Connect NTB Driver (PEND).

[0333] To this end, the NTB Transport (NTPT) executes a first memory window (1310) for requests from the Host Channel Adapter Channel (HNB) for TB and a second memory window (1320) for requests from the NTB NetDev (NNDV).

[0334] Meanwhile, the first memory window (1310) can allocate a queue pair for the HCA channel, and the second memory window (1320) can allocate a queue pair for the NTB NetDev (NNDV).

[0335] In addition, NTB Transport (NTPT) can execute a queue pair list manager (1330) that manages the list of each queue pair.

[0336] That is, NTB Transport (NTPT) can create and manage a list of each queue pair, assign a unique ID value to each device, and distinguish and process requests from each device.

[0337] Accordingly, the NTB Transport (NTPT) can process requests from the Host Channel Adapter Channel (HNB) for NTB separately from requests from the NTB NetDev (NNDV).

[0338] Specifically, on the one hand, the Opaque Bridge Transport (NTPT) can be processed by distinguishing between an Application Programming Interface (API) based on the Opaque Bridge (NTB) of the host channel adapter channel and an Application Programming Interface based on the Opaque Bridge NetDev.

[0339] Meanwhile, the opaque bridge transport (NTPT) can create and manage a queue-pair list.

[0340] Meanwhile, according to FIG. 13a, an application using a network interface controller (NIR) and an application using an RDMA API can simultaneously exchange data via PCI Express.

[0341] Figure 13c illustrates a storage device (925) divided into multiple spaces.

[0342] Referring to the drawing, the first computing node (CN1) or processor (175) can divide the storage device (925) into a plurality of regions or a plurality of memory windows (1410a to 1410n), and control each region or each memory window (1410a to 1410n) to be mapped to each queue pair.

[0343] Meanwhile, each queue pair can support multiple applications (APN1 to APNm).

[0344] Meanwhile, each area or each memory window (1410a to 1410n) may be equipped with a Low Latency Data Area (1411), an RDMA QP (1412), a Command Buffer (1414), a Virtual Doorbell Buffer (1416), an RDMA Transport QP (1418), and a NIC Transport QP (1419).

[0345] Meanwhile, the NIC Transport QP (1419) may be an area used by NTB NetDev (NNDV), the RDMA Transport QP (1418) may be an area where payload data to be transmitted via RDMA is read and written, and the Virtual Doorbell Buffer (1416) may be an area where Virtual Doorbell Event information is recorded.

[0346] Meanwhile, the Command Buffer (1414) may be an area where commands to be transmitted to a Peer are recorded, the RDMA QP (1412) may be an area where Configuration information and Send / Receive / Completion Queue information are recorded, and the Low Latency Data Area (1411) may be an area where small-sized data requiring low latency are recorded.

[0347] Meanwhile, in vehicle communication devices, data generation and processing are often asymmetric across domains.

[0348] For example, a processor (175) performing autonomous driving within a signal processing device (170) collects data in real time from numerous sensors and stores the data in a storage device (925), and a processor performing a connectivity service transmits the collected and stored data to a cloud server after undergoing some processing.

[0349] At this time, if read and write occur simultaneously for the same storage device (925), the performance of the system is greatly reduced, and great difficulties arise in data processing and management.

[0350] Accordingly, this disclosure proposes a method for operating the storage space of a storage device (925) separately. This simplifies data processing and management, and enhances system performance and stability.

[0351] The separation of storage space of the storage device (925) is described in more detail with reference to FIG. 14 and below.

[0352] FIG. 14 is a diagram illustrating the operation of a computing node in a vehicle communication device (1400) according to an embodiment of the present disclosure.

[0353] Referring to the drawing, a vehicle communication device (1400) according to an embodiment of the present disclosure may include a plurality of computing nodes (CNr to CNt).

[0354] The computing nodes (CNr~CNt) at this time can correspond to multiple processors or multiple signal processing devices.

[0355] Below, the description focuses on computing nodes (CNr~CNt) being processors (175, 177, 178).

[0356] The first computing node (CNr) or processor (175) can execute a storage device driver (NDR) for controlling a storage device (NM).

[0357] Meanwhile, the first computing node (CNr) or processor (175) can execute a Configuration Manager (CFM) on a storage device driver (NDR) and a Data Life-cycle Manager (DLCM) on the Configuration Manager (CFM).

[0358] Meanwhile, the first computing node (CNr) or processor (175) can execute an encryptor (ECR) for encryption, an authenticator (ANTR) for authentication, and a client event monitor (CEMT).

[0359] Meanwhile, the first computing node (CNr) or processor (175) can divide the storage device (925) into multiple areas.

[0360] Meanwhile, the storage device (NM) can be divided into a first area (1412) for a first computing node (CNr) or processor (175) as a host, a second area (1413) for a second computing node (CNs) or second processor (177) as a client, a third area (1414) for a third computing node (CNt) or third processor (178), a shared area (1416), a secure area (1418), and a reserved area (1419).

[0361] Meanwhile, the second computing node (CNs) or second processor (177) can execute an authentication requester (ANTra), a decrypter (DCRa), and a boot event manager (BEMa).

[0362] Meanwhile, the third computing node (CNt) or third processor (178) can execute an authentication requester (ANTrb), a decrypter (DCRb), and a boot event manager (BEMb).

[0363] Meanwhile, the first computing node (CNr) or processor (175) divides the storage device (925) into a plurality of areas, and maps them to each of the plurality of processors (175, 177, 178) or each of the plurality of signal processing devices (170, 170Z), and may exchange or replace some of the areas among the plurality of areas based on the power off or restart of some of the processors or some of the signal processing devices.

[0364] In the drawing, it is illustrated that the third area (1414) of the storage device (NM) is changed to the second area (1413).

[0365] Meanwhile, the boot event manager (BEMa, BEMb) running on the second computing node (CNs) or the third computing node (CNt), which is a client, transmits a related event to the client event monitor (CEMT) in the first computing node (CNr) or processor (175), which is a host, when each K-client is powered off or restarted.

[0366] The Client Event Monitor (CEMT) forwards events to the Data Life-cycle Manager (DLCM), which in turn forwards the events to the Configuration Manager (CFM).

[0367] The configuration manager (CFM) can control the exchange of the second area (1413) and the third area (1414), which are areas exclusively used by each client, through the storage device driver (NDR).

[0368] And, the areas within the exchanged storage devices (NM) can be applied as is when the system is restarted.

[0369] Meanwhile, when the system is restarted, each client, the second computing node (CNs) or the third computing node (CNt), must be authenticated by the host, the first computing node (CNr), in order to normally access the storage device (NM).

[0370] An authentication requester (ANTra, ANTrb) running on each client, the second computing node (CNs) or the third computing node (CNt), requests device authentication from an authenticator (ANTR) within the host, the first computing node (CNr), before loading the virtual storage device upon system restart.

[0371] An authenticator (ANTR) within the first computing node (CNr) can access the secure area (1418) of the storage device (NM), read the appropriate security key for device authentication, and authenticate the device if the request is valid.

[0372] Meanwhile, whether the client, the second computing node (CNs) or the third computing node (CNt), is authenticated is transmitted to the first computing node (CNr), and access to the storage device (NM) of the second computing node (CNs) or the third computing node (CNt) for which authentication has been completed is permitted.

[0373] Meanwhile, the second computing node (CNs) or third computing node (CNt) that failed authentication cannot access all areas of the storage device (NM).

[0374] Meanwhile, a second computing node (CNs) or a third computing node (CNt) that has successfully completed authentication can access all permitted areas without going through an authentication requester (ANTra, ANTrb).

[0375] However, in order for a second computing node (CNs) or a third computing node (CNt) that has successfully completed authentication to access the security area (1418), access must be granted through an authentication requester (ANTra, ANTrb) for each access.

[0376] Additionally, it is desirable that all read or write data (payload) for the secure area (1418) be encrypted or decrypted.

[0377] Meanwhile, the Configuration Manager (CFM) can validate the namespace upon reset and, if there is a problem, replace the namespace with a namespace that was on standby for safety.

[0378] Meanwhile, a first computing node (CNr) or processor (175) in a signal processing device (170) according to an embodiment of the present disclosure may control data input through an external flexible cable (CB) to be stored in a first area of ​​a storage device (NM), and a second computing node (CNs) or a second processor (177) may control data from the first area of ​​the storage device (NM) to be read and a namespace of the first area of ​​the storage device (NM) to be changed. Accordingly, while performing data communication based on the flexible cable (CB), high-performance and scalable data sharing can be provided.

[0379] Although the preferred embodiments of the present disclosure have been illustrated and described above, the present disclosure is not limited to the specific embodiments described above, and various modifications may be made by a person skilled in the art to which the present invention pertains without departing from the gist of the present disclosure as claimed in the claims, and such modifications should not be understood individually from the technical idea or prospect of the present disclosure.

Claims

1. Storage device; A signal processing device comprising a processor that executes a Peripheral Component Interconnect Express (PCI Express) driver, executes a Host Channel Adapter (HCA) driver on the PCI Express driver, and executes a Remote Direct Memory Access (RMDA) driver on the Host Channel Adapter driver.

2. In paragraph 1, The above processor, A signal processing device that executes a non-volatile memory express driver on the above remote direct memory access driver.

3. In paragraph 1, The above processor, A signal processing device that exchanges data with the storage device through a non-volatile memory express driver.

4. In paragraph 1, It further comprises an external component high-speed connection switch that receives data input through an external flexible cable; The above processor, A signal processing device that controls the storage device to store the data.

5. In paragraph 1, A signal processing device further comprising a second processor for exchanging data based on a high-speed connection between the processor or the storage device and the external component.

6. In paragraph 5, The above processor operates as a host, and the second processor operates as a client, The above processor, A signal processing device that controls the storage device in response to a request to write or read data from the second processor to the storage device.

7. In paragraph 5, The second processor, A signal processing device that executes the external component high-speed connection root complex (RC) for accessing the storage device, and executes a second external component high-speed connection driver on the external component high-speed connection root complex.

8. In paragraph 7, The second processor, A signal processing device that executes a second host channel adapter driver on the second external component high-speed connection driver and executes a second remote direct memory access driver on the second host channel adapter driver.

9. In paragraph 5, The above processor, A signal processing device that runs the external component high-speed connection endpoint (EP) for accessing the storage device of the second processor, and runs the host channel adapter driver on the external component high-speed connection endpoint.

10. In paragraph 1, The above processor, A signal processing device further executing a Non-Transparent Bridge (NTB) transport between the external component high-speed connection driver and the host channel adapter driver.

11. In paragraph 10, The above opaque bridge transport, A signal processing device that creates and manages a Que-Pair list.

12. In paragraph 10, The above opaque bridge transport, A signal processing device that processes and distinguishes between an application programming interface (API) based on an opaque bridge of a host channel adapter channel and an application programming interface based on an opaque bridge NetDev.

13. In paragraph 1, The above processor, A signal processing device that divides the above storage device into a plurality of areas and controls each area to be mapped to each queue pair.

14. In paragraph 1, The above processor, The above storage device is divided into multiple areas and mapped to each of multiple processors or each of multiple signal processing devices. A signal processing device that exchanges or replaces some of the plurality of regions based on power off or restart of some processors or some signal processing devices.

15. In paragraph 1, The above processor, A signal processing device that performs authentication based on a security key in response to an authentication request from another processor or another signal processing device and controls data exchange with the processor or signal processing device that has completed authentication.

16. In paragraph 1, The above processor, A signal processing device that controls encryption or decryption of data in a secure area within the above storage device.

17. In paragraph 1, further comprising a second processor; The above processor, Controlling data input through an external flexible cable to be stored in the first area of ​​the storage device, The second processor, A signal processing device that controls to read data from the first area of ​​the storage device and to change the namespace of the first area of ​​the storage device.

18. Storage device; A processor that controls data input through an external flexible cable to be stored in a first area of ​​the storage device; A signal processing device comprising a second processor that controls data reading from the first area of ​​the storage device and changing the namespace of the first area of ​​the storage device.

19. Signal processing device; A second signal processing device that exchanges data with the signal processing device; The above signal processing device, A vehicle communication device comprising a signal processing device according to any one of claims 1 to 18.

20. In paragraph 19, A vehicle communication device further comprising a retimer that receives data from the second signal processing device and transmits it to the signal processing device.

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