Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises an array substrate (10) and a color filter substrate (20) which are arranged opposite to each other, and a liquid crystal layer (LC) located between the array substrate (10) and the color filter substrate (20), the cell gap of the liquid crystal layer (LC) in a light-transmitting area of the display panel satisfying: when the refresh rate of the display panel is greater than or equal to 60 Hz but does not exceed 480 Hz, the reciprocal of the refresh rate of the display panel and the cell gap satisfy a quadratic polynomial relationship. The cell gap of the display panel is only correlated with the refresh rate of the display panel, thereby allowing for more simplified design complexity and higher design efficiency.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to a display panel and a display device. Background Art

[0002] With the continuous development of thin-film transistor liquid crystal display (TFT-LCD) products and the increasing demand for display quality from users, the demand for high refresh rate products is increasing day by day. High refresh rates require a smaller cell gap.

[0003] The Cell Gap is measured in the opening area, and is difficult to measure in the photo spacer (PS) area because it is opaque. For LCD products, the Cell Gap is affected by many factors, including the TFT Pillow (the height difference between the position or setting position of the photo spacer PS on the TFT substrate and the pixel's light-transmitting area), the color resistance step difference of the color filter substrate CF, the height of the photo spacer PS, and the amount of internal liquid crystal. Too many influencing factors increase the complexity of the Cell Gap and reduce the design accuracy. Since high refresh rate LCD display products require a lower Cell Gap, the reduction in Cell Gap design accuracy will significantly affect the design efficiency of display products.

[0004] Summary of the Invention

[0005] The purpose of the present disclosure is at least in part to provide a display panel and a display device that, at least to a certain extent, solves the technical problem of reduced efficiency in display product design due to complex and low-precision design of liquid crystal cell thickness.

[0006] In a first aspect, the present disclosure provides a display panel, comprising an array substrate, a color filter substrate, and a liquid crystal layer located between the array substrate and the color filter substrate; the liquid crystal box thickness of the liquid crystal layer in the light-transmitting area of ​​the display panel satisfies: when the refresh rate of the display panel is greater than or equal to 60 Hz and not more than 480 Hz, the inverse of the refresh rate of the display panel and the liquid crystal box thickness conform to a quadratic polynomial relationship.

[0007] In some embodiments, the liquid crystal cell thickness and the refresh rate satisfy: 1 / f = C2×d 2 +C1×d+C0;

[0008] In the above formula, f is the refresh rate, in Hz; d is the liquid crystal cell thickness, in μm; the value range of C2 is 0.003 to 0.004, the value range of C1 is -0.02 to -0.01, and the value range of C0 is 0.01 to 0.02.

[0009] In some embodiments, when the refresh rate of the display panel is greater than 480 Hz and does not exceed 1000 Hz, the liquid crystal cell thickness ranges from 1.044 μm to 1.6 μm.

[0010] In some embodiments, the array substrate includes a first substrate and a first spacer layer, and the first spacer layer is arranged on the side of the first substrate close to the color film substrate; the color film substrate includes a second substrate and a second spacer layer, and the second spacer layer is arranged on the side of the second substrate close to the array substrate; the first spacer layer includes at least one first main spacer and multiple first sub-spacers, and the first main spacer is spaced apart from the first sub-spacer; the second spacer layer includes at least one second main spacer and multiple second sub-spacers, and the second main spacer is spaced apart from the second sub-spacer; the first main spacer is in contact with the second main spacer, and the first sub-spacer and the second sub-spacer are arranged opposite to each other.

[0011] In some embodiments, the array substrate further includes a color resist layer and an organic film layer stacked on the first substrate, and the organic film layer is located between the color resist layer and the first spacer layer.

[0012] In some embodiments, a first groove is provided on the organic film layer, the first sub-spacer is disposed in the first groove, and the first main spacer is disposed on the organic film layer outside the first groove.

[0013] In some embodiments, the second main spacer and the second sub-spacer include a black matrix layer, and the color film substrate includes a flat protective layer covering the black matrix layer and the second substrate; in a direction perpendicular to the second substrate, the thickness of the black matrix layer is greater than the thickness of the flat protective layer covering the second substrate, and the flat protective layer on the second main spacer abuts against the first main spacer.

[0014] In some embodiments, the deviation between the sum of the thicknesses of the black matrix layer and the flat protective layer in the second main spacer after cell alignment and the height of the first main spacer after cell alignment is no more than 20%.

[0015] In some embodiments, the color film substrate includes a black matrix layer and a flat protective layer arranged on the side of the second substrate close to the array substrate, and the black matrix layer is located between the second substrate and the flat protective layer; a second groove is provided on the flat protective layer, the second sub-spacer is arranged in the second groove, and the second main spacer is arranged on the flat protective layer outside the second groove.

[0016] In some embodiments, the color film substrate includes a black matrix layer and a color resist layer arranged on the same layer on the second substrate, and a flat protective layer covering the black matrix layer and the color resist layer; the second main spacer and the second sub-spacer are arranged on the color resist layer, and their orthographic projections on the second substrate are located within the orthographic projection of the black matrix layer on the second substrate; in the direction perpendicular to the second substrate, the sum of the thicknesses of the black matrix layer and the flat protective layer is less than the sum of the thicknesses of the color resist layer and the flat protective layer.

[0017] In some embodiments, in the vertical direction of the color filter substrate, the top surface of the second sub-spacer is lower than the top surface of the second main spacer, and the height difference is 0.45μm to 0.55μm; or, in the vertical direction of the array substrate, the top surface of the first sub-spacer is lower than the top surface of the first main spacer, and the height difference is 0.45μm to 0.55μm.

[0018] In some embodiments, the product of the height of the first main spacer before aligning the box and the compression rate after aligning the box, and the sum of the height of the second main spacer after aligning the box are equal to the thickness of the liquid crystal box, and the compression rate ranges from 0.86 to 0.88.

[0019] In some embodiments, the deviation between the height of the first main spacer after the boxes are assembled and the height of the second main spacer after the boxes are assembled does not exceed 10%.

[0020] In some embodiments, the first main spacer is at the same height as the first secondary spacer, and the second secondary spacer is lower than the second main spacer; or, the second secondary spacer is at the same height as the second main spacer, and the first secondary spacer is lower than the first main spacer.

[0021] In a second aspect, the present disclosure provides a display device, comprising any display panel provided in the embodiments of the first aspect.

[0022] The display panel provided by the present disclosure has a liquid crystal cell thickness (cell gap) designed to satisfy a quadratic polynomial relationship with the inverse of the refresh rate of the display panel when the refresh rate of the display panel is greater than or equal to 60 Hz and not more than 480 Hz. By constructing a quadratic polynomial fitting relationship between the liquid crystal cell thickness and the inverse of the refresh rate, compared with the conventional design of the liquid crystal cell thickness based on the TFT Pillow, color resistance step difference, spacer height and liquid crystal amount, the influencing factors of the liquid crystal cell thickness are significantly reduced, which is conducive to reducing the design complexity of the liquid crystal cell thickness and improving the design accuracy, thereby improving the design efficiency of liquid crystal display products.

[0023] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG1 is a schematic diagram showing the testing principle of liquid crystal cell thickness;

[0025] FIG2 is a schematic diagram of a display panel according to an embodiment of the present disclosure;

[0026] FIG3 is a schematic diagram showing the fitting of the refresh rate and the liquid crystal cell thickness according to an embodiment of the present disclosure;

[0027] FIG4 is a schematic diagram of a sub-spacer Sub PS missing according to an embodiment of the present disclosure;

[0028] FIG5 is a schematic diagram of a display panel with an XPS design according to an embodiment of the present disclosure;

[0029] FIG6 is a schematic diagram of the arrangement of the first main spacer and the first auxiliary spacer according to an embodiment of the present disclosure;

[0030] FIG7 is a schematic diagram of the film structure of a display panel designed by combining XPS with COA according to an embodiment of the present disclosure;

[0031] FIG8A is a schematic diagram illustrating disposing a first auxiliary spacer in a first groove according to an embodiment of the present disclosure;

[0032] FIG8B is a schematic diagram of disposing a first main spacer and a first auxiliary spacer in a first groove according to an embodiment of the present disclosure;

[0033] FIG9 is a schematic diagram of forming a second spacer layer by using a black matrix layer and a flat protective layer according to an embodiment of the present disclosure;

[0034] FIG10 is a schematic diagram of disposing a second auxiliary spacer in a second groove according to an embodiment of the present disclosure;

[0035] FIG11 is a microscopic photograph of a second auxiliary spacer according to an embodiment of the present disclosure;

[0036] FIG12 is a spacer structure design on the CF side of an XPS display panel according to an embodiment of the present disclosure;

[0037] FIG13 is a schematic diagram of a display device according to an embodiment of the present disclosure;

[0038] Figure numerals: 10, array substrate; 11, first substrate; 12, first groove; 20, color filter substrate; 21, second substrate; 22, second groove; BM, black matrix layer; OC, flat protection layer; CRL, color resist layer; ORG, organic film layer; PS1, first spacer layer; Main PS1, first main spacer; Sub PS1, first sub-spacer; PS2, second spacer layer; Main PS2, second main spacer; Sub PS2, second sub-spacer. DETAILED DESCRIPTION

[0039] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessary confusion of the concepts of the present disclosure.

[0040] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0041] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or an intervening layer / element may be present therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed.

[0042] In the context of this disclosure, unless otherwise specified, the light-emitting side of a display panel is referred to as the "top side" or "upper side," and the opposite side is referred to as the "bottom side" or "lower side" to facilitate description of relative directions. Accordingly, the direction from the bottom side to the top side is the thickness direction of the display panel, and the direction perpendicular to the thickness direction is the "planar direction" or "extension direction" of the display panel. It should be understood that these directions are relative, not absolute, directions.

[0043] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0044] Cell Gap is a key parameter in TFT-LCD design. With the development of the industry and the improvement of quality technology, LCD products with high refresh rates and extremely low Cell Gap have emerged, posing challenges to Cell Gap design.

[0045] The principle of cell gap measurement is shown in Figure 1. When light is projected onto the liquid crystal cell, the linearly polarized light is affected by the birefringence of the liquid crystal and changes to elliptical light. This is because there is a phase difference between the x and y directions of the light. The magnitude of the phase deviation is determined by the liquid crystal cell thickness d and the refractive index difference Δn, as expressed by the following relationship: Re = Δn × d (1)

[0046] Therefore, the solution for the liquid crystal cell thickness d is: d = Re / Δn (2)

[0047] Re in the above formula is birefringence retardation, which refers to the phase difference between the decomposed vectors Ex and Ey before incident when linearly polarized light E is incident at a fixed angle. However, after the light passes through the sample, the difference in refractive index between x and y causes a phase shift, which is the birefringence retardation. Δn = Ne - No, where Ne and No are characteristic parameters of the liquid crystal material.

[0048] The process of measuring the thickness of the liquid crystal cell by the system is as follows:

[0049] Spectral measurement of elliptically polarized light → Analyze the Re value at 10nm intervals within the wavelength range of 400nm to 800nm ​​→ Use the least squares method to calculate the fitting formula on this data to determine the Re at any wavelength.

[0050] The design of the liquid crystal cell thickness is related to the structural design of the post spacer (PS). Based on the structural design of the post spacer, it can be divided into ordinary panels and XPS panels. In the manufacturing process of ordinary liquid crystal display panels, it is necessary to separately manufacture the array substrate (TFT) and the color filter substrate (CF). Then, the edges of the color filter substrate and the array substrate are bonded together with a sealant, and the liquid crystal is filled in the area sealed by the sealant to realize the production of the liquid crystal display device. Among them, the pixel area used for display and between the pixel area and the sealant are provided with a post spacer (PS) that plays a supporting role. The PS is usually set on the color filter substrate. For liquid crystal display panels manufactured using XPS technology, a layer of post spacer PS is formed on each of the color filter substrate and the array substrate and abuts against each other. In some embodiments, the two PS abutting each other on the array substrate and the color filter substrate are set to approximately the same height. In some embodiments, the cross-section of the two PS abutting each other on the array substrate and the color filter substrate in the direction parallel to the display panel is set to stripe and crossed to optimize PS Mura (unevenness) and panel strength.

[0051] The cell gap of an XPS-designed liquid crystal display product is designed as follows: Cell Gap = PSH × 2 × PS compression ratio - pixel step difference + TFTPillow (3)

[0052] In the above formula, PSH (Photo Space Height) is the free height of the columnar spacer PS on the array substrate side (TFT side) or the color film substrate (CF side) before box alignment, and the two are designed to be the same height; the PS compression rate is the compression rate of the columnar spacer PS after box alignment, for example, the optional value of the compression rate is about 87%; the pixel step difference is the pixel step difference of the sub-pixel RGB after the OC (flat protection layer), which is the step difference between the sub-pixel RGB and the black matrix; TFTPillow is the height difference between the setting position of the spacer PS on the TFT substrate and the light-transmitting area of ​​the pixel Pixel.

[0053] Currently, the extremely low PSH technology can reduce the height of the spacer on one side of the XPS product to 0.9μm, that is, the PSH on one side ≥ 0.9μm. According to formula (3) and the common values ​​of pixel step difference and TFT Pillow, it can be seen that the liquid crystal cell thickness of the XPS liquid crystal display panel will not be less than 1.57μm.

[0054] For common LCD products, a cell gap design is: Cell Gap = PSH × Compression Ratio - Pixel Step Difference + TFT Pillow (4)

[0055] Here, PSH (Photo Space Height) is the height of the columnar spacers PS on the color filter substrate side. Similarly, if PSH is no less than 0.9μm, it can be determined that the liquid crystal cell thickness of a typical LCD panel will not be less than 0.78μm.

[0056] As can be seen from the above, there are many factors that influence the cell gap, including the TFT pillow, CF color resistance step difference, spacer height, etc., and the internal liquid crystal volume is also an influencing factor. With the development of high-refresh display products, the demand for smaller cell gaps is increasing. Therefore, the deviation of cell gap design accuracy has a more significant impact on high-refresh display products.

[0057] In order to solve the above problems, in the first aspect, referring to FIG. 2 , the present disclosure provides a display panel, comprising an array substrate 10, a color filter substrate 20, and a liquid crystal layer LC located between the array substrate 10 and the color filter substrate 20. The liquid crystal cell thickness of the liquid crystal layer LC in the light-transmitting area of ​​the display panel satisfies the following conditions: when the refresh rate of the display panel is greater than or equal to 60 Hz and does not exceed 480 Hz, the inverse of the refresh rate of the display panel and the liquid crystal cell thickness conform to a quadratic polynomial relationship.

[0058] The relationship between the liquid crystal cell thickness and the refresh rate provided in the embodiments of the present disclosure is determined from the following sources:

[0059] A higher refresh rate for a display panel means a smaller or faster response time is required. Response time is the time it takes for an LCD to react to an input signal, that is, the time it takes for a pixel to change from dark to bright or from bright to dark. The smaller the response time, the faster the response speed when switching between screens, and the smoother the screen switching.

[0060] [Corrected 03.03.2025 in accordance with Rule 26] The formula for response time is as follows:

[0061] In formulas (5) and (6):

[0062] τ r Rise time refers to the time interval from when the brightness drops from 90% to 10% (normally white mode) or when it rises from 10% to 90% (normally black mode) during the process from power off to power on.

[0063] τ d Delay time, which indicates the time interval when the brightness reaches 10% of the maximum brightness during power off.

[0064] γ1: viscosity coefficient of liquid crystal material;

[0065] d: LCD cell thickness;

[0066] V: driving voltage;

[0067] V th : threshold voltage;

[0068] Δε: Dielectric constant of liquid crystal material.

[0069] [Corrected 03.03.2025 according to Rule 26] Let τ on =τ r +τ d , the refresh rate is f, then:

[0070] [Corrected 03.03.2025 in accordance with Rule 26] namely:

[0071] It can be seen that under the premise of the same liquid crystal material and driving voltage, the response time τ on，off It is proportional to the square of the thickness d of the liquid crystal cell, and the refresh rate is inversely correlated with the square of d.

[0072] Combining the above theoretical derivation, we conducted liquid crystal cell thickness design, simulation, and data verification. By integrating the data, we found that when the refresh rate is in the range of [60Hz, 480Hz], the following fitting relationship is obtained: 1 / f=C2×d 2 +C1×d+C0 (9)

[0073] In the above formula, f is the refresh rate in Hz; d is the thickness of the liquid crystal cell in μm; the value range of C2 is [0.003, 0.004], the value range of C1 is [-0.02, -0.01], and the value range of C0 is [0.01, 0.02].

[0074] Optionally, the coefficient term is: C2 = 0.0038, C1 = -0.0127, C2 = 0.0125, which satisfies: 1 / f = 0.0038d 2 –0.0127d+0.0125 (10)

[0075] The determination coefficient R of the fitting relationship of formula (10) 2 =0.9999, as shown in Figure 3; the coefficient of determination R 2 The numerical value of reflects the degree of fit between the estimated value of the trend line and the corresponding actual data. When the square value of R is equal to or close to 1, it indicates the highest reliability, otherwise the reliability is low.

[0076] According to equations (9) and (10), the display panel provided by the present disclosure has a liquid crystal cell gap (cell gap) designed to construct a quadratic polynomial fitting relationship between the inverse of the refresh rate and the liquid crystal cell gap when the refresh rate of the display panel is greater than or equal to 60 Hz and not more than 480 Hz. Compared with the conventional design of the liquid crystal cell gap based on the TFT Pillow, the color resistance step difference, the spacer height and the amount of liquid crystal, the influencing factors of the liquid crystal cell gap are significantly reduced, which is conducive to reducing the design complexity of the liquid crystal cell gap and improving the design accuracy, thereby improving the design efficiency of liquid crystal display products and providing a new cell gap design benchmark.

[0077] Optionally, for high-refresh display products with a refresh rate f greater than 480Hz, such as [480Hz, 1000Hz], the value range of the liquid crystal box thickness is [1.044μm, 1.6μm]. The trend is that the higher the refresh rate, the smaller the value of the liquid crystal box thickness. In some embodiments, under the premise of meeting the refresh rate, a higher liquid crystal box thickness can also be selected. The higher the liquid crystal box thickness, the higher the product transmittance. In addition, the liquid crystal box thickness can also be adjusted according to the customer's grayscale response time (GTG, gray to gray) requirements. According to the corresponding relationship between the liquid crystal box thickness and the refresh rate of the embodiment of the present disclosure, the range of the liquid crystal box thickness Cell Gap is 1.044μm to 3.8μm.

[0078] The correspondence between liquid crystal cell thickness and refresh rate provided in the embodiments of the present disclosure can be applied to both ordinary liquid crystal display panels and XPS liquid crystal display panels. Taking XPS liquid crystal display products used in notebook computers as an example, the common refresh rate range is 60Hz to 360Hz, with ≥120Hz being considered a high refresh rate product. The liquid crystal cell thickness requirement for high refresh rate products is also related to response time. When determining the liquid crystal material, the faster the response time and the higher the refresh rate, the lower the liquid crystal cell thickness.

[0079] The liquid crystal box thickness of some XPS LCD display products is designed as follows: the liquid crystal box thickness of 60Hz NB products is about 3.6μm, the liquid crystal box thickness of 90Hz NB products is about 3.18μm, the liquid crystal box thickness of 120Hz NB products is about 2.92μm, the liquid crystal box thickness of 240Hz NB products is about 2.4μm (GTG is 3ms), the liquid crystal box thickness of 360Hz NB products is about 2.0μm (GTG is 2ms), and the liquid crystal box thickness of 480Hz NB products is about 1.6μm (GTG is 1ms).

[0080] In order to ensure that there is a sufficient liquid crystal safety margin (LC Margin) for the display screen, the main spacer Main PS and the sub-spacer Sub PS can be set in the PS layer on the TFT side and the CF side respectively for the XPS liquid crystal display panel, where the Sub PS is thinner or lower in height; but if the Sub PS is too thin or too low, it is easy to cause problems such as Sub PS missing, morphological deformation or molding failure, as shown in Figure 4. In order to avoid Sub PS missing, its height should be controlled at more than 0.5μm. Therefore, the liquid crystal box thickness Cell Gap cannot be reduced indefinitely. If it is too small, it is easy to cause problems such as PS missing during production. The current extremely low PSH technology can reduce the Main PS height of XPS products to 0.9μm while ensuring that Sub PS is not missing.

[0081] For XPS liquid crystal display panels, on the one hand, PS layers are designed on the TFT side and the CF side respectively, which reduces the height of the PS layer on one side. On the other hand, due to the increase in refresh rate, the thickness of the liquid crystal box needs to be further reduced, which requires further reducing the height of the PS layer on one side. As mentioned above, if the height of the PS layer is too low, the process capability cannot be met, and the problem of PS missing is likely to occur, which will also limit the design of the liquid crystal box thickness.

[0082] To solve the above problem, in some embodiments, referring to FIG. 5 , a liquid crystal display panel having an XPS structure is provided, wherein a spacer layer is formed by combining a main spacer (Main PS) and a sub-spacer (Sub PS), including:

[0083] The array substrate 10 includes a first substrate 11 and a first spacer layer PS1, and the first spacer layer PS1 is arranged on the side of the first substrate 11 close to the color filter substrate 20; the color filter substrate 20 includes a second substrate 21 and a second spacer layer PS2, and the second spacer layer PS2 is arranged on the side of the second substrate 21 close to the array substrate 10; the first spacer layer PS1 includes at least one first main spacer Main PS1 and multiple first sub-spacers Sub PS1, and the first main spacer Main PS1 and the first sub-spacer Sub PS1 are arranged alternately; the second spacer layer PS2 includes at least one second main spacer Main PS2 and multiple second sub-spacers Sub PS2, and the second main spacer Main PS2 and the second sub-spacer Sub PS2 are arranged alternately; the first main spacer Main PS1 and the second main spacer Main PS2 are abutted, and the first sub-spacer Sub PS1 and the second sub-spacer Sub PS2 are arranged opposite to each other.

[0084] In some embodiments, the first substrate 11 is the base of the array substrate 10, also known as the base substrate or TFT substrate, and a transparent glass substrate TFT Glass can be used; the second substrate 21 is the base of the color filter substrate 20, also known as the CF substrate, and a transparent glass substrate CF Glass can also be used.

[0085] The structural options for the main and auxiliary spacers include:

[0086] ① When the PS step is formed on the color filter substrate 20 side (CF), as shown in FIG5 , the spacers on the TFT side are of equal height, that is, the first main spacer Main PS1 and the first sub-spacer Sub PS1 are of equal height, and the first main spacer Main PS1 can be designed to be thicker than the first sub-spacer Sub PS1; the spacers on the CF side are of unequal height, and the second sub-spacer Sub PS2 is lower than the second main spacer Main PS2; after the LCD panels are assembled, the first main spacer Main PS1 and the second main spacer Main PS2 are arranged to abut against each other, and the first sub-spacer Sub PS1 and the second sub-spacer Sub PS2 are arranged to face each other;

[0087] ② When the PS step difference is formed on the array substrate 10 side (TFT), the spacers on the CF side are of the same height, that is, the second main spacer Main PS2 and the second sub-spacer Sub PS2 are of the same height, and the second main spacer Main PS2 is thicker than the second sub-spacer Sub PS2; the spacers on the TFT side are of different heights, and the height of the first sub-spacer Sub PS1 is lower than that of the first main spacer Main PS1; after the liquid crystal panels are assembled, the first main spacer Main PS1 and the second main spacer Main PS2 are offset against each other, and the first sub-spacer Sub PS1 and the second sub-spacer Sub PS2 are opposite to each other.

[0088] Taking the first main spacer MainPS1 and the first sub-spacer SubPS1 as an example, the thicker first main spacer MainPS1 means that its cross-sectional area is larger than that of the first sub-spacer SubPS1 in the plane of the display panel. Both the first main spacer MainPS1 and the first sub-spacer SubPS1 can be designed as columnar structures, with cross-sections of the columnar structures being triangular, polygonal, circular, or elliptical, depending on actual needs. The first main spacer MainPS1 and the first sub-spacer SubPS1 can be spaced apart, with multiple first sub-spacers SubPS1 arranged between two first main spacers MainPS1, as shown in Figure 6, or multiple first main spacers MainPS1 arranged between two first sub-spacers SubPS1. The preferred solution is the former. The quantity ratio of the first main spacer Main PS1 to the first sub-spacer Sub PS1 can be determined according to actual needs. For example, the quantity ratio of the first main spacer Main PS1 to the first sub-spacer Sub PS1 is set to 1:10~300, which is not limited in the embodiment of the present disclosure.

[0089] When the shapes of the first main spacer MainPS1, the first sub-spacer SubPS1, the second main spacer MainPS2 and the second sub-spacer SubPS2 are designed using the above solution, the liquid crystal margin LC of the liquid crystal display panel can be further increased.

[0090] In some embodiments, the first main spacer Main PS1 and the first sub-spacer Sub PS1 on the TFT side, and the second main spacer MainPS2 and the second sub-spacer Sub PS2 on the CF side can be in the shape of strips, and their arrangement directions can be cross-shaped. For example, the offset first main spacer MainPS1 and the second main spacer MainPS2 are arranged in a cross-shaped pattern perpendicular to each other or in a non-cross-shaped pattern not perpendicular to each other, and the opposite first sub-spacer Sub PS1 and the second sub-spacer Sub PS2 are arranged in a cross-shaped pattern or a non-cross-shaped pattern. This can further optimize the PS mura problem and improve the panel strength.

[0091] The above solution provides an overall design of the spacer structure in the XPS liquid crystal display panel. Next, the film layer structures on the TFT side and the CF side are further described.

[0092] Regarding the film layer structure on the TFT side, in some embodiments, please refer to the schematic diagram of the stacked structure of the display panel shown in Figure 7. The array substrate 10 also includes a color resist layer (CRL) and an organic film layer (ORG) stacked on the first substrate 11. The organic film layer (ORG) is located between the color resist layer (CRL) and the first spacer layer (PS1). In other words, the array substrate 10 provided here is a COA substrate (Color Filter on Array), which is a technology that integrates the organic film layer (ORG) and the color resist layer (CRL) on the array substrate 10. The advantage of the COA substrate is that it eliminates the light leakage problem caused by the cell alignment and can effectively reduce the width of the black matrix layer (BM), thereby increasing the pixel aperture ratio and, in turn, the transmittance of the display panel.

[0093] Regarding the COA substrate, as shown in Figure 7 , the display panel includes a gate metal layer Gate, a gate dielectric layer GI, an amorphous silicon active layer a-Si, a source / drain metal layer SD, and a passivation layer PVX, stacked sequentially on a first substrate 11 (TFT substrate). These layers form thin-film transistors located in the display area AA' and those located in the peripheral area BB'. A color-resistance layer CRL and an organic film layer ORG are then stacked sequentially on the passivation layer. The color-resistance layer CRL located in the blue sub-pixel area is designated as the blue color-resistance layer B-CRL, the color-resistance layer CRL located in the green sub-pixel area is designated as the green color-resistance layer G-CRL, and the color-resistance layer CRL located in the red sub-pixel area is designated as the red color-resistance layer R-CRL. The color-resistance layer CRL and the organic film layer ORG form a color filter layer, which filters light and planarizes the opening area. A first spacer layer PS1 on the TFT side is disposed on the side of the organic film layer ORG that is closest to the color filter substrate 20. In addition, an ITO transparent electrode is stacked on the organic film layer ORG.

[0094] Since the RGB color filter layer in the COA substrate is arranged on the side of the TFT substrate and is planarized by the organic film layer ORG, the position of the spacer layer and the pixel opening area on the TFT side can ignore the pixel step difference.

[0095] It should be noted that the COA substrate integrates the color resist layer CRL into the TFT side of the array substrate 10. Although there is no color filter layer on the color film substrate 20 side, in order to facilitate the description and distinction of the array substrate 10 on the TFT side, it will still be referred to as the CF side in the following content.

[0096] In some embodiments, referring to FIG. 8A , a first groove 12 is provided on the organic film layer ORG, a first sub-spacer Sub PS1 is disposed within the first groove 12, and a first main spacer Main PS1 is disposed on the organic film layer ORG outside the first groove 12. The first groove 12 may be a blind hole formed by trenching in the organic film layer ORG, or a through hole penetrating the organic film layer ORG. A spacer material is then deposited to form the first sub-spacer Sub PS1 within the through hole or blind hole, and the first main spacer Main PS1 is formed on the organic film layer ORG outside the through hole or blind hole. By forming the first sub-spacer Sub PS1 in the first groove 12, on the one hand, the top surface of the first sub-spacer Sub PS1 can be made lower than the top surface of the first main spacer Main PS1 in the vertical direction of the array substrate 10, thereby forming a certain PS step difference between the first main spacer Main PS1 and the first sub-spacer Sub PS1, such as 0.45μm to 0.55μm, with a preferred value of 0.5μm. When this step difference is met, a normal mask can be used instead of a halftone mask to manufacture the first spacer layer PS1, thereby saving the mask production cost; on the other hand, while maintaining the PS step difference and further reducing the thickness of the liquid crystal cell, it can ensure that the height of the first sub-spacer Sub PS1 is not too low, thereby avoiding the problem of PS missing caused by the first sub-spacer Sub PS1 being too low.

[0097] In some embodiments, referring to FIG. 8B , more first grooves 12 can be provided on the organic film layer ORG, and both the first main spacer Main PS1 and the first sub-spacer Sub PS1 can be disposed within the first grooves 12, with a PS step difference formed between the first main spacer Main PS1 and the first sub-spacer Sub PS1. In this case, the second main spacer Main PS2 and the second sub-spacer Sub PS2 on the CF side can be designed with equal or approximately equal heights. This also allows the use of a normal mask instead of a halftone mask to manufacture the first spacer layer PS1, further reducing the cell thickness.

[0098] For the membrane structure on the CF side, the following two design options can be adopted:

[0099] Solution 1: Use the black matrix layer BM to form the second spacer layer PS2.

[0100] Please refer to Figures 7 and 9. The second main spacer Main PS2 and the second sub-spacer Sub PS2 include a black matrix layer BM, and the color filter substrate 20 includes a flat protective layer OC (Over Coat) covering the black matrix layer BM and the second substrate 21; in a direction perpendicular to the second substrate 21, the thickness of the black matrix layer BM is greater than the thickness of the flat protective layer OC covering the second substrate 21, and the flat protective layer OC in the second main spacer Main PS2 abuts against the first main spacer Main PS1.

[0101] The common XPS display panel design is to deposit a layer of PS material on the TFT side and the CF side to form a spacer layer. The display panel provided by Scheme 1 only needs to deposit a layer of PS material on the TFT side and make the first spacer layer PS1 through a composition process; and on the CF side, at a position opposite to the first spacer layer PS1 on the second substrate 21, a black matrix material thicker than conventional is deposited to form a second spacer layer PS2. Among them, the black matrix layer BM and the flat protective layer OC abutting the first main spacer Main PS1 form the second main spacer Main PS2, the black matrix layer BM and the flat protective layer OC opposite to the first sub-spacer Sub PS1 form the second sub-spacer Sub PS2, and the other black matrix layers BM can be used normally as a light-shielding structure. Therefore, Scheme 1 does not need to deposit PS material on the CF side to form the second spacer layer PS2, which can save a PS Mask process, thereby reducing manufacturing costs and improving production efficiency.

[0102] Figure 9 shows the film structure of the second main spacer Main PS2 and the second sub-spacer Sub PS2 formed by the black matrix layer BM and the flat protection layer OC. The height of the second spacer layer PS2 on the CF side can be adjusted by the thickness of the black matrix layer BM and the flat protection layer OC.

[0103] In some embodiments, the second main spacer Main PS2 and the second sub-spacer Sub PS2, formed using a black matrix layer BM and a flat overcoat layer OC, can be of equal or unequal heights, depending on whether the PS step is formed on the TFT side or the CF side. Optionally, the sum of the thicknesses of the black matrix layer BM and the flat overcoat layer OC in the second main spacer Main PS2 after cell alignment should not deviate from the height of the first main spacer Main PS1 after cell alignment by more than 20%. In other words, the first main spacer Main PS1 and the second main spacer Main PS2 can be designed with equal or approximately equal heights.

[0104] Considering that the first main spacer Main PS1 formed by the deposition of PS material will be compressed after cell alignment, while the black matrix layer BM will hardly be compressed, for the LCD panel of XPS combined with COA in Scheme 1, it is satisfied that the product of the height of the first main spacer Main PS1 before cell alignment and the compression rate after cell alignment, and the sum of the height of the second main spacer Main PS2 is equal to the thickness of the liquid crystal cell, that is: d = H1 × k + H t (11)

[0105] In the above formula, d is the thickness of the liquid crystal cell, H1 is the free height of the first main spacer Main PS1 before the cell is aligned, H t is the height of the second main spacer Main PS2, which is equal to the height of the black matrix layer BM after box alignment, or the sum of the heights of the black matrix layer BM and the flat protective layer OC after box alignment. k is the compression rate of the first main spacer MainPS1 after box alignment. The value range of k is 0.86~0.88, such as 0.87.

[0106] Equation (11) also indicates that the sum of the free height of the first main spacer Main PS1 on the TFT side before cell alignment or after disassembly, and the height of the second main spacer Main PS2, is greater than the liquid crystal cell thickness d, i.e., the thickness of the opening region. Furthermore, as shown in Figure 7, the first main spacer Main PS1 on the TFT side is positioned above the TFT device in the pixel region, which helps reduce the thickness of the opening region.

[0107] In some embodiments, the height PSH(H1×k) of the first main spacer Main PS1 on the TFT side after being compressed by cell alignment is equal to or approximately equal to the height Ht of the second main spacer Main PS2 on the CF side, to ensure that the PS layer height on one side is not too small, resulting in PS missing. Approximately equal means that the deviation between the height PSH1 of the first main spacer Main PS1 after cell alignment and the height Ht of the second main spacer Main PS2 after cell alignment does not exceed 10%.

[0108] It should be noted that if the height PSH of the first main spacer Main PS1 on the TFT side is ≥ 0.9μm and is consistent with the height of the second main spacer Main PS2 (the sum of the thicknesses of the black matrix layer BM and the flattening overcoat layer OC), the first main spacer Main PS1 and the first sub-spacer Sub PS1 can have different heights, forming the PS step on the TFT side. Because COA products can planarize the array substrate 10 using the color resist layer CRL and the organic film layer ORG, the pixel step can be ignored when positioning the first spacer layer PS1 and the pixel opening area on the TFT side. In this case, the cell gap can be controlled to no less than 1.56μm.

[0109] Solution 2: deposit PS material to form a second spacer layer PS2.

[0110] Please refer to Figure 10. The color filter substrate 20 includes a black matrix layer BM and a flat protective layer OC arranged on the side of the second substrate 21 close to the array substrate 10. The black matrix layer BM is located between the second substrate 21 and the flat protective layer OC; a second groove 22 is provided on the flat protective layer OC, and a second sub-spacer Sub PS2 is arranged in the second groove 22. The second main spacer Main PS2 is arranged on the flat protective layer OC outside the second groove 22.

[0111] In some embodiments, the width or area of ​​the black matrix layer BM is greater than the second spacer layer PS2 on the CF side. The orthographic projection of the second groove 22 on the second substrate 21 is located within the orthographic projection of the black matrix layer BM on the second substrate 21, that is, the second groove 22 is located above the black matrix layer BM. The second groove 22 can be a blind hole formed by trenching in the flat protective layer OC or a through hole extending through the flat protective layer OC, and can be designed according to actual needs. Spacer material is deposited in the second groove 22 to form a second sub-spacer Sub PS2. The orthographic projection of the second sub-spacer Sub PS2 on the second substrate 21 is located within the orthographic projection of the second groove 22 on the second substrate 21.

[0112] In some embodiments, the top surface of the second sub-spacer Sub PS2 located within the second groove 22 is lower than the top surface of the second main spacer Main PS2 in the vertical direction of the color filter substrate 20 or in the thickness direction of the color filter substrate 20. Specifically, the upper surface of the second sub-spacer Sub PS2 is lower than the upper surface of the surrounding second main spacers Main PS2, and the height difference between the two is approximately 0.45 μm to 0.55 μm. This creates a PS step on the color filter substrate 20 side, with a preferred value of 0.5 μm. This eliminates the need for a halftone mask and allows the use of a normal mask in the CF-side spacer, saving mask production costs. Furthermore, it allows the second main spacer Main PS2 and the second sub-spacer Sub PS2 to be designed even lower, further reducing the liquid crystal cell thickness while avoiding PS loss caused by the low height of the second sub-spacer Sub PS2. Studies have shown that PS loss is more likely to occur when the height of the second sub-spacer Sub PS2 is less than or equal to 0.5 μm. It should be noted that, since the PS step is formed on the color filter substrate 20 side, the top surfaces of the first main spacer Main PS1 and the first sub-spacer Sub PS1 are designed to be at the same height in the vertical direction or thickness direction on the array substrate 10 side.

[0113] A micrograph of the second sub-spacer Sub PS2 can be seen in Figure 11. The second sub-spacer Sub PS2 "stands" within a blind hole or trench in the flat overcoat layer OC. The trench depth can be adjusted based on design requirements to ensure that the top surface of the second sub-spacer Sub PS2 is approximately 0.5μm lower than the top surface of the surrounding second main spacer Main PS2, forming a perfect PS step. Based on this, the actual height of the second sub-spacer Sub PS2 can be designed to be equal to the actual height of the second main spacer Main PS2 to ensure that the second sub-spacer Sub PS2 is not missing. In this case, the minimum height of the second main spacer Main PS2 and the second sub-spacer Sub PS2 can be reduced to 0.6μm, significantly reducing the cell thickness.

[0114] When the heights of the first main spacer Main PS1 and the second main spacer Main PS2 are the same, the cell thickness Cell Gap satisfies: d = H1 × 2 × PS compression ratio (12)

[0115] H1 in formula (12) is the free height of the first main spacer Main PS1 on the TFT side before cell alignment, and is equal to the free height of the second main spacer Main PS2 before cell alignment and compression.

[0116] At this moment, if the PS compression ratio is 0.87, then d = 0.6 × 2 × 0.87 = 1.044 μm, so the liquid crystal cell thickness d can be controlled to a minimum of 1.044 μm, that is, d ≥ 1.044 μm.

[0117] In general, the XPS-based liquid crystal display panel provided in the above embodiments has the following characteristics:

[0118] 1) The color resist layer CRL is fabricated on one side of the array substrate 10 and planarized in combination with the organic film layer ORG. This eliminates the need to consider the effect of pixel step difference when designing the cell thickness. Furthermore, the influence of the TFT Pillow is eliminated, thus simplifying the influencing factors of the cell gap and enabling the cell thickness to be controlled to ≥1.56 μm.

[0119] 2) A first groove 12 is provided on the organic film layer ORG on the TFT side, and a first sub-spacer Sub PS1 is formed in the first groove 12, or a second groove 22 is provided on the flat protective layer OC on the CF side, and a second sub-spacer Sub PS2 is formed in the second groove 22. In this way, when the actual heights of the first main spacer MainPS1 and the first sub-spacer Sub PS1 on the TFT side are equal or similar, and the actual heights of the second main spacer Main PS2 and the second sub-spacer Sub PS2 on the CF side are equal or similar, a PS step difference is formed between the main spacer Main PS and the sub-spacer Sub PS by means of the first groove 12 or the second groove 22. On the one hand, a Normal Mask can be used instead of a Halftone Mask to prepare the PS layer, thereby saving the Mask production cost. On the other hand, the main spacer Main PS and the sub-spacer Sub PS can be designed to be lower, which can further reduce the thickness of the liquid crystal cell while avoiding the PS loss caused by the excessively low height of the Sub PS, thereby reducing the thickness of the liquid crystal cell. The gap is reduced from 1.5μm to 1.044μm, allowing XPS products to break through existing limitations and be designed towards higher refresh rates.

[0120] The above solution provides a structural design for the COA substrate. For a common display panel with a color filter layer (CRL) on the CF side, the following design can be adopted:

[0121] In some embodiments, referring to FIG. 12 , the color filter substrate 20 includes a black matrix layer BM and a color resist layer CRL disposed on the same layer on a second substrate 21, and a flat protective layer OC covering the black matrix layer BM and the color resist layer CRL; a second main spacer Main PS2 and a second sub-spacer Sub PS2 are disposed on the color resist layer CRL, and their orthographic projections on the second substrate 21 are located within the orthographic projections of the black matrix layer BM on the second substrate 21; in a direction perpendicular to the second substrate 21, the sum of the thicknesses of the black matrix layer BM and the flat protective layer OC is less than the sum of the thicknesses of the color resist layer CRL and the flat protective layer OC.

[0122] The black matrix layer BM is arranged in the non-light-transmitting area of ​​the color filter substrate 20, the color resist layer CRL is arranged in the light-transmitting area of ​​the color filter substrate 20, and the second main spacer Main PS2 and the second sub-spacer Sub PS2 are arranged on the flat protective layer OC directly above the black matrix layer BM. The bottom area of ​​the second main spacer Main PS2 and the second sub-spacer Sub PS2 is smaller than the area of ​​the black matrix layer BM to avoid affecting light transmission.

[0123] This solution does not dig grooves on the flat protective layer OC, but instead thins the total thickness of the black matrix layer BM and the flat protective layer OC at the second main spacer Main PS2 and the second sub-spacer Sub PS2, making it smaller than the total thickness of the color resist layer CRL and the flat protective layer OC in the surrounding area. While reducing the overall height of the second spacer layer PS2 and reducing the thickness of the liquid crystal cell, it also saves a groove digging process.

[0124] In some embodiments, the thickness of the flat protective layer OC located directly above the black matrix layer BM is greater than the thickness of the flat protective layer OC located directly above the color resist layer CRL outside the BM area. The second main spacer Main PS2 and the second sub-spacer Sub PS2 are arranged on the flat protective layer OC located directly above the black matrix layer BM. This can make the structure under the spacer more stable and not easy to peel off.

[0125] Optionally, a groove may be dug on the flat protective layer OC to provide a second main spacer Main PS2 and a second sub-spacer Sub PS2, which can also reduce the overall height of the second spacer layer PS2, thereby reducing the thickness of the liquid crystal cell.

[0126] It should be noted that the structure adopted in this case has alignment layers provided on both the upper and lower sides of the liquid crystal layer LC, and the alignment layers and the liquid crystal layer are in direct contact. Because one alignment layer has a uniform thickness, this case is not shown in the figure, nor is its thickness considered. Its existence is ignored in the description of the embodiment, but this does not mean that it does not actually exist.

[0127] In the second aspect, referring to FIG13 , the present disclosure provides a display device comprising the display panel provided in the embodiment of the first aspect. The display device can be an electronic device with a display screen, such as a desktop monitor, an all-in-one computer, a laptop, a tablet computer, an all-in-one conference machine, or a smartphone.

[0128] Although some embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including some embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0129] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A display panel, comprising an array substrate, a color filter substrate and a liquid crystal layer located between the array substrate and the color filter substrate; the liquid crystal layer in the light-transmitting area of ​​the display panel has a liquid crystal cell thickness that satisfies: When the refresh rate of the display panel is greater than or equal to 60 Hz and does not exceed 480 Hz, the reciprocal of the refresh rate of the display panel and the liquid crystal cell thickness conform to a quadratic polynomial relationship.

2. The display panel according to claim 1, wherein: The liquid crystal cell thickness and the refresh rate satisfy: 1 / f = C2×d 2 +C1×d+C0; In the above formula, f is the refresh rate, in Hz; d is the thickness of the liquid crystal box, in μm; the value range of C2 is 0.003 to 0.004, the value range of C1 is -0.02 to -0.01, and the value range of C0 is 0.01 to 0.

02.

3. The display panel according to claim 1, wherein: When the refresh rate of the display panel is greater than 480 Hz and does not exceed 1000 Hz, the thickness of the liquid crystal cell ranges from 1.044 μm to 1.6 μm.

4. The display panel according to claim 1, wherein: The array substrate comprises a first substrate and a first spacer layer, wherein the first spacer layer is arranged on a side of the first substrate close to the color filter substrate; the color filter substrate comprises a second substrate and a second spacer layer, wherein the second spacer layer is arranged on a side of the second substrate close to the array substrate; The first spacer layer includes at least one first main spacer and multiple first sub-spacers, and the first main spacer is spaced apart from the first sub-spacers; the second spacer layer includes at least one second main spacer and multiple second sub-spacers, and the second main spacer is spaced apart from the second sub-spacers; the first main spacer is in contact with the second main spacer, and the first sub-spacer is opposite to the second sub-spacer.

5. The display panel according to claim 4, wherein: The array substrate further includes a color resist layer and an organic film layer stacked on the first substrate, and the organic film layer is located between the color resist layer and the first spacer layer.

6. The display panel according to claim 5, wherein: A first groove is provided on the organic film layer, the first sub-spacer is arranged in the first groove, and the first main spacer is arranged on the organic film layer outside the first groove.

7. The display panel according to claim 4, wherein: The second main spacer and the second sub-spacer include a black matrix layer, and the color film substrate includes a flat protective layer covering the black matrix layer and the second substrate; in a direction perpendicular to the second substrate, the thickness of the black matrix layer is greater than the thickness of the flat protective layer covering the second substrate, and the flat protective layer on the second main spacer abuts against the first main spacer.

8. The display panel according to claim 7, wherein: The deviation between the sum of the thickness of the black matrix layer in the second main spacer and the flat protection layer after cell alignment and the height of the first main spacer after cell alignment does not exceed 20%.

9. The display panel according to claim 4, wherein: The color filter substrate comprises a black matrix layer and a flat protective layer arranged on a side of the second substrate close to the array substrate, wherein the black matrix layer is located between the second substrate and the flat protective layer; The flat protective layer is provided with a second groove, the second auxiliary spacer is arranged in the second groove, and the second main spacer is arranged on the flat protective layer outside the second groove.

10. The display panel according to claim 4, wherein: The color filter substrate comprises a black matrix layer and a color resist layer disposed on the second substrate, and a flat protective layer covering the black matrix layer and the color resist layer; the second main spacer and the second auxiliary spacer are disposed on the color resist layer, and the orthographic projection of the second spacer on the second substrate is located within the orthographic projection of the black matrix layer on the second substrate; In a direction perpendicular to the second substrate, the sum of the thicknesses of the black matrix layer and the flat protection layer is less than the sum of the thicknesses of the color resist layer and the flat protection layer.

11. The display panel according to claim 4, wherein: In the vertical direction of the color filter substrate, the top surface of the second sub-spacer is lower than the top surface of the second main spacer, and the height difference is 0.45μm to 0.55μm; or, in the vertical direction of the array substrate, the top surface of the first sub-spacer is lower than the top surface of the first main spacer, and the height difference is 0.45μm to 0.55μm.

12. The display panel according to claim 4, wherein: The product of the height of the first main spacer before aligning the box and the compression rate after aligning the box, and the sum of the height of the second main spacer after aligning the box are equal to the thickness of the liquid crystal box, and the compression rate ranges from 0.86 to 0.

88.

13. The display panel according to claim 4, wherein: The deviation between the height of the first main spacer after the box is assembled and the height of the second main spacer after the box is assembled does not exceed 10%.

14. The display panel according to claim 4, wherein: The first main spacer is as high as the first secondary spacer, and the second secondary spacer is lower than the second main spacer; or The second sub-spacer and the second main spacer are of the same height, and the first sub-spacer is lower than the first main spacer.

15. A display device comprising the display panel according to any one of claims 1 to 14.

Images