Method and system for processing task to be processed, and storage medium and electronic apparatus

Abstract

Provided in the embodiments of the present disclosure are a method and system for processing a task to be processed, and a storage medium and an electronic apparatus. The method for processing a task to be processed comprises: on the basis of parameter information and demand information of a task to be processed, determining an instruction set corresponding to the task to be processed, wherein the demand information is used for indicating a processing result corresponding to the task to be processed; determining a first instruction address of each instruction to be executed in the instruction set; and on the basis of the first instruction address of each instruction to be executed, executing each instruction to be executed, so as to process the task to be processed. By means of the present disclosure, the problem of the flexibility in designing a chip being relatively low is solved, thereby achieving the effect of improving the flexibility of the chip.

Description

Method and system for processing pending tasks, storage medium, and electronic device

[0001] This disclosure claims priority to the Chinese patent application filed with the China Patent Office on August 15, 2023, with application number 202311034305.X and invention name “Method and system for processing pending tasks, storage medium and electronic device”, the entire contents of which are incorporated by reference in this disclosure. Technical Field

[0002] The embodiments of the present disclosure relate to the field of communications, and in particular, to a method and system for processing tasks to be processed, a storage medium, and an electronic device. Background Art

[0003] Existing large-scale ASIC chips generally use a CPU processor plus hardware accelerator design. The CPU is large in area and power-hungry, but highly versatile. Its performance is low when handling complex services, and it generally handles flexible and changeable services. For specific or less flexible complex services, hardware accelerators are generally used to implement them, which can improve performance, save power and area, but the disadvantage is inflexibility.

[0004] A major design challenge for ASIC chips is the division between software and hardware—specifically, determining which services are implemented by the CPU and which by hardware accelerators. Because chip development cycles are long, and commercial scenarios often differ significantly from those used in the initial design phase, a certain degree of flexibility must be reserved during the initial chip design phase. However, this increases chip costs, creating a dilemma.

[0005] In view of the low flexibility of chip design and other issues in related technologies, no effective solutions have been proposed yet.

[0006] Summary of the Invention

[0007] The embodiments of the present disclosure provide a method and system for processing a task to be processed, a storage medium, and an electronic device, so as to at least solve the problem of low flexibility in chip design in related technologies.

[0008] According to one embodiment of the present disclosure, a method for processing a task to be processed is provided, which is applied to a hardware accelerator, and includes: determining an instruction set corresponding to the task to be processed based on parameter information and requirement information of the task to be processed, wherein the requirement information is used to indicate a processing result corresponding to the task to be processed; determining a first instruction address of each instruction to be executed in the instruction set; and executing each instruction to be executed based on the first instruction address of each instruction to be executed to process the task to be processed.

[0009] According to another embodiment of the present disclosure, a processing system for tasks to be processed is provided, including: an instruction extraction unit, configured to determine an instruction set corresponding to the task to be processed based on parameter information and requirement information of the task to be processed, wherein the requirement information is used to indicate a processing result corresponding to the task to be processed; determining an instruction address of each instruction to be executed in the instruction set; and an execution unit, configured to execute each instruction to be executed according to the instruction address of each instruction to be executed to process the task to be processed.

[0010] According to another embodiment of the present disclosure, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above method embodiments when running.

[0011] According to another embodiment of the present disclosure, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any one of the above method embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG1 is a hardware structure block diagram of a computer terminal for a method for processing tasks to be processed according to an embodiment of the present disclosure;

[0013] FIG2 is a flowchart of a method for processing a task to be processed according to an embodiment of the present disclosure;

[0014] FIG3 is a flowchart of a method for processing a task to be processed according to an optional embodiment of the present disclosure;

[0015] FIG4 is a diagram showing the internal structure of a hardware accelerator according to an embodiment of the present disclosure;

[0016] FIG5 is a schematic diagram of a general register according to an embodiment of the present disclosure;

[0017] FIG6 is a schematic diagram of an instruction according to an embodiment of the present disclosure (I);

[0018] FIG7 is a schematic diagram of an instruction according to an embodiment of the present disclosure (II);

[0019] FIG8 is a schematic diagram of an instruction according to an embodiment of the present disclosure (III);

[0020] FIG9 is a schematic diagram of an instruction according to an embodiment of the present disclosure (four);

[0021] FIG10 is a schematic diagram of an instruction according to an embodiment of the present disclosure (V);

[0022] FIG11 is a schematic diagram of an instruction according to an embodiment of the present disclosure (VI);

[0023] FIG12 is a schematic diagram of an instruction according to an embodiment of the present disclosure (VII);

[0024] FIG13 is a schematic diagram of a packet header format according to an embodiment of the present disclosure;

[0025] FIG14 is a structural block diagram of a system for processing tasks to be processed according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0028] The method embodiments provided in the embodiments of the present disclosure can be executed in a computer terminal or a similar computing device. Taking running on a computer terminal as an example, FIG1 is a hardware structure block diagram of a computer terminal of a method for processing a task to be processed according to an embodiment of the present disclosure. As shown in FIG1 , the computer terminal may include one or more (only one is shown in FIG1 ) processors 102 (the processor 102 may include but is not limited to a hardware accelerator, a microprocessor (Central Processing Unit, MCU), a programmable logic device (Field Programmable Gate Array, FPGA), an application-specific integrated circuit (Application-Specific Integrated Circuit, ASIC), a digital signal processor, a floating-point arithmetic unit, a coprocessor, a multi-core processor, a multi-threaded processor, etc.) and a memory 104 for storing data, wherein the above-mentioned computer terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It will be understood by those skilled in the art that the structure shown in FIG1 is only illustrative and does not limit the structure of the above-mentioned computer terminal. For example, the computer terminal may also include more or fewer components than shown in FIG1 , or have a configuration different from that shown in FIG1 .

[0029] The memory 104 can be configured to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the processing method of the task to be processed in the embodiment of the present disclosure. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implements the above-mentioned method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0030] The transmission device 106 is configured to receive or transmit data via a network. A specific example of the aforementioned network may include a wireless network provided by a computer terminal's communications provider. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module configured to communicate with the Internet wirelessly.

[0031] In this embodiment, a method for processing pending tasks running on the above-mentioned computer terminal is provided. FIG2 is a flow chart of the method for processing pending tasks according to an embodiment of the present disclosure. As shown in FIG2 , the flow chart includes the following steps:

[0032] Step S202: determining an instruction set corresponding to the task to be processed based on parameter information and requirement information of the task to be processed, wherein the requirement information is used to indicate a processing result corresponding to the task to be processed;

[0033] It's important to note that task requirements information refers to the specific requirements and objectives of a task, including its content, timeframe, and quantity requirements. Parameter information refers to the parameters required for the task, including input and output parameters. Input parameters are the data required to execute the task, while output parameters are the results obtained after the task is completed. These parameters can be numbers, text, dates, files, and other types of data. During task execution, task execution and output are completed based on the requirements information and parameter information.

[0034] Step S204, determining the first instruction address of each instruction to be executed in the instruction set;

[0035] It should be noted that an instruction address refers to the address of a memory location or storage unit that indicates a specific instruction to be executed in a computer program. In a computer's instruction set architecture, each instruction has a unique address, which is used to load the instruction into the processor for execution. The instruction address can be represented as a number or a memory address, which is not limited in the present embodiment.

[0036] Step S206 : executing each of the instructions to be executed according to the first instruction address of each of the instructions to be executed, so as to process the task to be processed.

[0037] Through the above steps, when a computer terminal receives a pending task, it sends the pending task to the hardware accelerator located on the computer terminal. Because the hardware accelerator can determine the instruction set of the pending task based on preset instructions (i.e., it implements task programming for the pending task), it then processes the pending task by executing the instructions in the instruction set. In other words, the hardware accelerator can flexibly handle different tasks. Therefore, the problem of low chip design flexibility can be solved, thereby achieving the effect of improving chip flexibility.

[0038] The execution subject of the above steps may be a hardware accelerator in the terminal, etc., but is not limited thereto.

[0039] Optionally, the above step S202 can be implemented by the following steps:

[0040] Step 11: Determine multiple logical processing methods for the task to be processed based on the parameter information and requirement information;

[0041] Step 12: Determine the instructions corresponding to the multiple logical processing modes, and determine the multiple instructions as the instruction set.

[0042] That is, the above-mentioned multiple logical processing methods can be understood as methods for determining the results obtained after the task is completed according to the parameter information and requirement information of the task to be processed.

[0043] The above logical processing methods include but are not limited to:

[0044] 1. AND operation: When both logical values ​​are true, the result is true; otherwise, the result is false.

[0045] 2. OR operation: When at least one of the two logical values ​​is true, the result is true; otherwise, the result is false.

[0046] 3. NOT: Performs the inversion operation on a logical value, that is, true becomes false and false becomes true.

[0047] For example, taking the parsing of classified messages as an example, assuming that a message header format is as shown in Figure 13, where bits 0 to 11 are DA fields, used to indicate the destination address; bits 12 to 23 are SA fields, used to indicate the source address; bits 24 to 27 are type, used to indicate the frame type; bits 28 to 31 are subtype, used to indicate the frame subtype.

[0048] In the embodiment of the present disclosure, the message type is determined by the subtype field. For example, a message with subtype equal to 0 is classified into the first category, and other cases are classified into the second category.

[0049] Write the packet header to DTCM address 0 through the upstream logic.

[0050] The instructions are written as follows and written into the instruction cache memory (ITCM) by the main control CPU writing registers:

[0051] 0: ADDI(32'b000000000001_00000_000_00011_0010011) initializes the data in address 3 of regfile to 1;

[0052] 1: LW (32'b000000000000_00000_010_00001_0000011) reads the data in DTCM address 0 into regfile address 1. LW instruction: reads back 32-bit data from memory and writes it back to register rd;

[0053] 2: SLLI(32'b0000000_11100_00001_001_00010_0010011) shifts the data in regfile address 1 left by 28 bits and writes it to regfile address 2;

[0054] 3: SRLI (32'b0000000_11100_00010_101_00001_0010011) shifts the data in regfile address 2 right by 28 bits and writes it to regfile address 1;

[0055] 4: BEQI(32'b0000000_00000_00001_010_00010_1100111) If the data in address 1 of regfile is equal to 0, jump to line 6, otherwise jump to line 5;

[0056] 5: SW(32'b0000000_00000_00000_010_00001_0100011) writes 0 to DTCM address 1;

[0057] 6: SW (32'b0000000_00011_00000_010_00001_0100011) writes 1 to DTCM address 1.

[0058] After starting the device, the downstream only needs to read the data in DTCM address 1. If it is 0, it means that the message is the second type, and if it is 1, it means that the message is the first type.

[0059] Optionally, if the requirements for message classification change and DA, SA, and type need to be used as the basis for classification, you only need to modify the instruction combination in ITCM to complete the combination judgment of any field in the 32-bit packet header, and thus it is no longer subject to the requirements of traditional hardware logic, thereby improving the flexibility of the chip.

[0060] Optionally, the above step S208 can be implemented by the following steps:

[0061] Step 21: Processing step: obtaining a second instruction address in a program counter, wherein the program counter is used to store an instruction address of a next instruction to be executed;

[0062] Step 22: determining, in the instruction set according to the first instruction address of each to-be-executed instruction, the to-be-executed instruction corresponding to the second instruction address, and executing the to-be-executed instruction;

[0063] Step 23: Execute the processing steps in a loop until each instruction to be executed in the instruction set is completed.

[0064] It's important to note that the program counter is a register in a computer that stores the address of the currently executing instruction or the address of the next instruction. It increments continuously during instruction execution to indicate the location of the next instruction to be executed. As the computer executes an instruction, the program counter automatically increments to the address of the next instruction, allowing it to be retrieved and executed. The program counter's value is typically expressed in binary and is updated with every computer clock cycle. Therefore, the instruction to be executed is determined based on the instruction address in the program counter until all instructions have been executed.

[0065] Optionally, before obtaining the instruction set corresponding to the task to be processed, the instructions need to be written. Specifically, the instructions can be written in the following manner: determine the second instruction information of the instruction to be written, wherein the second instruction information includes at least one of the following: a second instruction code, a second source operand, a second target operand, and a second immediate value, the second instruction code is used to indicate the function of the instruction to be written, and the second source operand and the second target operand are used to indicate the read and write addresses of the instruction to be written; determine the instruction to be written based on the second instruction information.

[0066] The instructions to be written in the embodiments of the present disclosure include: DTCM read and write instructions, basic integer operation instructions (addition, comparison, OR, AND, shift), unconditional jump instructions, conditional jump instructions (equal, unequal, greater than, less than, greater than or equal to, less than or equal to).

[0067] The contents of the instructions to be written include:

[0068] 1) Instruction code (required), used to identify the action the instruction is intended to perform;

[0069] 2) Operation address (required), the read / write address of DTCM (equivalent to the source operand in the above embodiment) or the read / write address of regfile (equivalent to the target operand in the above embodiment);

[0070] ) immediate value (optional), a specific operand.

[0071] Optionally, the instruction to be executed is executed in the following manner, including: parsing the instruction to be executed to obtain first instruction information corresponding to the instruction to be executed, wherein the first instruction information includes at least one of the following: a first instruction code, a first source operand, a first target operand, and a first immediate value; generating a control signal corresponding to the first instruction information, and sending the control signal to the corresponding execution unit of the hardware accelerator to execute the instruction to be executed.

[0072] That is, in the embodiment of the present disclosure, the execution unit of the hardware accelerator executes the instruction to be executed, and the execution unit performs corresponding arithmetic and logical operations, such as addition, multiplication, displacement, logical operations, etc.

[0073] Specifically, generating a control signal corresponding to the first instruction information includes at least one of the following: when the first instruction information includes: the first instruction encoding and the first source operand, generating first sub-control information according to the type of the first instruction encoding, and generating a second sub-control signal for reading an operand register according to the first source operand, wherein the control signal includes: the first sub-control signal and the second sub-control signal; when the first instruction information includes: the first instruction encoding, the first source operand, and the first target operand, generating first sub-control information according to the type of the first instruction encoding, generating a second sub-control signal for reading an operand register according to the first source operand, and generating a third sub-control signal for writing to a general register according to the first target operand, wherein the control signal includes: the first sub-control signal, the second sub-control signal, and the third sub-control signal; when the first instruction information includes: the first instruction encoding, the first immediate value, and the first target operand, generating first sub-control information according to the type of the first instruction encoding, generating a fourth sub-control signal for reading the first immediate value, and generating a third sub-control signal for writing to a general register according to the first target operand, wherein the control signal includes: the first sub-control signal, the fourth sub-control signal, and the third sub-control signal.

[0074] It can be understood that the first sub-control signal is a control signal for implementing operations such as addition, multiplication, shift, and logical operations; the second sub-control signal is a control signal for reading the operand register; the third sub-control signal is a control signal for writing target information to the target location of the general register; and the fourth sub-control signal is a control signal for reading the first immediate value.

[0075] For example: The Add Immediate Instruction (ADDI) instruction is used to instruct the addition operation of the integer value in the operand register rs1 and the 12-bit immediate value (sign bit extended), and the result is written back to the register RD. The SW instruction is parsed, the first sub-control signal is the control signal for the addition operation, the second sub-control signal is the control signal for reading the integer value in the operand register rs1, and the third sub-control signal is the control signal for writing the result back to the general register RD.

[0076] In order to better understand the process of the method for processing the above-mentioned tasks to be processed, the implementation method flow of the processing of the above-mentioned tasks to be processed is described below in combination with optional embodiments, but it is not used to limit the technical solution of the embodiment of the present disclosure.

[0077] In this embodiment, a method for processing pending tasks is provided. FIG3 is a flow chart of the method for processing pending tasks according to an optional embodiment of the present disclosure. As shown in FIG3 , the details are as follows:

[0078] Read instructions, decode instructions, execute instructions, access memory, and write back results. The disclosed embodiment uses a two-stage pipeline, in which reading instructions uses 1 beat, and decoding, execution, memory access, and writing back all use 1 beat. The state machine is programmable through the arrangement of different instructions.

[0079] In this embodiment, a hardware accelerator for processing tasks to be processed is also provided. FIG4 is a diagram showing the internal structure of the hardware accelerator according to an embodiment of the present disclosure. As shown in FIG4 , the hardware accelerator specifically includes:

[0080] Data Tightly-Coupled Memory (DTCM), configured as a high-speed data cache;

[0081] Instruction Fetch Unit (IFU), configured to fetch instructions and jump the PC;

[0082] Instruction Tightly Coupled Memory (ITCM) is the instruction cache space that supports offline reading and writing;

[0083] Instruction Decode Unit: (DeCode for short), set to decode;

[0084] Execution Unit (EXU), configured to complete the execution of instructions;

[0085] The register file (Register File, referred to as RegFile for short) is set to complete the operation of the internal general register.

[0086] In order to improve the flexibility of the chip, the present disclosure imposes certain constraints on the input content (instructions). That is, an instruction design scheme is provided in the embodiments of the present disclosure. Specifically:

[0087] The instructions include DTCM read and write instructions, basic integer operation instructions (addition, comparison, OR, AND, shift), unconditional jump instructions, conditional jump instructions (equal, not equal, greater than, less than, greater than or equal to, less than or equal to).

[0088] The content of the instruction needs to include:

[0089] The instruction code (required), used to identify the action the instruction is intended to complete;

[0090] Operation address (required), DTCM read / write address or regfile read / write address;

[0091] Immediate value (optional), a specific operand;

[0092] regfile is a set of 32 32-bit general-purpose registers used with instructions. As shown in Figure 5, the general-purpose register at address 0 is always 0 and cannot be written. PC is the address of the instruction currently being processed.

[0093] In the disclosed embodiment, the CPU writes the designed instructions into the ITCM and starts the device; the IFU controls the instruction read address and reads the instruction; the DeCode completes the instruction parsing; and the EXU completes the instruction execution and data write back.

[0094] The instructions designed in the disclosed embodiments are based on the RV32I basic instruction set in RSIC-V, directly borrowing some instructions and supplementing some custom instructions. The instruction design can be freely defined and expanded. The necessary instructions are read and write instructions, basic logical operation instructions and jump instructions.

[0095] 1. Storage read and write instructions:

[0096] This group of instructions performs memory read or write operations. The address to access the memory is obtained by adding the value in the operand register rs1 to the 12-bit immediate value (sign bit extended).

[0097] The LW instruction, as shown in Figure 6, reads 32 bits of data from the memory and writes it back to register rd;

[0098] The SW instruction, as shown in Figure 7, writes the 32-bit data in operand register rs2 back to the memory;

[0099] 2. Basic integer operation instructions:

[0100] This group of instructions performs basic integer arithmetic operations on registers and immediate values.

[0101] The ADDI instruction, shown in Figure 8, adds the integer value in operand register rs1 to a 12-bit immediate value (sign-extended), writing the result back to register RD. If overflow occurs, no special handling is required; the overflowed bits are discarded, retaining only the lower 32 bits of the result.

[0102] The SLTIU instruction, shown in Figure 9, compares the integer value in operand register rs1 with the 12-bit immediate value (sign-extended) as an unsigned integer. If the value in rs1 is less than the immediate value, the result is 1; otherwise, it is 0, and the result is written back to register RD.

[0103] The ANDI instruction, as shown in Figure 9, performs an AND operation on the integer value in the operand register rs1 and the 12-bit immediate value (sign-extended), and writes the result back to the register rd.

[0104] The ORI instruction, as shown in Figure 9, performs an OR operation on the integer value in the operand register rs1 and the 12-bit immediate value (sign-extended), and writes the result back to the register rd.

[0105] The XORI instruction, as shown in Figure 9, performs an exclusive OR (XOR) operation on the integer value in operand register rs1 and the 12-bit immediate value (sign-extended), and writes the result back to register rd.

[0106] The SLLI instruction, as shown in Figure 9, performs a logical left shift operation on the integer value in the operand register rs1 (filling the low bits with 0), the shift amount is a 5-bit immediate value, and the result is written back to the register rd.

[0107] The SRLI instruction, as shown in Figure 9, performs a logical right shift operation on the integer value in the operand register rs1 (filling the high bits with 0), the shift amount is a 5-bit immediate value, and the result is written back to the register rd.

[0108] 3. Data construction instructions:

[0109] The LUI instruction, as shown in Figure 10, shifts the value of the 20-bit immediate number left by 12 bits (fills the lower 12 bits with 0) to become a 32-bit number, and writes this number back to register rd.

[0110] 4. Jump instruction, as shown in Figure 11 and Figure 12:

[0111] Figure 11 shows the unconditional jump instruction:

[0112] JAL instruction: Use a 20-bit immediate number (signed number) as an offset, and then add it to the PC of the instruction to generate the final jump target address. The jal instruction writes the value of the PC of the next instruction (that is, the current instruction PC+1) into its result register rd.

[0113] JALR instruction: uses a 12-bit immediate value (signed number) as an offset and adds it to the value in the operand register rs1 to obtain the final jump target address. The jalr instruction writes the value of the PC of the next instruction (i.e. the current instruction PC + 1) to its result register rd.

[0114] Figure 12 shows the conditional jump instruction:

[0115] This group of instructions is a conditional jump instruction. It uses a 12-bit immediate value (signed) as an offset, which is then added to the instruction's PC to generate the final jump target address. Conditional jump instructions require the condition to be true before the jump occurs, as shown below.

[0116] BEQI instruction: It will jump only if the value in operand register rs1 is equal to the value of the 5-bit immediate value in the operand register.

[0117] BNEI instruction: It will jump only if the value in operand register rs1 is not equal to the value of the 5-bit immediate value in the operand register.

[0118] BGTUI instruction: It will jump only if the unsigned number in operand register rs1 is greater than the unsigned number of the 5-bit immediate value in operand register.

[0119] BLEUI instruction: It will jump only if the unsigned number in operand register rs1 is less than or equal to the unsigned number in operand register 5-bit immediate value.

[0120] BLTUI instruction: It will jump only if the unsigned number in operand register rs1 is less than the unsigned number of the 5-bit immediate value in operand register.

[0121] BGEUI instruction: It will jump only if the unsigned number in operand register rs1 is greater than or equal to the unsigned number in operand register 5-bit immediate value.

[0122] The disclosed embodiments design a hardware architecture and impose certain constraints on its input content (instructions). This adds software-like programmable functionality to conventional hardware designs, enabling programmable state machines and even logic functions. This provides a degree of flexibility with virtually no increase in chip power consumption and area. This addresses, to some extent, the dilemma of chip design requiring both flexibility and low cost.

[0123] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as a read-only memory / random access memory (ROM / RAM), a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present disclosure.

[0124] In this embodiment, a processing system for processing tasks to be processed is also provided. This system is used to implement the above-mentioned embodiments and preferred embodiments. Details already described will not be repeated here. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the systems described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0125] The embodiment of the present disclosure provides a system for processing tasks to be processed. The system for processing tasks to be processed in the embodiment of the present disclosure is located in the above-mentioned hardware accelerator. FIG14 is a structural block diagram of the system for processing tasks to be processed according to the embodiment of the present disclosure. As shown in FIG14 , the system includes:

[0126] The instruction extraction unit 1402 is configured to determine an instruction set corresponding to the task to be processed based on parameter information and requirement information of the task to be processed, wherein the requirement information is used to indicate a processing result corresponding to the task to be processed; and determine an instruction address of each instruction to be executed in the instruction set;

[0127] The execution unit 1404 is configured to execute each of the instructions to be executed according to the instruction address of each of the instructions to be executed, so as to process the task to be processed.

[0128] With this device, the hardware accelerator can determine the instruction set for the task to be processed based on preset instructions (i.e., it implements task programming for the task to be processed), and then process the task by executing the instructions in the instruction set. This means that the hardware accelerator can flexibly handle different tasks. This solves the problem of low chip design flexibility and achieves the effect of improving chip flexibility.

[0129] It should be noted that the processing system for the tasks to be processed in the embodiment of the present disclosure is located in the above-mentioned hardware accelerator, and the hardware accelerator processes the tasks to be processed through the processing system for the tasks to be processed. Therefore, the system structure of the processing system for the tasks to be processed in the embodiment of the present disclosure is similar to the internal structure of the above-mentioned hardware accelerator.

[0130] Since the system structure of the processing system for the task to be processed in the embodiment of the present disclosure is similar to the internal structure of the above-mentioned hardware accelerator, as shown in Figure 4, the processing system for the task to be processed also includes: a data tightly coupled memory, an instruction tightly coupled memory unit, an instruction decoding unit, an execution unit, and a register file.

[0131] It should be noted that, when the to-be-processed task is completed, the processing result is written back to the tightly coupled data memory in a preset format.

[0132] A register file is a component within a processing system that stores and manages the system's registers. Registers are a type of high-speed internal memory used to temporarily store instructions and data. A register file typically contains multiple registers, such as general-purpose registers and the program counter (PC). Register files provide the system with fast data storage and access capabilities to support instruction execution and data processing.

[0133] In an exemplary embodiment, the instruction extraction unit 1402 is configured to determine multiple logical processing methods of the task to be processed based on the parameter information and requirement information; determine the instructions corresponding to the multiple logical processing methods, and determine the multiple instructions as the instruction set.

[0134] In an exemplary embodiment, the instruction extraction unit is further configured to obtain a second instruction address in a program counter, wherein the program counter is used to store the instruction address of the next instruction to be executed; the instruction to be executed corresponding to the second instruction address is determined in the instruction set based on the first instruction address of each instruction to be executed; and the execution unit is further configured to execute the instruction to be executed.

[0135] In an exemplary embodiment, an instruction decoding unit is configured to parse the instruction to be executed to obtain first instruction information corresponding to the instruction to be executed, wherein the first instruction information includes at least one of the following: a first instruction code, a first source operand, a first target operand, and a first immediate value; generate a control signal corresponding to the first instruction information, and send the control signal to a corresponding execution unit to execute the instruction to be executed.

[0136] In an exemplary embodiment, the instruction decoding unit is further configured to be one of the following:

[0137] In a case where the first instruction information includes: the first instruction code and the first source operand, generating first sub-control information according to a type of the first instruction code, and generating a second sub-control signal for reading an operand register according to the first source operand, wherein the control signal includes: the first sub-control signal and the second sub-control signal;

[0138] In a case where the first instruction information includes: the first instruction code, the first source operand, and the first destination operand, generating first sub-control information according to a type of the first instruction code, generating a second sub-control signal for reading an operand register according to the first source operand, and generating a third sub-control signal for writing into a general register according to the first destination operand, wherein the control signal includes: the first sub-control signal, the second sub-control signal, and the third sub-control signal;

[0139] In the case where the first instruction information includes: the first instruction code, the first immediate value and the first target operand, first sub-control information is generated according to the type of the first instruction code, a fourth sub-control signal for reading the first immediate value is generated, and a third sub-control signal for writing to a general register is generated according to the first target operand, wherein the control signal includes: the first sub-control signal, the fourth sub-control signal and the third sub-control signal.

[0140] In an exemplary embodiment, the above-mentioned device also includes: an instruction writing unit, configured to determine second instruction information of the instruction to be written, wherein the second instruction information includes at least one of the following: a second instruction code, a second source operand, a second target operand, and a second immediate value, the second instruction code is used to indicate the function of the instruction to be written, and the second source operand and the second target operand are used to indicate the read and write addresses of the instruction to be written; the instruction to be written is determined based on the second instruction information.

[0141] It should be noted that the programmed instructions are stored in the instruction tightly coupled memory unit, and the instruction set is also stored in the instruction tightly coupled memory unit before being retrieved.

[0142] It should be noted that the above modules can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0143] To facilitate understanding of the technical solutions provided by the present disclosure, embodiments of specific scenarios will be described in detail below.

[0144] An embodiment of the present disclosure further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above method embodiments when run.

[0145] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0146] An embodiment of the present disclosure further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0147] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0148] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0149] Obviously, those skilled in the art should understand that the modules or steps of the present disclosure described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present disclosure is not limited to any particular combination of hardware and software.

[0150] The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations of the present disclosure are possible. Any modifications, equivalent substitutions, or improvements made within the principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A method for processing a task to be processed, characterized in that: Applied to hardware accelerators, including: Determine an instruction set corresponding to the task to be processed according to parameter information and requirement information of the task to be processed, wherein the requirement information is used to indicate a processing result corresponding to the task to be processed; Determining a first instruction address of each instruction to be executed in the instruction set; Each of the instructions to be executed is executed according to the first instruction address of each of the instructions to be executed, so as to process the task to be processed.

2. The method according to claim 1, wherein: Determining an instruction set corresponding to the task to be processed according to the parameter information and requirement information of the task to be processed includes: Determine multiple logical processing modes of the task to be processed according to the parameter information and the requirement information; Instructions corresponding to the multiple logical processing modes are determined, and the multiple instructions are determined as the instruction set.

3. The method according to claim 1, wherein: Executing each of the instructions to be executed according to the first instruction address of each of the instructions to be executed includes: Processing steps: obtaining a second instruction address in a program counter, wherein the program counter is configured to store an instruction address of a next instruction to be executed; Determine, in the instruction set, the instruction to be executed corresponding to the second instruction address according to the first instruction address of each instruction to be executed, and execute the instruction to be executed; The processing steps are executed in a loop until each instruction to be executed in the instruction set is completed.

4. The method according to claim 3, wherein: Executing the to-be-executed instruction includes: Parsing the instruction to be executed to obtain first instruction information corresponding to the instruction to be executed, wherein the first instruction information includes at least one of the following: a first instruction code, a first source operand, a first target operand, and a first immediate value; Generate a control signal corresponding to the first instruction information, and send the control signal to the corresponding execution unit of the hardware accelerator to execute the instruction to be executed.

5. The method according to claim 4, wherein: Generating a control signal corresponding to the first instruction information includes at least one of the following: In a case where the first instruction information includes: the first instruction code and the first source operand, generating first sub-control information according to the type of the first instruction code, and generating a second sub-control signal for reading an operand register according to the first source operand, wherein the control signal includes: the first sub-control signal and the second sub-control signal; In the case where the first instruction information includes: the first instruction code, the first source operand, and the first target operand, first sub-control information is generated according to the type of the first instruction code, a second sub-control signal for reading an operand register is generated according to the first source operand, and a second sub-control signal for writing a general register is generated according to the first target operand. A third sub-control signal, wherein the control signal includes: the first sub-control signal, the second sub-control signal and the third sub-control signal; In the case where the first instruction information includes: the first instruction code, the first immediate value and the first target operand, first sub-control information is generated according to the type of the first instruction code, a fourth sub-control signal for reading the first immediate value is generated, and a third sub-control signal for writing into a general register is generated according to the first target operand, wherein the control signal includes: the first sub-control signal, the fourth sub-control signal and the third sub-control signal.

6. The method according to claim 1, wherein: Before obtaining the instruction set corresponding to the task to be processed, the method further includes: Determine second instruction information of the instruction to be written, wherein the second instruction information includes at least one of the following: a second instruction code, a second source operand, a second target operand, and a second immediate value, the second instruction code is used to indicate the function of the instruction to be written, and the second source operand and the second target operand are used to indicate the read and write addresses of the instruction to be written; The instruction to be written is determined according to the second instruction information.

7. A processing system for tasks to be processed, comprising: An instruction extraction unit is configured to determine an instruction set corresponding to the task to be processed according to parameter information and requirement information of the task to be processed, wherein the requirement information is used to indicate a processing result corresponding to the task to be processed; and determine an instruction address of each instruction to be executed in the instruction set; The execution unit is configured to execute each of the instructions to be executed according to the instruction address of each of the instructions to be executed, so as to process the task to be processed.

8. The system according to claim 7, wherein: Also includes: The instruction fetching unit is further configured to obtain a second instruction address in a program counter, wherein the program counter is used to store an instruction address of a next instruction to be executed; and determine, in the instruction set, an instruction to be executed corresponding to the second instruction address according to the first instruction address of each instruction to be executed; The execution unit is further configured to execute the instruction to be executed.

9. The system according to claim 8, wherein: Also includes: An instruction decoding unit is configured to parse the instruction to be executed to obtain first instruction information corresponding to the instruction to be executed, wherein the first instruction information includes at least one of the following: a first instruction code, a first source operand, a first target operand, and a first immediate value; Generate a control signal corresponding to the first instruction information, and send the control signal to a corresponding execution unit to execute the instruction to be executed.

10. A computer-readable storage medium having a computer program stored therein, wherein: When the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 6 are implemented.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method described in any one of claims 1 to 6 when executing the computer program.

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