Process task control method and semiconductor device

Abstract

The present application provides a process task control method and a semiconductor device. The method comprises: on the basis of a plurality of preset times in a process recipe, calculating a bottleneck time of a semiconductor device and a maximum task operation cycle of a single process task; on the basis of the bottleneck time and the maximum task operation cycle, calculating a minimum task quantity; on the basis of the minimum task quantity and the maximum task operation cycle, calculating a target time interval, and controlling the interval between the start times of two adjacent process tasks in the minimum task quantity to be the target time interval, so that the yield of the semiconductor device reaches a target productivity. In the control method, the target productivity is calculated on the basis of the bottleneck time, and the minimum task quantity and the target time interval are calculated on the basis of the maximum task operation cycle, so as to determine the optimal start occasion of process tasks, so that the production capacity of the semiconductor device reaches the target productivity.

Description

Process task control method and semiconductor equipment Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a control method for a process task and a semiconductor device. Background Art

[0002] Currently, when semiconductor equipment is in a stable operating state, the production capacity of a semiconductor device is typically measured by the number of wafers produced per unit time, or WPH (wafers per hour). Existing methods primarily use mixed integer programming to mathematically model semiconductor equipment. This involves constructing variables, generating constraints and objective functions based on these variables, optimizing the constructed model through a solver, and performing statistical analysis on the results to generate production capacity data. While this method can analyze the production capacity of semiconductor equipment, if the data lacks regularity or periodicity, as the number of process tasks (jobs) increases, the production capacity data gradually converges and fluctuates within a certain range, rarely stabilizing at a single value, leading to calculation errors. Furthermore, this method is time-consuming and can easily miss the optimal time to start a job, resulting in the inability to start a job that could have been started. This can directly lead to material stagnation in the process tank, indirectly affecting the production capacity of the semiconductor device. Therefore, how to control the process tasks of semiconductor equipment to achieve the theoretical optimal production capacity is an urgent problem that needs to be solved.

[0003] Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a control method for process tasks and semiconductor equipment to alleviate the above-mentioned problems. Based on the bottleneck time, the target production volume is calculated, and the minimum number of tasks and the target time interval are calculated in combination with the maximum value of the task operation cycle to determine the optimal start time of the process task, thereby achieving the production capacity of the semiconductor equipment to reach the target production volume, thereby improving the control accuracy of the process tasks in the semiconductor equipment.

[0005] In a first aspect, an embodiment of the present application provides a method for controlling a process task, which is applied to a semiconductor device, wherein the semiconductor device includes: a material storage area, a wafer transfer area, a first robot, a second robot, and a plurality of process chambers; the method includes:

[0006] Obtain a process recipe; wherein the process recipe includes a plurality of preset times, the preset times including: transfer time, preparation time, residence time and process time, the transfer time is used to represent the time for the wafer to be transferred between the wafer transfer area and the plurality of process chambers by the first robot, and the time for the wafer to be transferred between the material storage area and the wafer transfer area by the second robot; the preparation time is used to represent the movement time of the first robot before transferring the next wafer after the previous wafer is transferred; the residence time is used to represent the maximum allowable residence time of the wafer in the process chamber; the process time is used to represent the time for the wafer to be processed in each of the process chambers;

[0007] Calculating the bottleneck time of the semiconductor equipment and the maximum value of the task operation cycle of a single process task according to the plurality of preset times;

[0008] The minimum number of tasks is calculated based on the bottleneck time and the maximum value of the task operation cycle;

[0009] A target time interval is calculated based on the minimum number of tasks and the maximum value of the task operation cycle, and the interval between the start times of two adjacent process tasks in the minimum number of tasks is controlled to be the target time interval, so that the output of the semiconductor equipment reaches the target production volume; wherein, the target production volume is determined based on the bottleneck time, and is used to characterize the maximum number of wafers generated by the continuous operation of the semiconductor equipment in unit time.

[0010] In some embodiments, the transfer time includes: a first transfer time, a second transfer time, and a third transfer time; wherein the first transfer time includes a first transfer sub-time and a first second transfer sub-time, and the first transfer sub-time includes: the time for transferring the current wafer in the current process chamber to the next process chamber via the first robot and the time for transferring the next wafer in the previous process chamber to the current process chamber via the first robot; the first two transfer sub-times include: the time for transferring the wafer from the wafer transfer area to the first process chamber via the first robot, and the time for transferring the wafer from the last process chamber to the wafer transfer area via the first robot; the second transfer time is used to characterize the time for transferring the wafer from the material storage area to the wafer transfer area via the second robot; the third transfer time is used to characterize the time for transferring the wafer from the wafer transfer area to the material storage area via the second robot;

[0011] The step of calculating the bottleneck time of the semiconductor equipment and the maximum value of the task operation cycle of a single process task according to the plurality of preset times comprises:

[0012] calculating a theoretical value of an independent operation cycle of each process chamber based on the first transfer sub-time, the process time, and the preparation time corresponding to each process chamber, and taking the maximum value of the theoretical values ​​of the independent operation cycles of the plurality of process chambers as a first bottleneck time; wherein the first bottleneck time is used to represent the theoretical bottleneck time corresponding to the process chamber;

[0013] A second bottleneck time is calculated based on the first transmission sub-time and the preparation time corresponding to the plurality of process chambers; wherein the second bottleneck time is used to represent the theoretical bottleneck time corresponding to the first robot;

[0014] A third bottleneck time is calculated based on the first and second transmission sub-times, the second transmission time, the third transmission time, and the preparation time; wherein the third bottleneck time is used to characterize the theoretical bottleneck time corresponding to the wafer execution task moving-in process and task moving-out process, the task moving-in process is used to characterize the process of the wafer being transferred from the material storage area to the wafer transfer area by the second robot, and the task moving-out process is used to characterize the process of the wafer being transferred from the wafer transfer area to the material storage area by the second robot;

[0015] taking the maximum value of the first bottleneck time, the second bottleneck time and the third bottleneck time as the bottleneck time of the semiconductor device;

[0016] The maximum value of the task operation cycle is calculated according to the first transmission time, the second transmission time, the third transmission time, the residence time and the process time.

[0017] In some embodiments, the step of calculating a theoretical value of an independent operation cycle of each process chamber based on the first-first transfer sub-time, the process time, and the preparation time corresponding to each process chamber includes:

[0018] The calculation formula of the theoretical value of the independent operation cycle is as follows:

[0019] CycleTime i =T i-(i+1) +Pre(i+1)-(i-1)+T (i-1)-i +P i

[0020] Among them, CycleTime i represents the theoretical value of the independent operation cycle of the i-th process chamber, T i-(i+1)represents the time it takes for the first robot to transfer the wafer processed in the i-th process chamber from the i-th process chamber to the i+1-th process chamber, Pre(i+1)-(i-1) represents the preparation time for the first robot to move from the i+1-th process chamber to the i-1-th process chamber to transfer the next wafer, and T (i-1)-i represents the time it takes to transfer the next wafer in the i-1th process chamber to the i-th process chamber via the first robot, P i represents the process time for the next wafer to be processed in the i-th process chamber, i∈{1,2,3...n}, n represents the total number of the process chambers, and i=0 or i=n+1 represents the wafer transfer area.

[0021] In some embodiments, the step of calculating the second bottleneck time based on the first transfer sub-times and the preparation time corresponding to the plurality of process chambers includes:

[0022] The calculation formula of the second bottleneck time is as follows:

[0023] Among them, CycleTime Trans represents the second bottleneck time, T i-(i+1) It represents the time for the wafer processed in the i-th process chamber to be transferred from the i-th process chamber to the i+1-th process chamber via the first robot, Pre(i+1)-(i-1) represents the preparation time for the first robot to move from the i+1-th process chamber to the i-1-th process chamber to transfer the next wafer, i∈{1,2,3...n}, n represents the total number of the process chambers, and i=0 or i=n+1 represents the wafer transfer area.

[0024] In some embodiments, the step of calculating the third bottleneck time based on the first and second transmission sub-times, the second transmission time, the third transmission time, and the preparation time includes:

[0025] The calculation formula of the third bottleneck time is as follows:

[0026] CycleTimejobOut-jobIn=T jobOut +T jobIn +T 0-1 +Pre 1-n +T n-(n+1)

[0027] Wherein, CycleTimejobOut-jobIn represents the third bottleneck time, T jobOut represents the third transmission time, T jobIn represents the second transmission time, T 0-1T represents the time it takes for the first robot to transfer the wafer from the wafer transfer area to the first process chamber. n-(n+1) represents the time for transferring the wafer from the last process chamber to the wafer transfer area by the first robot, 1-n represents the preparation time of the first robot from the first process chamber to the last process chamber, i∈{1,2,3...n}, n represents the total number of the process chambers, and i=0 or i=n+1 represents the wafer transfer area.

[0028] In some embodiments, the step of calculating the maximum value of the task operation period based on the first transmission time, the second transmission time, the third transmission time, the residence time, and the process time includes:

[0029] The calculation formula for the maximum value of the task operation period is as follows:

[0030] Among them, T jobMax Indicates the maximum value of the task operation period, T jobIn represents the second transmission time, T jobOut represents the third transmission time, T (i-1)-i represents the time it takes to transfer the next wafer in the i-1th process chamber to the i-th process chamber via the first robot, P i represents the process time for the next wafer to be processed in the i-th process chamber, T n-(n+1) represents the time it takes for the first robot to transfer the wafer from the last process chamber to the wafer transfer area, Δi represents the residence time of the wafer in the i-th process chamber, i∈{1,2,3...n}, n represents the total number of process chambers, and i=0 or i=n+1 represents the wafer transfer area.

[0031] In some embodiments, the step of calculating the minimum number of tasks based on the bottleneck time and the maximum value of the task execution period includes:

[0032] The calculation formula for the minimum number of tasks is as follows:

[0033] N min =1+T jobMax / Bottleneck

[0034] Among them, N min represents the minimum number of tasks, Bottleneck represents the bottleneck time of the semiconductor equipment, T jobMax Indicates the maximum value of the task's running period.

[0035] In some embodiments, the step of calculating the target time interval based on the minimum number of tasks and the maximum value of the task running period includes:

[0036] The target time interval is calculated as follows:

[0037] Interval=T jobMax / N min

[0038] Where Interval represents the target time interval, N min Represents the minimum number of tasks, T jobMax Indicates the maximum value of the task's running period.

[0039] In a second aspect, an embodiment of the present application further provides a semiconductor device, comprising a controller and an actuator connected to the controller; wherein the actuator comprises: a material storage area, a wafer transfer area, a first robot, a second robot, and a plurality of process chambers; the material storage area and the wafer transfer area are both used to store wafers, and the process chamber is used to process the wafers;

[0040] The first robot is used to transfer the wafer from the wafer transfer area to the process chamber; or, to transfer the wafer from the process chamber to the wafer transfer area; or, to transfer the wafer from one process chamber to another process chamber;

[0041] The second robot is used to transfer the wafer from the material storage area to the wafer transfer area, or to transfer the wafer from the wafer transfer area to the material storage area;

[0042] The controller is used to control the execution mechanism to execute the process task using the control method of the process task of the first aspect, so that the output of the semiconductor device reaches the target production volume.

[0043] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the control method of the process task of the first aspect are executed.

[0044] The embodiments of the present application bring the following beneficial effects:

[0045] The embodiments of the present application provide a process task control method and semiconductor equipment. The method calculates the bottleneck time of the semiconductor equipment and the maximum task operation cycle of a single process task based on multiple preset times in the process recipe; calculates the minimum number of tasks based on the bottleneck time and the maximum task operation cycle; calculates the target time interval based on the minimum number of tasks and the maximum task operation cycle, and controls the start time interval of two adjacent process tasks to be the target time interval so that the output of the semiconductor equipment reaches the target production volume. In the above control method, the target production volume is determined based on the bottleneck time, and the minimum number of tasks and the target time interval are calculated in combination with the maximum task operation cycle to determine the optimal start time of the process task, thereby achieving the target production volume of the semiconductor equipment production capacity and improving the control accuracy of the process tasks in the semiconductor equipment.

[0046] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or understood by practicing the present application. The purpose and other advantages of the present application are realized and obtained by the structures particularly pointed out in the description and drawings.

[0047] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0049] FIG1 is a schematic diagram of a structure of a semiconductor device provided in an embodiment of the present application;

[0050] FIG2 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application;

[0051] FIG3 is a flow chart of a method for controlling a process task provided in an embodiment of the present application;

[0052] FIG4 is a flow chart of calculating theoretical values ​​of an independent operation cycle of a process chamber provided in an embodiment of the present application;

[0053] FIG5 is a flow chart of another method for controlling a process task provided by an embodiment of the present application;

[0054] FIG6 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0056] As shown in Figure 1, semiconductor equipment includes: material storage area, FTR (Foup Transport Robot, crystal box robot), pre-scan port, ATM robot (abbreviated as ATM), wafer transfer area, wafer pre-storage area, PTM robot (abbreviated as PTM) and process area; among them, the material storage area is used as a temporary place for FOUP (Front Opening Unified Pod, wafer carrier) cache area, mainly used to support the simultaneous operation of multiple process tasks (Job); the pre-scan port is used to realize the function of opening and closing the door of the wafer carrier and scanning and verifying the material information. The pre-scan port includes pre-scan port 1 and pre-scan port 2. Pre-scan port 2 is used to complete the process task, and pre-scan port 1 is used to complete the remaining tasks; FTR is mainly responsible for transferring FOUP between the material storage area and the pre-scan port; ATM is mainly responsible for the two-way wafer transmission between the pre-scan port and the wafer transfer area, and the wafer can only be transmitted in one direction at the same time. ATM can grab a group of 25 wafers at most at a time; the wafer transfer area can hold up to two groups of 50 wafers at a time, mainly to move the wafer to the process area for processing; the wafer pre-storage area can hold up to two groups of 50 wafers at a time, mainly responsible for performing calibration operations on the wafer; the process area includes multiple PMs (Process Module, process chamber), represented as a set {PMi}, i∈{1,2,3...n}; PTM is used to transfer wafers between PMs in both directions, and can grab up to two groups of 50 wafers at a time.

[0057] Specifically, the process of material transfer for process tasks in the above-mentioned semiconductor equipment is as follows: ① The FTR moves the FOUP from the material storage area to the pre-scan port 2 and opens the FOUP door; ② The ATM moves the wafers in the FOUP on the pre-scan port 2 to the wafer transfer area; ③ The FOUP door is closed, and the FTR puts the empty FOUP on the pre-scan port 2 back to the material storage area; ④ Determine whether there is material in the process area, and if so, If not, then proceed to step ⑤. If not, proceed to step ⑥. ⑤ The PTM places the wafers in the wafer transfer area into the wafer pre-storage area for calibration. ⑥ The PTM transfers the wafers in the wafer transfer area to the process area, ensuring that all wafers complete the process in the process area according to the process recipe sent by the factory. ⑦ After the process is complete, the FTR moves the empty FOUP from the material storage area to pre-scan port 2 and opens the FOUP door. ⑧ The PTM transfers the wafers from the process area to the wafer transfer area, and the ATM moves the wafers in the wafer transfer area into the FOUP on pre-scan port 2, closing the FOUP door. ⑨ The FTR returns the FOUP on pre-scan port 2 to the material storage area. Therefore, controlling the process tasks of semiconductor equipment to achieve theoretically optimal production capacity is crucial.

[0058] Based on this, the embodiments of the present application provide a control method for process tasks and semiconductor equipment, which determines the target production volume based on the bottleneck time, and calculates the minimum number of tasks and the target time interval in combination with the maximum value of the task operation cycle to determine the optimal start time of the process task, thereby achieving the production capacity of the semiconductor equipment to reach the target production volume and improving the control accuracy of the process tasks in the semiconductor equipment.

[0059] To facilitate understanding of this embodiment, the control method for the process task provided by the embodiment of the present application is first introduced in detail below. Among them, the method is applied to semiconductor equipment, as shown in Figure 2, the semiconductor equipment includes: a controller (not shown) and an actuator connected to the controller; wherein the actuator includes: a material storage area (including an FTR), a wafer transfer area, a first manipulator, a second manipulator and a plurality of process chambers (PM); wherein the first manipulator is a PTM manipulator, i.e., a PTM, and the second manipulator is an ATM manipulator, i.e., an ATM. In addition, the semiconductor equipment also includes a wafer pre-storage area, which is mainly responsible for performing calibration operations on the wafer.

[0060] Among them, the material storage area and the wafer transfer area are both used to store wafers, and the process chamber (PM) is used to perform process processing on the wafers; the first robot is used to transfer the wafers from the wafer transfer area to the process chamber, such as transferring the unprocessed wafers in the wafer transfer area to a process chamber for process processing; or, transferring the wafers from the process chamber to the wafer transfer area, such as transferring the wafers that have completed processing in the last process chamber to the wafer transfer area; or, transferring the wafers from one process chamber to another process chamber, such as transferring the wafers that have completed process processing in the current process chamber to the next process chamber for process processing, etc.

[0061] The second robot is used to transfer wafers from the material storage area to the wafer transfer area, or to transfer wafers from the wafer transfer area to the material storage area; for example, the second robot transfers unprocessed wafers from the material storage area to the wafer transfer area, or transfers processed wafers from the wafer transfer area to the material storage area. It should be noted that in the process of transferring wafers from the material storage area or transferring wafers to the material storage area, the second robot also needs to cooperate with the FTR of the material storage area to realize the transportation of wafers. For details, please refer to the process of material process task transmission in the above-mentioned semiconductor equipment. The embodiments of this application will not be described in detail here.

[0062] In addition, for the sake of convenience, as shown in FIG2 , the embodiment of the present application divides the semiconductor equipment into a transfer area (i.e., module A, JobIn / Out) and a process area (i.e., module B, JobMid), wherein module A includes the JobIn (task in) process of transferring materials from the material storage area to the wafer transfer area (material storage area->FTR->pre-scan port 2->ATM->wafer transfer area) and the JobOut (task out) process of transferring materials from the wafer transfer area to the material storage area (wafer transfer area->ATM->pre-scan port 2>FTR->material storage area). In module B, the transfer and processing process of transferring materials from the wafer transfer area to the process chamber and then to the wafer transfer area is called JobMid (wafer transfer area->wafer pre-storage area->process chamber->wafer transfer area). It should be noted that here -> indicates transfer to.

[0063] In addition, the above-mentioned controller is used to control the execution mechanism to perform tasks using the control method of the following process tasks so that the output of the semiconductor equipment reaches the target production volume, thereby solving the shortcomings of the semiconductor equipment in the evaluation of theoretical production capacity (i.e., target production volume), providing a basis for the semiconductor equipment to achieve theoretical production capacity evaluation, and improving the control accuracy of the process tasks in the semiconductor equipment.

[0064] Example 1

[0065] Based on the above semiconductor device, an embodiment of the present application provides a method for controlling a process task, as shown in FIG3 , the method comprising the following steps:

[0066] Step S302, obtaining a process recipe; wherein the process recipe includes a plurality of preset times;

[0067] Specifically, in order to ensure the processing accuracy and efficiency of the wafers, the process recipe (Recipe) obtained by the controller includes not only multiple production steps, but also multiple preset times. Among them, the preset times include: transfer time T, preparation time Pre, residence time and process time P; in the actual processing process, the transfer time T is used to characterize the time it takes for the wafer to be transferred between the wafer transfer area and multiple process chambers by the first robot, and the time it takes for the wafer to be transferred between the material storage area and the wafer transfer area by the second robot; that is, in the wafer processing process, the time during the wafer transfer process is called the transfer time, as shown in Figure 2. Here, the transfer time at least includes: the transfer time corresponding to the JobIn (task move in) process, the transfer time corresponding to the JobOut (task move out) process, and the transfer time corresponding to the wafer in JobMid, etc.

[0068] Furthermore, the preparation time (Pre) represents the time it takes the first robot to move after completing the transfer of the previous wafer before transferring the next wafer. This refers to the time it takes the first robot to transfer the next wafer after completing the transfer of the previous wafer. Furthermore, the residence time (P) represents the maximum allowable residence time of a wafer in a process chamber. The process time (P) represents the time it takes for a wafer to undergo processing in each process chamber. Because each process chamber performs different processing on wafers, the process time (P) for each process chamber may be the same or different, and is set based on the actual processing conditions.

[0069] Step S304, calculating the bottleneck time of the semiconductor equipment and the maximum value of the task operation cycle of a single process task according to a plurality of preset times;

[0070] Specifically, as shown in FIG2 , the process task process in the entire semiconductor device can be divided into multiple bottleneck modules, where the bottleneck module includes JobIn, JobOut, a process module (including multiple process chambers), and an internal transport module (PTM), etc. Here, the process module and the internal transport module (PTM) jointly implement the JobMid process. The independent operation cycle of each bottleneck module can be calculated based on multiple preset times, thereby obtaining the bottleneck time of the entire semiconductor device; and, due to the residence time constraint of the wafer in the process chamber, the task operation cycle of a single process task has a dynamic range, that is, the task operation cycle includes the task operation cycle maximum value T jobMax And the minimum value of the task operation cycle T jobMinTherefore, the controller can calculate the bottleneck time and the maximum value of the task operation cycle of the semiconductor equipment according to the multiple preset times in the process recipe.

[0071] Step S306, calculating the minimum number of tasks based on the bottleneck time and the maximum value of the task running cycle;

[0072] In the actual processing process, the theoretical optimal production capacity is achieved under the condition of uninterrupted operation of the module where the bottleneck of the entire semiconductor equipment is located. Once the bottleneck module has idle time during the operation of the process task, the production capacity of the semiconductor equipment will decrease and the theoretical optimal production capacity (that is, the target production volume) cannot be achieved.

[0073] For example, when the number of jobs running simultaneously in the process area is N now =1, it is equivalent to a single job running, and the job running time is the minimum value of the task running cycle T jobMin , the production volume WPH of semiconductor equipment is the lowest, WPH=3600*50 / T jobMin ; As the number of jobs running simultaneously increases, N now As the number of wafers running simultaneously in the process area increases, the production volume of semiconductor equipment gradually increases. However, due to the maximum residence time constraint of the wafer in the process chamber, the task running time T job Will not always follow the minimum time T jobMin Running, it will not exceed the maximum time, that is, the maximum value of the task running cycle T jobMax , that is, the running time range of each task is within T jobMin and T jobMax Therefore, in order to achieve the theoretical optimal capacity (i.e. target production) WPH0, it is necessary to calculate the minimum number of tasks N that can be run simultaneously within the operation cycle of a Job. min , that is, the minimum number of tasks N min It is used to characterize the minimum number of tasks that can be run simultaneously when the production output of semiconductor equipment reaches the target production output within the task operation cycle.

[0074] In addition, when a complete task runs for period T job The number of tasks running simultaneously N now <N min When N now >>N min When N now ≥N min When n≤N min-1, that is, the number of process chambers occupied at the same time (n, n=1,2,...,n 总 , n 总 is the total number of process chambers) is less than or equal to the minimum number of tasks (N min ) and the number of wafer transfer areas (1), the semiconductor equipment will have a bottleneck module idle due to insufficient wafers in the process area, and the actual production volume will not reach the target production volume. For example, if there are 6 process chambers, that is, n 总 =6, the minimum number of tasks is 4, that is, N min =4, indicating that at least 4 groups of jobs exist in the process area at each moment to achieve the maximum production capacity. If there are less than 4 groups, the bottleneck module will be idle (i.e. when n=1, 2 or 3, n≤N min -1 is established), resulting in the actual production volume being lower than the target production volume.

[0075] Therefore, based on the bottleneck time and the maximum task running cycle, the minimum number of tasks is calculated according to the following formula:

[0076] N min =1+T jobMax / Bottleneck (1)

[0077] Among them, N min represents the minimum number of tasks, Bottleneck represents the bottleneck time of semiconductor equipment, T jobMax Represents the maximum value of the task operation cycle. It should be noted that the minimum number of tasks is determined according to the above formula (1), and within the task operation cycle, the number of tasks is run according to the minimum number of tasks to ensure that the bottleneck module in the semiconductor equipment will not be idle, so that the production output of the semiconductor equipment can reach the target production output.

[0078] Step S308 , calculating a target time interval based on the minimum number of tasks and the maximum value of the task operation cycle, and controlling the start time interval between two adjacent process tasks in the minimum number of tasks to be the target time interval, so that the output of the semiconductor equipment reaches the target production volume.

[0079] The target production volume represents the maximum number of wafers that can be produced by a semiconductor device during continuous operation per unit time. The target production volume can also be referred to as the theoretical optimal capacity or theoretical maximum capacity of the semiconductor device. Specifically, the target production volume is determined based on the bottleneck time, and its calculation formula is as follows:

[0080] WPH0=3600*M / Bottleneck (2)

[0081] Where WPH0 represents the target production volume, Bottleneck represents the bottleneck time of the semiconductor equipment, 3600 represents 3600 seconds per hour, and M represents the number of wafers in a job. For example, if the number of wafers in a job is 50, then M = 50.

[0082] Specifically, in order to ensure that within the running cycle T of a Job job The minimum number of tasks that can run simultaneously is N min , then the calculation formula for the interval between the start times of two adjacent tasks, that is, the target time interval, is as follows:

[0083] Interval=T jobMax / N min (3)

[0084] Among them, Interval represents the target time interval, N min Indicates the minimum number of tasks, T jobMax Indicates the maximum task running period.

[0085] Therefore, in a job's running cycle T job The number of tasks that the controller controls to run simultaneously is N min Moreover, the interval between the start times of two adjacent process tasks in the minimum number of tasks is Interval. At this time, not only will the bottleneck module in the semiconductor equipment not be idle, but it will also avoid the situation where the wafer stays in the process area for too long, thereby achieving the target production capacity of the semiconductor equipment.

[0086] The control method for process tasks provided in the embodiment of the present application calculates the target production volume based on the bottleneck time, and calculates the minimum number of tasks and the target time interval in combination with the maximum value of the task operation cycle to determine the optimal start time of the process task, thereby achieving the production capacity of the semiconductor equipment to reach the target production volume and improving the control accuracy of the process tasks in the semiconductor equipment.

[0087] In one embodiment, the above-mentioned transmission time includes: a first transmission time, a second transmission time and a third transmission time; wherein the first transmission time includes a first transmission sub-time and a first second transmission sub-time, and the first transmission sub-time includes: the time for transferring the current wafer in the current process chamber to the next process chamber via the first robot and the time for transferring the next wafer in the previous process chamber to the current process chamber via the first robot; the first second transmission sub-time includes: the time for transferring the wafer from the wafer transfer area to the first process chamber via the first robot, and the time for transferring the wafer from the last process chamber to the wafer transfer area via the first robot; the second transmission time is used to characterize the time for transferring the wafer from the material storage area to the wafer transfer area via the second robot, that is, the transmission time T corresponding to the task moving in (JobIn) process jobIn The third transmission time is used to characterize the time it takes for the wafer to be transferred from the wafer transfer area to the material storage area by the second robot, that is, the transmission time T corresponding to the task out (JobOut) process jobOut In particular, for ease of explanation, the total number of process chambers is set to n.

[0088] Specifically, the step of calculating the bottleneck time of the semiconductor equipment and the maximum value of the task operation cycle of a single process task according to multiple preset times includes the following steps:

[0089] (A1) calculating a theoretical value of an independent operating cycle of each process chamber based on a first transfer sub-time, a process time, and a setup time corresponding to each process chamber, and taking the maximum value of the theoretical values ​​of the independent operating cycles of the plurality of process chambers as a first bottleneck time; wherein the first bottleneck time is used to represent the theoretical bottleneck time corresponding to the process chamber;

[0090] Specifically, for the process module, as shown in Figure 4, first determine whether all process chambers have been calculated. If so, end the calculation of the theoretical value of the independent operation cycle of the process module; if not, obtain the process time of the current process chamber, and obtain the transfer time of the wafer from the current process chamber to the next process chamber, as well as obtain the preparation time of the first robot from the next process chamber to the previous process chamber, and finally obtain the transfer time of the next wafer from the previous process chamber to the current process chamber. Repeat this process until the theoretical values ​​of the independent operation cycles of all process chambers are calculated.

[0091] Therefore, in order to calculate the theoretical value of the independent operating cycle corresponding to each process chamber, the first transfer sub-time corresponding to each process chamber includes: the time for transferring the current wafer in the current process chamber to the next process chamber via the first robot and the time for transferring the next wafer in the previous process chamber to the current process chamber via the first robot.

[0092] For ease of understanding, the i-th process chamber is used as an example. ① After the wafer completes the process in the i-th process chamber, the first robot (PTM) transfers the wafer to the next process chamber, i.e., the i+1-th process chamber. The transfer time is T i-(i+1) ;② The first robot moves from the i+1th process chamber to the i-1th process chamber (i.e., the previous process chamber), and the preparation time for transferring the next wafer is Pre(i+1)-(i-1); ③ The first robot transfers the next wafer from the i-1th process chamber to the i-th process chamber, and the transfer time is T (i-1)-i ④ The next wafer is processed in the i-th process chamber, and the process time is P i Therefore, for the i-th process chamber, the corresponding first transmission sub-time includes: the time T for transferring the current wafer in the current process chamber to the next process chamber via the first robot i-(i+1) And the time T for transferring the next wafer in the previous process chamber to the current process chamber via the first robot (i-1)-i .

[0093] Specifically, the calculation formula for the theoretical value of the independent operation cycle of the i-th process chamber is as follows:

[0094] CycleTime i =T i-(i+1) +Pre(i+1)-(i-1)+T (i-1)-i +P i (4)

[0095] Among them, CycleTime i represents the theoretical value of the independent operation cycle of the i-th process chamber, T i-(i+1) represents the time it takes for the first robot to transfer the wafer processed in the i-th process chamber from the i-th process chamber to the i+1-th process chamber. Pre(i+1)-(i-1) represents the preparation time for the first robot to move from the i+1-th process chamber to the i-1-th process chamber to transfer the next wafer. T (i-1)-i represents the time it takes to transfer the next wafer in the i-1th process chamber to the i-th process chamber via the first robot, P i represents the process time of the next wafer being processed in the i-th process chamber, i∈{1,2,3...n}, n represents the total number of process chambers, and i=0 or i=n+1 represents the wafer transfer area.

[0096] And, based on the above formula (4), and repeating the above ① to ④, the theoretical value of the independent operation cycle of each process chamber can be calculated as CycleTime i and pass Max(CycleTime i) determines the maximum theoretical value of the independent operation cycle of multiple process chambers, and sets Max(CycleTime i ) is used as the first bottleneck time, that is, the theoretical bottleneck time corresponding to the process module or process chamber.

[0097] (A2) calculating a second bottleneck time based on the first transfer sub-times and the preparation time corresponding to the plurality of process chambers; wherein the second bottleneck time is used to represent a theoretical bottleneck time corresponding to the first robot;

[0098] Specifically, for the internal transfer module, since wafer transfer is mainly performed by the first robot, the theoretical bottleneck time corresponding to the first robot can be calculated as the theoretical value of the independent operation cycle of the internal transfer module. At this time, the first transfer sub-time of each process chamber includes the time it takes the first robot to transfer the wafer in the process chamber to the next process chamber. For example, for the i-th process chamber, its corresponding first transfer sub-time includes the time T for transferring the current wafer in the current process chamber to the next process chamber via the first robot. i-(i+1) .

[0099] The calculation formula for the second bottleneck time is as follows:

[0100] Among them, CycleTime Trans represents the second bottleneck time, T i-(i+1) It represents the time for the wafer processed in the i-th process chamber to be transferred from the i-th process chamber to the i+1-th process chamber by the first robot. Pre(i+1)-(i-1) represents the preparation time for the first robot to move from the i+1-th process chamber to the i-1-th process chamber to transfer the next wafer. i∈{1,2,3...n}, n represents the total number of process chambers, and i=0 or i=n+1 represents the wafer transfer area.

[0101] For ease of understanding, here is an example. If under steady-state conditions, the process path is JobIn->wafer transfer area->PM1->PM2->PM3->wafer transfer area->JobOut, there are three groups of wafers in PM1, PM2 and PM3 respectively. When the PM3 process is completed, the first robot PTM first performs the transfer Move (T from PM3 to the wafer transfer area) 3-(4) ) to transfer the wafer processed in the process chamber PM3 to the wafer transfer area; then, the wafer is JobOut (time is not included in the calculation), and at the same time the first robot (PTM) prepares the wafer transfer area -> PM2 Move (Pre 4-(2) ), then the first manipulator (PTM) performs the transfer Move (T 2-(3)), that is, the wafer in the process chamber PM2 is transferred to PM3, and then the first robot (PTM) prepares PM3->PM1 Move (Pre 3-(1) ), then the first manipulator (PTM) performs the transfer Move (T 1-(2) ), that is, the wafer in PM1 is transferred to PM2, and then the first robot (PTM) prepares PM2->wafer transfer area Move (Pre 2-(0) ), while the wafer is doing JobIn (time is not included in the calculation), and then the first robot (PTM) performs the transfer Move (T 0-(1) ), that is, the wafer in the wafer transfer area is transferred to PM1, and then the first robot (PTM) prepares PM1->PM3 Move (Pre 1-(-1) ), forming a closed loop, and then repeating the previous steps. At this time, the theoretical value of the independent operation cycle of the internal transmission module is calculated according to the following formula:

[0102] It should be noted that, for ease of explanation, the wafer transfer area in the above formula (6) is represented by i = 0 or i = 4. Furthermore, in order to achieve the theoretically optimal production capacity of semiconductor equipment, each module of the default bottleneck time does not have idle time. Therefore, wafers in the wafer transfer area do not need to be transferred to the wafer pre-storage area for calibration before waiting for wafer processing in PM1. Therefore, in the calculation process of the theoretical value of the independent operation cycle of the internal transfer module, that is, the second bottleneck time corresponding to the first robot, the situation of the wafer in the wafer pre-storage area does not need to be considered.

[0103] (A3) calculating a third bottleneck time based on the first and second transmission sub-times, the second transmission time, the third transmission time, and the preparation time; wherein the third bottleneck time is used to characterize the theoretical bottleneck time corresponding to the wafer execution task moving-in process (JobIn) and task moving-out process (JobOut), the task moving-in process is used to characterize the process of transferring the wafer from the material storage area to the wafer transfer area via the second robot, and the task moving-out process is used to characterize the process of transferring the wafer from the wafer transfer area to the material storage area via the second robot;

[0104] The calculation formula for the third bottleneck time is as follows:

[0105] CycleTimejobOut-jobIn=T jobOut +T jobIn +T 0-1 +Pre 1-n +T n-(n+1) (7)

[0106] Among them, CycleTimejobOut-jobIn represents the third bottleneck time, TjobOut T represents the third transfer time, which is the time it takes for the wafer to be transferred from the last process chamber to the wafer transfer area by the first robot (PTM) and then to be returned to the material storage area after executing the JobOut process in the wafer transfer area. That is, the time it takes for the wafer to be transferred from the wafer transfer area to the material storage area by the second robot (ATM); jobIn T represents the second transfer time, which refers to the transfer time of the wafer from the material storage area to the wafer transfer area during the JobIn process. This is the time it takes for the wafer to be transferred from the material storage area to the wafer transfer area by the second robot (ATM), excluding the time it takes for the first robot (PTM) to transfer the wafer from the wafer transfer area to the first process chamber for processing. 0-1 T represents the time it takes for the first robot (PTM) to transfer the wafer from the wafer transfer area to the first process chamber, that is, the time it takes for the first robot (PTM) to transfer the wafer from the wafer transfer area to the first process chamber after JobIn is completed; n-(n+1) It indicates the time it takes to transfer the wafer from the last process chamber to the wafer transfer area via the first robot (PTM). 1-n represents the preparation time of the first robot from the first process chamber to the last process chamber, that is, the preparation time of the first robot from the first process chamber to the last process chamber to prepare to transfer the wafer that is about to complete the process in the last process chamber, i∈{1,2,3...n}, n represents the total number of process chambers, i=0 or i=n+1 represents the wafer transfer area, so the above T 0-1 and T n-(n+1) The first and second transmission sub-times are composed.

[0107] In addition, when calculating the third bottleneck time according to the above formula (7), in addition to considering the time for the wafer to execute the JobIn process and the JobOut process, it also includes the transfer time T of the wafer from the wafer transfer area to the first process chamber by the first robot after the JobIn is completed. 0-1 , and the transfer time T of the wafer from the last process chamber to the wafer transfer area via the first robot n-(n+1) and the preparation time of the first manipulator Pre 1-n , thereby ensuring that there is no delay in wafer transmission, and thus making the target production volume reach the theoretical optimum.

[0108] It should be noted that the above steps (A1) to (A3) can be performed simultaneously or in a certain order according to actual conditions, and this embodiment of the present application does not limit this.

[0109] (A4) taking the maximum of the first bottleneck time, the second bottleneck time, and the third bottleneck time as the bottleneck time of the semiconductor device;

[0110] Specifically, after the above calculation obtains the first bottleneck time corresponding to the process chamber, the second bottleneck time corresponding to the internal transmission module, and the third bottleneck time corresponding to JobIn and JobOut, the maximum value of the first bottleneck time, the second bottleneck time and the third bottleneck time is used as the bottleneck time of the semiconductor equipment.

[0111] The bottleneck time calculation formula for semiconductor equipment is as follows:

[0112] Bottleneck=Max(Max(CycleTime i ),CycleTime trans ,CycleTimejobOut-jobIn) (8)

[0113] Among them, Bottleneck represents the bottleneck time of semiconductor equipment, Max(CycleTime i ) represents the first bottleneck time, CycleTime Trans Indicates the second bottleneck time, and CycleTimejobOut-jobIn indicates the third bottleneck time.

[0114] It should be noted that since the theoretical optimal production capacity is achieved under the condition that the module where the bottleneck of the entire machine is located is operating continuously, once the bottleneck module has idle time during the job operation, the production capacity of the machine will decrease and cannot reach the theoretical optimal production capacity. Therefore, through the above formula (8), the maximum bottleneck time of all related modules in the job process of the semiconductor equipment is used as the bottleneck time of the semiconductor equipment. In theory, a new job can be started from module A in Figure 2 at most every time the bottleneck time Bottleneck passes, and the semiconductor equipment can reach the theoretical optimal production capacity.

[0115] (A5) Calculate the maximum value of the task operation period according to the first transmission time, the second transmission time, the third transmission time, the residence time, and the process time.

[0116] Specifically, due to the residence time constraint of the wafer in the process area, the operation cycle of a single job is T job It has a dynamic range, that is, the task operation cycle includes the maximum value and the minimum value of the task operation cycle, that is, T jobMin ≤T job ≤T jobMax The calculation formula for the maximum task operation period is as follows:

[0117] Among them, T jobMax Indicates the maximum task running period, T jobInrepresents the second transmission time, T jobOut represents the third transmission time, T (i-1)-i represents the time it takes to transfer the next wafer in the i-1th process chamber to the i-th process chamber via the first robot, P i It represents the process time for the next wafer to be processed in the i-th process chamber, T n-(n+1) It represents the time it takes for the first robot to transfer the wafer from the last process chamber to the wafer transfer area. Δi represents the residence time of the wafer in the i-th process chamber. i∈{1,2,3...n}, n represents the total number of process chambers, and i=0 or i=n+1 represents the wafer transfer area.

[0118] In addition, the minimum value of the task operation cycle can be calculated based on the first transmission time, the second transmission time, the third transmission time and the process time. The calculation formula for the minimum value of the task operation cycle is as follows:

[0119] Among them, T jobMin Indicates the minimum value of the task operation cycle, T jobIn represents the second transmission time, T jobOut represents the third transmission time, T (i-1)-i represents the time it takes to transfer the next wafer in the i-1th process chamber to the i-th process chamber via the first robot, P i It represents the process time for the next wafer to be processed in the i-th process chamber, T n-(n+1) It represents the time for the first robot to transfer the wafer from the last process chamber to the wafer transfer area, i∈{1,2,3...n}, n represents the total number of process chambers, and i=0 or i=n+1 represents the wafer transfer area.

[0120] It should be noted that the bottleneck time and the maximum value of the task operation cycle of the above-mentioned semiconductor equipment can be set to be calculated simultaneously, or the order can be set according to actual conditions. The embodiment of the present application does not limit this.

[0121] Example 2

[0122] For ease of understanding, let's take an example: suppose a job has a minimum run time of 3600s, a maximum run time of 4000s, a bottleneck time of 1100s, and four process chambers PM1, PM2, PM3, and PM4.

[0123] If the interval for starting a new job is set to the bottleneck time of 1100 seconds, that is, during the maximum job running time of 4000 seconds, a new job is started every 1100 seconds. At this time, the maximum number of jobs running simultaneously within 4000 seconds is 4000 / 1100 = 3. Suppose that five jobs are started: Job1, Job2, Job3, Job4, and Job5. When Job1 returns to the material storage area, Job2 is in PM4, Job3 is in PM3, Job4 is in PM1, and Job5 is in the material storage area waiting to be started. Since the shortest time interval for starting a new job is 1100s, the time interval between the current position of each job and the current position of its previous job is approximately 1100s, that is, after about 1100s, Job2 returns to the material storage area, Job3 is located at PM4, Job4 is located at PM3, and Job5 should be located at PM1 to achieve the target production volume. However, Job5 cannot be located at the position where Job4 was located 1100s ago, because 4000–2*1100=1800s is much greater than 1100s. Job5 needs to wait for about 1800–1100=700s to reach the position of Job4 at that time, resulting in insufficient wafers, that is, idle time of the bottleneck module in the semiconductor equipment, resulting in the actual production capacity of the semiconductor equipment being lower than the target production volume.

[0124] Based on this, according to the control method of the process task provided in the embodiment of the present application, first, according to formula (2), the minimum number of tasks can be calculated to be 1+4000 / 1100=4, and then, according to formula (3), the target time interval can be calculated to be 4000 / 4=1000s. When the control job is started according to the interval time of 1000s, at this time, when Job1 returns to the material storage area, Job2 is located at PM4, Job3 is located at PM3, Job4 is located at PM2, and Job5 is located at PM1. After 1000s, Job2 returns to the material storage area, Job3 is located at PM4, Job4 is located at PM3, Job5 is located at PM2, and Job6 is located at PM1, and so on. Every 1000s, Job i+1 Can achieve the job i At the position before 1000s, the bottleneck module of the semiconductor equipment will not be idle, and the situation where the wafer stays in the process area for too long is avoided, thereby achieving the target production capacity of the semiconductor equipment.

[0125] In summary, the control method for process tasks provided by the embodiment of the present application realizes the theoretical analysis of the bottleneck and target production volume of semiconductor equipment under steady-state conditions. First, starting from the semiconductor equipment module, the semiconductor equipment model is decomposed and analyzed independently. The theoretical value of the operating cycle of each module is first calculated to determine the bottleneck time of the semiconductor equipment, and the target production volume is calculated based on the bottleneck time of the semiconductor equipment; at the same time, the minimum number of tasks is calculated in combination with the maximum value of the task operating cycle. Finally, the optimal start time of the process task is theoretically analyzed based on the minimum number of tasks and the maximum value of the task operating cycle, so as to achieve the actual production capacity of the semiconductor equipment to reach the target production volume. Thus, the shortcomings of semiconductor equipment in theoretical capacity evaluation are solved through the static analysis method, which provides a basis for the production capacity evaluation of semiconductor equipment and improves the control accuracy of process tasks in semiconductor equipment.

[0126] Example 3

[0127] Based on FIG3 , the embodiment of the present application provides another method for controlling a process task, as shown in FIG5 . The method includes the following steps:

[0128] (1) obtaining initialization information of the semiconductor device; that is, obtaining multiple preset times in the process recipe. For specific preset times, reference can be made to the above embodiment;

[0129] (2) calculating the bottleneck time of the associated modules, including respectively calculating: the first bottleneck time corresponding to the process chamber, the second bottleneck time corresponding to the first robot, and the third bottleneck time corresponding to JobIn and JobOut;

[0130] (3) determining the bottleneck time of the semiconductor device based on the first bottleneck time, the second bottleneck time, and the third bottleneck time; that is, determining the maximum value of the first bottleneck time, the second bottleneck time, and the third bottleneck time as the bottleneck time of the semiconductor device;

[0131] (4) Calculating the maximum value of the task operation cycle; that is, calculating the maximum value of the task operation cycle based on the first transmission time, the second transmission time, the third transmission time, the retention time, and the process time;

[0132] (5) Calculate the minimum number of tasks based on the bottleneck time and the maximum value of the task operation cycle;

[0133] (6) Calculating a target time interval based on the minimum number of tasks and the maximum value of the task operation cycle, and controlling the start time interval of two adjacent process tasks in the minimum number of tasks to be the target time interval, so that the output of the semiconductor equipment reaches the target production volume.

[0134] Specifically, after the controller calculates the target time interval, it controls the start time interval of two adjacent process tasks to be the target time interval. For example, after the previous job is started, when the time after startup reaches the target time interval, it controls the current job to start running, and controls the semiconductor equipment to process the materials of each job running at the same time.

[0135] For ease of understanding, the current job is used as an example to illustrate the operation process of the job. Specifically, after the current job is started, ① the FTR in the semiconductor equipment is controlled to move the FOUP carrying the wafers in the current job from the material storage area to the pre-scan port 2, and open the FOUP door; ② the second robot ATM is controlled to move the wafers in the FOUP on the pre-scan port 2 to the wafer transfer area; ③ the FOUP door is controlled to close, and the FTR is controlled to put the empty FOUP on the pre-scan port 2 back to the material storage area; ④ the first robot PTM is controlled to transfer the wafers in the wafer transfer area to the process area, where the wafers are first transferred to the first process chamber in the process area and processed in the first process chamber. Upon completion, the wafer is transferred to the second process chamber, and so on, until the last process chamber completes wafer processing. ⑦ After the process is completed, the FTR is controlled to move the empty FOUP from the material storage unit to the pre-scan port 2 and open the FOUP door. ⑧ The first robot PTM is controlled to transfer the wafer in the last process chamber from the process area to the wafer transfer area, and the first robot ATM is controlled to move the wafer in the wafer transfer area to the FOUP on the pre-scan port 2, and the FOUP door is controlled to close. ⑨ The FTR is controlled to place the FOUP on the pre-scan port 2 back into the material storage area to complete the current job. For each of the remaining jobs, you can refer to the execution process of the current job, and this embodiment of the application will not be described in detail.

[0136] It should be noted that the calculation process of each of the above steps can refer to the aforementioned embodiment, and the embodiment of the present application will not be described in detail here.

[0137] Therefore, after obtaining the initialization information of the semiconductor device, the above-mentioned process task control method can theoretically evaluate the production capacity bottleneck of the semiconductor device and determine the conditions required to achieve the optimal production capacity (including the minimum number of tasks and the target time interval) by calculation, so that the production capacity of the semiconductor device can reach the theoretical optimal production capacity (i.e., the target production volume). In addition, this method can also be applied to other semiconductor devices with different process paths, different process modules, and process residence time constraints. Specifically, adaptive adjustments can be made according to actual conditions. The embodiments of this application will not be described in detail here.

[0138] An embodiment of the present application also provides a semiconductor device, including a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions to implement the control method of the above-mentioned process task.

[0139] 6 , the semiconductor device includes a processor 100 and a memory 101 . The memory 101 stores machine executable instructions that can be executed by the processor 100 . The processor 100 executes the machine executable instructions to implement the control method of the above process task.

[0140] Furthermore, the semiconductor device shown in FIG6 further includes a bus 102 and a communication interface 103 , and the processor 100 , the communication interface 103 and the memory 101 are connected via the bus 102 .

[0141] The memory 101 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage. The communication connection between the system network element and at least one other network element is achieved through at least one communication interface 103 (which may be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. may be used. The bus 102 may be an ISA (Industrial Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Enhanced Industry Standard Architecture) bus. The above-mentioned buses can be divided into address buses, data buses, control buses, etc. For ease of representation, only one bidirectional arrow is used in Figure 6, but this does not mean that there is only one bus or one type of bus.

[0142] The processor 100 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by an integrated logic circuit of hardware in the processor 100 or by instructions in the form of software. The above-mentioned processor 100 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, or discrete hardware components. The various methods, steps, and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as being executed by a hardware decoding processor, or can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium well-known in the art, such as a random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or register. The storage medium is located in the memory 101. The processor 100 reads the information in the memory 101 and, in conjunction with its hardware, completes the steps of the method of the aforementioned embodiment.

[0143] This embodiment further provides a machine-readable storage medium storing machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the control method for the above-mentioned process task.

[0144] The process task control method and the computer program product for semiconductor equipment provided in the embodiments of the present application include a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the previous method embodiments. For specific implementation, please refer to the method embodiments and will not be repeated here.

[0145] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems and devices can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0146] In addition, in the description of the embodiments of this application, unless otherwise specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0147] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0148] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0149] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The scope of protection of the present application is not limited thereto. Although the present application has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed in the present application, or perform equivalent replacements for some of the technical features thereof. These modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the scope of protection of the claims.

Claims

1. A control method for a process task, applied to a semiconductor device, characterized in that The semiconductor device includes: a material storage area, a wafer transfer area, a first robot, a second robot, and a plurality of process chambers; the method includes: Obtaining a process recipe; wherein, the process recipe includes a plurality of preset times, and the preset times include: a transfer time, a preparation time, a residence time, and a process time. The transfer time is used to characterize the time for the wafer to be transferred between the wafer transfer area and the plurality of process chambers by the first robot, and the time for the wafer to be transferred between the material storage area and the wafer transfer area by the second robot; the preparation time is used to characterize the movement time of the first robot after the transfer of the previous wafer is completed and before the transfer of the next wafer; the residence time is used to characterize the maximum allowable residence time of the wafer in the process chamber; the process time is used to characterize the time for the wafer to be processed in each process chamber; Calculating the bottleneck time of the semiconductor device and the maximum value of the task operation cycle of a single process task according to the plurality of preset times; Calculating the minimum number of tasks according to the bottleneck time and the maximum value of the task operation cycle; Calculating a target time interval according to the minimum number of tasks and the maximum value of the task operation cycle, and controlling the interval between the start times of two adjacent process tasks in the minimum number of tasks to be the target time interval, so that the output of the semiconductor device reaches the target production volume; wherein, the target production volume is determined according to the bottleneck time and is used to characterize the maximum number of wafers continuously produced by the semiconductor device per unit time.

2. The method according to claim 1, characterized in that, The transfer time includes: a first transfer time, a second transfer time, and a third transfer time; wherein, the first transfer time includes a first one transfer sub-time and a first two transfer sub-time. The first one transfer sub-time includes: the time for transferring the current wafer in the current process chamber to the next process chamber by the first robot and the time for transferring the next wafer in the previous process chamber to the current process chamber by the first robot; the first two transfer sub-time includes: the time for transferring the wafer from the wafer transfer area to the first process chamber by the first robot, and the time for transferring the wafer from the last process chamber to the wafer transfer area by the first robot; the second transfer time is used to characterize the time for transferring the wafer from the material storage area to the wafer transfer area by the second robot; the third transfer time is used to characterize the time for transferring the wafer from the wafer transfer area to the material storage area by the second robot; The step of calculating the bottleneck time of the semiconductor device and the maximum value of the task operation cycle of a single process task according to the plurality of preset times includes: Calculating the theoretical value of the independent operation cycle of each process chamber according to the first one transfer sub-time, the process time, and the preparation time corresponding to each process chamber, and taking the maximum value of the theoretical values of the independent operation cycles of the plurality of process chambers as the first bottleneck time; wherein, the first bottleneck time is used to characterize the theoretical bottleneck time corresponding to the process chamber; Calculate a second bottleneck time based on the first transfer sub-time and the preparation time corresponding to multiple said process chambers; wherein, the second bottleneck time is used to characterize the theoretical bottleneck time corresponding to the first robot. Calculate a third bottleneck time based on the second transfer sub-time, the second transfer time, the third transfer time, and the preparation time; wherein, the third bottleneck time is used to characterize the theoretical bottleneck time corresponding to the process of the wafer moving into and out of the task, the process of moving into the task is used to characterize the process of the wafer being transferred from the material storage area to the wafer transfer area by the second robot, and the process of moving out of the task is used to characterize the process of the wafer being transferred from the wafer transfer area to the material storage area by the second robot. Take the maximum value of the first bottleneck time, the second bottleneck time, and the third bottleneck time as the bottleneck time of the semiconductor device. Calculate the maximum value of the task operation cycle according to the first transfer time, the second transfer time, the third transfer time, the residence time, and the process time.

3. The method according to claim 2, wherein The step of calculating the theoretical value of the independent operation cycle of the process chamber according to the first transfer sub-time, the process time, and the preparation time corresponding to each said process chamber includes: The calculation formula of the theoretical value of the independent operation cycle is as follows: CycleTime i = T i-(i+1) + Pre(i + 1)-(i - 1)+ T (i-1)-i + P i Among them, CycleTime i represents the theoretical value of the independent operation cycle of the i-th process chamber, T i-(i+1) represents the time for the wafer processed in the i-th process chamber to be transferred from the i-th process chamber to the (i + 1)-th process chamber by the first robot, Pr e(i+1)-(i-1) represents the preparation time for the first robot to move from the (i + 1)-th process chamber to the (i - 1)-th process chamber to transfer the next wafer, T (i-1)-i represents the time for transferring the next wafer in the (i - 1)-th process chamber to the i-th process chamber by the first robot, P i represents the process time for the next wafer to be processed in the i-th process chamber, i ∈ {1, 2, 3... n}, n represents the total number of the process chambers, and i = 0 or i = n + 1 represents the wafer transfer area.

4. The method according to claim 3, wherein The step of calculating the second bottleneck time according to the first transfer sub-time and the preparation time corresponding to multiple said process chambers includes: The calculation formula for the second bottleneck time is as follows: Among them, CycleTime Trans represents the second bottleneck time, T i-(i+1) represents the time for the wafer processed in the i-th process chamber to be transferred from the i-th process chamber to the (i + 1)-th process chamber by the first robot, Pr e(i + 1)-(i - 1) represents the preparation time for the first robot to move from the (i + 1)-th process chamber to the (i - 1)-th process chamber to transfer the next wafer, i ∈ {1, 2, 3... n}, n represents the total number of the process chambers, and i = 0 or i = n + 1 represents the wafer transfer area.

5. The method according to claim 4, wherein The step of calculating the third bottleneck time according to the second transfer sub-time, the second transfer time, the third transfer time, and the preparation time includes: The calculation formula of the third bottleneck time is as follows: CycleTimejobOut - jobIn=T jobOut +T jobIn +T 0-1 +Pre 1-n +T n-(n+1) Among them, CycleTimejobOut-jobIn represents the third bottleneck time, T jobOut represents the third transfer time, T jobIn represents the second transfer time, T 0-1 represents the time for transferring the wafer from the wafer transfer area to the first process chamber by the first robot, T n-(n+1) represents the time for transferring the wafer from the last process chamber to the wafer transfer area by the first robot, Pr e 1-n represents the preparation time of the first robot from the first process chamber to the last process chamber, i ∈ {1, 2, 3... n}, n represents the total number of the process chambers, and i = 0 or i = n + 1 represents the wafer transfer area.

6. The method according to claim 5, characterized in that, The step of calculating the maximum value of the task operation cycle according to the first transfer time, the second transfer time, the third transfer time, the residence time, and the process time includes: The calculation formula for the maximum value of the task running period is as follows: Among them, T jobMax represents the maximum value of the task operation cycle, T jobIn represents the second transmission time, T jobOut represents the third transmission time, T (i-1)-i represents the time for transferring the next wafer in the (i - 1)-th process chamber to the i-th process chamber by the first manipulator, P i represents the process time for the next wafer to undergo process in the i-th process chamber, T n-(n+1) represents the time for transferring the wafer from the last process chamber to the wafer transfer area by the first manipulator, Δi represents the residence time of the wafer in the i-th process chamber, i ∈ {1, 2, 3... n}, n represents the total number of the process chambers, and i = 0 or i = n + 1 represents the wafer transfer area.

7. The method according to claim 6, wherein The step of calculating the minimum number of tasks according to the bottleneck time and the maximum value of the task operation cycle includes: The calculation formula of the minimum number of tasks is as follows: N min = 1 + T jobMax / Bottleneck Among them, N min represents the minimum number of tasks, Bottleneck represents the bottleneck time of the semiconductor device, and T jobMax represents the maximum value of the task operation cycle.

8. The method according to claim 7, wherein The step of calculating the target time interval according to the minimum number of tasks and the maximum value of the task operation cycle includes: The calculation formula of the target time interval is as follows: Interval=T jobMax / N min wherein, Interval represents the target time interval, N min represents the minimum number of tasks, T jobMax represents the maximum value of the task running period.

9. A semiconductor device, characterized in that, The semiconductor device includes a controller and an actuator connected to the controller; wherein, the actuator includes: a material storage area, a wafer transfer area, a first robot, a second robot, and multiple process chambers; both the material storage area and the wafer transfer area are used to store wafers, and the process chambers are used to process the wafers. The first robot is used to transfer the wafer from the wafer transfer area to the process chamber; or, transfer the wafer from the process chamber to the wafer transfer area; or, transfer the wafer from one process chamber to another process chamber. The second manipulator is used to transfer the wafer from the material storage area to the wafer transfer area, or transfer the wafer from the wafer transfer area to the material storage area; The controller is configured to control the actuator to perform a process task by using the control method of the process task according to any one of claims 1-8, so that the output of the semiconductor device reaches the target production volume.

10. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is run by a processor, it executes the steps of the control method of the process task according to any one of claims 1-8 above.

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