multiplexer

Abstract

This multiplexer comprises: a first filter having a passband of a first band; and a second filter connected to a terminal shared with the first filter and having a passband of a second band. The first filter has a series arm capacitive element connected between an input terminal and an output terminal, and a parallel arm resonator connected between a node on a path connecting the input terminal and the output terminal and a ground terminal. The series arm capacitive element has a piezoelectric layer having a first main surface and a second main surface on the reverse side from the first main surface, and an IDT electrode formed on the first main surface or the second main surface of the piezoelectric layer and including a plurality of electrode fingers arranged in a predetermined direction. The parallel arm resonator includes a piezoelectric layer, an upper electrode provided on a first main surface of the piezoelectric layer, and a lower electrode provided on a second main surface of the piezoelectric layer. The resonance frequency of the series arm capacitive element is located in the passband of the second band.

Description

Multiplexer

[0001] The present invention relates to a multiplexer.

[0002] A multiplexer including a plurality of acoustic wave filter devices having different passbands is known. As acoustic wave filter devices used in such a multiplexer, Patent Documents 1 to 3 describe acoustic wave devices (referred to as acoustic wave devices in Patent Document 2 and as electrical components in Patent Document 3) including SAW (Surface Acoustic Wave) elements using surface waves or BAW (Bulk Acoustic Wave) elements using bulk waves.

[0003] International Publication No. 2017 / 110308 Japanese Patent Application Laid-Open No. 2016-152612 Japanese Patent Application Laid-Open No. 2010-526456

[0004] In such multiplexers, there is a demand for improved isolation between adjacent communication bands.

[0005] An object of the present invention is to provide a multiplexer that can improve isolation between adjacent communication bands.

[0006] According to one aspect, a multiplexer includes a first filter having a passband of a first band, and a second filter connected to a terminal common to the first filter and having a passband of a second band, wherein the first filter includes a series arm capacitive element connected between an input terminal and an output terminal, and a parallel arm resonator connected between a node on a path connecting the input terminal and the output terminal and a ground terminal, wherein the series arm capacitive element includes a piezoelectric layer having a first main surface and a second main surface opposite to the first main surface, and an IDT (Interdigital Transducer) electrode formed on the first main surface or the second main surface of the piezoelectric layer and including a plurality of electrode fingers arranged in a predetermined direction, and the parallel arm resonator includes the piezoelectric layer, an upper electrode provided on the first main surface of the piezoelectric layer, and a lower electrode provided on the second main surface of the piezoelectric layer, and a resonant frequency of the series arm capacitive element is located in the passband of the second band.

[0007] The multiplexer of the present invention can improve isolation between adjacent communication bands.

[0008] FIG. 1 is a circuit diagram showing a multiplexer according to the first embodiment. FIG. 2 is a circuit diagram showing a first filter according to the first embodiment. FIG. 3 is a plan view showing the first filter according to the first embodiment. FIG. 4 is a cross-sectional view taken along line IV-IV′ in FIG. 3. FIG. 5 is a graph schematically showing the pass characteristics of a multiplexer according to an example. FIG. 6 is a graph schematically showing the pass characteristics of a multiplexer according to a comparative example. FIG. 7 is a plan view schematically showing an enlarged IDT electrode. FIG. 8 is a plan view showing a first filter according to a second embodiment. FIG. 9 is a plan view showing a first filter according to a modified example of the second embodiment. FIG. 10 is a table showing example combinations of the first band of the first filter and the second band of the second filter in a multiplexer according to a third embodiment. FIG. 11 is an explanatory diagram illustrating the frequency bands of each band.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the present disclosure is not limited to these embodiments. Note that each embodiment described in the present disclosure is illustrative, and partial substitution or combination of configurations between different embodiments is possible. In modified examples and the second and subsequent embodiments, descriptions of matters common to the first embodiment will be omitted, and only differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0010] First Embodiment Fig. 1 is a circuit diagram showing a multiplexer according to a first embodiment. The multiplexer 10 shown in Fig. 1 is used in communication devices such as mobile phones and wearable devices. The multiplexer 10 is configured to be compatible with, for example, 4G (fourth generation mobile communication) standards and 5G (fifth generation mobile communication) standards.

[0011] 1, the multiplexer 10 includes a first filter 11, a second filter 12, a first terminal T1, a second terminal T2, and a common terminal T3. The common terminal T3 is connected to an antenna element 13.

[0012] The first filter 11 is connected on a path connecting the common terminal T3 and the first terminal T1. The second filter 12 is connected on a path connecting the common terminal T3 and the second terminal T2. That is, the first filter 11 and the second filter 12 are electrically connected to the antenna element 13 through the common terminal T3. The first filter 11 has a pass band of a first band. Furthermore, the second filter 12 has a pass band of a second band different from the first band.

[0013] Although not shown, the first terminal T1 and the second terminal T2 of the multiplexer 10 are connected to various high-frequency circuits that constitute communication equipment, such as a power amplifier and an RFIC.

[0014] 2 is a circuit diagram showing a first filter according to the first embodiment. As shown in FIG. 2, the first filter 11 is a so-called ladder filter having series arm capacitive elements C1 and C2 and a parallel arm resonator P1. The series arm capacitive elements C1 and C2 are configured with IDT (Interdigital Transducer) electrodes. The parallel arm resonator P1 is a resonator that utilizes bulk waves, i.e., a BAW (Bulk Acoustic Wave) element.

[0015] The plurality of series arm capacitive elements C1 and C2 are connected in series to a signal path between an input terminal 61 and an output terminal 62. The parallel arm resonator P1 is connected in parallel between a node N1 on the signal path connecting the input terminal 61 and the output terminal 62 and a ground terminal 63. In other words, in the first filter 11 of this embodiment, no resonator is provided in the series arm connecting the input terminal 61 and the output terminal 62.

[0016] More specifically, one terminal of each of the series-connected series arm capacitive elements C1 and C2 is electrically connected to the input terminal 61, and the other terminal is electrically connected to the output terminal 62. One terminal of the parallel arm resonator P1 is electrically connected to a node on the signal path connecting the series arm capacitive elements C1 and C2, and the other terminal is electrically connected to the ground terminal 63. This configuration is not limited to this, and a resonator may be provided in the series arm connecting the input terminal 61 and the output terminal 62. In this case, if the isolation between the first filter 11 and the second filter 12 is insufficient with only the series arm resonator, the isolation can be improved by providing the series arm capacitive elements C1 and C2. Furthermore, a configuration without a resonator in the series arm can be made more compact than the above-described configuration with a series arm resonator.

[0017] Next, a configuration example of the first filter 11 according to the first embodiment will be described with reference to Fig. 3 and Fig. 4. Fig. 3 is a plan view showing the first filter according to the first embodiment. Fig. 4 is a cross-sectional view taken along line IV-IV' in Fig. 3.

[0018] As shown in FIGS. 3 and 4, the first filter 11 has a support member 17, a piezoelectric layer 20, an upper electrode 31, a lower electrode 32, and IDT (Interdigital Transducer) electrodes 40 and 40A.

[0019] In the following description, the thickness direction of the piezoelectric layer 20 is referred to as the Z direction, the direction perpendicular to the Z direction is referred to as the X direction, and the direction perpendicular to the Z direction and the X direction is referred to as the Y direction. The X direction and the Y direction are each parallel to the surface (first main surface 20a) of the piezoelectric layer 20. In the following description, a plan view refers to the positional relationship when viewed from a direction perpendicular to the first main surface 20a of the piezoelectric layer 20 (Z direction).

[0020] 4, the parallel arm resonator P1 is formed by laminating a lower electrode 32 (main electrode portion 32a), a piezoelectric layer 20, and an upper electrode 31 (main electrode portion 31a) in this order on a support member 17. IDT electrodes 40, 40A are formed on the first main surface 20a of the piezoelectric layer 20 to form series arm capacitive elements C1, C2 (the IDT electrode 40A (series arm capacitive element C2) is not shown in FIG. 4).

[0021] The support member 17 is disposed opposite the second main surface 20b of the piezoelectric layer 20. The support member 17 includes a support substrate 15 and an insulating layer 16. The support substrate 15 is made of silicon (Si), quartz crystal, or the like. The insulating layer 16 is disposed between the support substrate 15 and the piezoelectric layer 20. The insulating layer 16 is formed of an insulating material such as silicon oxide. Note that the support member 17 may not include the insulating layer 16, and the piezoelectric layer 20 may be disposed on the support substrate 15. An adhesion layer of Ti, NiCr, or the like may be disposed between the lower electrode 32 and the insulating layer 16.

[0022] A cavity 18 (hollow portion) is formed on the surface of the support member 17 (insulating layer 16) facing the second main surface 20b of the piezoelectric layer 20. The cavity 18 is provided so as to overlap, in plan view, with the excitation region of the parallel arm resonator P1, which is configured by overlapping the piezoelectric layer 20, the upper electrode 31, and the lower electrode 32. This allows bulk waves to be reflected by the cavity 18.

[0023] The piezoelectric layer 20 is in the form of a flat plate having a first main surface 20a and a second main surface 20b opposite to the first main surface 20a. The piezoelectric layer 20 is made of lithium niobate (LiNbO ３ ) or lithium tantalate (LiTaO ３ The substrate is made of a single crystal of aluminum nitride (AlN). The thickness of the piezoelectric layer 20 is not particularly limited, but is preferably 1 μm or less. Note that materials other than single crystal, such as aluminum nitride (AlN), may also be used.

[0024] The upper electrode 31 is provided on the first principal surface 20a of the piezoelectric layer 20. The upper electrode 31 has a main electrode portion 31a and a connection portion 31b. The main electrode portion 31a is provided in the excitation region of the parallel arm resonator P1 (a region overlapping with the cavity portion 18 of the insulating layer 16) and is formed in a substantially circular shape. The connection portion 31b is connected to the main electrode portion 31a and extends in the Y direction. The connection portion 31b connects the main electrode portion 31a to the IDT electrodes 40 and 40A. As shown in FIG. 3 , the connection point between the connection portion 31b and a connection wiring 45 that connects the IDT electrode 40 and the IDT electrode 40A corresponds to a node N1.

[0025] The lower electrode 32 is provided on the second main surface 20b of the piezoelectric layer 20 in a region at least partially overlapping with the upper electrode 31. The lower electrode 32 has a main electrode portion 32a and a connection portion 32b. The main electrode portion 32a is provided in the excitation region of the parallel arm resonator P1 (a region overlapping with the cavity portion 18 of the insulating layer 16) and is formed in a substantially circular shape. That is, the main electrode portion 32a of the lower electrode 32 is provided in a region overlapping with the main electrode portion 31a of the upper electrode 31, with the piezoelectric layer 20 sandwiched therebetween. The connection portion 32b is connected to the main electrode portion 32a and extends in the Y direction on the side opposite to the connection portion 31b of the upper electrode 31. The connection portion 31b is electrically connected to the ground terminal 63 (see FIG. 2 ).

[0026] The parallel arm resonator P1 has a so-called membrane structure in which a cavity 18 (hollow portion) is provided on the second main surface 20b side of the piezoelectric layer 20. In the region overlapping with the cavity 18, the piezoelectric layer 20 is disposed between the upper electrode 31 and the lower electrode 32 in the Z direction. This allows bulk waves to propagate between the upper electrode 31 and the lower electrode 32.

[0027] The upper electrode 31 and the lower electrode 32 are formed of a metal such as aluminum (Al), platinum (Pt), copper (Cu), tungsten (W), or molybdenum (Mo), or an alloy containing at least one of these materials. The upper electrode 31 and the lower electrode 32 may be a laminated film.

[0028] As shown in FIG. 3 , the series arm capacitive element C1 includes an IDT electrode 40. The IDT electrode 40 of the series arm capacitive element C1 has electrode fingers 41 and 42 and busbar electrodes 43 and 44. The electrode fingers 41 extend in the X direction, and one end of the electrode fingers 41 is connected to the busbar electrode 43. The electrode fingers 42 extend in the X direction, and the other end of the electrode fingers 42 is connected to the busbar electrode 44. The electrode fingers 41 and the electrode fingers 42 are alternately arranged in the Y direction with a gap therebetween. The busbar electrodes 43 and 44 each extend in the Y direction and are spaced apart in the X direction. The electrode fingers 41 and 42 are arranged between the busbar electrodes 43 and 44.

[0029] The busbar electrode 43 of the IDT electrode 40 is connected to the IDT electrode 40A of the series arm capacitive element C2 and the upper electrode 31 of the parallel arm resonator P1 through a connection wiring 45 (node ​​N1). The busbar electrode 44 of the IDT electrode 40 is electrically connected to the input terminal 61 (see FIG. 2 ) through a connection wiring 46. As shown in FIG. 4 , the IDT electrode 40 and the connection wirings 45 and 46 are provided on the first main surface 20 a of the piezoelectric layer 20 in the same layer as the upper electrode 31.

[0030] The series arm capacitive element C2 includes an IDT electrode 40A. The IDT electrode 40A of the series arm capacitive element C2 has electrode fingers 41A and 42A and bus bar electrodes 43A and 44A. The IDT electrode 40A has a configuration similar to that of the above-described IDT electrode 40, and therefore a repeated description will be omitted.

[0031] The bus bar electrode 44A of the IDT electrode 40A is connected to the IDT electrode 40 of the series arm capacitive element C1 and the upper electrode 31 of the parallel arm resonator P1 through a connection wiring 45 (node ​​N1). The bus bar electrode 43A of the IDT electrode 40A is electrically connected to the output terminal 62 (see FIG. 2 ) through a connection wiring 47. Although not shown, the IDT electrode 40A and the connection wiring 47 are provided on the first main surface 20a of the piezoelectric layer 20 in the same layer as the IDT electrode 40 and the upper electrode 31.

[0032] With the above-described configuration, the series arm capacitive elements C1 and C2 and the parallel arm resonator P1 are formed on the common piezoelectric layer 20. As described above, the connection point between the connection portion 31b of the upper electrode 31 and the connection wiring 45 corresponds to the node N1 in Fig. 2. That is, the IDT electrodes 40 and 40A are provided in the same layer as the main electrode portion 31a of the upper electrode 31 (parallel arm resonator P1), which is connected to the common node N1.

[0033] 1 may be an acoustic wave filter device including at least one of a BAW element and an IDT electrode, similar to the first filter 11. However, the second filter 12 is not limited to this, and may have any configuration as long as it has a pass band adjacent to the pass band of the first band of the first filter 11.

[0034] Next, the pass characteristics of the first filter 11 and the second filter 12 in the multiplexer 10 will be described with reference to Fig. 5 and Fig. 6. Fig. 5 is a graph schematically showing the pass characteristics of the multiplexer according to the example. Fig. 6 is a graph schematically showing the pass characteristics of the multiplexer according to the comparative example.

[0035] The multiplexer according to the embodiment shown in Fig. 5 includes an acoustic wave filter device having the series arm capacitance elements C1 and C2 and the parallel arm resonator P1 shown in Fig. 2 to Fig. 4. The multiplexer according to the comparative example shown in Fig. 6 is configured such that the series arm capacitance elements C1 and C2 of the multiplexer 10 shown in Fig. 2 to Fig. 4 do not have the IDT electrodes 40 and 40A, but are provided with chip capacitors.

[0036] The vertical axis of graph 1 shown in Fig. 5 and graph 2 shown in Fig. 6 represents the pass characteristic (level (dB) of S parameter S21), and the horizontal axis of graph 1 shown in Fig. 5 and graph 2 shown in Fig. 6 represents frequency (GHz).

[0037] As shown in Figures 5 and 6, in both the multiplexer according to the embodiment and the multiplexer according to the comparative example, the pass band of the first band of the first filter and the pass band of the second band of the second filter have different frequency bands and are arranged adjacent to each other.

[0038] As shown in Figures 5 and 6, the pass band of the second band that the second filter has, which is a frequency band that is farther away from the pass band of the first band than the center frequency of the second band, is represented as a first band B1.

[0039] 6 shows two attenuation poles indicated by arrows F1 and F2 in the pass characteristics of the first filter. The two attenuation poles indicated by arrows F1 and F2 are due to the parallel arm resonators of the first filter. Furthermore, since the comparative example uses a chip capacitor as the series arm capacitive element, it does not have an attenuation pole due to the series arm capacitive element.

[0040] In the multiplexer according to the comparative example, the level of the S parameter S21 of the first filter tends to be higher on the lower frequency side of the pass band of the first band (lower frequency side of the attenuation pole indicated by the arrow F1). Focusing on the pass band of the second filter, the level of the S parameter S21 of the first filter is higher on the first band B1 side than in the frequency band closer to the pass band of the first band.

[0041] In the multiplexer according to the embodiment shown in Fig. 5, the pass characteristics of the first filter show three attenuation poles indicated by arrows F1, F2, and F3. The two attenuation poles indicated by arrows F1 and F2 are caused by the parallel arm resonators of the first filter. The attenuation pole indicated by arrow F3 is caused by the series arm capacitive element (IDT electrode) of the first filter. The resonance of the IDT electrode indicated by arrow F3 exhibits a lower Q value than the resonance of the parallel arm resonators indicated by arrows F1 and F2.

[0042] In the multiplexer according to the embodiment, the resonant frequency of the series arm capacitor is located in the pass band of the second band. More specifically, the resonant frequency of the series arm capacitor is located in the first band B1 of the pass band of the second band.

[0043] This shows that, in the multiplexer according to the example, the level of the S parameter S21 of the first filter is suppressed at a frequency lower than the pass band of the first band (lower than the attenuation pole indicated by the arrow F1) compared to the comparative example. Also, compared to the comparative example, the level of the S parameter S21 of the first filter is suppressed at a frequency band overlapping with the first band B1 of the second filter. This shows that, in the multiplexer according to the example, it is possible to improve the isolation between the first band of the first filter and the second band of the second filter.

[0044] Furthermore, in the multiplexer according to the embodiment, the resonant frequency of the series arm capacitor is outside the pass band of the first band, so that the insertion loss of the series arm capacitor can be suppressed.

[0045] Furthermore, the multiplexer according to the embodiment has IDT electrodes 40, 40A as the series arm capacitance elements C1, C2, and therefore can be made smaller than the multiplexer according to the comparative example which has chip capacitors.

[0046] FIG. 7 is a plan view showing a schematic enlarged view of an IDT electrode. As shown in FIG. 7 , the resonant frequency of the IDT electrode 40 of the series arm capacitance element C1 can be adjusted by changing the arrangement pitch p of the electrode fingers 41. The arrangement pitch p of the electrode fingers 41 is the distance between the sides of two electrode fingers 41 adjacent to each other in the Y direction with one electrode finger 42 sandwiched between them (the lower sides of the electrode fingers 41 in FIG. 7 ). Note that while the arrangement pitch p of the electrode fingers 41 has been described in FIG. 7 , the arrangement pitch p of the electrode fingers 42 is also equal to the arrangement pitch p of the electrode fingers 41. The arrangement pitch p of the electrode fingers 41A and 42A of the IDT electrode 40A of the series arm capacitance element C2 is also defined in the same way as the arrangement pitch p shown in FIG. 7 .

[0047] As described above, the multiplexer 10 of this embodiment includes the first filter 11 having a passband of a first band and the second filter 12 connected to a common terminal (common terminal T3) with the first filter 11 and having a passband of a second band. The first filter 11 includes series arm capacitive elements C1 and C2 connected between the input terminal 61 and the output terminal 62, and a parallel arm resonator P1 connected between a node N1 on a path connecting the input terminal 61 and the output terminal 62 and a ground terminal 63. The series arm capacitive elements C1 and C2 include a piezoelectric layer 20 and IDT electrodes 40 and 40A formed on a first main surface 20a of the piezoelectric layer 20. The parallel arm resonator P1 includes the piezoelectric layer 20, an upper electrode 31, and a lower electrode 32. The resonant frequencies of the series arm capacitive elements C1 and C2 are located in the passband of the second band (first band B1).

[0048] As a result, in the multiplexer 10 of this embodiment, the level of the S parameter S21 in the pass characteristic of the first filter 11 is suppressed in the frequency band that overlaps with the pass band of the second filter 12. This improves the isolation between the first band of the first filter 11 and the second band of the second filter 12.

[0049] In the above-described embodiment, the IDT electrodes 40, 40A of the series arm capacitive elements C1, C2 are formed on the first main surface 20a of the piezoelectric layer 20. However, the present invention is not limited to this. The IDT electrodes 40, 40A of the series arm capacitive elements C1, C2 may be formed on the second main surface 20b of the piezoelectric layer 20.

[0050] Second Embodiment Fig. 8 is a plan view showing a first filter according to a second embodiment. As shown in Fig. 8, a first filter 11A according to the second embodiment has a different configuration from the first embodiment in that the series arm capacitive element C1 includes a first capacitive element C1a and a second capacitive element C1b. The first capacitive element C1a and the second capacitive element C1b are connected in series on a path between the input terminal 61 and a node N1 (a connection point between one terminal of the parallel arm resonator P1 and the connection wiring 45).

[0051] The first capacitance element C1a and the second capacitance element C1b have IDT electrodes 40a and 40b, respectively. The IDT electrode 40a constituting the first capacitance element C1a has electrode fingers 41a and 42a and busbar electrodes 43a and 44a. The IDT electrode 40b constituting the second capacitance element C1b has electrode fingers 41b and 42b and busbar electrodes 43b and 44b. The configuration of the IDT electrodes 40a and 40b is the same as that of the IDT electrode 40 described above, so repeated description will be omitted.

[0052] In this embodiment, the arrangement pitch p of the electrode fingers 41 a, 42 a of the first capacitance element C1 a is different from the arrangement pitch p of the electrode fingers 41 b, 42 b of the second capacitance element C1 b, which makes it possible to make the resonant frequencies of the first capacitance element C1 a and the second capacitance element C1 b different from each other, thereby enabling the pass characteristics of the first filter 11A to be well adjusted.

[0053] 8, the series arm capacitive element C1 has two capacitive elements, a first capacitive element C1a and a second capacitive element C1b. However, this is merely an example, and the series arm capacitive element C1 may have three or more capacitive elements. Furthermore, the series arm capacitive element C2 may have a plurality of capacitive elements.

[0054] 9 is a plan view showing a first filter according to a modification of the second embodiment. As shown in Fig. 9, a first filter 11B according to the modification of the second embodiment differs from the second embodiment in that the first capacitance element C1a and the second capacitance element C1b of the series arm capacitance element C1 are connected in parallel between the input terminal 61 and the node N1.

[0055] One terminal of the first capacitance element C1a and one terminal of the second capacitance element C1b are electrically connected through connection wirings 46 and 46a. The other terminal of the first capacitance element C1a and the other terminal of the second capacitance element C1b are electrically connected through connection wirings 45 and 45a and connected to a common node N1.

[0056] The configurations of the IDT electrodes 40 a, 40 b of the first capacitive element C1 a and the second capacitive element C1 b are the same as those in the second embodiment, and therefore will not be described again. Also in this modification, the arrangement pitch p of the electrode fingers 41 a, 42 a of the first capacitive element C1 a is different from the arrangement pitch p of the electrode fingers 41 b, 42 b of the second capacitive element C1 b.

[0057] 10 is a table showing examples of combinations of the first band of the first filter and the second band of the second filter in a multiplexer according to a third embodiment. FIG. 11 is an explanatory diagram for explaining the frequency range of each band.

[0058] As shown in FIGS. 10 and 11, the first filter 11 and the second filter 12 of the multiplexer 10 can be an appropriate combination of, for example, n46 to n97 of the 5G NR (New Radio) standard.

[0059] For example, the first band of the first filter 11 is n79 of 5GNR, and the second band of the second filter 12 is n77 or n78 of 5GNR (Case 1). The frequency range of n77 of 5GNR is 3.3 GHz or more and 4.2 GHz or less. The frequency range of n78 of 5GNR is 3.3 GHz or more and 3.8 GHz or less. The frequency range of n79 of 5GNR is 4.4 GHz or more and 5.0 GHz or less.

[0060] For example, the first band of the first filter 11 is n46 of 5GNR, and the second band of the second filter 12 is n79 of 5GNR (Case 2). The frequency range of n46 of 5GNR is 5.15 GHz or more and 5.925 GHz or less.

[0061] For example, the first band of the first filter 11 is n96 or n97 of 5GNR, and the second band of the second filter 12 is n46 of 5GNR (Case 3). The frequency range of n96 of 5GNR is 5.925 GHz or more and 6.425 GHz or less. The frequency range of n97 of 5GNR is 5.925 GHz or more and 7.125 GHz or less.

[0062] As shown in FIGS. 10 and 11 , even when the first band of the first filter 11 and the second band of the second filter 12 are close to each other, the isolation between the first filter 11 and the second filter 12 can be improved by setting the resonant frequencies of the series arm capacitive elements C1 and C2 to be located in the pass band of the second band.

[0063] The combination of the first band of the first filter and the second band of the second filter shown in FIG. 10 is merely an example, and other combinations may be used.

[0064] The above-described embodiment is intended to facilitate understanding of the present invention, and is not intended to limit the present invention. The present invention may be modified or improved without departing from the spirit and scope of the present invention, and equivalents thereof are also included in the present invention.

[0065] The present disclosure may also have the following configurations.

[0066] (1) A multiplexer comprising: a first filter having a pass band of a first band; and a second filter connected to a common terminal with the first filter and having a pass band of a second band, wherein the first filter comprises: a series arm capacitive element connected between an input terminal and an output terminal; and a parallel arm resonator connected between a node on a path connecting the input terminal and the output terminal and a ground terminal, wherein the series arm capacitive element comprises: a piezoelectric layer having a first main surface and a second main surface opposite to the first main surface; and an IDT (Interdigital Transducer) electrode formed on the first main surface or the second main surface of the piezoelectric layer and including a plurality of electrode fingers arranged in a predetermined direction, wherein the parallel arm resonator comprises the piezoelectric layer, an upper electrode provided on the first main surface of the piezoelectric layer, and a lower electrode provided on the second main surface of the piezoelectric layer, wherein a resonant frequency of the series arm capacitive element is located in the pass band of the second band. (2) The multiplexer according to (1), wherein a resonant frequency of the series arm capacitive element is located in a pass band of the second band and in a frequency band that is farther from the pass band of the first band than a center frequency of the second band. (3) The multiplexer according to (1) or (2), wherein the first filter has a plurality of the series arm capacitive elements, the plurality of series arm capacitive elements being connected in series between the input terminal and the output terminal, one terminal of the parallel arm resonator being connected to a node on a path between the plurality of series arm capacitive elements and the other terminal of the parallel arm resonator being connected to the ground terminal, and no resonator being provided in the series arm between the input terminal and the output terminal. (4) The multiplexer according to any one of (1) to (3), wherein the series arm capacitive elements of the first filter include a first capacitive element and a second capacitive element, the first capacitive element and the second capacitive element each having the IDT electrode, and an arrangement pitch of the electrode fingers of the first capacitive element is different from an arrangement pitch of the electrode fingers of the second capacitive element. (5) The multiplexer according to (4), wherein the first capacitive element and the second capacitive element are connected in series on a path between the input terminal and one terminal of the parallel arm resonator.(6) The multiplexer according to (4), wherein the first capacitive element and the second capacitive element are connected in parallel on a path between the input terminal and one terminal of the parallel arm resonator. (7) The multiplexer according to any one of (1) to (6), wherein the first band is n79 of a 5G NR, and the second band is n77 or n78 of a 5G NR. (8) The multiplexer according to any one of (1) to (6), wherein the first band is n46 of a 5G NR, and the second band is n79 of a 5G NR. (9) The multiplexer according to any one of (1) to (6), wherein the first band is n96 or n97 of a 5G NR, and the second band is n46 of a 5G NR.

[0067] REFERENCE SIGNS LIST 10 Multiplexer 11 First filter 12 Second filter 13 Antenna element 15 Support substrate 16 Insulating layer 17 Support member 18 Cavity portion 20 Piezoelectric layer 20a First main surface 20b Second main surface 31 Upper electrode 32 Lower electrode 40, 40A, 40a, 40b IDT electrodes 61 Input terminal 62 Output terminal 63 Ground terminal B1 First band C1, C2 Series arm capacitance element C1a First capacitance element C1b Second capacitance element N1 Node P1 Parallel arm resonator

Claims

1. A multiplexer comprising: a first filter having a pass band of a first band; and a second filter connected to a terminal common to the first filter and having a pass band of a second band, wherein the first filter comprises: a series arm capacitance element connected between an input terminal and an output terminal; and a parallel arm resonator connected between a node on a path connecting the input terminal and the output terminal and a ground terminal, wherein the series arm capacitance element comprises a piezoelectric layer having a first main surface and a second main surface opposite to the first main surface, and an IDT (Interdigital Transducer) electrode formed on the first main surface or the second main surface of the piezoelectric layer and including a plurality of electrode fingers arranged in a predetermined direction, and the parallel arm resonator includes the piezoelectric layer, an upper electrode provided on the first main surface of the piezoelectric layer, and a lower electrode provided on the second main surface of the piezoelectric layer, and a resonant frequency of the series arm capacitance element is located in the pass band of the second band.

2. The multiplexer according to claim 1, wherein the resonant frequency of the series arm capacitive element is located in a pass band of the second band, and in a frequency band farther away from the pass band of the first band than a center frequency of the second band.

3. A multiplexer as claimed in claim 1 or 2, wherein the first filter has a plurality of the series arm capacitive elements, the plurality of series arm capacitive elements being connected in series between the input terminal and the output terminal, one terminal of the parallel arm resonator being connected to a node on a path between the plurality of series arm capacitive elements and the other terminal of the parallel arm resonator being connected to the ground terminal, and no resonator being provided in the series arm between the input terminal and the output terminal.

4. A multiplexer as claimed in any one of claims 1 to 3, wherein the series arm capacitance element of the first filter includes a first capacitance element and a second capacitance element, the first capacitance element and the second capacitance element each have the IDT electrode, and the arrangement pitch of the electrode fingers of the first capacitance element is different from the arrangement pitch of the electrode fingers of the second capacitance element.

5. The multiplexer according to claim 4, wherein the first capacitive element and the second capacitive element are connected in series on a path between the input terminal and one terminal of the parallel arm resonator.

6. The multiplexer according to claim 4, wherein the first capacitive element and the second capacitive element are connected in parallel on a path between the input terminal and one terminal of the parallel arm resonator.

7. A multiplexer according to any one of claims 1 to 6, wherein the first band is n79 of 5G NR, and the second band is n77 or n78 of 5G NR.

8. A multiplexer according to any one of claims 1 to 6, wherein the first band is n46 of 5GNR, and the second band is n79 of 5GNR.

9. A multiplexer according to any one of claims 1 to 6, wherein the first band is n96 or n97 of 5G NR, and the second band is n46 of 5G NR.

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