Heterojunction solar cell, manufacturing method therefor, photovoltaic module and photovoltaic system

Abstract

A heterojunction solar cell, a manufacturing method therefor, a photovoltaic module and a photovoltaic system. The heterojunction solar cell comprises a substrate, the substrate being provided with a light receiving surface and a back lighting surface which are arranged opposite to each other. The back lighting surface is provided with microstructure areas and polished areas adjacent to the microstructure areas, microstructures being provided in the microstructure areas. The light receiving surface and the back lighting surface are each provided with, successively stacked, an intrinsic amorphous silicon layer, a doped layer, a transparent conductive layer and grid line electrodes, the orthographic projections of the grid line electrodes of the back lighting surface side on the back lighting surface being at least partially located in the microstructure areas.

Description

Heterojunction solar cell and manufacturing method thereof, photovoltaic module and photovoltaic system

[0001] Related applications

[0002] This application claims priority to Chinese patent application No. 202311064123.7, filed on August 22, 2023, entitled “Heterojunction Solar Cells and Methods for Making Them, Photovoltaic Modules and Photovoltaic Systems,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the technical field of solar cells, and in particular to heterojunction solar cells and manufacturing methods thereof, photovoltaic modules and photovoltaic systems. Background Art

[0004] PERC cells (passivated emitter rear cell), the mainstream solar cell in the current market, have already reached their theoretical production efficiency limit. However, the market's pursuit of higher photoelectric conversion efficiency is inexhaustible, leading the industry to urgently pursue next-generation high-efficiency technologies. Currently, mainstream technologies under development include TOPCon (tunneling oxide passivation contact), IBC (interdigitated back contact), and heterojunction (HJT). Heterojunction solar cells offer a range of advantages, including high conversion efficiency, minimal manufacturing steps, and suitability for thin silicon wafer applications. They are considered the third evolutionary direction of the photovoltaic industry.

[0005] Summary of the Invention

[0006] Based on this, it is necessary to provide a heterojunction solar cell and a manufacturing method thereof, a photovoltaic module and a photovoltaic system.

[0007] According to one aspect of the present application, an embodiment of the present application provides a heterojunction solar cell, comprising:

[0008] A substrate having a light-receiving surface and a backlight surface opposite to each other; the backlight surface having a microstructure region and a polishing region adjacent to the microstructure region, wherein the microstructure region is provided with a microstructure; and

[0009] An intrinsic amorphous silicon layer, a doped layer, a transparent conductive layer and a gate electrode are respectively stacked in sequence on the light-receiving surface and the backlight surface;

[0010] Wherein, at least a portion of the orthographic projection of the gate line electrode located on the backlight surface side on the backlight surface is located within the microstructure region.

[0011] In one embodiment, the orthographic projections of the gate line electrodes on the backlight side on the backlight side are all located within the microstructure area; or

[0012] A portion of the orthographic projection of the gate line electrode located on the backlight surface side is located in the microstructure area, and the other portion is located in the polishing area.

[0013] In one embodiment, the ratio of the area of ​​the orthographic projection of the gate line electrode on the backlight side to the area of ​​the microstructure region is 0.5-2.

[0014] In one embodiment, the portion of the backlight surface located in the microstructure area is configured to be recessed relative to the portion of the backlight surface located in the polishing area.

[0015] In one embodiment, the microstructure comprises a textured structure.

[0016] In one embodiment, the doped layer located on the backlight side is one of a P-type amorphous silicon layer, a P-type microcrystalline silicon layer, or a P-type nanocrystalline silicon layer;

[0017] The doped layer located on the light-receiving surface side is one of an N-type amorphous silicon layer, an N-type microcrystalline silicon layer or an N-type nanocrystalline silicon layer.

[0018] In one embodiment, the light-receiving surface is provided with a velvet structure.

[0019] According to another aspect of the present application, an embodiment of the present application provides a method for manufacturing a heterojunction solar cell, comprising:

[0020] Providing a substrate; wherein the substrate includes a light-receiving surface and a backlight surface disposed opposite to each other, the backlight surface having a microstructure region and a polishing region adjacent to the microstructure region, and the microstructure region is provided with a microstructure;

[0021] forming an intrinsic amorphous silicon layer, a doping layer, a transparent conductive layer and a gate electrode on the light-receiving surface and the backlight surface respectively in sequence;

[0022] Wherein, at least a portion of the orthographic projection of the gate line electrode located on the backlight surface side on the backlight surface is located within the microstructure region.

[0023] In one embodiment, providing a substrate comprises:

[0024] Polishing the light-receiving surface and the backlight surface;

[0025] forming a protective layer on the polished backlight surface;

[0026] forming a mask pattern on the protective layer on the backlight surface to expose a target area of ​​the backlight surface;

[0027] forming a velvet structure in a target area; wherein the target area constitutes a microstructure area, and the velvet structure in the target area constitutes a microstructure;

[0028] Remove the protective layer.

[0029] In one embodiment, the method further comprises forming a velvet structure on the light-receiving surface while forming the velvet structure on the target area.

[0030] In one embodiment, providing a substrate comprises:

[0031] A velvet structure is formed on the light-receiving surface, and a microstructure is formed on the backlight surface;

[0032] forming a protective layer on the light-receiving surface and the backlight surface; wherein the protective layer on the light-receiving surface covers the suede structure, and the protective layer on the backlight surface covers the microstructure;

[0033] forming a mask pattern on the protective layer on the backlight surface to expose a target area of ​​the backlight surface;

[0034] performing polishing on the target area to form a polished area;

[0035] Remove the protective layer.

[0036] In one embodiment, the microstructure is formed by a predetermined process;

[0037] The preset process includes one of an etching process, a texturing process, and a polishing process.

[0038] In one embodiment, the protective layer is one of a silicon oxide layer, a silicon nitride layer, a phosphorus diffusion and absorption layer, an organic thin film layer, and an organic-inorganic composite thin film layer.

[0039] According to another aspect of the present application, an embodiment of the present application provides a photovoltaic assembly, comprising the heterojunction solar cell in any one of the above embodiments; or

[0040] A heterojunction solar cell manufactured by the method for manufacturing a heterojunction solar cell in any of the above embodiments.

[0041] According to another aspect of the present application, an embodiment of the present application provides a photovoltaic system, including the photovoltaic component in any of the above embodiments.

[0042] In the embodiments of the above-mentioned heterojunction solar cell and its manufacturing method, photovoltaic module and photovoltaic system, the backlight surface of the substrate of the heterojunction solar cell has a microstructure area and a polished area adjacent to the microstructure area. The polished area of ​​the backlight surface has better contact with the corresponding intrinsic amorphous silicon layer, which can effectively reduce the thickness of the corresponding intrinsic amorphous silicon layer and improve the uniformity and film quality of the corresponding intrinsic amorphous silicon layer and the corresponding doped layer. In the case where the doped layer corresponding to the polished area of ​​the backlight surface is an emitter, it is more conducive to the adjustment of the emitter band gap. At the same time, under the same process conditions, since the ratio of the specific surface area of ​​the microstructure area of ​​the backlight surface to the specific surface area of ​​the polished area of ​​the backlight surface is greater than 1, the corresponding thin film deposition thickness will be less than the thin film deposition thickness of the polished surface area of ​​the backlight surface. Therefore, in the embodiment of the present application, it is only necessary to make the polished area of ​​the backlight surface have the same passivation thickness and passivation effect as when the backlight surface is entirely a microstructure area, and then the deposition thickness of the corresponding intrinsic amorphous silicon layer can be appropriately reduced, thereby saving process time. Moreover, because the microstructure region thickness of the backlight surface is thinner in the embodiment of the present application, the series resistance of the grid electrode and the substrate can be reduced when most of the regions are passivated. Further, the polished region can also reflect the light incident on the back surface of the front surface, increase the light absorption of the substrate, and then increase the short-circuit current. Thus, on the basis of having balanced the passivation performance and the series resistance, the series resistance can be reduced when obtaining a better passivation effect, and the short-circuit current can also be improved, thereby improving the photoelectric conversion efficiency of the solar cell as a whole. In addition, not only can the contact area of ​​the grid electrode at the back side be increased by means of the microstructure region, the welding pulling force can be improved, and the reliability of the grid electrode can be improved, but also the mutual coordination of the microstructure region and the polished region can be used to obtain a thinner transparent conductive layer, which can also reduce the consumption of the transparent conductive layer and reduce manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0044] FIG1 is a schematic structural diagram of a heterojunction solar cell in one embodiment of the present application.

[0045] FIG2 is a schematic structural diagram of a substrate of a heterojunction solar cell according to an embodiment of the present application.

[0046] FIG3 is a schematic structural diagram of a heterojunction solar cell in another embodiment of the present application.

[0047] FIG4 is a flow chart of a method for manufacturing a heterojunction solar cell according to an embodiment of the present application.

[0048] FIG5 is a flowchart of step S110 in one embodiment of the present application.

[0049] FIG6 is a flowchart of step S110 in another embodiment of the present application.

[0050] Description of reference numerals:

[0051] Substrate 100, light-receiving surface m1, backlight surface m2, microstructure area z1, polishing area z2;

[0052] a first intrinsic amorphous silicon layer 200 a and a second intrinsic amorphous silicon layer 200 b ;

[0053] a first doping layer 300a and a second doping layer 300b;

[0054] A first transparent conductive layer 400a and a second transparent conductive layer 400b;

[0055] A first gate line electrode 500a and a second gate line electrode 500b. DETAILED DESCRIPTION

[0056] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0057] In the description of this application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0058] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include at least one of such features. In the description of this application, if the term "plurality" appears, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0059] In this application, unless otherwise clearly specified and limited, if the terms "installed", "connected", "connected", "fixed" and the like appear, these terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. It is worth noting that in the following description and the attached claims, "electrical connection" between one feature and another feature not only includes one feature being in direct contact with another feature to form an electric energy transmission or current transmission channel, but also includes an intermediate feature between one feature and another feature, and the one feature, the other feature and the intermediate feature between them form an electric energy transmission channel or a current transmission channel to achieve electric energy transmission or transmission. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0060] In this application, unless otherwise expressly specified or limited, if a first feature is described as being "above" or "below" a second feature, or similar descriptions, this may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is described as being "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is described as being "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0061] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only embodiment.

[0062] In the related art, heterojunction solar cells use intrinsic amorphous silicon passivation on both sides, which has high open-circuit voltage characteristics. However, heterojunction solar cells have the problem of large series resistance, which makes it difficult to improve the conversion efficiency of solar cells.

[0063] Excessively thick intrinsic amorphous silicon and doped layers can lead to diffusion and drift of photogenerated carriers, causing them to recombine within the film, resulting in low short-circuit current. Furthermore, excessive thickness can increase the series resistance required for photogenerated carriers to travel to the gate electrode, reducing the solar cell's fill factor and conversion efficiency. Excessively thin intrinsic amorphous silicon and doped layers can't fully passivate substrate defects, compromising passivation effectiveness and impacting solar cell performance such as hidden open-circuit voltage, dark saturation current density, and internal quantum efficiency in the short-wavelength range, ultimately affecting the solar cell's photoelectric conversion efficiency. Consequently, it's difficult to balance the passivation performance and series resistance of the intrinsic amorphous silicon and doped layers.

[0064] Based on this, the embodiments of the present application improve some of the aforementioned problems by balancing the passivation performance and series resistance of the intrinsic amorphous silicon layer and the doped layer, so as to improve the photoelectric conversion efficiency of the heterojunction solar cell as a whole.

[0065] Figure 1 shows a schematic diagram of the structure of a heterojunction solar cell according to an embodiment of the present application; Figure 2 shows a schematic diagram of the structure of a substrate for a heterojunction solar cell according to an embodiment of the present application. For ease of illustration, only the details relevant to the embodiment of the present application are shown. Figure 2 exemplarily illustrates a microstructure region z1 and a polishing region z2.

[0066] In some embodiments, referring to FIG. 1 , an embodiment of the present application provides a heterojunction solar cell, including a substrate 100 , an intrinsic amorphous silicon layer, a doping layer, a transparent conductive layer, and a gate electrode.

[0067] The substrate 100 can be selected based on actual needs. For example, the substrate 100 can be a silicon substrate 100. The doping type of the substrate 100 is not specifically limited. For example, the substrate 100 can be an N-type doped silicon substrate 100, or a P-type doped silicon substrate 100. In one specific embodiment, the substrate 100 can be an N-type single crystal silicon wafer.

[0068] The substrate 100 has a light-receiving surface m1 and a backlight surface m2 that are relatively arranged. It can be understood that the light-receiving surface m1 and the backlight surface m2 are relative. The light-receiving surface m1 specifically refers to the surface on the substrate 100 that is mainly irradiated by sunlight in a solar cell or in a photovoltaic module. The light-receiving surface m1 can be provided with a velvet structure, which can increase the light absorption area, increase the photocurrent, and help improve the efficiency of the heterojunction solar cell. With reference to Figure 2, the backlight surface m2 has a microstructure area z1 and a polishing area z2 adjacent to the microstructure area z1. A microstructure is provided on the microstructure area z1. A microstructure refers to a tiny structure that protrudes relative to the backlight surface m2. The microstructure can be a velvet structure, a rough structure obtained by semi-polishing treatment, or other structures such as a rough structure obtained by etching process. It can be set according to the specific usage, and the embodiments of the present application do not impose specific restrictions on this.

[0069] It should be noted that the microstructure area z1 and the polishing area z2 are relative terms. The polishing area z2 here refers to the area on the backlight surface m2 where no microstructure is formed and which has been polished. When the polishing area z2 is a polished area and a microstructure is provided on the microstructure area z1, the polishing area z2 is flatter than the microstructure area z1, while the microstructure area z1 is more uneven. The light-receiving surface m1 and the backlight surface m2 are each sequentially stacked with an intrinsic amorphous silicon layer, a doped layer, a transparent conductive layer, and a gate electrode. Now, in conjunction with Figure 1, the light-receiving surface m1 and the backlight surface m2 are used for explanation.

[0070] A first intrinsic amorphous silicon layer 200a, a first doped layer 300a, a first transparent conductive layer 400a, and a first gate electrode 500a are sequentially stacked on the light-receiving surface m1. A second intrinsic amorphous silicon layer 200b, a second doped layer 300b, a second transparent conductive layer 400b, and a second gate electrode 500b are sequentially stacked on the backlight surface m2. The first doped layer 300a and the second doped layer 300b have different doping types. In one embodiment, the first doped layer 300a may be an N-type doped semiconductor layer, and the second doped layer 300b may be a P-type doped semiconductor layer. In another embodiment, the first doped layer 300a may be a P-type doped semiconductor layer, and the second doped layer 300b may be an N-type doped semiconductor layer.

[0071] In some specific embodiments, the doping layer located on the light-receiving surface m1 side (i.e., the first doping layer 300a) is one of an N-type amorphous silicon layer, an N-type microcrystalline silicon layer, or an N-type nanocrystalline silicon layer, and the doping layer located on the backlight surface m2 side (i.e., the second doping layer 300b) is one of a P-type amorphous silicon layer, a P-type microcrystalline silicon layer, or a P-type nanocrystalline silicon layer. It can be flexibly set according to the specific usage, and the embodiments of the present application do not impose specific restrictions on this. The first intrinsic amorphous silicon layer 200a and the second intrinsic amorphous silicon layer 200b can achieve chemical passivation. When the substrate 100 is an N-type single crystal silicon wafer, the first doping layer 300a is an N-type doped semiconductor layer, and the second doping layer 300b is a P-type doped semiconductor layer, the first doping layer 300a can achieve field passivation, and the second doping layer 300b can serve as an emitter.

[0072] At least a portion of the orthographic projection of the gateline electrode (i.e., the second gateline electrode 500b) located on the backlight surface m2 side is located within the microstructure region z1. That is, the orthographic projection of the second gateline electrode 500b on the backlight surface m2 may be entirely located within the microstructure region z1, or may be partially located within the microstructure region z1 and partially located within the polishing region z2. In the embodiment of FIG1 , the orthographic projection of the second gateline electrode 500b on the backlight surface m2 is entirely located within the microstructure region z1.

[0073] Since the polished area z2 of the backlight surface m2 has better contact with the second intrinsic amorphous silicon layer 200b, the thickness of the second intrinsic amorphous silicon layer 200b can be effectively reduced, and the uniformity and film quality of the second intrinsic amorphous silicon layer 200b and the second doped layer 300b can be improved. When the second doped layer 300b is a microcrystalline silicon layer or a nanocrystalline silicon layer, the crystallization rate of the second doped layer 300b can be improved. When the second doped layer 300b is an emitter, it is more conducive to the adjustment of the emitter band gap. At the same time, under the same process conditions, since the specific surface area of ​​the microstructure area z1 of the backlight surface m2 is greater than 1, the corresponding thin film deposition thickness of the microstructure area z1 of the backlight surface m2 will be less than the thin film deposition thickness of the polished surface area z2 of the backlight surface m2. The specific surface area is defined as the ratio of the surface area of ​​the microstructure area z1 of the backlight surface m2 to the bottom area. Therefore, in the embodiment of the present application, it is sufficient to ensure that the polished area z2 of the backlight surface m2 has the same passivation thickness and passivation effect as when the backlight surface m2 is entirely composed of the microstructure area z1. This can appropriately reduce the deposition thickness of the second intrinsic amorphous silicon layer 200b, thereby saving process time. Furthermore, because the microstructure area z1 of the backlight surface m2 is relatively thin in the embodiment of the present application, the series resistance between the second gate line electrode 500b and the substrate 100 can be reduced while passivating the majority of the area.

[0074] It can be understood that in the above process, the difference between the thickness of the second intrinsic amorphous silicon layer 200b and the second doped layer 300b in the polishing area z2 and the thickness of the second intrinsic amorphous silicon layer 200b and the second doped layer 300b in the microstructure area z1 can be adjusted by adjusting the size of the microstructure. This difference can be adjusted according to usage requirements to meet different types of usage requirements.

[0075] Furthermore, the polished area z2 can also reflect light incident from the front surface to the back surface, thereby increasing the light absorption of the substrate 100 and thereby increasing the short-circuit current.

[0076] Therefore, on the basis of balancing the passivation performance and the series resistance, it is possible to obtain a better passivation effect while reducing the series resistance and increasing the short-circuit current, thereby improving the photoelectric conversion efficiency of the solar cell as a whole.

[0077] Furthermore, the provision of the microstructured region z1 increases the contact area of ​​the second gateline electrode 500b on the back surface, reducing the contact resistivity and bulk resistance of the second gateline electrode 500b, improving welding tension, and reducing the risk of gate breakage, thereby enhancing the reliability of the second gateline electrode 500b. Furthermore, the interaction between the microstructured region z1 and the polished region z2 allows for a thinner second transparent conductive layer 400b, which reduces the amount of transparent conductive layer used and reduces manufacturing costs.

[0078] Compared to a case where the entire backlight surface m2 is provided with a velvet structure, the heterojunction solar cell provided in the embodiment of the present application has superior passivation performance and possesses some of the advantages mentioned above, which are not further elaborated here. Compared to a case where the entire backlight surface m2 is polished, the second gridline electrode 500b of the heterojunction solar cell provided in the embodiment of the present application has superior reliability and possesses some of the advantages mentioned above, which are not further elaborated here.

[0079] In some embodiments, the ratio of the area of ​​the orthographic projection of the gateline electrode (i.e., the second gateline electrode 500b) on the backlight surface m2 to the area of ​​the microstructure region z1 is 0.5 to 2. For example, the ratio may be 0.5, 1, 1.2, 1.5, 1.8, or 2. Exemplarily, the ratio of the area of ​​the orthographic projection of the second gateline electrode 500b on the backlight surface m2 to the area of ​​the microstructure region z1 is 1, and the area of ​​the orthographic projection of the second gateline electrode 500b on the backlight surface m2 overlaps with the microstructure region z1.

[0080] It should be noted that in the embodiments of the present application, two numerical values ​​connected by the symbol “~” represent a numerical range, and the numerical range here includes the endpoint values ​​at both ends of the symbol “~”.

[0081] This is not only beneficial for balancing the passivation performance and series resistance of the second intrinsic amorphous silicon layer 200 b and the second doped layer 300 b , but also beneficial for fabricating the microstructure.

[0082] In some embodiments, the portion of the backlight surface m2 located in the microstructure region z1 is configured to protrude relative to the portion of the backlight surface m2 located in the polished region z2. That is, the second intrinsic amorphous silicon layer 200b, the second doped layer 300b, and the second transparent conductive layer 400b, which are sequentially stacked on the backlight surface m2, protrude in the portion corresponding to the microstructure region z1. Accordingly, at least a portion of the second gate electrode 500b can be disposed on the protruding portion of the second transparent conductive layer 400b.

[0083] FIG3 shows a schematic structural diagram of a heterojunction solar cell in another embodiment of the present application. For ease of explanation, only the contents related to the embodiment of the present application are shown.

[0084] In some embodiments, referring to FIG. 3 , the portion of the backlight surface m2 located in the microstructure region z1 is recessed relative to the portion of the backlight surface m2 located in the polished region z2. That is, the second intrinsic amorphous silicon layer 200b, the second doped layer 300b, and the second transparent conductive layer 400b, which are sequentially stacked on the backlight surface m2, are recessed in the portion corresponding to the microstructure region z1. Accordingly, at least a portion of the second gate electrode 500b can be accommodated within the recess formed by the second transparent conductive layer 400b, forming an at least partially buried gate structure.

[0085] It is understood that the depth of the recess of the portion of the backlight surface m2 located in the microstructure region z1 can be adjusted accordingly based on usage requirements, thereby adjusting the buried depth of the second gate electrode 500b. This is not a specific limitation. For example, using FIG. 3 as an example, a portion of the second gate electrode 500b is located in the recess of the second transparent conductive layer 400b, while another portion extends externally. This facilitates the fabrication of structures such as solder strips on the second gate electrode 500b.

[0086] In this way, the contact area between the second gate line electrode 500b and the second transparent conductive layer 400b can be further increased, thereby further reducing the contact resistivity and bulk resistance of the second gate line electrode 500b, further increasing the welding tension, and improving the reliability of the second gate line electrode 500b.

[0087] In some embodiments, the microstructure includes a velvet structure, that is, the microstructure region z1 may be a velvet region.

[0088] In this way, during the preparation process of the heterojunction solar cell, the backlight surface m2 can be textured while the light-receiving surface m1 of the substrate 100 is textured, which is beneficial to the production and improves the production efficiency.

[0089] FIG4 is a schematic flow chart of a method for manufacturing a heterojunction solar cell in an embodiment of the present application. For ease of explanation, only the content related to the embodiment of the present application is shown.

[0090] Based on the same inventive concept, referring to FIG. 4 , the present embodiment further provides a method for manufacturing a heterojunction solar cell, comprising the following steps:

[0091] Step S110, providing a substrate; wherein the substrate includes a light-receiving surface and a backlight surface disposed opposite to each other, the light-receiving surface may be provided with a suede structure, and the backlight surface has a microstructure region and a polishing region adjacent to the microstructure region, and the microstructure region is provided with a microstructure;

[0092] Step S120, forming an intrinsic amorphous silicon layer, a doping layer, a transparent conductive layer and a gate line electrode on the light-receiving surface and the backlight surface respectively; wherein at least part of the orthographic projection of the gate line electrode on the backlight surface side is located within the microstructure area.

[0093] The advantages of the heterojunction solar cell illustrated in some of the above embodiments are also possessed by the heterojunction solar cell obtained by the method for manufacturing the heterojunction solar cell, and will not be described in detail here.

[0094] FIG5 shows a flow chart of step S110 in an embodiment of the present application; for ease of explanation, only the contents related to the embodiment of the present application are illustrated.

[0095] In some embodiments, referring to FIG. 5 , step S110 includes the following steps:

[0096] Step S111a, polishing the light-receiving surface and the backlight surface;

[0097] Step S112a, forming a protective layer on the polished backlight surface;

[0098] Step S113a, forming a mask pattern on the protective layer on the backlight surface to expose a target area of ​​the backlight surface;

[0099] Step S114a, forming a velvet structure on the target area; wherein the target area constitutes a microstructure area, and the velvet structure located in the target area constitutes a microstructure. Optionally, a velvet structure is formed on the light-receiving surface while the velvet structure is formed on the target area;

[0100] Step S115a: removing the protective layer.

[0101] In step S111a, the polishing process can be a chemical polishing process or a physical polishing process. For example, the backlight surface can be subjected to alkaline polishing, and the alkaline polishing solution can be KOH. The alkaline polishing solution can be selected according to the specific situation and is not specifically limited in this embodiment of the present application.

[0102] In step S112a, the protective layer can be one of a silicon oxide layer, a silicon nitride layer, a phosphorus diffusion and absorption layer, an organic thin film layer, and an organic-inorganic composite thin film layer. That is, a silicon oxide layer can be formed as a protective layer by high-temperature oxidation of the backlight surface of the substrate, an organic thin film layer can be formed as a protective layer on the backlight surface of the substrate by screen printing, and a silicon oxide layer can be deposited on the backlight surface of the substrate by atmospheric pressure chemical vapor deposition (APCVD) or low pressure chemical vapor deposition (LPCVD) as a protective layer. The method for forming the protective layer can be selected according to specific needs, and the embodiment of the present application does not impose any specific restrictions on this.

[0103] In step S113a, the protective layer located on the backlight surface can be etched to form a mask pattern. For example, wet etching or dry etching can be used to form a mask pattern on the protective layer according to the specific type of the protective layer. In another embodiment, steps S112a to S113a can be replaced by printing a mask pattern on the backlight surface to expose the target area of ​​the backlight surface. Specifically, it may include selectively printing a patterned protective layer by screen printing. The method for forming the mask pattern can be selected according to specific needs, and the embodiment of the present application does not impose specific restrictions on this. The target area of ​​the backlight surface is exposed to the outside from the patterned protective layer, i.e., the mask pattern.

[0104] In step S114a, if the microstructure is a velvet structure, a protective layer can be provided only on the backlight side, and a velvet structure can be formed simultaneously on the target areas of both the light-receiving and backlight sides through a texturing process, simplifying the overall process, facilitating production, and improving production efficiency. It will be appreciated that the morphology of the microstructure in the microstructured area can be adjusted as needed, thereby adjusting the depth of the depression of the portion of the backlight side located in the microstructured area relative to the portion of the backlight side located in the polished area. During the texturing process, a texturing additive that has a protective effect on the protective layer can be used to facilitate protection of the protective layer.

[0105] In step S115 a , the protective layer may be removed by a cleaning process.

[0106] FIG6 shows a flow chart of step S110 in another embodiment of the present application; for ease of explanation, only the content related to the embodiment of the present application is shown.

[0107] In some embodiments, referring to FIG. 6 , step S110 includes the following steps:

[0108] Step S111b, forming a suede structure on the light-receiving surface and forming a microstructure on the backlight surface;

[0109] Step S112b, forming a protective layer on the light-receiving surface and the backlight surface; wherein the protective layer on the light-receiving surface covers the suede structure, and the protective layer on the backlight surface covers the microstructure;

[0110] Step S113b, forming a mask pattern on the protective layer on the backlight surface to expose a target area of ​​the backlight surface;

[0111] Step S114b, performing polishing on the target area to form a polishing area;

[0112] Step S115b: Remove the protective layer. Unlike the embodiment of FIG5 , the embodiment of FIG6 performs the protective layer after texturing. The specific methods of polishing, texturing, and fabricating the protective layer and mask pattern can be referred to the previous embodiment and will not be repeated here.

[0113] Therefore, in the manufacturing method illustrated in FIG6 , before executing step S111b, the light-receiving surface and the backlight surface can be polished to facilitate the execution of step S111b. The microstructure can be formed by a preset process. The preset process includes one of an etching process, a texturing process, and a polishing process. In step S114b, during the polishing process, a polishing additive that has a protective effect on the protective layer can be used, which is beneficial to protecting the protective layer. In this way, the heterojunction solar cell shown in FIG1 can be obtained using the manufacturing method illustrated in FIG6 .

[0114] It can be understood that in the manufacturing method illustrated in FIG5, since the steps of polishing, protective layer preparation, and texturing are performed in sequence, the protective layer is used to protect the polished area of ​​the backlight surface, while in the manufacturing method illustrated in FIG6, the protective layer is used to protect the microstructure area of ​​the backlight surface. The manufacturing method illustrated in FIG5 can be used to manufacture a heterojunction solar cell as shown in FIG3, so that the microstructure area z1 of the backlight surface m2 is recessed relative to the polished area z2. The manufacturing method illustrated in FIG6 can be used to manufacture the heterojunction solar cell illustrated in FIG1, in which the microstructure area z1 of the backlight surface m2 in FIG1 is convex relative to the polished area z2. That is, the microstructure area z1 of the backlight surface m2 illustrated in FIG3 can further help increase the contact area of ​​the second grid line electrode 500b, further reduce the contact resistivity and body resistance of the second grid line electrode 500b, further increase the welding tension, improve the situation of grid breakage, and thereby improve the reliability of the second grid line electrode 500b. Moreover, in this process, compared with the manufacturing method shown in FIG6 , only one polishing is required to produce a protective layer, which is more conducive to improving production efficiency and reducing manufacturing costs.

[0115] It should be noted that in order to adjust the thickness difference between the polishing area and the microstructure area, the protective layer can be produced multiple times. The thickness of the protective layer produced each time may be inconsistent, and the material of the protective layer produced each time may be the same or different. It can be selected according to the specific situation. The embodiment of the present application does not impose any specific restrictions on this.

[0116] In some embodiments, the substrate is pretreated before being provided. The pretreatment process includes cleaning, polishing, and other processes to facilitate subsequent processes. The required pretreatment process can be selected according to the use case and is not specifically limited in the present embodiment.

[0117] 1 is taken as an example to illustrate the formation process of the intrinsic amorphous silicon layer, the doping layer and the transparent conductive layer.

[0118] First, a first intrinsic amorphous silicon layer 200a and a second intrinsic amorphous silicon layer 200b can be deposited on the light-receiving surface m1 and the backlight surface m2 respectively by chemical vapor deposition (e.g., plasma-enhanced chemical vapor deposition, PECVD). The thicknesses of the first intrinsic amorphous silicon layer 200a and the second intrinsic amorphous silicon layer 200b can be the same or different.

[0119] Next, a first doping layer 300a may be deposited on the first intrinsic amorphous silicon layer 200a, and a second doping layer 300b may be deposited on the second intrinsic amorphous silicon layer 200b by chemical vapor deposition (eg, plasma enhanced chemical vapor deposition, PECVD).

[0120] Again, the first transparent conductive layer 400a may be deposited on the first doped layer 300a, and the second transparent conductive layer 400b may be deposited on the second doped layer 300b by physical vapor deposition (eg, magnetron sputtering, PVD).

[0121] Finally, a first gate line electrode 500a and a second gate line electrode 500b can be formed on the first transparent conductive layer 400a and the second transparent conductive layer 400b on the sides facing away from the substrate 100, respectively, by screen printing, laser transfer, or electroplating. The first gate line electrode 500a is electrically connected to the first transparent conductive layer 400a, and the second gate line electrode 500b is electrically connected to the second transparent conductive layer 400b.

[0122] In this way, the desired heterojunction solar cell can be obtained through the implementation methods illustrated in some of the above embodiments.

[0123] The performance of the heterojunction solar cell provided by the embodiments of the present application is described below based on the contents illustrated in some of the above embodiments and related comparative examples.

[0124] In Example 1, Example 2, Example 3, Example 4 and Example 5 of the embodiments of the present application, Example 1, Example 2, Example 3 and Example 4 adopt the manufacturing method process illustrated in Figure 6 to manufacture the heterojunction solar cell illustrated in Figure 1, and Example 5 adopts the manufacturing method process illustrated in Figure 5 to manufacture the heterojunction solar cell illustrated in Figure 3. In Example 1, Example 2, Example 3, Example 4 and Example 5 of the present application, the microstructures located in the microstructure area of ​​the backlight surface all adopt a velvet structure, and a velvet structure is provided on the light-receiving surface. The heterojunction solar cell in Comparative Example 1 is a heterojunction solar cell in which both the light-receiving surface and the backlight surface are subjected to velvet treatment, and the entire backlight surface has a velvet structure. The heterojunction solar cell in Comparative Example 2 is a heterojunction solar cell in which the light-receiving surface is subjected to velvet treatment and the backlight surface is subjected to polishing treatment, and the entire backlight surface is polished. In Examples 1, 2, 3, 4, 5, Comparative Examples 1, and 2, parameters such as the thickness of the intrinsic amorphous silicon layer and the doped layer remained unchanged. The width of the gate electrode on the backlight side was 40 microns, and the width of the microstructure region z1 was 60 microns, so that the orthographic projection of the gate electrode on the backlight side of the substrate was entirely within the microstructure region z1. The base width of each pyramid in the velvet structure was 1.83 microns, and the pyramid specific surface area (i.e., the ratio of the pyramid's surface area to its base area) was approximately 1.3.

[0125] Table 1

[0126] In Table 1, for Example 1, Example 2, Example 3, Example 4, Example 5 and Comparative Example 2, the i(p) thickness is the thickness of the intrinsic amorphous silicon layer located in the polished area on the backlight surface. For Comparative Example 1, the i(p) thickness is the thickness corresponding to the thickness of the intrinsic amorphous silicon layer located in the velvet area on the backlight surface after conversion. The thickness is calculated by dividing the specific surface area to obtain the approximate thickness, that is, the thickness can be obtained by dividing the intrinsic amorphous silicon layer thickness located in the velvet area on the backlight surface by the velvet specific surface area. As can be seen from Table 1, the case where the backlight surface illustrated in Comparative Example 2 is a polished surface has better passivation performance than the case where the backlight surface illustrated in Comparative Example 1 is a velvet structure. However, due to the poor contact between the polished surface and the gate electrode, the contact resistance of the gate electrode on the backlight surface is greater and the welding tension is smaller. As the i(p) thickness decreases, the series resistance Rs becomes significantly smaller, and the passivation performance is also slightly affected. Among them, Examples 3 and 5 have the best efficiency, with an efficiency improvement of more than 0.12% compared to Comparative Example 1. Since the back gate electrode in Example 5 is a buried gate structure, Example 5 has better performance than Example 3. Therefore, it can be seen that the heterojunction solar cell provided by the embodiments of the present application can achieve better passivation effect, lower series resistance, and higher welding tension on the basis of balancing passivation performance and series resistance, thereby improving the overall photoelectric conversion efficiency of the solar cell.

[0127] Based on the same inventive concept, embodiments of the present application provide a photovoltaic module, including the heterojunction solar cell of any of the above embodiments; or, including the heterojunction solar cell produced by the method for producing a heterojunction solar cell of any of the above embodiments. The advantages of the heterojunction solar cell of any of the above embodiments, or the advantages of the heterojunction solar cell produced by the method for producing a heterojunction solar cell of any of the above embodiments, are also possessed by this photovoltaic module and will not be further elaborated here.

[0128] Based on the same inventive concept, the embodiment of the present application provides a photovoltaic system, including the photovoltaic module in any of the above embodiments. The advantages of the above photovoltaic modules are also possessed by the photovoltaic system, which will not be repeated here.

[0129] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0130] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A heterojunction solar cell, characterized in that: include: A substrate having a light-receiving surface and a backlight surface that are arranged opposite to each other; The backlight surface has a microstructure area and a polishing area adjacent to the microstructure area, and the microstructure area is provided with a microstructure; and An intrinsic amorphous silicon layer, a doped layer, a transparent conductive layer and a gate electrode, wherein the light-receiving surface and the backlight surface are respectively and sequentially stacked with the intrinsic amorphous silicon layer, the doped layer, the transparent conductive layer and the gate electrode; Wherein, at least part of the orthographic projection of the gate line electrode located on the backlight surface side on the backlight surface is located within the microstructure region.

2. The heterojunction solar cell according to claim 1, characterized in that: The orthographic projections of the gate line electrodes located on the backlight surface side on the backlight surface are all located within the microstructure area; or A portion of the orthographic projection of the gate line electrode located on the backlight surface side on the backlight surface is located in the microstructure area, and another portion is located in the polishing area.

3. The heterojunction solar cell according to claim 1 or 2, characterized in that: The ratio of the area of ​​the orthographic projection of the gate line electrode located on the backlight surface side on the backlight surface to the area of ​​the microstructure region is 0.5-2.

4. The heterojunction solar cell according to any one of claims 1 to 3, characterized in that: The portion of the backlight surface located in the microstructure area is configured to be recessed relative to the portion of the backlight surface located in the polishing area.

5. The heterojunction solar cell according to any one of claims 1 to 4, characterized in that: The microstructure includes a velvet structure.

6. The heterojunction solar cell according to any one of claims 1 to 5, characterized in that: The doped layer located on the backlight side is one of a P-type amorphous silicon layer, a P-type microcrystalline silicon layer or a P-type nanocrystalline silicon layer; and / or The doped layer located on the light receiving surface side is one of an N-type amorphous silicon layer, an N-type microcrystalline silicon layer or an N-type nanocrystalline silicon layer.

7. The heterojunction solar cell according to any one of claims 1 to 6, characterized in that: The light receiving surface is provided with a velvet structure.

8. A method for manufacturing a heterojunction solar cell, characterized in that: include: Providing a substrate; wherein the substrate comprises a light-receiving surface and a backlight surface that are arranged opposite to each other, the backlight surface has a microstructure region, and a polishing region adjacent to the microstructure region, and the microstructure region is provided with a microstructure; Forming an intrinsic amorphous silicon layer, a doping layer, a transparent conductive layer and a gate electrode on the light-receiving surface and the backlight surface respectively in sequence; Wherein, at least part of the orthographic projection of the gate line electrode located on the backlight side on the backlight side is located on the within the microstructure region.

9. The method for manufacturing a heterojunction solar cell according to claim 8, characterized in that: The providing of a substrate comprises: Polishing the light-receiving surface and the backlight surface; forming a protective layer on the polished backlight surface; Forming a mask pattern on the protective layer located on the backlight surface to expose a target area of ​​the backlight surface; Forming a suede structure in the target area; wherein the target area constitutes the microstructure area, and the suede structure located in the target area constitutes the microstructure; The protective layer is removed.

10. The method for manufacturing a heterojunction solar cell according to claim 9, characterized in that: Also includes: The velvet structure is formed on the target area and the velvet structure is also formed on the light receiving surface.

11. The method for manufacturing a heterojunction solar cell according to claim 8, characterized in that: The providing of a substrate comprises: Forming a suede structure on the light-receiving surface and a microstructure on the backlight surface; A protective layer is formed on the light-receiving surface and the backlight surface; wherein the protective layer on the light-receiving surface covers the velvet structure, and the protective layer on the backlight surface covers the microstructure; Forming a mask pattern on the protective layer located on the backlight surface to expose a target area of ​​the backlight surface; Performing a polishing process on the target area to form the polishing area; The protective layer is removed.

12. The method for manufacturing a heterojunction solar cell according to claim 11, characterized in that: The microstructure is formed by a preset process; The preset process includes one of a texturing process, an etching process, and a polishing process.

13. The method for manufacturing a heterojunction solar cell according to any one of claims 9 to 12, characterized in that: The protective layer is one of a silicon oxide layer, a silicon nitride layer, a phosphorus diffusion and absorption layer, an organic thin film layer, and an organic-inorganic composite thin film layer.

14. A photovoltaic module, characterized in that: A heterojunction solar cell comprising the heterojunction solar cell according to any one of claims 1 to 7; or A heterojunction solar cell manufactured by the method for manufacturing a heterojunction solar cell according to any one of claims 8 to 13.

15. A photovoltaic system, characterized in that: Comprising the photovoltaic module as claimed in claim 14.

Images