Electronic device and method for fast fourier transform

Abstract

According to an embodiment, an electronic device may comprise: a memory; and at least one processing circuit for orthogonal frequency division multiplexing (OFDM) modulation for changing the domain of a symbol sequence from a first domain to a second domain. The at least one processing circuit may be configured to obtain a first symbol sequence related to the first domain. The at least one processing circuit may be configured to obtain a second symbol sequence related to the second domain by performing, on the first symbol sequence, an inverse fast Fourier transform (IFFT) operation using a cyclic shift operation. The at least one processing circuit may be configured to generate a transmission signal by performing a cyclic extension operation on the basis of the second symbol sequence.

Description

Electronic devices and methods for fast Fourier transforms

[0001] The present disclosure relates to an electronic device and method for fast Fourier transform.

[0002] In wireless communication systems, the fast Fourier transform (FFT) operation is used to convert a time-domain sequence into a frequency-domain sequence when receiving a signal. When transmitting a signal, the cyclic extension operation is used to insert a cyclic prefix (CP) into the signal to prevent inter-channel interference.

[0003] The above information may be provided as background art to aid in understanding the present disclosure. No claim or determination is made as to whether any of the above is applicable as prior art related to the present disclosure.

[0004] According to one embodiment, an electronic device may include a memory and at least one processing circuit for orthogonal frequency division multiplexing (OFDM) modulation that changes a domain of a symbol sequence from a first domain to a second domain. The at least one processing circuit may be configured to obtain a first symbol sequence for the first domain. The at least one processing circuit may be configured to obtain a second symbol sequence for the second domain by performing an inverse fast Fourier transform (IFFT) operation using a cyclic shift operation on the first symbol sequence. The at least one processing circuit may be configured to generate a transmission signal by performing a cyclic extension operation based on the second symbol sequence. The IFFT operation using the above circular shift operation may include an operation of changing the value of the most significant bit (MSB) of the bit sequence of each FFT index from 0 to 1 or from 1 to 0 among the FFT indices for the first domain according to the FFT (fast Fourier transform) size.

[0005] According to one embodiment, a method of an electronic device may include an operation of obtaining a first symbol sequence for a first domain. The method may include an operation of obtaining a second symbol sequence for a second domain by performing an inverse fast Fourier transform (IFFT) operation using a cyclic shift operation on the first symbol sequence. The method may include an operation of generating a transmission signal by performing a cyclic extension operation based on the second symbol sequence. The IFFT operation using the cyclic shift operation may include an operation of changing a value of a most significant bit (MSB) of a bit sequence of each FFT index among FFT indexes for the first domain according to an FFT size from 0 to 1 or from 1 to 0.

[0006] According to one embodiment, an electronic device may include a memory, and at least one processing circuit for orthogonal frequency division multiplexing (OFDM) modulation that changes a domain of a symbol sequence from a first domain to a second domain. The at least one processing circuit may be configured to obtain a first symbol sequence for the first domain. The at least one processing circuit may be configured to obtain a second symbol sequence by performing a cyclic shift operation on the first symbol sequence. The at least one processing circuit may be configured to obtain a third symbol sequence for the second domain by performing an inverse fast Fourier transform (IFFT) operation for a cyclic extension operation based on the second symbol sequence. The at least one processing circuit may be configured to generate a transmission signal by performing the cyclic extension operation on the third symbol sequence. The IFFT operation for the above cyclic expansion operation may include an operation of changing the value of at least one bit of a bit sequence of each FFT index from 0 to 1 or from 1 to 0 among the FFT indices for the second domain according to the FFT (fast Fourier transform) size.

[0007] Figure 1 illustrates a wireless communication system.

[0008] Figure 2a illustrates a front-hole interface.

[0009] Figure 2b illustrates the fronthaul interface of an O(open)-RAN(radio access network).

[0010] Figure 3a illustrates the functional configuration of a distributed unit (DU).

[0011] Figure 3b illustrates the functional configuration of a RU (radio unit).

[0012] Figure 4 illustrates an example of function split between DU and RU.

[0013] Figure 5 illustrates an example of the operation of an OFDM (orthogonal frequency division multiplexing) modulation circuit.

[0014] Figure 6 illustrates an example of a cyclic shift operation.

[0015] Figure 7 illustrates an example of a cyclic extension operation.

[0016] Figure 8 illustrates a signal flow graph regarding the FFT operation of the DIF FFT (decimation in frequency fast Fourier transform) structure.

[0017] Figure 9 illustrates a signal flow diagram for an FFT operation using a circular shift operation of a DIF FFT structure.

[0018] Fig. 10 illustrates an OFDM modulation circuit for performing an IFFT operation using a circular shift operation.

[0019] Figure 11 illustrates a signal flow graph regarding the FFT operation of the DIT FFT (decimation in time fast Fourier transform) structure.

[0020] Figure 12 illustrates a signal flow diagram for an FFT operation for a cyclic expansion operation of a DIT FFT structure.

[0021] Figure 13 illustrates an OFDM modulation circuit for performing an IFFT operation for a cyclic expansion operation.

[0022] Figure 14 shows an example of input and output for the second buffer.

[0023] Fig. 15 illustrates a flowchart regarding the operation of an electronic device according to a DIF FFT structure.

[0024] Fig. 16 illustrates a flowchart regarding the operation of an electronic device according to the DIT FFT structure.

[0025] Figure 17 shows an example of the configuration of a processing device.

[0026] The terms used in this disclosure are used only to describe specific embodiments and may not be intended to limit the scope of other embodiments. The singular expression may include plural expressions unless the context clearly indicates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by those of ordinary skill in the art described in this disclosure. Terms defined in general dictionaries among the terms used in this disclosure may be interpreted as having the same or similar meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined in this disclosure. In some cases, even if a term is defined in this disclosure, it cannot be interpreted to exclude embodiments of the present disclosure.

[0027] The various embodiments of the present disclosure described below illustrate a hardware-based approach as an example. However, since the various embodiments of the present disclosure include techniques utilizing both hardware and software, the various embodiments of the present disclosure do not exclude a software-based approach.

[0028] In the following description, terms referring to signals (e.g., signal, information, message, signaling), terms referring to resources (e.g., symbol, slot, subframe, radio frame, subcarrier, resource element (RE), resource block (RB), bandwidth part (BWP), occasion), terms for operational states (e.g., step, operation, procedure), terms referring to data (e.g., packet, user stream, information, bit, symbol, codeword), terms referring to channels, terms referring to network entities, terms referring to components of devices, etc. are examples for convenience of description. Therefore, the present disclosure is not limited to the terms described below, and other terms having equivalent technical meanings may be used.

[0029] In addition, in the present disclosure, expressions such as "more than" or "less than" may be used to determine whether a specific condition is satisfied or fulfilled, but this is merely a description for expressing an example and does not exclude descriptions such as "more than" or "less than." A condition described as "more than" may be replaced with "more than," a condition described as "less than" may be replaced with "less than," and a condition described as "more than and less than" may be replaced with "more than and less than." In addition, hereinafter, "A" to "B" mean at least one of elements from A (including A) to B (including B). hereinafter, "C" and / or "D" mean at least one of "C" or "D," that is, including {"C", "D", "C" and "D"}.

[0030] Although the present disclosure describes various embodiments using terms used in some communication standards (e.g., 3rd Generation Partnership Project (3GPP), extensible radio access network (xRAN), open-radio access network (O-RAN), etc.), these are merely examples for explanation. The various embodiments of the present disclosure can be easily modified and applied to other communication systems.

[0031] Figure 1 illustrates a wireless communication system.

[0032] Referring to FIG. 1, FIG. 1 illustrates a base station (110) and a terminal (120) as some of the nodes utilizing a wireless channel in a wireless communication system. Although FIG. 1 illustrates only one base station, the wireless communication system may further include other base stations identical or similar to the base station (110).

[0033] The base station (110) is a network infrastructure that provides wireless access to the terminal (120). The base station (110) has coverage defined based on the distance at which a signal can be transmitted. In addition to the base station, the base station (110) may be referred to as an 'access point (AP)', 'eNodeB (eNB)', '5th generation node', 'next generation nodeB (gNB)', 'wireless point', 'transmission / reception point (TRP)', or other terms having equivalent technical meanings.

[0034] The terminal (120) is a device used by a user and communicates with the base station (110) via a wireless channel. The link from the base station (110) to the terminal (120) is referred to as a downlink (DL), and the link from the terminal (120) to the base station (110) is referred to as an uplink (UL). In addition, although not shown in FIG. 1, the terminal (120) and another terminal may communicate with each other via a wireless channel. In this case, the link between the terminal (120) and another terminal (device-to-device link, D2D) is referred to as a sidelink, and the sidelink may be used interchangeably with the PC5 interface. In some other embodiments, the terminal (120) may be operated without the involvement of a user. According to one embodiment, the terminal (120) is a device that performs machine type communication (MTC) and may not be carried by the user. Additionally, according to one embodiment, the terminal (120) may be an NB (narrowband)-IoT (internet of things) device.

[0035] The terminal (120) may be referred to as a terminal, or other terms such as 'user equipment (UE),' 'customer premises equipment (CPE),' 'mobile station,' 'subscriber station,' 'remote terminal,' 'wireless terminal,' 'electronic device,' or 'user device,' or other terms having equivalent technical meanings.

[0036] The base station (110) and the terminal (120) can perform beamforming. The base station (110) and the terminal (120) can transmit and receive wireless signals in a relatively low frequency band (e.g., FR 1 (frequency range 1) of NR). In addition, the base station (110) and the terminal (120) can transmit and receive wireless signals in a relatively high frequency band (e.g., FR 2 (or, FR 2-1, FR 2-2, FR 2-3), FR 3 of NR), millimeter wave (mmWave) band (e.g., 28 GHz, 30 GHz, 38 GHz, 60 GHz)). To improve channel gain, the base station (110) and the terminal (120) can perform beamforming. Here, the beamforming can include transmission beamforming and reception beamforming. The base station (110) and the terminal (120) can impart directionality to the transmitted or received signal. To this end, the base station (110) and the terminal (120) can select serving beams through a beam search or beam management procedure. After the serving beams are selected, subsequent communication can be performed through resources that have a QCL relationship with the resource that transmitted the serving beams.

[0037] If large-scale characteristics of a channel carrying a symbol on a first antenna port can be inferred from a channel carrying a symbol on a second antenna port, the first antenna port and the second antenna port can be evaluated to have a QCL relationship. For example, the large-scale characteristics may include at least one of delay spread, Doppler spread, Doppler shift, average gain, average delay, and a spatial receiver parameter.

[0038] Although both the base station (110) and the terminal (120) are described as performing beamforming in FIG. 1, the embodiments of the present disclosure are not necessarily limited thereto. In some embodiments, the terminal may or may not perform beamforming. Furthermore, the base station may or may not perform beamforming. That is, either only one of the base station and the terminal may perform beamforming, or neither the base station nor the terminal may perform beamforming.

[0039] In the present disclosure, a beam refers to a spatial flow of a signal in a wireless channel, and is formed by one or more antennas (or antenna elements), and this forming process may be referred to as beamforming. Beamforming may include at least one of analog beamforming and digital beamforming (e.g., precoding). Reference signals transmitted based on beamforming may include, for example, a demodulation-reference signal (DM-RS), a channel state information-reference signal (CSI-RS), a synchronization signal / physical broadcast channel (SS / PBCH), and a sounding reference signal (SRS). In addition, as a configuration for each reference signal, an IE such as a CSI-RS resource or an SRS-resource may be used, and this configuration may include information associated with the beam. Information associated with a beam may mean whether the configuration (e.g., a CSI-RS resource) uses the same spatial domain filter as another configuration (e.g., another CSI-RS resource within the same CSI-RS resource set) or a different spatial domain filter, or whether it is quasi-co-located (QCL) with a reference signal, and if so, what type it is (e.g., QCL type A, B, C, D).

[0040] In the past, in communication systems with relatively large cell radius of base stations, each base station was installed to include the functions of a digital processing unit (or distributed unit (DU)) and a radio frequency (RF) processing unit (or radio unit (RU)). However, as higher frequency bands are used in 4G (4th generation) and / or subsequent communication systems (e.g., 5G) and the cell coverage of base stations decreases, the number of base stations to cover a specific area has increased. The installation costs for operators to install base stations have also increased. In order to minimize the installation costs of base stations, a structure has been proposed in which the DU and RU of a base station are separated, one or more RUs are connected to one DU via a wired network, and one or more RUs are geographically distributed to cover a specific area. Hereinafter, the deployment structure and expanded examples of base stations according to various embodiments of the present disclosure are described through FIGS. 2A and 2B.

[0041] FIG. 2A illustrates a fronthaul interface. Unlike the backhaul between a base station and a core network, fronthaul refers to the connection between entities between a wireless LAN and a base station. FIG. 2A illustrates an example of a fronthaul structure between a DU (210) and one RU (220), but this is merely for convenience of explanation and the present disclosure is not limited thereto. In other words, embodiments of the present disclosure can also be applied to a fronthaul structure between one DU and multiple RUs. For example, embodiments of the present disclosure can be applied to a fronthaul structure between one DU and two RUs. Furthermore, embodiments of the present disclosure can also be applied to a fronthaul structure between one DU and three RUs.

[0042] Referring to FIG. 2A, a base station (110) may include a DU (210) and an RU (220). A fronthaul (215) between the DU (210) and the RU (220) may be operated via an FX interface. For operation of the fronthaul (215), an interface such as an enhanced common public radio interface (eCPRI) or radio over ethernet (ROE) may be used, for example.

[0043] As communications technology advances, mobile data traffic increases, significantly increasing the bandwidth requirements for the fronthaul between the digital unit and the radio unit. In deployments such as C-RAN (centralized / cloud radio access network), the DU performs functions for the packet data convergence protocol (PDCP), radio link control (RLC), media access control (MAC), and physical layer (PHY), while the RU can be implemented to perform additional functions for the PHY layer in addition to its radio frequency (RF) functions.

[0044] DU (210) may be responsible for upper layer functions of a wireless network. For example, DU (210) may perform functions of the MAC layer and a part of the PHY layer. Here, a part of the PHY layer refers to functions performed at a higher level among the functions of the PHY layer, and may include, for example, channel encoding (or channel decoding), scrambling (or descrambling), modulation (or demodulation), and layer mapping (or layer demapping). According to an embodiment, if DU (210) complies with the O-RAN standard, it may be referred to as O-DU (O-RAN DU). DU (210) may be replaced with a first network entity for a base station (e.g., gNB) in embodiments of the present disclosure, if necessary.

[0045] The RU (220) may be responsible for lower layer functions of a wireless network. For example, the RU (220) may perform a part of the PHY layer, an RF function. Here, a part of the PHY layer refers to functions of the PHY layer that are performed at a relatively lower level than the DU (210), and may include, for example, iFFT transformation (or FFT transformation), CP (cyclic prefix) insertion (CP removal), and digital beamforming. An example of such specific functional separation is described in detail in FIG. 4. The RU (220) may be referred to as an 'access unit (AU)', an 'access point (AP)', a 'transmission / reception point (TRP)', a 'remote radio head (RRH)', a 'radio unit (RU)', or other terms having an equivalent technical meaning thereto. In one embodiment, if RU (220) complies with the O-RAN standard, it may be referred to as O-RU (O-RAN RU). RU (220) may be replaced with a second network entity for a base station (e.g., gNB) in embodiments of the present disclosure, if necessary.

[0046] Although FIG. 2A illustrates that the base station (110) includes a DU (210) and a RU (220), the embodiments of the present disclosure are not limited thereto. The base station according to the embodiments may be implemented in a distributed deployment according to a centralized unit (CU) configured to perform functions of upper layers of an access network (e.g., packet data convergence protocol (PDCP), radio resource control (RRC)) and a distributed unit (DU) configured to perform functions of lower layers. In this case, the distributed unit (DU) may include the digital unit (DU) and radio unit (RU) of FIG. 1. Between a core (e.g., 5GC (5G core) or NGC (next generation core)) network and a radio network (RAN), the base station may be implemented in a structure in which CU, DU, and RU are arranged in that order. The interface between CU and DU (distributed unit) can be referred to as the F1 interface.

[0047] A centralized unit (CU) can be connected to one or more DUs and can be responsible for functions at a higher layer than the DU. For example, the CU can be responsible for functions at the radio resource control (RRC) and packet data convergence protocol (PDCP) layers, while the DU and RU can be responsible for functions at lower layers. The DU can perform some functions (high PHY) of the radio link control (RLC), media access control (MAC), and physical (PHY) layers, while the RU can be responsible for the remaining functions (low PHY) of the PHY layer. In addition, for example, a digital unit (DU) can be included in a distributed unit (DU) depending on the implementation of a distributed deployment of the base station. Hereinafter, unless otherwise defined, the operations of DU (digital unit) and RU are described, but various embodiments of the present disclosure can be applied to both a base station deployment including CU and a deployment in which DU is directly connected to the core network (i.e., a base station in which CU and DU are integrated as a single entity (e.g., NG-RAN node)).

[0048] Figure 2b illustrates the fronthaul interface of an open RAN (radio access network). A base station (110) according to a distributed deployment is exemplified as an eNB or gNB.

[0049] Referring to FIG. 2b, the base station (110) may include an O-DU (251) and O-RUs (253-1, …, 253-n). Hereinafter, for convenience of explanation, the operation and function of the O-RU (253-1) may be understood as a description of each of the other O-RUs (e.g., O-RU (253-n)).

[0050] The O-DU (251) is a logical node that includes functions, excluding functions exclusively assigned to the O-RU (253-1), among the functions of a base station (e.g., eNB, gNB) according to FIG. 4 described below. The O-DU (251) can control the operation of the O-RUs (253-1, …, 253-n). The O-DU (251) may be referred to as an LLS (lower layer split) CU (central unit). The O-RU (253-1) is a logical node that includes a subset of the functions of a base station (e.g., eNB, gNB) according to FIG. 4 described below. Real-time aspects of control plane (C-plane) communication and user plane (U-plane) communication with the O-RU (253-1) can be controlled by the O-DU (251).

[0051] The O-DU (251) can communicate with the O-RU (253-1) through an LLS interface. The LLS interface corresponds to a fronthaul interface. The LLS interface refers to a logical interface between the O-DU (251) and the O-RU (253-1) that utilizes lower layer functional split (i.e., intra-PHY based functional split). The LLS-C between the O-DU (251) and the O-RU (253-1) provides the C-plane through the LLS interface. The LLS-U between the O-DU (251) and the O-RU (253-1) provides the U-plane through the LLS interface.

[0052] In FIG. 2B, to explain the O-RAN, entities of the base station (110) are described as O-DU and O-RU. However, these names are not to be construed as limiting the embodiments of the present disclosure. In the embodiments described below, it is obvious that the operations of the DU (210) can be performed by the O-DU (251). The description of the DU (210) can be applied to the O-DU (251). Similarly, in the embodiments described below, it is obvious that the operations of the RU (220) can be performed by the O-RU (253-1). The description of the RU (220) can be applied to the O-DU (253-1).

[0053] Fig. 3a illustrates the functional configuration of a DU (distributed unit). The configuration illustrated in Fig. 3a can be understood as the configuration of the DU (210) of Fig. 2a (or the O-DU (250) of Fig. 2b) as part of a base station. Terms such as "...unit" and "...unit" used hereinafter mean a unit that processes at least one function or operation, and this can be implemented by hardware, software, or a combination of hardware and software.

[0054] Referring to FIG. 3a, DU (210) includes a transceiver (310), memory (320), and processor (330).

[0055] The transceiver (310) can perform functions for transmitting and receiving signals in a wired communication environment. The transceiver (310) can include a wired interface for controlling direct connections between devices via a transmission medium (e.g., copper wire, optical fiber). For example, the transceiver (310) can transmit electrical signals to other devices via copper wire, or perform conversion between electrical signals and optical signals. The DU (210) can communicate with a radio unit (RU) via the transceiver (310). The DU (210) can be connected to a core network or a CU in a distributed arrangement via the transceiver (310).

[0056] The transceiver (310) may perform functions for transmitting and receiving signals in a wireless communication environment. For example, the transceiver (310) may perform a conversion function between a baseband signal and a bit stream according to the physical layer specifications of the system. For example, when transmitting data, the transceiver (310) generates complex symbols by encoding and modulating the transmitted bit stream. In addition, when receiving data, the transceiver (310) restores the received bit stream by demodulating and decoding the baseband signal. In addition, the transceiver (310) may include multiple transmission and reception paths. Furthermore, according to one embodiment, the transceiver (310) may be connected to the core network or other nodes (e.g., an integrated access backhaul (IAB).

[0057] The transceiver (310) can transmit and receive signals. For example, the transceiver (310) can transmit a management plane (M-plane) message. For example, the transceiver (310) can transmit a management plane (S-plane) message. For example, the transceiver (310) can transmit a control plane (C-plane) message. For example, the transceiver (310) can transmit a user plane (U-plane) message. For example, the transceiver (310) can receive a user plane message. Although only the transceiver (310) is illustrated in FIG. 3A, in other implementations, the DU (210) may include two or more transceivers.

[0058] The transceiver (310) transmits and receives signals as described above. Accordingly, all or part of the transceiver (310) may be referred to as a "communication unit," a "transmitter," a "receiver," or a "transmitter-receiver unit." Furthermore, in the following description, transmission and reception performed via a wireless channel are used to mean that the transceiver (310) performs the processing described above.

[0059] Although not illustrated in FIG. 3A, the transceiver (310) may further include a backhaul transceiver for connection to the core network or other base stations. The backhaul transceiver provides an interface for communicating with other nodes within the network. That is, the backhaul transceiver converts a bit stream transmitted from the base station to other nodes, such as other access nodes, other base stations, upper nodes, the core network, etc., into a physical signal, and converts a physical signal received from other nodes into a bit stream.

[0060] The memory (320) stores data such as basic programs, application programs, and setting information for the operation of the DU (210). The memory (320) may be referred to as a storage unit. The memory (320) may be composed of volatile memory, nonvolatile memory, or a combination of volatile memory and nonvolatile memory. In addition, the memory (320) provides stored data upon request from the processor (330).

[0061] The processor (330) controls the overall operations of the DU (210). The processor (380) may be referred to as a control unit. For example, the processor (330) transmits and receives signals through the transceiver (310) (or through the backhaul communication unit). In addition, the processor (330) records and reads data from the memory (320). In addition, the processor (330) may perform the functions of the protocol stack required by the communication standard. Although only the processor (330) is illustrated in FIG. 3A, the DU (210) may include two or more processors according to other implementation examples.

[0062] The configuration of DU (210) illustrated in FIG. 3A is merely an example, and examples of DUs performing embodiments of the present disclosure are not limited to the configuration illustrated in FIG. 3A. In some embodiments, some configurations may be added, deleted, or changed.

[0063] Fig. 3b illustrates the functional configuration of a radio unit (RU). The configuration illustrated in Fig. 3b can be understood as a configuration of the RU (220) of Fig. 2b or the O-RU (253-1) of Fig. 2b as part of a base station. Terms such as "...unit" and "...unit" used hereinafter mean a unit that processes at least one function or operation, and this can be implemented by hardware, software, or a combination of hardware and software.

[0064] Referring to FIG. 3b, the RU (220) includes an RF transceiver (360), a fronthaul transceiver (365), a memory (370), and a processor (380).

[0065] The RF transceiver (360) performs functions for transmitting and receiving signals via a wireless channel. For example, the RF transceiver (360) upconverts a baseband signal into an RF band signal and transmits it via an antenna, and downconverts an RF band signal received via the antenna into a baseband signal. For example, the RF transceiver (360) may include a transmit filter, a receive filter, an amplifier, a mixer, an oscillator, a DAC, an ADC, and the like.

[0066] The RF transceiver (360) may include multiple transmission and reception paths. Furthermore, the RF transceiver (360) may include an antenna unit. The RF transceiver (360) may include at least one antenna array composed of multiple antenna elements. In terms of hardware, the RF transceiver (360) may be composed of digital circuits and analog circuits (e.g., a radio frequency integrated circuit (RFIC)). Here, the digital circuits and analog circuits may be implemented in a single package. In addition, the RF transceiver (360) may include multiple RF chains. The RF transceiver (360) may perform beamforming. The RF transceiver (360) may apply beamforming weights to a signal to be transmitted and received in order to impart directionality according to the settings of the processor (380). According to one embodiment, the RF transceiver (360) may include a radio frequency (RF) block (or RF section).

[0067] According to one embodiment, the RF transceiver (360) can transmit and receive signals on a radio access network. For example, the RF transceiver (360) can transmit a downlink signal. The downlink signal can include a synchronization signal (SS), a reference signal (RS) (e.g., a cell-specific reference signal (CRS), a demodulation (DM)-RS), system information (e.g., a MIB, a SIB, remaining system information (RMSI), other system information (OSI)), a configuration message, control information, or downlink data. In addition, for example, the RF transceiver (360) can receive an uplink signal. The uplink signal may include a random access related signal (e.g., a random access preamble (RAP) (or Msg1 (message 1)), Msg3 (message 3)), a reference signal (e.g., a sounding reference signal (SRS), DM-RS), or a power headroom report (PHR). Although only the RF transceiver (360) is illustrated in FIG. 3b, in other implementation examples, the RU (220) may include two or more RF transceivers.

[0068] According to embodiments, the RF transceiver (460) may transmit a RIM-RS. The RF transceiver (460) may transmit a first type of RIM-RS (e.g., RIM-RS type 1 of 3GPP) to indicate the detection of far-field interference. The RF transceiver (460) may transmit a second type of RIM-RS (e.g., RIM-RS type 2 of 3GPP) to indicate the presence or absence of far-field interference.

[0069] The fronthaul transceiver (365) can transmit and receive signals. According to one embodiment, the fronthaul transceiver (365) can transmit and receive signals on the fronthaul interface. For example, the fronthaul transceiver (365) can receive a management plane (M-plane) message. For example, the fronthaul transceiver (365) can receive a management plane (S-plane) message. For example, the fronthaul transceiver (365) can receive a control plane (C-plane) message. For example, the fronthaul transceiver (365) can transmit a user plane (U-plane) message. For example, the fronthaul transceiver (365) can receive a user plane message. Although only the fronthaul transceiver (365) is shown in FIG. 3b, according to other implementation examples, the RU (220) may include two or more fronthaul transceivers.

[0070] The RF transceiver (360) and the fronthaul transceiver (365) transmit and receive signals as described above. Accordingly, all or part of the RF transceiver (360) and the fronthaul transceiver (365) may be referred to as a 'communication unit', a 'transmitter unit', a 'receiver unit', or a 'transmitter-receiver unit'. In addition, in the following description, transmission and reception performed through a wireless channel are used to mean that the processing as described above is performed by the RF transceiver (360). In the following description, transmission and reception performed through a wireless channel are used to mean that the processing as described above is performed by the RF transceiver (360).

[0071] The memory (370) stores data such as basic programs, application programs, and setting information for the operation of the RU (220). The memory (370) may be referred to as a storage unit. The memory (370) may be configured as volatile memory, non-volatile memory, or a combination of volatile memory and non-volatile memory. In addition, the memory (370) provides the stored data according to a request from the processor (380). According to one embodiment, the memory (370) may include a memory for conditions, commands, or setting values ​​related to the SRS transmission method.

[0072] The processor (380) controls the overall operations of the RU (220). The processor (380) may be referred to as a control unit. For example, the processor (380) transmits and receives signals through the RF transceiver (360) or the fronthaul transceiver (365). In addition, the processor (380) records and reads data in the memory (370). In addition, the processor (380) may perform functions of a protocol stack required by a communication standard. Although only the processor (380) is illustrated in FIG. 3B, the RU (220) may include two or more processors according to other implementation examples. The processor (380) may be a set of instructions or codes stored in the memory (370), or may be a storage space that stores instructions / codes or instructions / codes that are at least temporarily residing in the processor (380), or may be a part of the circuitry that constitutes the processor (380). Additionally, the processor (380) may include various modules for performing communication. The processor (380) may control the RU (220) to perform operations according to the embodiments described below.

[0073] The configuration of RU (220) illustrated in FIG. 3b is merely an example, and examples of RUs performing embodiments of the present disclosure are not limited to the configuration illustrated in FIG. 3b. In some embodiments, some configurations may be added, deleted, or changed.

[0074] Figure 4 illustrates an example of function split between DUs and RUs. As wireless communication technologies advance (e.g., the introduction of 5G (5th generation) communication systems (or NR (new radio) communication systems), the frequency bands used have increased further. As the cell radius of a base station has become significantly smaller, the number of RUs required for installation has also increased further. Furthermore, in 5G communication systems, the amount of data transmitted has increased by a factor of up to ten, significantly increasing the transmission capacity of the wired network transmitted to the fronthaul. Due to the factors described above, the installation cost of the wired network in the 5G communication system may increase significantly. Therefore, in order to lower the transmission capacity of the wired network and reduce the installation cost of the wired network, 'function split' can be utilized, which transfers some of the functions of the modem of the DU to the RU to lower the transmission capacity of the fronthaul.

[0075] To reduce the burden on the DU, the role of the RU, which is traditionally solely responsible for RF functions, can be expanded to include some physical layer functions. As the RU performs higher-layer functions, its throughput increases, which can increase transmission bandwidth in the fronthaul while reducing latency requirements due to response processing. However, as the RU performs higher-layer functions, virtualization gains decrease, and the RU's size, weight, and cost increase. Considering the trade-offs between the advantages and disadvantages described above, implementing an optimal functional separation is required.

[0076] Referring to Figure 4, the functional separation in the physical layer below the MAC layer is illustrated. For the downlink (DL) that transmits a signal to a terminal through a wireless network, the base station can sequentially perform channel encoding / scrambling, modulation, layer mapping, antenna mapping, RE mapping, digital beamforming (e.g., precoding), iFFT transform / CP insertion, and RF transform. For the uplink (UL) that receives a signal from a terminal through a wireless network, the base station can sequentially perform RF transform, FFT transform / CP removal, digital beamforming (pre-combining), RE demapping, channel estimation, layer demapping, demodulation, and decoding / descrambling. The separation of uplink and downlink functions can be defined in various types depending on the needs of vendors, discussions in standards, etc., according to the above-mentioned trade-offs.

[0077] In the first functional separation (405), the RU performs the RF function, and the DU performs the PHY function. The first functional separation is one in which the PHY function is not substantially implemented in the RU, and may be referred to as Option 8, for example. In the second functional separation (410), the RU performs iFFT conversion / CP insertion in the DL and FFT conversion / CP removal in the UL of the PHY function, and the DU performs the remaining PHY functions. As an example, the second functional separation (410) may be referred to as Option 7-1. In the third functional separation (420a), the RU performs iFFT conversion / CP insertion in the DL and FFT conversion / CP removal and digital beamforming in the UL of the PHY function, and the DU performs the remaining PHY functions. As an example, the third functional separation (420a) may be referred to as Option 7-2x Category A. In the fourth functional separation (420b), the RU performs up to digital beamforming in both the DL and UL, and the DU performs upper PHY functions after the digital beamforming. For example, the fourth functional separation (420b) may be referred to as Option 7-2x Category B. In the fifth functional separation (425), the RU performs up to RE mapping (or RE demapping) in both the DL and UL, and the DU performs upper PHY functions after RE mapping (or RE demapping). For example, the fifth functional separation (425) may be referred to as Option 7-2. In the sixth functional separation (430), the RU performs up to modulation (or demodulation) in both the DL and UL, and the DU performs upper PHY functions after modulation (or demodulation). For example, the sixth functional separation (430) may be referred to as Option 7-3. In the seventh functional separation (440), the RU performs encoding / scrambling (or decoding / descrambling) in both the DL and UL, and the DU performs subsequent upper PHY functions up to modulation (or demodulation). For example, the seventh functional separation (440) may be referred to as Option 6.

[0078] In one embodiment, when a large amount of signal processing is expected, such as in the FR 1 MMU, functional separation at a relatively high layer (e.g., the fourth functional separation (420b)) may be required to reduce fronthaul capacity. In addition, functional separation at too high a layer (e.g., the sixth functional separation (430)) may complicate the control interface and cause a burden on the implementation of the RU due to the inclusion of a large number of PHY processing blocks within the RU. Therefore, appropriate functional separation may be required depending on the arrangement and implementation method of the DU and the RU.

[0079] In one embodiment, if the precoding of data received from the DU cannot be processed (i.e., if the precoding capability of the RU is limited), the third functional separation (420a) or a lower functional separation (e.g., the second functional separation (410)) may be applied. Conversely, if the DU has the capability to process the precoding of data received from the DU, the fourth functional separation (420b) or a higher functional separation (e.g., the sixth functional separation (430)) may be applied.

[0080] Hereinafter, embodiments in the present disclosure are described based on the third functional separation (420a) (which may be referred to as category A (CAT-A)) or the fourth functional separation (420b) (which may be referred to as category B (CAT-B)) for performing beamforming processing in an RU unless otherwise specified. The O-RAN standard distinguishes the types of O-RUs depending on whether the precoding function is located at the interface of the O-DU or the O-RU interface. An O-RU that does not perform precoding (i.e., has low complexity) may be referred to as a CAT-A O-RU. An O-RU that performs precoding may be referred to as a CAT-B O-RU.

[0081] Hereinafter, the term "upper-PHY" refers to physical layer processing handled in the DU of the fronthaul interface. For example, the upper-PHY may include FEC encoding / decoding, scrambling, and modulation / demodulation. Hereinafter, the term "lower-PHY" refers to physical layer processing handled in the RU of the fronthaul interface. For example, the lower-PHY may include FFT / iFFT, digital beamforming, PRACH (physical random access channel) extraction, and filtering. However, the above-described criteria do not exclude embodiments through other functional separations. The functional configuration, signaling, or operation of the embodiments described below may be applied not only to the third functional separation (420a) or the fourth functional separation (420b), but also to other functional separations.

[0082] Embodiments of the present disclosure exemplarily describe the standards of eCPRI and O-RAN as fronthaul interfaces when transmitting messages between a DU (e.g., DU (210) of FIG. 2a) and an RU (e.g., RU (220) of FIG. 2a). The Ethernet payload of the message may include an eCPRI header, an O-RAN header, and additional fields. Hereinafter, various embodiments of the present disclosure are described using standard terms of eCPRI or O-RAN, but other expressions having equivalent meanings to each term may be used instead in various embodiments of the present disclosure. Hereinafter, various embodiments of the present disclosure are described using standard terms of eCPRI or O-RAN, but are not limited thereto. For example, in various embodiments of the present disclosure, the CPRI standard may be used as the fronthaul interface.

[0083] The fronthaul transport protocol can use Ethernet and eCPRI, which are easy to share with networks. The Ethernet payload can include an eCPRI header and an O-RAN header. The eCPRI header can be located at the beginning of the Ethernet payload. The contents of the eCPRI header are as follows.

[0084] 1) ecpriVersion (4 bits): This parameter indicates the eCPRI protocol version.

[0085] 2) ecpriReserved (3 bits): This parameter is reserved for further use by eCPRI.

[0086] 3) ecpriConcatenation (1 bit): This parameter indicates when eCPRI concatenation is in use.

[0087] 4) ecpriMessage (1 byte): This parameter indicates the type of service carried by the message type. For example, the parameter indicates an IQ data message, a real-time control data message, or a transmission network delay measurement message.

[0088] 5) ecpriPayload (2 bytes): This parameter indicates the byte size of the payload portion of the eCPRI message.

[0089] 6) ecpriRtcid / ecpriPcid (2 bytes): This parameter is the eAxC (extended antenna-carrier) identifier (eAxC ID) and identifies a specific data flow associated with each C-plane (ecpriRtcid) or U-plane (ecpriPcid) message.

[0090] 7) ecpriSeqid (2 bytes): This parameter provides unique message identification and ordering at both levels. The first octet of this parameter is a sequence ID used to identify the order of messages within the eAxC message stream. The sequence ID is used to ensure that all messages are received and to reorder out-of-order messages. The second octet of this parameter is a subsequence ID. The subsequence ID is used to ensure ordering and implement reordering when radio-transport-level (eCPRI or IEEE-1914.3) fragmentation occurs.

[0091] The eAxC identifier (ID) includes a band and sector identifier ('BandSector_ID'), a component carrier identifier ('CC_ID'), a spatial stream identifier ('RU_Port_ID'), and a distributed unit identifier ('DU_Port_ID'). The bit allocation of the eAxC ID can be distinguished as follows.

[0092] 1) DU_port ID: The DU_port ID is used to distinguish processing units (e.g., different baseband cards) in the O-DU. The O-DU is expected to allocate bits for the DU_port ID, and the O-RU is expected to append the same value to the UL U-plane message carrying the same sectionId data.

[0093] 2) BandSector_ID: Aggregated cell identifier (band and sector distinction supported by O-RU).

[0094] 3) CC_ID: CC_ID identifies the carrier component supported by the O-RU.

[0095] 4) RU_port ID: The RU_port ID specifies logical flows such as data layer or spatial streams, and signaling channels that require separate numerologies (e.g. PRACH) or special antenna allocation such as SRS.

[0096] The application protocol of the fronthaul may include a control plane (C-plane), a user plane (U-plane), a synchronization plane (S-plane), and a management plane (M-plane).

[0097] The control plane may be configured to provide scheduling information and beamforming information via control messages. The control plane refers to real-time control between DUs and RUs. The user plane may include IQ sample data transmitted between DUs and RUs. The user plane may include user downlink data (IQ data or SSB / RS), uplink data (IQ data or SRS / RS), or PRACH data. A weight vector of the beamforming information described above may be multiplied by the user's data. The synchronization plane generally refers to traffic between DUs and RUs for a synchronization controller (e.g., IEEE grand master). The synchronization plane may be related to timing and synchronization. The management plane refers to non-real-time control between DUs and RUs. The management plane may be related to initial setup, non-realtime reset or reset, and non-realtime report.

[0098] Control plane messages, or C-plane messages, can be encapsulated based on a two-layer header approach. The first layer can consist of the eCPRI common header or the IEEE 1914.3 common header, which contains fields used to indicate the message type. The second layer is the application layer, which contains fields necessary for control and synchronization. Within the application layer, sections define the characteristics of U-plane data transmitted or received on a beam with a single pattern ID. The following section types are supported within the C-plane:

[0099] Section Type can indicate the purpose of control messages transmitted on the control plane. For example, the purposes of each Section Type are as follows.

[0100] 1) sectionType=0: Used to indicate resource blocks or symbols not used in DL or UL.

[0101] 2) sectionType=1: Used for most DL / UL wireless channels. Here, "most" refers to channels that do not require time or frequency offsets, such as those required for mixed numerology channels.

[0102] 3) sectionType=2: reserved for further use

[0103] 4) sectionType=3: PRACH and mixed-numerology channels. Channels that require a time or frequency offset or differ from the nominal SCS value(s).

[0104] 5) sectionType=4: reserved for further use

[0105] 6) sectionType=5: UE scheduling information. Transmits UE scheduling information so that the RU can perform real-time BF weight calculations (O-RAN optional BF method).

[0106] 7) sectionType=6: Transmits UE-specific channel information. Periodically transmits UE channel information to enable the RU to perform real-time BF weight calculations (O-RAN optional BF method).

[0107] 8) sectionType=7: Used for LAA support

[0108] In the following specification, an electronic device (e.g., a base station of FIG. 1 or an RU (220) of FIGS. 2A to 3B) may include at least one processing circuit for orthogonal frequency division multiplexing (OFDM) modulation that changes a domain of a symbol sequence from a first domain to a second domain. The at least one processing circuit may include a memory (or buffer) for OFDM modulation. For example, the at least one processing circuit may be referred to as an OFDM modulation circuit. In the following, technical features for minimizing (or optimizing) the memory and delay time of the OFDM modulation circuit will be described.

[0109] Figure 5 illustrates an example of the operation of an OFDM (orthogonal frequency division multiplexing) modulation circuit.

[0110] Figure 6 illustrates an example of a cyclic shift operation.

[0111] Figure 7 illustrates an example of a cyclic extension operation.

[0112] A system (e.g., a base station or user equipment (UE)) of the NR (new radio) standard or LTE (long term evolution) standard may include an OFDM modulation circuit.

[0113] For example, an OFDM modulation circuit can change the domain of a signal (or symbol sequence) from the frequency domain to the time domain based on performing an FFT operation. As an example, a base station can change the domain of a downlink signal from the frequency domain to the time domain through an OFDM modulation circuit. The base station can transmit the downlink signal in the time domain to the UE. As an example, a UE can change the domain of an uplink signal from the frequency domain to the time domain through an OFDM modulation circuit. The UE can transmit the uplink signal in the time domain to the base station.

[0114] For example, an OFDM modulation circuit can change the domain of a signal (or a symbol sequence, a symbol) from the time domain to the frequency domain based on performing an IFFT operation. As an example, a base station can change the domain of an uplink signal from the time domain to the frequency domain through an OFDM modulation circuit. The base station can identify data of an uplink signal based on changing the domain of an uplink signal received from a UE from the time domain to the frequency domain. As an example, a UE can change the domain of a downlink signal from the time domain to the frequency domain through an OFDM modulation circuit. The UE can identify data of a downlink signal based on changing the domain of a downlink signal received from a base station from the time domain to the frequency domain.

[0115] Referring to FIG. 5, the OFDM modulation circuit (500) may include a first buffer (510), an inverse fast Fourier transform (IFFT) operation circuit (520), and / or a second buffer (520).

[0116] The first buffer (510) may be used for a cyclic shift operation. For example, the OFDM modulation circuit (500) may perform a cyclic shift operation on a signal (or symbol sequence, symbol). The cyclic shift operation may be referred to as a pre-IFFT operation or an IFFT shift operation.

[0117] Referring to FIG. 6, for a circular shift operation, a signal (or symbol sequence, symbol) can be divided into a signal (601) of a first band (e.g., high band) and a signal (602) of a second band (e.g., low band). For example, the number of tones for the signal can be n. The number of tones for the signal (601) can be n / 2. The number of tones for the signal (602) can be n / 2.

[0118] The OFDM modulation circuit (500) can change the order of the signal (601) and the signal (602). The OFDM modulation circuit (500) can configure the signal (601) as a front end of an input for an IFFT operation. The OFDM modulation circuit (500) can configure the signal (602) as a rear end of an input for an IFFT operation. The OFDM modulation circuit (500) can configure a guard band between the signal (601) and the signal (602). In order to configure the guard band, the OFDM modulation circuit (500) can set the input values ​​for the IFFT operation corresponding to the guard band to 0. Based on the above-described process, the OFDM modulation circuit (500) can perform a circular shift operation. N_FFT in FIG. 6 can represent the FFT size.

[0119] The OFDM modulation circuit (500) may utilize a first buffer (510) to perform a circular shift operation. The size of the first buffer (510) may be configured to be twice the maximum number of tones (or FFT size) of the signal. For example, a dual buffer having a depth twice the maximum number of tones (or FFT size) of the signal may be used for the first buffer (510).

[0120] Referring to FIG. 5, the IFFT operation circuit (520) may be configured with a DIF (decimation in frequency) FFT structure of the Cooley-Tukey FFT algorithm for pipelined FFT. When the IFFT operation circuit (520) is configured with a DIF IFFT structure (or DIF FFT structure), a signal (or symbol sequence, symbol) in a bit-reversed order may be output based on a signal (or symbol sequence, symbol) in a natural bit order (or natural order) being input to the IFFT operation circuit (520).

[0121] As described above, when the IFFT operation circuit (520) is configured with a DIF IFFT structure, a signal (or symbol sequence, symbol) in a bit-reversed order is output, so the OFDM modulation circuit (500) can perform a reordering operation (or function) to change the signal (or symbol sequence, symbol) back to the natural bit order. The reordering operation (or function) can be set as in the following mathematical expression 1.

[0122]

[0123] Referring to mathematical expression 1, x is the natural order index. y is the bit-reversed order index. N FFT is the size of the FFT.

[0124] The second buffer (530) may be used for a cyclic extension operation. For example, the OFDM modulation circuit (500) may perform a cyclic extension operation on the output signal of the IFFT operation circuit (520). For example, the OFDM modulation circuit (500) may perform the cyclic extension operation based on inserting a cyclic prefix (CP) into the signal. The cyclic extension operation may be referred to as a CP insertion operation.

[0125] Referring to FIG. 7, a CP insertion operation can be performed by inserting a signal (701) (or data) of the last designated time interval of an OFDM symbol (700) in the time domain into the front of the OFDM symbol (700). In a signal on which a CP insertion operation has been performed, a signal (701) can be configured in front of the OFDM symbol (700). The signal (701) can be referred to as a CP (cyclic prefix).

[0126] Referring to Fig. 5, the reordering operation (or function) and the CP insertion operation (or function) can only be performed when all sample data are stored. Since data is continuously output in a pipelined FFT structure, the size of the second buffer (530) can be configured to be twice the FFT size. For example, a dual buffer having a depth twice the FFT size can be used for the second buffer (530).

[0127] In one embodiment, multiple antennas may be used in a wireless communication system for the purposes of spatial multiplexing, interference reduction between signals, diversity, and / or reliability enhancement. As the number of antennas increases, the FFT point size may increase due to real-time multi-antenna signal processing and bandwidth expansion. As the FFT point size increases, the hardware resource usage (e.g., memory usage) within the OFDM modulation circuit (or OFDM modulation demodulation circuit) may increase.

[0128] The increase in hardware resource usage, as described above, can lead to increased system latency and decreased response speed. Increased power consumption can also lead to increased capital expenditures and operating expenditures. Furthermore, increased heat generation can lead to increased product size for heat dissipation. Therefore, technical features may be required to prevent this in OFDM modulation circuits (or OFDM demodulation circuits). Below, technical features for reducing hardware resource usage in OFDM modulation circuits (or OFDM demodulation circuits) will be described.

[0129] Below, technical features for optimizing memory in an OFDM modulation circuit of a DIF (decimation in frequency) FFT structure and an OFDM modulation circuit of a DIT (decimation in time) FFT structure can be described.

[0130] First, the DFT (discrete Fourier transform) operation for the FFT operation can be configured as in mathematical expression 2.

[0131]

[0132]

[0133] For example, the twiddle factor can be constructed as in mathematical formula 3.

[0134]

[0135] Based on the above-described DFT operation, an FFT operation can be constructed. For the FFT operation, N=2 p For a complex input x(n), a signal flow graph of p stages (or steps) is constructed, and N / 2 butterfly structure operations can be performed for each stage.

[0136] For convenience of explanation, a 16-point FFT operation will be described below. However, this is for convenience of explanation, and the FFT size may vary depending on the embodiment.

[0137] If the above mathematical expression 2 is decomposed into binary steps, it can be constructed as mathematical expression 4.

[0138]

[0139] Based on the FFT operation configured as in mathematical expression 4, an OFDM modulation circuit of a DIF IFFT structure (or DIF FFT structure) and an OFDM modulation circuit of a DIT IFFT structure (or DIT FFT structure) can be configured.

[0140] In FIGS. 8 to 10, an example in which a circular shift operation is performed according to an IFFT operation in an OFDM modulation circuit of a DIF IFFT structure will be described.

[0141] In FIGS. 11 to 14, an example in which a cyclic expansion operation is performed according to an IFFT operation in an OFDM modulation circuit of a DIT IFFT structure will be described.

[0142] Figure 8 illustrates a signal flow graph regarding the FFT operation of the DIF FFT structure.

[0143]

[0144]

[0145] In Equation 5, depending on the expansion for n2, n3, and n4, the FFT operation can be configured as in Equation 6.

[0146]

[0147] A signal flow diagram (800) can be constructed according to mathematical expression 6. The signal flow diagram (800) illustrates an FFT operation, but a signal flow diagram according to an IFFT operation, which is an inverse operation of the FFT operation, can be constructed similarly to the signal flow diagram (800). For convenience of explanation, a signal flow diagram according to an IFFT operation can be described as a signal flow diagram (800).

[0148] For example, referring to the signal flow diagram (800), as an IFFT operation is performed on a symbol sequence (or symbol) constructed based on a natural bit order, a symbol sequence (or symbol) constructed based on a bit inversion order can be output (or acquired). Accordingly, in order to align (or align FFT indices (time domain indices)) the symbol sequence (or symbols) constructed based on the bit inversion order, all data regarding the symbol sequence can be stored in a memory (e.g., the second buffer (520) of FIG. 5) and then output.

[0149] According to one embodiment, the signal flow diagram (800) may be composed of multiple stages. For example, the signal flow diagram (800) may include stages (801), (802), (803), and (804). The OFDM modulation circuit may perform the operation of Equation 6 by sequentially performing operations on stages (801) to (804).

[0150] Figure 9 illustrates a signal flow diagram for an FFT operation using a circular shift operation of a DIF FFT structure.

[0151] Referring to Fig. 9, in order to configure an IFFT operation circuit utilizing a circular shift operation, n1 in the above-described mathematical expression 4 can be replaced with 'n1. For example, n1 can be the MSB of the bit sequence of the FFT index (frequency domain index). For example, 'n1 can be configured as in mathematical expression 7.

[0152]

[0153] Referring to mathematical expression 7, 'n1' is the value obtained by performing a modulo 2 operation on n1+1.

[0154] In mathematical expression 4, as n1 is replaced with 'n1' according to mathematical expression 7, the FFT operation of the DIF FFT structure can be configured as in mathematical expression 8.

[0155]

[0156] As the circular shift is performed by half the size of the FFT, the FFT operation of the DIF FFT structure can be configured as in the above-described mathematical expression 8.

[0157] Comparing mathematical expressions 6 and 8, if the sign of the twiddle factor of the first stage in mathematical expression 6 is changed to a negative number, a mathematical expression identical to mathematical expression 8 can be identified.

[0158] A signal flow diagram (900) can be constructed according to mathematical expression 8. The signal flow diagram (900) illustrates an FFT operation, but a signal flow diagram according to an IFFT operation, which is an inverse operation of the FFT operation, can be constructed similarly to the signal flow diagram (900). For convenience of explanation, a signal flow diagram according to an IFFT operation can be described as a signal flow diagram (900).

[0159] As the signs of the twiddle factors are changed to negative in the first stage (801) in the signal flow diagram (800) of Fig. 8, the signal flow diagram (900) can be configured. The complexity of the IFFT operation circuit configured according to mathematical expression 8 can be the same as or similar to the complexity of the IFFT operation circuit configured according to mathematical expression 6.

[0160] According to one embodiment, the signal flow diagram (900) may be composed of a plurality of stages. For example, the signal flow diagram (900) may include stages (901), (902), (903), and (904). The OFDM modulation circuit may perform the operation of Equation 6 by sequentially performing operations on stages (901) to (904). Stage (901) may be configured by changing the signs of the twiddle factors of stage (801) of FIG. 8 to negative numbers.

[0161] According to mathematical expression 8 (or signal flow diagram (900)), a circular shift operation can be performed by half the size of the FFT depending on a change in structure (or a change in operation).

[0162] Fig. 10 illustrates an OFDM modulation circuit for performing an IFFT operation using a circular shift operation.

[0163] Referring to FIG. 10, the OFDM modulation circuit (1000) may include an IFFT operation circuit (1010) and a second buffer (1020). For example, the IFFT operation circuit (1010) may be configured based on the signal flow diagram (900) of FIG. 9 (or the mathematical expression 8 described above). The second buffer (1020) may correspond to the second buffer (530) of FIG. 5.

[0164] Since an output in which a circular shift operation is performed by half the FFT size can be obtained through the IFFT operation circuit (1010), a separate buffer for the circular shift operation (e.g., the first buffer (510) of FIG. 5) may not be used. Accordingly, compared to the OFDM modulation circuit (500) of FIG. 5, an additional buffer for the circular shift operation is not required in the OFDM modulation circuit (1000), so that the hardware resource usage can be reduced. In addition, when the OFDM modulation circuit (1000) is configured, the processing speed of a signal (or symbol sequence, symbol) can be increased.

[0165] In the above-described embodiments (e.g., the embodiments of FIGS. 8 to 10), an example in which the size of the FFT is set to 16 has been described, but this is for convenience of explanation, and the size of the FFT may be set in various ways. In addition, although the above-described embodiments have been described based on the Radix 2 algorithm, this is for convenience of explanation. The technical features according to the above-described embodiments can be applied to various algorithms, including the Radix 4 algorithm and the Radix 2^2 algorithm.

[0166] Figure 11 illustrates a signal flow graph regarding the FFT operation of the DIT FFT structure.

[0167] Referring to Fig. 11, the above-described mathematical expression 4 can be expanded as the above-described mathematical expression 5. In the mathematical expression 5, depending on the expansion for n2, n3, and n4, the FFT operation can be configured as in the mathematical expression 9.

[0168]

[0169] A signal flow diagram (1100) can be constructed according to mathematical expression 9. The signal flow diagram (1100) illustrates an FFT operation, but a signal flow diagram according to an IFFT operation, which is an inverse operation of the FFT operation, can be constructed similarly to the signal flow diagram (1100). For convenience of explanation, a signal flow diagram according to an IFFT operation can be described as a signal flow diagram (1100).

[0170] Referring to the signal flow diagram (1100), as an IFFT operation is performed on a symbol sequence (or symbol) constructed based on a bit-reversal order, a symbol sequence (or symbol) constructed based on a natural bit order may be output (or acquired). As the IFFT operation is performed, since the symbol sequence (or symbol) is constructed based on the natural bit order, memory for aligning the symbol sequence (or symbol) (or aligning the FFT index (time domain index)) may not be required. However, memory for performing a cyclic expansion operation may be required.

[0171] According to one embodiment, the signal flow diagram (1100) may be composed of multiple stages. For example, the signal flow diagram (1100) may include stages (1101), (1102), (1103), and (1104). The OFDM modulation circuit may perform the operation of Equation 9 by sequentially performing operations on stages (1101) to (1104).

[0172] Figure 12 illustrates a signal flow diagram for an FFT operation for a cyclic expansion operation of a DIT IFFT structure.

[0173] Referring to Fig. 12, in order to configure an IFFT operation circuit for a cyclic expansion operation, in the above-described mathematical expression 9, k3 can be replaced with 'k3, and k4 can be replaced with 'k4. For example, 'k3 can be configured as in mathematical expression 10. 'k4 can be configured as in mathematical expression 11.

[0174]

[0175]

[0176] In the above mathematical expression 9, a signal flow diagram (1200) can be constructed according to the mathematical expression in which k3 is replaced with 'k3' and k4 is replaced with 'k4'.

[0177] Referring to FIG. 11, in mathematical expression 9, the operations of the stage (1103) and the stage (1104) according to n4, k1, k2, k3, and k4 can be configured as shown in the table below.

[0178]

[0179] Referring to Table 1, the rows regarding the third addition represent the addition (or subtraction) process of stage (1103). The rows regarding the fourth addition represent the addition (or subtraction) process of stage (1104).

[0180] Therefore, when k3 in mathematical expression 9 is replaced with 'k3' and k4 is replaced with 'k4', the operation process of stage (1103) and the operation process of stage (1104) may be changed.

[0181] For example, the addition or subtraction operations of stages (1103) and (1104) may be changed, and the twiddle factors of stage (1104) may be changed. Based on the change in the addition or subtraction operations of stages (1103) and (1104) and the change in the twiddle factors of stage (1104), stages (1203) and (1204) of the signal flow diagram (1200) may be configured.

[0182] The signal flow diagram (1200) illustrates an FFT operation, but a signal flow diagram according to an IFFT operation, which is the inverse operation of the FFT operation, can be configured similarly to the signal flow diagram (1200). For convenience of explanation, the signal flow diagram according to the IFFT operation can be described as the signal flow diagram (1200).

[0183] Referring to the signal flow diagram (1200), when the FFT indices are divided into four groups, the samples (or data) of the last group may be output first. Since the CP does not exceed 0.25 times the FFT size for all subcarrier spacings (e.g., 15 kHz to 240 kHz), the output of the IFFT operation may be configured to facilitate the CP insertion operation (or cyclic expansion operation).

[0184] Figure 13 illustrates an OFDM modulation circuit for performing an IFFT operation for a cyclic expansion operation.

[0185] Referring to FIG. 13, the OFDM modulation circuit (1300) may include a first buffer (1310), an IFFT operation circuit (1320), and a second buffer (1330). For example, the first buffer (1310) may correspond to the first buffer (510) of FIG. 5. The IFFT operation circuit (1320) may be configured based on the signal flow diagram (1200) of FIG. 12. The second buffer (1330) may be configured for a cyclic expansion operation (e.g., a CP insertion operation).

[0186] Based on the signal flow diagram (1200) of FIG. 12, when an IFFT operation circuit (1320) is configured, as an IFFT operation on a symbol sequence (or symbol) configured based on a bit inversion order is performed in the IFFT operation circuit (1320), a symbol sequence (or symbol) configured based on a natural bit order can be output (or obtained) by being circularly shifted by 1 / 4 of the FFT size.

[0187] For example, the first buffer (1310) may be used to perform a circular shift operation (or function) and a reordering operation (or function). The reordering operation (or function) may be used to construct a symbol sequence (or symbol) constructed based on a bit-reversal order. The first buffer (1310) may be configured to output a symbol sequence on which both the circular shift operation (or function) and the reordering operation (or function) have been performed.

[0188] Since the symbol sequence (or symbol) is stored in the memory (e.g., the first buffer (1310)) before being input to the IFFT operation circuit (1320), the OFDM modulation circuit (1300) can output (e.g., read) the symbol sequence (or symbol) stored in the memory (e.g., the first buffer (1320)) based on the bit inversion order to perform the reordering operation (or function). For example, the OFDM modulation circuit (1300) can set a read address for outputting the symbol sequence (or symbol) based on the bit inversion order. The symbol sequence (or symbol) configured according to the bit inversion order can be input to the IFFT operation circuit (1320).

[0189] Since CP does not exceed 1 / 4 of the FFT size, if the output circularly shifted by 1 / 4 of the FFT size is first output through the IFFT operation circuit (1320), the size of the memory (e.g., the second buffer (1330)) for the circular expansion operation can be reduced. The size of the second buffer (530) in FIG. 5 is set to twice the FFT size, but the size of the second buffer (1330) can be set to 1 / 4 of the FFT size. Accordingly, the size of the second buffer (1330) can be set to 1 / 8 of the size of the second buffer (530).

[0190] A portion (or data) of a symbol sequence (or symbol) may be stored in a second buffer (1330) according to the output of the IFFT operation circuit (1320). An example in which a portion (or data) of a symbol sequence (or symbol) is stored in a second buffer (1330) according to the output of the IFFT operation circuit (1320) and is configured as an output of an OFDM modulation circuit (1300) will be described through FIG. 14.

[0191] Figure 14 shows an example of input and output for the second buffer.

[0192] Referring to FIG. 14, in the IFFT operation circuit (1320), an IFFT operation for a cyclic expansion operation can be performed based on the signal flow diagram (1200) of FIG. 12. The output of the IFFT operation circuit (1320) can be set as a signal (1401) (or symbol). The signal (1401) can be configured based on the time domain. The signal (1401) can include a signal (1410), a signal (1420), a signal (1430), and a signal (1440).

[0193] The output of the IFFT operation circuit (1320) may be composed in the order of signal (1440), signal (1410), signal (1420), and signal (1430). Based on the signal (1440) being output from the IFFT operation circuit (1320), the second buffer (1330) may store the signal (1440).

[0194] A CP (1441) may be configured according to a cyclic expansion operation (e.g., a CP insertion operation). For example, the CP (1441) may be configured as a part of the signal (1440). Based on a specified time interval, a part of the signal (1440) may be configured as the CP (1441). According to the pipelined FFT structure, the CP (1441), the signal (1410), the signal (1420), and the signal (1430) may be sequentially output in the OFDM modulation circuit (1300). The OFDM modulation circuit (1300) may output the signal (1410), the signal (1420), and the signal (1430), which are outputs of the IFFT operation circuit (1320), as they are, thereby not using the second buffer (1330).

[0195] The OFDM modulation circuit (1300) can output a signal (1440) stored in the second buffer (1330) after outputting the signal (1430). As described above, the OFDM modulation circuit (1300) can output a signal (1402), which is a transmission signal, based on sequentially outputting the CP (1441), the signal (1410), the signal (1420), the signal (1430), and the signal (1440).

[0196] As described above, when only 1 / 4 of the signal (1401) is stored in the second buffer (1330), the signal (1402) can be output through the OFDM modulation circuit (1300). Therefore, the size of the second buffer (1330) can be set to 1 / 8 of the size of the second buffer (530). The size of the second buffer (1330) can be set to 1 / 4 of the FFT size.

[0197] In the above-described embodiments (e.g., the embodiments of FIGS. 11 to 14), an example in which the size of the FFT is set to 16 has been described, but this is for convenience of explanation, and the size of the FFT may be set in various ways. In addition, although the above-described embodiments have been described based on the Radix 2 algorithm, this is for convenience of explanation. The technical features according to the above-described embodiments can be applied to various algorithms, including the Radix 4 algorithm and the Radix 2^2 algorithm.

[0198] Fig. 15 illustrates a flowchart regarding the operation of an electronic device according to a DIF FFT (decimation in frequency fast Fourier transform) structure.

[0199] In operations 1510 to 1530, the electronic device may include at least one processing circuit for OFDM modulation that changes the domain of a symbol sequence from a first domain to a second domain. For example, an example of the electronic device according to operations 1510 to 1530 may be the OFDM modulation circuit (1000) of FIG. 10.

[0200] In operation 1510, at least one processing circuit may obtain a first symbol sequence for a first domain. For example, the at least one processing circuit may obtain a pre-coded signal. The at least one processing circuit may obtain the first symbol sequence for the first domain based on the pre-coded signal. For example, the pre-coded signal may be obtained from another electronic device performing the function of the DU. For example, the first domain may include a frequency domain. The first symbol sequence may be configured based on the frequency domain.

[0201] For example, the first symbol sequence may be constructed based on the natural bit order. That the first symbol sequence is constructed based on the natural bit order may mean that the FFT index (or frequency domain index) is constructed sequentially. As an example, that the first symbol sequence is constructed based on the natural bit order may mean that the FFT index (or frequency domain index) is constructed similarly to the input of the signal flow diagram (900) of FIG. 9.

[0202] In operation 1520, at least one processing circuit can obtain a second symbol sequence for a second domain by performing an IFFT operation using a circular shift operation on the first symbol sequence.

[0203] According to one embodiment, at least one processing circuit can perform an IFFT operation using a circular shift operation on the first symbol sequence. For example, the IFFT operation using a circular shift operation can be configured as in the mathematical expression 8 described above.

[0204] According to one embodiment, an IFFT operation using a circular shift operation may include an operation of changing, for each FFT index among FFT indices (or frequency domain indices) for a first domain according to an FFT size, an MSB (most significant bit) value of a bit sequence of the corresponding FFT index from 0 to 1 or from 1 to 0.

[0205] For example, an IFFT operation using a circular shift operation can be performed based on a plurality of twiddle factors. The sign of at least one of the plurality of twiddle factors can be changed based on an operation that changes the MSB value of the bit string of the corresponding FFT index from 0 to 1 or from 1 to 0.

[0206] An IFFT operation using a circular shift operation may be composed of a plurality of stages (or multiple stages) based on a plurality of twiddle factors. The multiple stages may include stages (901) to (904) of the signal flow diagrams of FIG. 9. At least one twiddle factor whose sign changes may be associated with a first stage (e.g., stage (901)) among the multiple stages. For example, as the sign of at least one twiddle factor changes, the first stage among the multiple stages may change similarly to the change from stage (801) of FIG. 8 to stage (901) of FIG. 9.

[0207] For example, at least one processing circuit can perform an IFFT operation using a circular shift operation on a first symbol sequence without a first buffer for the circular shift operation. Since the first symbol sequence is configured based on a natural bit order, the first symbol sequence can be sequentially input to a circuit configured for the IFFT operation (e.g., the IFFT operation circuit (1010) of FIG. 10). For example, FFT indices for the first domain can be sequentially configured. Accordingly, at least one processing circuit may not use a first buffer for the circular shift operation. A storage area for the first buffer may not be configured within the electronic device (200) (or the at least one processing circuit).

[0208] According to one embodiment, at least one processing circuit can obtain a second symbol sequence for a second domain. For example, the at least one processing circuit can obtain the second symbol sequence for the second domain based on the result of an IFFT operation using a circular shift operation. For example, the second domain can include the time domain. The second symbol sequence can be constructed based on the time domain.

[0209] For example, the second symbol sequence may be constructed based on a bit-reversed order. That the second symbol sequence is constructed based on a bit-reversed order may mean that the FFT index (or time domain index) is constructed similarly to the output of the signal flow diagram (900) of FIG. 9.

[0210] In operation 1530, at least one processing circuit can generate a transmission signal by performing a cyclic expansion operation based on the second symbol sequence.

[0211] For example, at least one processing circuit can obtain a transmission signal constructed based on a natural bit order, based on a second symbol sequence constructed based on a bit-reversal order, using a second buffer for a cyclic expansion operation.

[0212] In one embodiment, the size of the second buffer may be set based on the FFT size. For example, the size of the second buffer may be set to twice the FFT size.

[0213] As described above, at least one processing circuit can obtain a transmission signal configured based on a natural bit order based on performing a reordering operation.

[0214] Fig. 16 illustrates a flowchart regarding the operation of an electronic device according to a DIT FFT (decimation in time fast Fourier transform) structure.

[0215] In operations 1610 to 1640, the electronic device may include at least one processing circuit for OFDM modulation that changes the domain of a symbol sequence from a first domain to a second domain. For example, an example of the electronic device according to operations 1610 to 1640 may be the OFDM modulation circuit (1300) of FIG. 13.

[0216] Referring to FIG. 16, in operation 1610, at least one processing circuit may obtain a first symbol sequence for a first domain. For example, the at least one processing circuit may obtain a pre-coded signal. Based on the pre-coded signal, the at least one processing circuit may obtain the first symbol sequence for the first domain. For example, the pre-coded signal may be obtained from another electronic device performing the function of the DU. For example, the first domain may include a frequency domain. The first symbol sequence may be configured based on the frequency domain.

[0217] In operation 1620, at least one processing circuit can obtain a second symbol sequence by performing a cyclic shift operation on the first symbol sequence. For example, the at least one processing circuit can obtain the second symbol sequence by performing the cyclic shift operation on the first symbol sequence using a first buffer for the cyclic shift operation (e.g., the first buffer (1310) of FIG. 13). For example, the at least one processing circuit can divide the second symbol sequence into a symbol sequence of a first band and a symbol sequence of a second band. The at least one processing circuit can change the positions of the symbol sequence of the first band and the symbol sequence of the second band. The at least one processing circuit can configure a guard band between the symbol sequence of the first band and the symbol sequence of the second band. The at least one processing circuit can perform the cyclic shift operation based on the above-described operation.

[0218] In operation 1630, at least one processing circuit can obtain a third symbol sequence by performing an IFFT operation for a cyclic expansion operation based on the second symbol sequence.

[0219] For example, a first symbol sequence may be constructed based on a natural bit order. A second symbol sequence may be constructed based on a reversed bit order. A third symbol sequence may be constructed based on a natural bit order. That the second symbol sequence is constructed based on a bit-reversed order may mean that an FFT index (or a frequency domain index) is constructed similarly to an input of the signal flow diagram (1200) of FIG. 12. For example, at least one processing circuit may obtain a second symbol sequence constructed based on a reversed bit order using a first buffer, based on the first symbol sequence constructed based on a natural bit order. According to an embodiment, at least one processing circuit may obtain the second symbol sequence from the first symbol sequence based on performing a reordering operation.

[0220] According to one embodiment, at least one processing circuit can obtain a third symbol sequence by performing an IFFT operation for a cyclic expansion operation on the second symbol sequence. The third symbol sequence can be constructed based on a natural bit order.

[0221] For example, an IFFT operation for a cyclic expansion operation may include an operation of changing, for each FFT index among FFT indices (or time domain indices) for the second domain according to the FFT size, the value of at least one bit of the bit sequence of the corresponding FFT index from 0 to 1 or from 1 to 0.

[0222] According to one embodiment, the number of at least one bit of the bit string of the corresponding FFT index may be set based on the FFT size. For example, when the FFT size is 16, the number of at least one bit of the bit string of the corresponding FFT index may be set to 0.25 times the FFT size.

[0223] For example, an IFFT operation for a circular expansion operation may be performed based on a plurality of twiddle factors. At least one of the plurality of twiddle factors may be changed based on an operation that changes each of at least one bit value of the bit string of the corresponding FFT index from 0 to 1 or from 1 to 0.

[0224] An IFFT operation for a cyclic expansion operation may be composed of a plurality of stages (or multiple stages) based on a plurality of twiddle factors. For example, the multiple stages may include stages (1201) to (1204) of the signal flow diagrams of FIG. 12. At least one twiddle factor that changes in response to a change in at least one bit value of a bit string of an FFT index may be associated with a fourth stage (e.g., stage (1204)) among the multiple stages.

[0225] The computational processes of some of the multiple stages may change depending on a change in at least one bit value of the bit string of the FFT index. For example, the computational processes (e.g., addition, subtraction) of the third stage (e.g., stage (1203)) and the fourth stage (e.g., stage (1204)) of the multiple stages may change.

[0226] In operation 1640, at least one processing circuit can generate a transmission signal by performing a cyclic expansion operation on a third symbol sequence.

[0227] According to one embodiment, at least one processing circuit can perform a cyclic expansion operation on a third symbol sequence using a second buffer for the cyclic expansion operation. At least one processing circuit can generate a transmission signal based on performing the cyclic expansion operation on the third symbol sequence using the second buffer.

[0228] For example, at least one processing circuit can store a portion corresponding to 1 / 4 of the third symbol sequence according to the output of the IFFT operation in the second buffer. At least one processing circuit can configure the output of the IFFT operation from the point in time when the CP section starts among the portion corresponding to 1 / 4 of the third symbol sequence as the output of at least one processing circuit (e.g., OFDM modulation circuit). After the output of the IFFT operation is completed, the at least one processing circuit can output a portion corresponding to 1 / 4 of the symbol sequence stored in the second buffer.

[0229] In one embodiment, the size of the second buffer may be set based on the FFT size. For example, the size of the second buffer may be set to 0.25 times the FFT size.

[0230] According to the above-described operation, at least one processing circuit can perform a cyclic expansion operation (CP insertion operation).

[0231] Figure 17 shows an example of the configuration of a processing device.

[0232] Referring to FIG. 17, the processing device (1700) may be composed of one or more chips. For example, the processing device (1700) may be composed of a field programmable gate array (FPGA). For example, the processing device (1700) may be composed based on an application specific integrated circuit (ASIC). For example, an example of the processing device (1700) may be the electronic device (or OFDM modulation circuit) described above. For example, the processing device (1700) may perform at least some or all of the functions of the RU. However, the present invention is not limited thereto. The processing device (1700) may also perform at least some or all of the functions of the DU.

[0233] For example, the processing unit (1700) may be controlled by a processor (or at least a portion of a processor). As an example, the processing unit (1700) may be controlled by the processor (380) of FIG. 3B. For example, the processing unit (1700) may also be configured as at least a portion of a processor.

[0234] According to one embodiment, the processing device (1700) may include a processing circuit (1710) and a memory (1720).

[0235] For example, an example of a processing circuit (1710) may be at least one of the processing circuits of FIGS. 15 and 16. The processing circuit (1710) may include at least one component for OFDM modulation. The processing circuit (1710) may perform an IFFT operation of a DIT FFT structure and / or a DIF FFT structure, depending on the configuration of the at least one component.

[0236] The memory (1720) may include a plurality of storage spaces. The memory (1720) may be divided into a plurality of storage spaces. For example, the memory (1720) may include a first storage space (1721), a second storage space (1722), and / or a third storage space (1723). For example, the first storage space (1721) may be allocated for the first buffer described above (e.g., the first buffer (510) of FIG. 5, the first buffer (1310) of FIG. 13). The second storage space (1722) may be allocated for the second buffer described above (e.g., the second buffer (530) of FIG. 5, the second buffer (1020) of FIG. 10, the second buffer (1330) of FIG. 13). Depending on the embodiment, the memory (1720) may be configured as one memory (or one storage circuit). For example, a storage space may be divided within a single memory, and a plurality of storage spaces (e.g., a first storage space (1721), a second storage space (1722), and a third storage space (1723)) may be configured. According to an embodiment, the memory (1720) may be configured with a plurality of memories (or a plurality of storage circuits). A first number of memories among the plurality of memories may be used for the first storage space (1721). A second number of memories among the plurality of memories may be used for the second storage space (1722). A third number of memories among the plurality of memories may be used for the third storage space (1723).

[0237] Here, the term '~ unit' (or processor, at least a part of the processor) used in the present embodiment means software or hardware components such as FPGA or ASIC, and the '~ unit' performs certain roles. However, the '~ unit' is not limited to software or hardware. The '~ unit' may be configured to be on an addressable storage medium and may be configured to play one or more processors. Accordingly, as an example, the '~ unit' includes components such as software components, object-oriented software components, class components, and task components, processes, functions, properties, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided within the components and '~ units' may be combined into a smaller number of components and '~ units' or further separated into additional components and '~ units'. Additionally, components and '~parts' may be implemented to regenerate one or more CPUs within a device or secure multimedia card.

[0238] According to one embodiment, an electronic device may include a memory and at least one processing circuit for orthogonal frequency division multiplexing (OFDM) modulation that changes a domain of a symbol sequence from a first domain to a second domain. The at least one processing circuit may be configured to obtain a first symbol sequence for the first domain. The at least one processing circuit may be configured to obtain a second symbol sequence for the second domain by performing an inverse fast Fourier transform (IFFT) operation using a cyclic shift operation on the first symbol sequence. The at least one processing circuit may be configured to generate a transmission signal by performing a cyclic extension operation based on the second symbol sequence. The IFFT operation using the above circular shift operation may include an operation of changing the value of the most significant bit (MSB) of the bit sequence of each FFT index from 0 to 1 or from 1 to 0 among the FFT indices for the first domain according to the FFT (fast Fourier transform) size.

[0239] For example, the IFFT operation using the circular shift operation may be performed based on a plurality of twiddle factors. The sign of at least one twiddle factor among the plurality of twiddle factors may be changed based on an operation that changes the value of the MSB of the bit string of the corresponding FFT index from 0 to 1 or from 1 to 0.

[0240] For example, the IFFT operation utilizing the circular shift operation may be composed of a plurality of steps based on the plurality of twiddle factors. The at least one twiddle factor may be associated with a first step among the plurality of steps.

[0241] For example, the first symbol sequence may be constructed based on a natural bit order. The second symbol sequence may be constructed based on a bit-reversed order.

[0242] For example, the at least one processing circuit may be configured to perform the IFFT operation using the circular shift operation on the first symbol sequence without a first buffer for the circular shift operation.

[0243] For example, the at least one processing circuit may be configured to obtain the transmission signal constructed based on the natural bit order, based on the second symbol sequence constructed based on the bit inversion order.

[0244] For example, the size of the second buffer may be set to twice the size of the FFT.

[0245] According to one embodiment, a method of an electronic device may include an operation of obtaining a first symbol sequence for a first domain. The method may include an operation of obtaining a second symbol sequence for a second domain by performing an inverse fast Fourier transform (IFFT) operation using a cyclic shift operation on the first symbol sequence. The method may include an operation of generating a transmission signal by performing a cyclic extension operation based on the second symbol sequence. The IFFT operation using the cyclic shift operation may include an operation of changing a value of a most significant bit (MSB) of a bit sequence of each FFT index among FFT indexes for the first domain according to an FFT size from 0 to 1 or from 1 to 0.

[0246] For example, the IFFT operation using the circular shift operation may be performed based on a plurality of twiddle factors. The sign of at least one twiddle factor among the plurality of twiddle factors may be changed based on an operation that changes the value of the MSB of the bit string of the corresponding FFT index from 0 to 1 or from 1 to 0.

[0247] For example, the IFFT operation utilizing the circular shift operation may be composed of a plurality of steps based on the plurality of twiddle factors. The at least one twiddle factor may be associated with a first step among the plurality of steps.

[0248] For example, the first symbol sequence may be constructed based on a natural bit order. The second symbol sequence may be constructed based on a bit-reversed order.

[0249] For example, the method may include performing the IFFT operation using the circular shift operation on the first symbol sequence without a first buffer for the circular shift operation.

[0250] For example, the method may include an operation of obtaining the transmission signal constructed based on the natural bit order, based on the second symbol sequence constructed based on the bit inversion order.

[0251] For example, the size of the second buffer may be set to twice the size of the FFT.

[0252] According to one embodiment, an electronic device may include a memory, and at least one processing circuit for orthogonal frequency division multiplexing (OFDM) modulation that changes a domain of a symbol sequence from a first domain to a second domain. The at least one processing circuit may be configured to obtain a first symbol sequence for the first domain. The at least one processing circuit may be configured to obtain a second symbol sequence by performing a cyclic shift operation on the first symbol sequence. The at least one processing circuit may be configured to obtain a third symbol sequence for the second domain by performing an inverse fast Fourier transform (IFFT) operation for a cyclic extension operation based on the second symbol sequence. The at least one processing circuit may be configured to generate a transmission signal by performing the cyclic extension operation on the third symbol sequence. The IFFT operation for the above cyclic expansion operation may include an operation of changing the value of at least one bit of a bit sequence of each FFT index from 0 to 1 or from 1 to 0 among the FFT indices for the second domain according to the FFT (fast Fourier transform) size.

[0253] For example, the number of at least one bit of the bit string of the corresponding FFT index can be set based on the FFT size.

[0254] For example, the IFFT operation for the cyclic expansion operation may be performed based on a plurality of twiddle factors. At least one twiddle factor among the plurality of twiddle factors for the IFFT operation for the cyclic expansion operation may be changed based on an operation that changes each value of the at least one bit of the bit sequence of the corresponding FFT index from 0 to 1 or from 1 to 0.

[0255] For example, the at least one processing circuit may be configured to obtain the second symbol sequence by performing the circular shift operation on the first symbol sequence using the first buffer for the circular shift operation allocated to the memory.

[0256] For example, the at least one processing circuit may be configured to obtain the second symbol sequence constructed based on a bit-reversed order using the first buffer.

[0257] For example, the third symbol sequence can be constructed based on the natural bit order.

[0258] For example, the at least one processing circuit may be configured to generate the transmission signal by performing the cyclic expansion operation on the third symbol sequence using a second buffer for the cyclic expansion operation allocated to the memory.

[0259] For example, the size of the second buffer may be set to 0.25 times the size of the FFT.

[0260] According to one embodiment, an OFDM modulation circuit may include buffers for input and output of a pipelined FFT. For example, a first buffer may be used (or configured) for input of the pipelined FFT. A second buffer may be used (or configured) for output of the pipelined FFT. A memory having a depth twice the FFT size (or FFT point size) may be used for input (or output) of the pipelined FFT. According to the above embodiment, the input buffer may not be used or the size of the output buffer may be reduced without performance degradation through a simple formula change. According to the above embodiment, since the storage procedure is simplified, the latency of more than an OFDM symbol may be reduced. According to the above embodiment, as the hardware resource usage is reduced, heat generation and power consumption may be reduced. Since the OFDM modulation circuit must perform an IFFT operation per antenna, heat generation and power consumption may be significantly reduced in a system with a large bandwidth and many antennas.

[0261] The methods according to the embodiments described in the claims or specification of the present disclosure may be implemented in the form of hardware, software, or a combination of hardware and software.

[0262] When implemented in software, a computer-readable storage medium storing one or more programs (software modules) may be provided. The one or more programs stored in the computer-readable storage medium are configured to be executed by one or more processors within an electronic device. The one or more programs include instructions that cause the electronic device to execute methods according to embodiments described in the claims or specification of the present disclosure. The one or more programs may be provided as a computer program product. The computer program product may be traded between a seller and a buyer as a commodity. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read only memory (CD-ROM)), or may be distributed online (e.g., downloaded or uploaded) via an application store (e.g., Play Store™) or directly between two user devices (e.g., smart phones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily created in a device-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

[0263] These programs (software modules, software) may be stored in random access memory, non-volatile memory including flash memory, read only memory (ROM), electrically erasable programmable read only memory (EEPROM), magnetic disc storage devices, compact disc-ROM (CD-ROM), digital versatile discs (DVDs) or other forms of optical storage devices, magnetic cassettes, or may be stored in memories formed by a combination of some or all of these. In addition, each configuration memory may include multiple copies.

[0264] Additionally, the program may be stored on an attachable storage device that is accessible via a communication network, such as the Internet, an intranet, a local area network (LAN), a wide area network (WAN), a storage area network (SAN), or a combination thereof. Such a storage device may be connected to a device performing an embodiment of the present disclosure via an external port. Additionally, a separate storage device on the communication network may be connected to a device performing an embodiment of the present disclosure.

[0265] In the specific embodiments of the present disclosure described above, components included in the disclosure are expressed in the singular or plural form, depending on the specific embodiment presented. However, the singular or plural expressions are selected to suit the presented situation for convenience of explanation, and the present disclosure is not limited to singular or plural components. Components expressed in the plural form may be composed of singular elements, or components expressed in the singular form may be composed of plural elements.

[0266] According to embodiments, one or more of the components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (e.g., modules or programs) may be integrated into a single component. In such a case, the integrated component may perform one or more functions of each of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. According to embodiments, the operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

[0267] Meanwhile, although the detailed description of the present disclosure has described specific embodiments, it is obvious that various modifications are possible within the scope of the present disclosure.

Claims

1. In electronic devices, memory; and At least one processing circuit for orthogonal frequency division multiplexing (OFDM) modulation that changes the domain of a symbol sequence from a first domain to a second domain, At least one processing circuit of the above, Obtaining a first symbol sequence for the first domain, By performing an inverse fast Fourier transform (IFFT) operation using a cyclic shift operation on the first symbol sequence, a second symbol sequence for the second domain is obtained, It is set to generate a transmission signal by performing a cyclic extension operation based on the second symbol sequence, The IFFT operation using the above circular shift operation is, for each FFT index among the FFT indices for the first domain according to the FFT (fast Fourier transform) size: An operation that includes changing the value of the most significant bit (MSB) of the bit sequence of the corresponding FFT index from 0 to 1 or from 1 to 0. Electronic devices.

2. In the first paragraph, the IFFT operation using the circular shift operation is performed based on a plurality of twiddle factors, The sign of at least one twiddle factor among the above plurality of twiddle factors is, Based on an operation of changing the value of the MSB of the bit string of the corresponding FFT index from 0 to 1 or from 1 to 0, Electronic devices.

3. In the second paragraph, the IFFT operation using the circular shift operation is It consists of multiple steps based on the above multiple twiddle factors, wherein said at least one twiddle factor is associated with a first step of said plurality of steps, Electronic devices.

4. In the first paragraph, the first symbol sequence is, It is structured based on the natural bit order, The above second symbol sequence is, It is constructed based on bit-reversed order, Electronic devices.

5. In the fourth paragraph, at least one processing circuit, Further configured to perform the IFFT operation using the circular shift operation on the first symbol sequence without a first buffer for the circular shift operation. Electronic devices.

6. In the fifth paragraph, at least one processing circuit, Further set to obtain the transmission signal based on the natural bit order, based on the second symbol sequence configured based on the bit inversion order. Electronic devices.

7. In the 6th paragraph, the size of the second buffer is Set to twice the above FFT size, Electronic devices.

8. In the method of an electronic device, An operation of obtaining a first symbol sequence for a first domain; An operation of obtaining a second symbol sequence for a second domain by performing an inverse fast Fourier transform (IFFT) operation using a cyclic shift operation on the first symbol sequence; and An operation for generating a transmission signal by performing a cyclic extension operation based on the second symbol sequence, The IFFT operation using the above circular shift operation is, for each FFT index among the FFT indices for the first domain according to the FFT (fast Fourier transform) size: An operation that includes changing the value of the most significant bit (MSB) of the bit sequence of the corresponding FFT index from 0 to 1 or from 1 to 0. method.

9. In the 8th paragraph, the IFFT operation using the circular shift operation is performed based on a plurality of twiddle factors, The sign of at least one twiddle factor among the above plurality of twiddle factors is, Based on an operation of changing the value of the MSB of the bit string of the corresponding FFT index from 0 to 1 or from 1 to 0, method.

10. In the 9th paragraph, the IFFT operation using the circular shift operation, It consists of multiple steps based on the above multiple twiddle factors, The at least one twiddle factor is associated with a first step of the plurality of steps. method.

11. In the 8th paragraph, the first symbol sequence is, It is structured based on the natural bit order, The above second symbol sequence is, It is constructed based on bit-reversed order. method.

12. In paragraph 11, Further comprising an operation of performing the IFFT operation using the circular shift operation on the first symbol sequence without a first buffer for the circular shift operation. method.

13. In paragraph 12, Further comprising an operation of obtaining the transmission signal constructed based on the natural bit order, based on the second symbol sequence constructed based on the bit inversion order. method.

14. In the 13th paragraph, the size of the second buffer is Set to twice the above FFT size, method.

15. In the 8th paragraph, the first domain, Contains the frequency domain, The above second domain is, Including the time domain, method.

Images