Array substrate, display panel, and display device

Abstract

Provided are an array substrate, a display panel, and a display device. The array substrate comprises: a base (1); a plurality of gate lines (2) located on one side of the base (1), the plurality of gate lines (2) extending in a first direction (X); a plurality of data lines (3), the main body directions of the plurality of data lines (3) extending in a second direction (Y), and the orthographic projections of the data lines (3) on the base (1) being bent; and a plurality of pixel electrodes (4), the orthographic projection of each pixel electrode (4) on the base (1) being located between the orthographic projections of adjacent data lines (3) on the base (1), the pixel electrodes (4) comprising a plurality of slits (F), and the extension direction of the orthographic projection of each slit (F) on the base (1) being consistent with the extension directions of the orthographic projections of adjacent data lines (3) on the base (1).

Description

Array substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] The name UV2A comes from the multiplication of ultraviolet (UV) light and the VA method of the liquid crystal panel. This technology can precisely manipulate the alignment of liquid crystal molecules through ultraviolet light, greatly improving the light transmittance.

[0003] The key to UV2A lies in its use of a special polymer material as an alignment film, precisely controlling the tilt of liquid crystal molecules along the direction of ultraviolet light. This accuracy is measured in picometers (one trillionth of a meter). UV2A's advantage lies in its simple LCD panel structure, free of protrusions and slits. This "dream of LCD technicians" was explored as early as 30 years ago. Today, thanks to the availability of new materials, production equipment, and a refined processing process, this dream has become a reality. This simple LCD panel structure not only improves production efficiency but also offers numerous advantages in image quality.

[0004] Summary of the Invention

[0005] The present disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0006] substrate;

[0007] A plurality of gate lines are located on one side of the substrate, and the plurality of gate lines extend along a first direction;

[0008] a plurality of data lines, wherein main directions of the plurality of data lines extend along a second direction, and an orthographic projection of the data lines on the substrate is a bent shape;

[0009] A plurality of pixel electrodes, wherein the orthographic projections of the pixel electrodes on the substrate are located between the orthographic projections of adjacent data lines on the substrate; the pixel electrodes include a plurality of slits, and the extension direction of the orthographic projections of the slits on the substrate is consistent with the extension direction of the orthographic projections of adjacent data lines on the substrate.

[0010] In a possible implementation manner, the orthographic projection of the gate line on the substrate passes through a central area of ​​the orthographic projection of the pixel electrode on the substrate;

[0011] The pixel electrode has a first gap in the area where the gate line is located; the pixel electrode includes: a first pixel electrode located on one side of the gate line, a second pixel electrode located on the other side of the gate line, and a connecting portion connecting at least a portion of the first pixel electrode and at least a portion of the second pixel electrode.

[0012] In a possible implementation, the array substrate further includes: a plurality of transistors; the pixel electrodes are electrically connected to the data lines via the plurality of transistors;

[0013] The first pixel electrode includes: a first sub-pixel electrode and a second sub-pixel electrode distributed along the second direction; the second pixel electrode includes: a third sub-pixel electrode and a fourth sub-pixel electrode distributed along the second direction; wherein the second sub-pixel electrode is located on a side of the first sub-pixel electrode away from the electrically connected data line, and the fourth sub-pixel electrode is located on a side of the third sub-pixel electrode away from the electrically connected data line;

[0014] One of the first sub-pixel electrode and the second sub-pixel electrode is electrically connected to one of the third sub-pixel electrode and the fourth sub-pixel electrode via the connection portion.

[0015] In a possible implementation, the first sub-pixel electrode and the fourth sub-pixel electrode are electrically connected via the connecting portion at the layer where the pixel electrode is located; the second sub-pixel electrode and the third sub-pixel electrode are independent of each other at the layer where the pixel electrode is located.

[0016] In a possible implementation, the array substrate further includes: a first common wiring located on one side of the gate line and extending along the first direction; the plurality of transistors include: a first transistor, a second transistor, and a third transistor;

[0017] The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the connecting portion;

[0018] The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode;

[0019] The control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is electrically connected to the first common wiring.

[0020] In a possible implementation, the second electrode of the first transistor includes: a first transistor first portion extending along the first direction;

[0021] The array substrate further includes a first overlapping portion connected to the connecting portion, wherein an orthographic projection of the first overlapping portion on the substrate overlaps with an orthographic projection of the first portion of the first transistor on the substrate.

[0022] In a possible implementation, the connecting portion includes: a first connecting portion extending along the first direction, a second connecting portion, and a third connecting portion extending along the second direction;

[0023] One end of the first connecting portion is electrically connected to the first sub-pixel electrode, the other end of the first connecting portion is electrically connected to one end of the third connecting portion; the other end of the third connecting portion is electrically connected to one end of the second connecting portion; and the other end of the second connecting portion is electrically connected to the fourth sub-pixel electrode.

[0024] The first overlapping portion is electrically connected to the first connecting portion and is away from a side of the first sub-pixel electrode to which it is connected.

[0025] In a possible implementation manner, a second gap exists between the first connecting portion and the first sub-pixel electrode to which it is connected, and a third gap exists between the second connecting portion and the fourth sub-pixel electrode to which it is electrically connected.

[0026] In a possible implementation manner, a length of the first overlapping portion in the second direction is greater than a length of the first connecting portion in the second direction.

[0027] In a possible implementation manner, the second electrode of the second transistor includes: a second transistor first portion extending along the first direction, and a second transistor second portion extending from the second transistor first portion along the second direction;

[0028] The array substrate further includes: a first transition portion extending along the first direction, a second transition portion extending along the second direction, and a second overlapping portion; one end of the first transition portion is electrically connected to the second sub-pixel electrode, and the other end is electrically connected to one end of the second transition portion; the other end of the second transition portion is electrically connected to the second overlapping portion; an orthographic projection of the second transistor portion on the substrate overlaps with an orthographic projection of the second overlapping portion on the substrate;

[0029] The array substrate also includes: a third transition portion along the first direction and a third overlapping portion; one end of the third transition portion is electrically connected to the third sub-pixel electrode, and the other end is electrically connected to the third overlapping portion; the orthographic projection of the first portion of the second transistor on the substrate has an overlapping area with the orthographic projection of the third overlapping portion on the substrate.

[0030] In a possible implementation manner, a fourth gap is provided between the first transition portion and the second sub-pixel electrode, and a fifth gap is provided between the third transition portion and the third sub-pixel electrode.

[0031] In a possible implementation, the length of the second overlapping portion in the first direction is greater than the length of the second transition portion in the first direction; the length of the third overlapping portion in the second direction is greater than the length of the third transition portion in the second direction.

[0032] In a possible implementation, the second electrode of the third transistor includes: a third transistor first portion extending along the second direction, and a third transistor second portion extending from the third transistor first portion along the first direction;

[0033] The array substrate further includes: a fourth bridging portion; the first common wiring includes: a first common wiring main portion, and a first common bridging portion connected to one side of the first common wiring main portion;

[0034] The orthographic projection of the second portion of the third transistor on the substrate has an overlapping area with the orthographic projection of the fourth overlapping portion on the substrate; the orthographic projection of the first common overlapping portion on the substrate has an overlapping area with the orthographic projection of the fourth overlapping portion on the substrate.

[0035] In a possible implementation, the fourth overlapping portion has a fourth overlapping portion outer edge along the first direction, and the second overlapping portion has a second overlapping portion outer edge extending along the first direction;

[0036] An extension line of the outer edge of the fourth overlapping portion coincides with an extension line of the outer edge of the second overlapping portion.

[0037] In a possible implementation, the first overlapping portion has a first overlapping portion outer edge extending along the second direction, and the third overlapping portion has a third overlapping portion outer edge extending along the second direction;

[0038] An extension line of the outer edge of the first overlapping portion coincides with an extension line of the outer edge of the third overlapping portion.

[0039] In a possible embodiment, the array substrate further includes: a second common routing group electrically connected to the first common routing group and extending away from the gate line, the second common routing group including: two second common routing lines; an orthographic projection of the data line on the substrate and a gap between two second common routing lines of the same second common routing group have an overlapping area on the orthographic projection of the substrate;

[0040] The orthographic projection of the second common line on the substrate is in a meandering shape, and the bend shape of the orthographic projection of the second common line on the substrate is consistent with the bend shape of the orthographic projection of the data line on the substrate.

[0041] In a possible implementation, the array substrate further includes: a third common wiring located on the other side of the gate line and extending along the first direction, and a fourth common wiring group connected to the third common wiring and extending away from the gate line;

[0042] The third common routing line is disconnected at a position where it intersects with the data line; the fourth common routing line group includes: two fourth common routing lines; the orthographic projection of the data line on the substrate and the gap between the two fourth common routing lines of the same fourth common routing line group have an overlapping area on the orthographic projection of the substrate;

[0043] The orthographic projection of the fourth common line on the substrate is in a meandering shape, and the bend shape of the orthographic projection of the fourth common line on the substrate is consistent with the bend shape of the orthographic projection of the data line on the substrate.

[0044] In a possible implementation, the first pixel electrode is an integrated structure, and the second pixel electrode is an integrated structure.

[0045] In a possible implementation, one end of the first pixel electrode away from the gate line is an opening; and one end of the second pixel electrode away from the gate line is an opening.

[0046] In a possible implementation manner, the orthographic projection shape of the connecting portion on the substrate is a rectangle.

[0047] In a possible implementation manner, the gate line has a gate line hollow, and the orthographic projection of the gate line hollow on the substrate covers at least a portion of the orthographic projection of the connecting portion on the substrate.

[0048] In a possible implementation, the first pixel electrode includes: a first sub-electrode portion distributed along the second direction, and a second sub-electrode portion, wherein an extension direction of the first sub-electrode portion is different from an extension direction of the second sub-electrode portion;

[0049] The second pixel electrode includes: a third sub-electrode portion distributed along the second direction, and a fourth sub-electrode portion; an extension direction of the third sub-electrode portion is different from an extension direction of the fourth sub-electrode portion.

[0050] In a possible implementation manner, the extension direction of the first sub-electrode portion is the same as the extension direction of the fourth sub-electrode portion; and the extension direction of the second sub-electrode portion is the same as the extension direction of the third sub-electrode portion.

[0051] In a possible implementation manner, the extension direction of the first sub-electrode portion is the same as the extension direction of the third sub-electrode portion; and the extension direction of the second sub-electrode portion is the same as the extension direction of the fourth sub-electrode portion.

[0052] In a possible implementation manner, an extending direction of the slit in the first sub-electrode portion is the same as an extending direction of the first sub-electrode portion;

[0053] An extending direction of the slit in the second sub-electrode portion is the same as an extending direction of the second sub-electrode portion;

[0054] An extending direction of the slit in the third sub-electrode portion is the same as an extending direction of the third sub-electrode portion;

[0055] An extending direction of the slit in the fourth sub-electrode portion is the same as an extending direction of the fourth sub-electrode portion.

[0056] In a possible embodiment, the data line includes: a first data portion located on one side of the first sub-electrode portion and extending in the same direction as the first sub-electrode, a second data portion located on one side of the second sub-electrode portion and extending in the same direction as the second sub-electrode, a third data portion located on one side of the third sub-electrode portion and extending in the same direction as the third sub-electrode, and a fourth data portion located on one side of the fourth sub-electrode portion and extending in the same direction as the fourth sub-electrode.

[0057] In a possible implementation manner, the data line further includes: a fifth data portion extending along the second direction and connecting the second data portion and the third data portion.

[0058] In a possible implementation, the first pixel electrode and the second pixel electrode both extend along a third direction; and an outer edge of the first pixel electrode along the extension direction does not overlap with an outer edge of the second pixel electrode along the extension direction.

[0059] In a possible implementation manner, the data line includes: a sixth data portion located on one side of the first pixel electrode, and a seventh data portion located on one side of the second pixel electrode;

[0060] An extension direction of the sixth data portion is the same as an extension direction of the seventh data portion; and an extension line of the sixth data portion does not overlap with an extension line of the seventh data portion.

[0061] In a possible implementation manner, the data line further includes an eighth data portion extending along the second direction and connecting the sixth data portion and the seventh data portion.

[0062] In a possible implementation manner, the orthographic projection of the gate line on the substrate is located on one side of the orthographic projection of the pixel electrode on the substrate.

[0063] In a possible embodiment, the array substrate further includes: a first conductive layer located on the side of the pixel electrode facing the substrate, and a fifth common wiring on the same layer as the gate line; the first conductive layer and the fifth common wiring are electrically connected through a via.

[0064] In a possible implementation, the fifth common trace has a first common protrusion on a side facing the gate line; at least a portion of the first common protrusion in an orthographic projection of the substrate overlaps with at least a portion of the via in an orthographic projection of the substrate.

[0065] In a possible implementation manner, the gate line has a first recess on a side facing the fifth common wiring, which is opposite to the first common protrusion.

[0066] In a possible implementation manner, one side of the pixel electrode has a fifth overlapping portion;

[0067] The gate line has the second notch on a side facing the fifth common wiring; the orthographic projection of the second notch on the substrate covers the orthographic projection of the fifth overlapping portion on the substrate.

[0068] In a possible implementation, the pixel electrode includes: a first sub-electrode portion, a second sub-electrode portion, a third sub-electrode portion, and a fourth sub-electrode portion sequentially distributed along the second direction;

[0069] An extending direction of the first sub-electrode portion is different from an extending direction of the second sub-electrode portion; and an extending direction of the third sub-electrode portion is different from an extending direction of the fourth sub-electrode portion.

[0070] In a possible implementation manner, the extension direction of the first sub-electrode portion is the same as the extension direction of the fourth sub-electrode portion; and the extension direction of the second sub-electrode portion is the same as the extension direction of the third sub-electrode portion.

[0071] In a possible embodiment, the data line includes: a first data portion located on one side of the first sub-electrode portion and extending in the same direction as the first sub-electrode portion, a second data portion located on one side of the second sub-electrode portion and extending in the same direction as the second sub-electrode portion, a third data portion located on one side of the third sub-electrode portion and extending in the same direction as the third sub-electrode portion, and a fourth data portion located on one side of the fourth sub-electrode portion and extending in the same direction as the fourth sub-electrode portion; the second data portion is directly connected to the third data portion.

[0072] In a possible embodiment, the pixel electrode includes: a fifth sub-electrode portion, a sixth sub-electrode portion, and a seventh sub-electrode portion distributed in sequence along the second direction; the extension direction of the fifth sub-electrode portion is the same as the extension direction of the seventh sub-electrode portion; the extension direction of the sixth sub-electrode portion is different from the extension direction of the fifth sub-electrode portion.

[0073] An extension length of the sixth sub-electrode portion is greater than an extension length of the fifth sub-electrode portion, and greater than an extension length of the seventh sub-electrode portion.

[0074] In a possible embodiment, the data line includes: a ninth data portion located on one side of the fifth sub-electrode portion and extending in the same direction as the fifth sub-electrode portion, a tenth data portion located on one side of the sixth sub-electrode portion and extending in the same direction as the sixth sub-electrode portion, and an eleventh data portion located on one side of the seventh sub-electrode portion and extending in the same direction as the seventh sub-electrode portion.

[0075] The embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure and an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate includes a common electrode layer.

[0076] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] FIG1A is a schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0078] FIG1B is an enlarged schematic diagram of the dotted line frame S1 in FIG1A ;

[0079] FIG1C is a schematic diagram of a single film layer where the gate lines are located in FIG1A ;

[0080] FIG1D is a schematic diagram of a single film layer of the active layer in FIG1A ;

[0081] FIG1E is a schematic diagram of a single film layer where the data line is located in FIG1A ;

[0082] FIG1F is a schematic diagram of a single film layer of the first insulating layer in FIG1A ;

[0083] FIG1G is a schematic diagram of a single film layer where the pixel electrode is located in FIG1A ;

[0084] FIG1H is a schematic diagram of the black matrix layer corresponding to FIG1A ;

[0085] FIG1I may be a schematic cross-sectional view taken along dotted line EF in FIG1B ;

[0086] FIG2A is a second schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0087] FIG2B is an enlarged schematic diagram of the dotted line frame S1 in FIG2A ;

[0088] FIG2C is a schematic diagram of a single film layer where the gate lines are located in FIG2A;

[0089] FIG2D is a schematic diagram of a single film layer of the active layer in FIG2A;

[0090] FIG2E is a schematic diagram of a single film layer where the data line is located in FIG2A ;

[0091] FIG2F is a schematic diagram of a single film layer of the first insulating layer in FIG2A ;

[0092] FIG2G is a schematic diagram of a single film layer of the first conductive layer in FIG2A ;

[0093] FIG2H is a schematic diagram of the second insulating layer corresponding to FIG2A ;

[0094] FIG2I is a schematic diagram of a pixel electrode layer corresponding to FIG2A ;

[0095] FIG2J is a schematic diagram of the black matrix layer corresponding to FIG2A ;

[0096] FIG3A is a third schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0097] FIG3B is an enlarged schematic diagram of the dotted line frame S1 in FIG3A ;

[0098] FIG3C is a schematic diagram of a single film layer where the gate lines are located in FIG3A;

[0099] FIG3D is a schematic diagram of a single film layer of the active layer in FIG3A;

[0100] FIG3E is a schematic diagram of a single film layer where the data line is located in FIG3A ;

[0101] FIG3F is a schematic diagram of a single film layer of the first insulating layer in FIG3A ;

[0102] FIG3G is a schematic diagram of a single film layer of the first conductive layer in FIG3A ;

[0103] FIG3H is a schematic diagram of the second insulating layer corresponding to FIG3A ;

[0104] FIG3I is a schematic diagram of a pixel electrode layer corresponding to FIG3A ;

[0105] FIG3J is a schematic diagram of the black matrix layer corresponding to FIG3A ;

[0106] FIG4A is a fourth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0107] FIG4B is an enlarged schematic diagram of the dotted line frame S1 in FIG4A ;

[0108] FIG4C is a schematic diagram of a single film layer where the gate lines are located in FIG4A;

[0109] FIG4D is a schematic diagram of a single film layer of the active layer in FIG4A;

[0110] FIG4E is a schematic diagram of a single film layer where the data line is located in FIG4A ;

[0111] FIG4F is a schematic diagram of a single film layer of the first insulating layer in FIG4A ;

[0112] FIG4G is a schematic diagram of a single film layer of the first conductive layer in FIG4A ;

[0113] FIG4H is a schematic diagram of the second insulating layer corresponding to FIG4A ;

[0114] FIG4I is a schematic diagram of a pixel electrode layer corresponding to FIG4A ;

[0115] FIG4J is a schematic diagram of the black matrix layer corresponding to FIG4A ;

[0116] FIG5A is a fifth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0117] FIG5B is an enlarged schematic diagram of the dotted line frame S1 in FIG5A ;

[0118] FIG5C is a schematic diagram of a single film layer where the gate lines are located in FIG5A;

[0119] FIG5D is a schematic diagram of a single film layer of the active layer in FIG5A;

[0120] FIG5E is a schematic diagram of a single film layer where the data line is located in FIG5A ;

[0121] FIG5F is a schematic diagram of a single film layer of the first insulating layer in FIG5A ;

[0122] FIG5G is a schematic diagram of a single film layer of the first conductive layer in FIG5A ;

[0123] FIG5H is a schematic diagram of the second insulating layer corresponding to FIG5A ;

[0124] FIG5I is a schematic diagram of a pixel electrode layer corresponding to FIG5A ;

[0125] FIG5J is a schematic diagram of the black matrix layer corresponding to FIG5A ;

[0126] FIG6 is a light effect simulation diagram of a display panel in a UV2A alignment mode at a sub-pixel;

[0127] FIG7 is a light effect simulation diagram of a display panel with an SUVA alignment mode at a sub-pixel;

[0128] FIG8 is a light effect simulation diagram of a display panel in a SUVA-ADS alignment mode at a sub-pixel when the data lines are arranged vertically;

[0129] FIG9 is a light effect simulation diagram of a sub-pixel of a display panel provided by an embodiment of the present disclosure;

[0130] FIG10 is a schematic diagram of liquid crystal alignment at a sub-pixel of a display panel in UV2A alignment mode;

[0131] FIG11 is a schematic diagram of liquid crystal alignment at a sub-pixel of a display panel provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0132] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. The implementation methods can be implemented in multiple different forms. Ordinary technicians in the relevant technical field can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following implementation methods. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other in any way.

[0133] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0134] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" may mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%. In this specification, "approximately the same" may refer to values ​​that are within 10% of each other.

[0135] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0136] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0137] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0138] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0139] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode (gate), a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0140] The gate of a transistor can also be referred to as the control electrode. The functions of the "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source electrode" and "drain electrode" may be interchanged.

[0141] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0142] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0143] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0144] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0145] The key to UV2A is the use of a special polymer material as an alignment film to precisely control the tilt of liquid crystal molecules along the direction of ultraviolet light. However, this optical alignment method has its own disadvantages, namely poor color cast.

[0146] In view of this, refer to Figures 1A-1H, 2A-2J, 3A-3J, 4A-4J, and 5A-5J, wherein Figure 1A is one of the schematic diagrams of the array substrate provided in an embodiment of the present disclosure, Figure 1B is an enlarged schematic diagram of the dotted line frame S1 in Figure 1A, Figure 1C is a schematic diagram of a single film layer of the layer where the gate line is located in Figure 1A, Figure 1D is a schematic diagram of a single film layer of the active layer in Figure 1A, Figure 1E is a schematic diagram of a single film layer of the layer where the data line is located in Figure 1A, Figure 1F is a schematic diagram of a single film layer of the first insulating layer in Figure 1A, Figure 1G is a schematic diagram of a single film layer of the layer where the pixel electrode is located in Figure 1A, Figure 1H is a schematic diagram of the black matrix layer corresponding to Figure 1A, Figure 2A is a second schematic diagram of the array substrate provided in an embodiment of the present disclosure, and Figure 2B 2A , FIG2C is a schematic diagram of a single film layer of the layer where the gate line is located in FIG2A , FIG2D is a schematic diagram of a single film layer of the active layer in FIG2A , FIG2E is a schematic diagram of a single film layer of the layer where the data line is located in FIG2A , FIG2F is a schematic diagram of a single film layer of the first insulating layer in FIG2A , FIG2G is a schematic diagram of a single film layer of the first conductive layer in FIG2A , FIG2H is a schematic diagram of the second insulating layer corresponding to FIG2A , FIG2I is a schematic diagram of the pixel electrode layer corresponding to FIG2A , FIG2J is a schematic diagram of the black matrix layer corresponding to FIG2A , FIG3A is a third schematic diagram of the array substrate provided in an embodiment of the present disclosure, FIG3B is an enlarged schematic diagram of the dotted line frame S1 in FIG3A , FIG3C is a schematic diagram of a single film layer of the layer where the gate line is located in FIG3A , FIG3 D is a schematic diagram of a single film layer of the active layer in Figure 3A, Figure 3E is a schematic diagram of a single film layer of the layer where the data line is located in Figure 3A, Figure 3F is a schematic diagram of a single film layer of the first insulating layer in Figure 3A, Figure 3G is a schematic diagram of a single film layer of the first conductive layer in Figure 3A, Figure 3H is a schematic diagram of the second insulating layer corresponding to Figure 3A, Figure 3I is a schematic diagram of the pixel electrode layer corresponding to Figure 3A, Figure 3J is a schematic diagram of the black matrix layer corresponding to Figure 3A, Figure 4A is a fourth schematic diagram of the array substrate provided in an embodiment of the present disclosure, Figure 4B is an enlarged schematic diagram of the dotted line frame S1 in Figure 4A, Figure 4C is a schematic diagram of a single film layer of the layer where the gate line is located in Figure 4A, Figure 4D is a schematic diagram of a single film layer of the active layer in Figure 4A, Figure 4E is a schematic diagram of a single film layer of the layer where the data line is located in Figure 4A, and Figure 4F is a schematic diagram of a single film layer of the first insulating layer in FIG4A , FIG4G is a schematic diagram of a single film layer of the first conductive layer in FIG4A , FIG4H is a schematic diagram of the second insulating layer corresponding to FIG4A , FIG4I is a schematic diagram of the pixel electrode layer corresponding to FIG4A , FIG4J is a schematic diagram of the black matrix layer corresponding to FIG4A , FIG5A is a fifth schematic diagram of the array substrate provided in an embodiment of the present disclosure, FIG5B is an enlarged schematic diagram of the dotted line frame S1 in FIG5A , FIG5C is a schematic diagram of a single film layer of the layer where the gate line is located in FIG5A , FIG5D is a schematic diagram of a single film layer of the active layer in FIG5A , FIG5E is a schematic diagram of a single film layer of the layer where the data line is located in FIG5A , FIG5F is a schematic diagram of a single film layer of the first insulating layer in FIG5A , and FIG5G is a schematic diagram of a single film layer of the first conductive layer in FIG5A ,FIG5H is a schematic diagram of the second insulating layer corresponding to FIG5A , FIG5I is a schematic diagram of the pixel electrode layer corresponding to FIG5A , and FIG5J is a schematic diagram of the black matrix layer corresponding to FIG5A . An embodiment of the present disclosure provides an array substrate, comprising:

[0147] Substrate 1;

[0148] A plurality of gate lines 2 are located on one side of the substrate 1 and extend along a first direction X;

[0149] A plurality of data lines 3, wherein the main direction of the plurality of data lines 3 extends along a second direction Y, and the orthographic projection of the data lines 3 on the substrate 1 is a bent shape; specifically, the second direction Y may intersect the first direction X; specifically, the second direction Y may be perpendicular to the first direction X; specifically, the second direction Y may be a direction of pixel electrode columns, and the first direction X may be a direction of pixel electrode rows;

[0150] Multiple pixel electrodes 4, wherein the orthographic projections of the pixel electrodes 4 on the substrate 1 are located between the orthographic projections of adjacent data lines 3 on the substrate 1; the pixel electrodes 4 include multiple slits F, and the extending directions of the orthographic projections of the slits F on the substrate 1 are consistent with the extending directions of the orthographic projections of the adjacent data lines 3 on the substrate 1. Specifically, for example, as shown in FIG1A , the pixel electrode 4 includes four sub-electrode portions sequentially distributed along the second direction Y, namely, a first sub-electrode portion P1, a second sub-electrode portion P2, a third sub-electrode portion P3, and a fourth sub-electrode portion P4. The extending directions of the slits F in the first sub-electrode portion P1 are consistent with the extending directions of the data lines 3 on both sides thereof in the region, the extending directions of the slits F in the second sub-electrode portion P2 are consistent with the extending directions of the data lines 3 on both sides thereof in the region, the extending directions of the slits F in the third sub-electrode portion P3 are consistent with the extending directions of the data lines 3 on both sides thereof in the region, and the extending directions of the slits F in the fourth sub-electrode portion P4 are consistent with the extending directions of the data lines 3 on both sides thereof in the region.

[0151] In the embodiment of the present disclosure, the orthographic projection of the data line 3 on the substrate 1 is bent, and the extension direction of the orthographic projection of the slit F of the pixel electrode 4 on the substrate 1 is consistent with the extension direction of the orthographic projection of the adjacent data line 3 on the substrate 1, so that the edge electric field of the pixel electrode 4 and the internal electric field of the pixel electrode 4 can be made to have the same direction, the liquid crystal disorder phenomenon is reduced or eliminated, and the dark lines on the edge of the pixel electrode 4 also disappear; moreover, the appearance of 90° / 270° oriented liquid crystal molecules in the area where the pixel electrode 4 is located can be reduced or eliminated, thereby improving the viewing angle color deviation of the display panel in the first direction X (left and right).

[0152] Specifically, see Figures 6 to 9, wherein Figure 6 is a light effect simulation diagram of a display panel with a UV2A alignment mode at a sub-pixel, Figure 7 is a light effect simulation diagram of a display panel with a SUVA alignment mode at a sub-pixel, Figure 8 is a light effect simulation diagram of a display panel with a SUVA-ADS alignment mode at a sub-pixel when the data line is vertically aligned, and Figure 9 is a light effect simulation diagram of a display panel provided by an embodiment of the present disclosure at a sub-pixel. It can be seen that the traditional UV2A alignment mode structure and the SUVA alignment mode structure, the SUVA-ADS alignment mode structure, when the data line is vertical When the data line is bent in the direction (i.e., along the second direction Y), dark lines will appear on the edge of the data line. That is, because the liquid crystal of the edge electric field is horizontal (i.e., along the first direction X), while the liquid crystal in the sub-pixel is oriented at 45 degrees, the liquid crystal will be disordered in different directions at the edge of the data line. After the data line is changed to a bent (45°) design, the direction of the edge electric field and the electric field in the pixel are the same, the liquid crystal disorder disappears, and the dark lines on the edge also disappear. In addition, the presence of 90° / 270° liquid crystal molecules will increase the overall Δn of the liquid crystal (the difference in refractive index between the long and short axes of the liquid crystal), which will affect the color deviation of large viewing angles. As shown in Figures 10 and 11, the array substrate structure provided by the embodiments of the present disclosure can reduce or eliminate the appearance of 90° / 270° liquid crystal molecules in the sub-pixels, thereby improving the color deviation of large viewing angles.

[0153] It should be noted that the main direction of the data line 3 extends along the second direction Y. It can be understood that the data line 3 as a whole extends along the second direction Y, but when it comes to the area corresponding to each pixel electrode 4, it can be bent.

[0154] In a possible embodiment, referring to Figures 1A-1H, 2A-2J, 4A-4J, and 5A-5J, the bending shape of the slit F in the same pixel electrode 4 projected on the substrate 1 is consistent with the bending shape of the adjacent data line 3 projected on the substrate 1.

[0155] In a possible embodiment, referring to Figures 1A-1H, 2A-2J, and 3A-3J, the orthographic projection of the gate line 2 on the substrate 1 passes through the central area of ​​the orthographic projection of the pixel electrode 4 on the substrate 1; the pixel electrode 4 has a first gap J1 in the area where the gate line 2 is located; the pixel electrode 4 includes: a first pixel electrode 41 located on one side of the gate line 2, a second pixel electrode 42 located on the other side of the gate line 2, and a connecting portion 43 connecting at least a portion of the first pixel electrode 41 and at least a portion of the second pixel electrode 42.

[0156] In the embodiment of the present disclosure, the gate line 2 passes through the central area of ​​the pixel electrode 4, that is, the pixel electrode 4 is divided by the gate line 2 into a first pixel electrode 41 located on one side of the gate line 2, and a second pixel electrode 42 located on the other side of the gate line 2. At least part of the first pixel electrode 41 is electrically connected to at least part of the second pixel electrode 42, so that two different display effects of light and dark can be achieved in one pixel electrode 4. In conjunction with the liquid crystal alignment direction of different sub-electrode parts in the pixel electrode 4, it is beneficial to achieve an 8-domain distribution in one pixel electrode 4. While improving the edge dark lines, improving the transmittance, and improving the color deviation by bending the data line 3, the dark lines can be further reduced and the color deviation can be improved by realizing multiple domain phases in one pixel electrode 4.

[0157] In one possible embodiment, as shown in FIG1A to FIG1H , the array substrate further includes: a plurality of transistors T; the pixel electrode 4 is electrically connected to the data line 3 via the plurality of transistors T; the first pixel electrode 41 includes: a first sub-pixel electrode 411 and a second sub-pixel electrode 412 distributed along a first direction X; the second pixel electrode 42 includes: a third sub-pixel electrode 421 and a fourth sub-pixel electrode 422 distributed along the first direction X; the second sub-pixel electrode 412 is located on a side of the first sub-pixel electrode 411 away from the electrically connected data line 3, and the fourth sub-pixel electrode 422 is located on a side of the third sub-pixel electrode 421 away from the electrically connected data line 3; and one of the first sub-pixel electrode 411 and the second sub-pixel electrode 412 is electrically connected to one of the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422 via a connecting portion 43. The brightness of the two electrically connected sub-pixel electrodes is different from the brightness of the other two sub-pixel electrodes. Specifically, for example, the first sub-pixel electrode 411 may be electrically connected to the third sub-pixel electrode 421, and the second sub-pixel electrode 412 may be electrically connected to the fourth sub-pixel electrode 422; or, the first sub-pixel electrode 411 may be electrically connected to the fourth sub-pixel electrode 422, and the second sub-pixel electrode 412 may be electrically connected to the third sub-pixel electrode 421.

[0158] In the disclosed embodiment, one of the first sub-pixel electrode 411 and the second sub-pixel electrode 412 is electrically connected to one of the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422 via a connecting portion 43. The brightness of the two electrically connected electrodes is different from that of the other two electrodes, thereby achieving two different light and dark display effects in a single pixel electrode 4. By combining the liquid crystal alignment directions of the different sub-electrode portions in the pixel electrode 4, an eight-domain distribution can be achieved in a single pixel electrode 4. While improving edge dark lines, enhancing transmittance, and improving color shift by bending the data line 3, the four portions of the pixel electrode 4 are cross-connected electrically in pairs, further reducing dark lines and improving color shift by achieving multiple domain phases in a single pixel electrode 4.

[0159] It should be noted that in the disclosed embodiment, the electrical connection between the first sub-pixel electrode 411 and the second sub-pixel electrode 412 and the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422 may be achieved at the same layer as the pixel electrode 4, while the other two sub-pixel electrodes may not be connected at the same layer as the pixel electrode 4, but may be electrically connected via other structures, for example, both being connected to the same transistor drain. Specifically, for example, the first sub-pixel electrode 411 and the third sub-pixel electrode 421 may be electrically connected at the same layer as the pixel electrode 4, and both exhibit one brightness; while the second sub-pixel electrode 412 and the third sub-pixel electrode 421 may not be electrically connected at the same layer as the pixel electrode 4, but may be connected to the same transistor drain to achieve a different brightness. The brightness of the two sub-pixel electrodes connected at the same layer as the pixel electrode 4 may be different from the brightness of the other two sub-pixel electrodes.

[0160] It can be understood that the brightness of the two electrically connected together is different from the brightness of the other two, and refers to the brightness comparison within a sub-pixel when the display panel is powered on and illuminated.

[0161] In a possible embodiment, referring to FIG. 1A to FIG. 1H , the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 are electrically connected via a connecting portion 43 at the layer where the pixel electrode 4 is located; the second sub-pixel electrode 412 and the third sub-pixel electrode 421 are independent of each other at the layer where the pixel electrode 4 is located.

[0162] In a possible embodiment, referring to Figures 1A-1H, multiple transistors electrically connected to the same pixel electrode 4 are all electrically connected to the same data line 3 and the same gate line 2. For example, as shown in Figure 1B, there are three transistors electrically connected to the same pixel electrode 4, namely, a first transistor T1, a second transistor T2, and a third transistor T3. The three transistors are all electrically connected to the same data line 3 and the same gate line 2.

[0163] It should be noted that the multiple transistors electrically connected to the same pixel electrode 4 may refer to transistors electrically connected to the same pixel electrode 4 directly or indirectly. For example, the first transistor T1 and the second transistor T2 may be directly electrically connected to the pixel electrode 4, and the third transistor T3, since it is electrically connected to the second transistor T2, may also be considered to be electrically connected to the pixel electrode 4. Specifically, the multiple transistors electrically connected to the same pixel electrode 4 may also be transistors that drive the same pixel electrode 4 to emit light.

[0164] In a possible embodiment, referring to FIG. 1A to FIG. 1H , the array substrate further includes: a first common trace 21 located on one side of the gate line 2 and extending along the first direction X; the plurality of transistors T include: a first transistor T1 , a second transistor T2 , and a third transistor T3 ;

[0165] The control electrode TA of the first transistor T1 is electrically connected to the gate line 2, the first electrode TB of the first transistor T1 is electrically connected to the data line 3, and the second electrode TC of the first transistor T1 is electrically connected to the connecting portion 43. Specifically, the second electrode TC of the first transistor T1 can be electrically connected to the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422 through the first via hole K1.

[0166] The control electrode TA of the second transistor T2 is electrically connected to the gate line 2, the first electrode TB of the second transistor T2 is electrically connected to the data line 3, and the second electrode TC of the second transistor T2 is electrically connected to the second sub-pixel electrode 412 and the third sub-pixel electrode 421. Specifically, the second electrode TC of the second transistor T2 can be electrically connected to the third sub-pixel electrode 421 through a second via hole K2; the second electrode TC of the second transistor T2 can be electrically connected to the second sub-pixel electrode 412 through a third via hole K3.

[0167] The control electrode TA of the third transistor T3 is electrically connected to the gate line 2, the first electrode TB of the third transistor T3 reuses the second electrode TC of the second transistor T2, and the second electrode TC of the third transistor T3 is electrically connected to the first common wiring 21. Specifically, the second electrode TC of the third transistor T3 can be electrically connected to the first common wiring 21 through a fourth via K4.

[0168] In the embodiment of the present disclosure, since the third transistor T3 is connected to the second transistor T2, the voltage applied to the second sub-pixel electrode 412 and the third sub-pixel electrode 421 will be partially distributed to the first common wiring 21 through the third transistor T3, so that the voltage obtained by the second sub-pixel electrode 412 and the third sub-pixel electrode 421 is lower than the voltage obtained by the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, and thus the luminous brightness of the second sub-pixel electrode 412 and the third sub-pixel electrode 421 is lower than the luminous brightness of the first sub-pixel electrode 411 and the fourth sub-pixel electrode 422, thereby forming a display effect with different brightness and darkness in the sub-pixels.

[0169] In one possible embodiment, as shown in Figures 1A-1H , the second electrode TC of the first transistor T1 includes a first transistor first portion T1C1 extending along a first direction X. The array substrate also includes a first connecting portion PD1 connected to the connecting portion 43. The orthographic projection of the first connecting portion PD1 on the substrate 1 overlaps with the orthographic projection of the first transistor first portion T1C1 on the substrate 1. In this way, the first transistor first portion T1C1 and the first connecting portion PD1 are electrically connected in the overlapping region through the first via K1.

[0170] In one possible embodiment, referring to Figures 1A-1H, the second electrode TC of the first transistor T1 includes: a first transistor second portion T1C2 extending along the second direction Y and electrically connected to the first transistor first portion T1C1; specifically, the orthographic projection of the first transistor second portion T1C2 on the substrate 1 may have an overlapping area with the orthographic projection of the active pattern 5 on the substrate 1.

[0171] In a possible embodiment, referring to FIG. 1A to FIG. 1H , the connection portion 43 includes: a first connection portion 431 extending along a first direction X, a second connection portion 432 , and a third connection portion 433 extending along a second direction Y;

[0172] One end of the first connecting portion 431 is electrically connected to the first sub-pixel electrode 411 , and the other end of the first connecting portion 431 is electrically connected to one end of the third connecting portion 433 ; the other end of the third connecting portion 433 is electrically connected to one end of the second connecting portion 432 ; and the other end of the second connecting portion 432 is electrically connected to the fourth sub-pixel electrode 422 .

[0173] The first connecting portion PD1 is electrically connected to the first connecting portion 431 and is away from a side of the connected first sub-pixel electrode 411 .

[0174] In the disclosed embodiment, the connecting portion 43 includes: a first connecting portion 431 extending along the first direction X, a second connecting portion 432, and a third connecting portion 433 extending along the second direction Y. The wiring of the connecting portion 43 is regular, which is conducive to simple wiring between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects that may occur during etching patterning when the layout of multiple patterns is complex; moreover, the connecting portion 43 is also connected to the first overlapping portion PD1, so as to facilitate the electrical connection between the first overlapping portion PD1 and the second electrode TC of the first transistor T1 through the first via K1.

[0175] In a possible implementation, as shown in FIG. 1A to FIG. 1H , a second gap J2 is provided between the first connecting portion 431 and the connected first sub-pixel electrode 411 , and a third gap J3 is provided between the second connecting portion 432 and the electrically connected fourth sub-pixel electrode 422 .

[0176] In one possible embodiment, as shown in FIG1G , a length a1 of the first connecting portion PD1 in the second direction Y is greater than a length a2 of the first connecting portion 431 in the second direction Y. This allows the first connecting portion PD1 to have sufficient area to be electrically connected to the first portion of the first transistor T1C1 through the first via K1.

[0177] In one possible embodiment, referring to FIG. 1A to FIG. 1H , the second electrode TC of the second transistor T2 includes: a first second transistor portion T2C1 extending along a first direction X, and a second second transistor portion T2C2 extending from the first second transistor portion T2C1 along a second direction Y;

[0178] The array substrate further includes: a first transition portion PZ1 extending along a first direction X, a second transition portion PZ2 extending along a second direction Y, and a second connecting portion PD2; one end of the first transition portion PZ1 is electrically connected to the second sub-pixel electrode 412, and the other end is electrically connected to one end of the second transition portion PZ2; the other end of the second transition portion PZ2 is electrically connected to the second connecting portion PD2; an orthographic projection of the second transistor second portion T2C2 on the substrate 1 overlaps with an orthographic projection of the second connecting portion PD2 on the substrate 1; in this way, the second connecting portion PD2 is electrically connected to the second transistor second portion T2C2 at the overlapping position through the third via K3;

[0179] The array substrate further includes: a third transition portion PZ2 and a third bridging portion PD3 along the first direction X; one end of the third transition portion PZ2 is electrically connected to the third subpixel electrode 421, and the other end is electrically connected to the third bridging portion PD3; the orthographic projection of the first portion of the second transistor T2C1 on the substrate 1 overlaps with the orthographic projection of the third bridging portion PD3 on the substrate 1. In this manner, the third bridging portion PD3 and the first portion of the second transistor T2C1 are electrically connected at the overlapping position through the second via K2.

[0180] In the embodiment of the present disclosure, a first transition portion PZ1, a second transition portion PZ2 extending along the second direction Y, and a second overlap portion PD2 are further provided on one side of the second sub-pixel electrode 412. In this way, the second sub-pixel electrode 412 is electrically connected to the second electrode TB of the second transistor T2, and the wiring method for electrically connecting the second sub-pixel electrode 412 to the second electrode TB of the second transistor T2 is simple and regular, which is conducive to the simple wiring between the gap between the first pixel electrode 41 and the second pixel electrode 42, and avoids the risk of short circuit defects that may occur during etching patterning when the layout of multiple patterns is more complex.

[0181] In a possible embodiment, referring to FIG1G , the second electrode TC of the second transistor T2 may further include: a second transistor third portion T2C3 electrically connected to the other end of the second transistor first portion T2C1 and extending along the second direction Y. Specifically, the orthographic projection of the second transistor third portion T2C3 on the substrate 1 may have an overlapping area with the orthographic projection of the active pattern 6 on the substrate 1.

[0182] In a possible implementation, as shown in FIG. 1G , a fourth gap J4 is defined between the first transition portion PZ1 and the second sub-pixel electrode 412 , and a fifth gap J5 is defined between the third transition portion PZ3 and the third sub-pixel electrode 421 .

[0183] In one possible embodiment, referring to FIG1G , a length a3 of the second overlap portion PD2 in the first direction X is greater than a length a4 of the second transition portion PZ2 in the first direction X, so that the second overlap portion PD2 has sufficient area to be electrically connected to the second transistor second portion T2C2 through the third via K3; a length a5 of the third overlap portion PD3 in the second direction Y is greater than a length a6 of the third transition portion PZ3 in the second direction Y, so that the third overlap portion PD3 has sufficient area to be electrically connected to the second transistor first portion T2C1 through the second via K2.

[0184] In one possible embodiment, referring to FIG. 1A to FIG. 1I , the second electrode TC of the third transistor T3 includes: a first third transistor portion T3C1 extending along the second direction Y, and a second third transistor portion T3C2 extending from the first third transistor portion T3C1 along the first direction X;

[0185] The array substrate further includes: a fourth connecting portion PD4; the first common wiring 21 includes: a first common wiring main portion 211, and a first common connecting portion 212 connected to one side of the first common wiring main portion 211;

[0186] The orthographic projection of the first common overlap portion 212 on the substrate 1 has an overlapping area with the orthographic projection of the fourth overlap portion PD4 on the substrate 1; in this way, the first common overlap portion 212 and the second part of the third transistor T3C2 are connected through the fourth via K4 at the overlapping area; the orthographic projection of the second part of the third transistor T3C2 on the substrate 1 has an overlapping area with the orthographic projection of the fourth overlap portion PD4 on the substrate; in this way, the fourth overlap portion PD4 and the second part of the third transistor T3C2 are connected through the fourth via K4 at the overlapping area.

[0187] In one possible embodiment, referring to FIG. 1I , which is a schematic cross-sectional view taken along the dotted line EF in FIG. 1B , the fourth via K4 may be a semi-via design. The fourth via K4 partially exposes the first common trace 21 and partially exposes the second electrode TC of the third transistor T3 . The fourth bridging portion PD4 partially contacts the first common trace 21 and partially contacts the second electrode TC of the third transistor T3 at the fourth via K4 , thereby electrically connecting the first common trace 21 to the second portion T3C2 of the third transistor via the fourth bridging portion PD4 . Specifically, the semi-via design of the fourth via K4 may form a stepped structure within the fourth via K4 , thereby draining the alignment liquid and preventing moiré patterns from appearing on the image.

[0188] In a possible implementation, referring to FIG. 1E , an extension direction of the first portion T3C1 of the third transistor is parallel to an extension direction of the second portion T2C2 of the second transistor.

[0189] In one possible embodiment, as shown in FIG1E , at least a portion of the first portion T1C1 of the first transistor extends parallel to at least a portion of the first portion T2C1 of the second transistor. This facilitates simple wiring between the first pixel electrode 41 and the second pixel electrode 42 and avoids the risk of short circuits during etching and patterning when multiple patterns are arranged in a complex manner.

[0190] In a possible embodiment, referring to FIG1G , the fourth overlap portion PD4 has a fourth overlap portion outer edge f1 along the first direction X, and the second overlap portion PD2 has a second overlap portion outer edge f2 extending along the first direction X; the extension line of the fourth overlap portion outer edge f1 coincides with the extension line of the second overlap portion outer edge f2, so that the pattern distribution between the first pixel electrode 41 and the second pixel electrode 42 can be simple and regular, avoiding the risk of short circuit defects during etching patterning when the layout of multiple patterns is more complex.

[0191] In a possible embodiment, referring to FIG1G , the first overlap portion PD1 has a first overlap portion outer edge f3 extending along the second direction Y, and the third overlap portion PD3 has a third overlap portion outer edge f4 extending along the second direction Y; the extension line of the first overlap portion outer edge f3 coincides with the extension line of the third overlap portion outer edge f4, so that the pattern distribution between the first pixel electrode 41 and the second pixel electrode 42 can be simple and regular, avoiding the risk of short circuit defects during etching patterning when the layout of multiple patterns is complex.

[0192] In one possible embodiment, referring to Figures 1A to 1H, the array substrate further includes: a second common routing group 22 electrically connected to the first common routing 21 and extending toward a side away from the gate line 2, the second common routing group 22 including: two second common routing lines 220; an orthographic projection of the data line 3 on the substrate 1 and a gap between two second common routing lines 220 of the same second common routing group 22 having an overlapping area in an orthographic projection on the substrate 1; the orthographic projection of the second common routing line 220 on the substrate 1 is in a bent shape, and the bent shape of the orthographic projection of the second common routing line 220 on the substrate 1 is consistent with the bent shape of the orthographic projection of the data line 3 on the substrate 1. In the disclosed embodiment, the bent shape of the second common routing line 220 is consistent with the bent shape of the data line 3 and can match the bend of the data line 3, and the orthographic projection of the second common routing line 220 on the substrate 1 is located on both sides of the orthographic projection of the data line 3 on the substrate 1, which can improve the coupling capacitance between the data line 3 and the second pixel electrode 42.

[0193] In a possible embodiment, referring to Figures 1A to 1H, the array substrate further includes: a third common routing line 23 located on the other side of the gate line 2 and extending along the first direction X, and a fourth common routing line group 24 connected to the third common routing line 23 and extending toward a side away from the gate line 2; the third common routing line 23 is disconnected at the intersection with the data line 3, so as to avoid the third common routing line 23 and the data line 3 from overlapping, thereby increasing the load of the data line 3 and affecting the signal transmission of the data line 3; the fourth common routing line group 24 includes: two fourth common routing lines 240; the orthographic projection of the data line 3 on the substrate 1 and the gap between the two fourth common routing lines 240 of the same fourth common routing line group 24 have an overlapping area in the orthographic projection on the substrate 1; the orthographic projection of the fourth common routing line 240 on the substrate 1 is bent, and the bent shape of the orthographic projection of the fourth common routing line 240 on the substrate 1 is consistent with the bent shape of the orthographic projection of the data line 3 on the substrate 1. In the embodiment of the present disclosure, the bending shape of the fourth common routing 240 is consistent with the bending shape of the data line 3, and can match the bending of the data line 3, and the orthographic projection of the fourth common routing 240 on the substrate 1 is located on both sides of the orthographic projection of the data line 3 on the substrate 1, which can improve the coupling capacitance between the data line 3 and the first pixel electrode 41.

[0194] In one possible embodiment, as shown in Figures 2A to 2J , the first pixel electrode 41 is an integral structure, and the second pixel electrode 42 is an integral structure. That is, in one possible embodiment, as shown in Figure 2I , the first pixel electrode 41 on one side of the gate line 2 is no longer divided in the left-right direction, and the second pixel electrode 42 on the other side of the gate line 2 is no longer divided in the left-right direction. This simplifies the production of the pixel electrode 4 and reduces the risk of short circuit defects in the array substrate due to the complex pattern of the pixel electrode 4.

[0195] In one possible implementation, as shown in FIG2I , the end of the first pixel electrode 41 away from the gate line 2 is open, and the end of the second pixel electrode 42 away from the gate line 2 is open. In the disclosed embodiment, the ends of the first pixel electrode 41 and 42 away from the gate line 2 are open, which can reduce dark lines on the edges of the pixel electrodes 4 and improve the transmittance of the display panel.

[0196] It should be noted that when the first pixel electrode 41 and the second pixel electrode 42 have multiple branch electrodes and slits F located between adjacent branches, the end of the first pixel electrode 41 away from the gate line 2 is an opening; the end of the second pixel electrode 42 away from the gate line 2 is an opening. It can be understood that the ends of the branch electrodes are not connected to each other, and the ends of the slits F are not connected to each other.

[0197] In one possible embodiment, as shown in FIG2I , the orthographic projection of the connecting portion 43 on the substrate 1 is a rectangle, thereby simplifying the production of the pixel electrode 4 and reducing the risk of short circuit defects in the array substrate due to the complex pattern of the pixel electrode 4 .

[0198] In one possible embodiment, as shown in FIG2I , the connection portion 43 is a block-shaped electrode. In one possible embodiment, as shown in FIG2I , the connection portion 43 may include: a first side edge f5 extending along the second direction Y, and a second side edge f6.

[0199] In one possible embodiment, referring to Figures 2A-2J , the gate line 2 has a gate line hollow 20, and the orthographic projection of the gate line hollow 20 on the substrate 1 covers at least a portion of the orthographic projection of the connecting portion 43 on the substrate 1. In the embodiment of the present disclosure, the gate line 2 has a gate line hollow 20, and the orthographic projection of the gate line hollow 20 on the substrate 1 at least partially covers the orthographic projection of the connecting portion 43 on the substrate 1. This can avoid the pixel electrode 4 and the gate line 2 from overlapping at the connecting portion 43, causing the two to generate coupling capacitance, thereby increasing the load on the gate line 2 and affecting the signal transmission of the gate line 2.

[0200] In one possible embodiment, referring to Figures 2A to 2J , the orthographic projection of the gate line hollow 20 on the substrate 1 may cover the entire orthographic projection of the connecting portion 43 on the substrate 1. In another possible embodiment, the orthographic projection of the gate line hollow 20 on the substrate 1 may also cover only the portion of the orthographic projection of the connecting portion 43 on the substrate 1.

[0201] In one possible embodiment, as shown in Figures 2A to 2J , the array substrate may be provided with only one fourth transistor T4 at each pixel electrode 4. The fourth transistor T4 may include: a gate TA, an active pattern 5, a first electrode TB, and a second electrode TC. The gate TA may be reused as the gate line 2, the first electrode TB may be reused as the data line 2, and the second electrode TC may include: a first fourth transistor portion T4C1, a second fourth transistor portion T4C2, and a third fourth transistor portion T4C3, sequentially distributed along a first direction X. The orthographic projection of the third fourth transistor portion T4C3 on the substrate 1 overlaps with the orthographic projection of the connecting portion 43 on the substrate 1. Thus, the connecting portion 43 is electrically connected to the third fourth transistor portion T4C3 via a first insulating layer via 910 penetrating the first insulating layer 91 and a second insulating layer via 920 penetrating the second insulating layer 92, thereby further achieving electrical connection between the pixel electrode 4 and the fourth transistor T4.

[0202] In one possible embodiment, referring to Figures 1A-1H and 2A-2J, the first pixel electrode 41 includes: a first sub-electrode portion P1 distributed along the second direction Y, and a second sub-electrode portion P2, wherein the first sub-electrode portion P1 extends in a direction different from that of the second sub-electrode portion P2; the second pixel electrode 42 includes: a third sub-electrode portion P3 distributed along the second direction Y, and a fourth sub-electrode portion P4, wherein the third sub-electrode portion P3 extends in a direction different from that of the fourth sub-electrode portion P4. In this way, the pixel electrode 4 matches the bend shape of the data line 3, and the fringe electric field of the pixel electrode 4 and the internal electric field of the pixel electrode 4 are aligned in the same direction, thereby reducing or eliminating liquid crystal disorder, improving dark fringes on the edge of the pixel electrode 4, and improving the left-right viewing angle color deviation of the display panel.

[0203] In a possible embodiment, the first pixel electrode 41 is an integrated structure, and the second pixel electrode 42 is an integrated structure, as shown in Figure 2I, the first pixel electrode 41 may include: a first sub-electrode portion P1 distributed along the second direction Y, and a second sub-electrode portion P2, and the second pixel electrode 42 may include: a third sub-electrode portion P3 distributed along the second direction Y, and a fourth sub-electrode portion P4; when the first pixel electrode 41 further includes: a first sub-pixel electrode 411 and a second sub-pixel electrode 412 distributed in sequence along the first direction X; and the second pixel electrode 42 further includes: a third sub-pixel electrode 421 and a fourth sub-pixel electrode 422 distributed in sequence along the first direction X, the first sub-pixel electrode 411 and the second sub-pixel electrode 412 may both include: a first sub-electrode portion P1 distributed along the second direction Y, and a second sub-electrode portion P2; and the third sub-pixel electrode 421 and the fourth sub-pixel electrode 422 may both include: a third sub-electrode portion P3 distributed along the second direction Y, and a fourth sub-electrode portion P4.

[0204] In one possible embodiment, referring to Figures 1A-1H , the extension direction of the first sub-electrode portion P1 is the same as the extension direction of the fourth sub-electrode portion P4; the extension direction of the second sub-electrode portion P2 is the same as the extension direction of the third sub-electrode portion P3. Specifically, for example, referring to Figures 1A-1H , the angle formed between the extension direction of the first sub-electrode portion P1 and the first direction X can be 40° to 50°, for example, 45°; the angle formed between the extension direction of the second sub-electrode portion P2 and the first direction X can be 130° to 140°, for example, 135°; the angle formed between the extension direction of the third sub-electrode portion P3 and the first direction X can be 130° to 140°, for example, 135°; and the angle formed between the extension direction of the fourth sub-electrode portion P4 and the first direction X can be 40° to 50°, for example, 45°.

[0205] In one possible embodiment, referring to Figures 2A to 2J , the extension direction of the first sub-electrode portion P1 is the same as the extension direction of the third sub-electrode portion P3; the extension direction of the second sub-electrode portion P2 is the same as the extension direction of the fourth sub-electrode portion P4. Specifically, for example, referring to Figures 1A to 1H , the angle formed between the extension direction of the first sub-electrode portion P1 and the first direction X can be 40° to 50°, for example, 45°; the angle formed between the extension direction of the second sub-electrode portion P2 and the first direction X can be 130° to 140°, for example, 135°; the angle formed between the extension direction of the third sub-electrode portion P3 and the first direction X can be 40° to 50°, for example, 45°; and the angle formed between the extension direction of the fourth sub-electrode portion P4 and the first direction X can be 130° to 140°, for example, 135°.

[0206] In one possible embodiment, as shown in Figures 1A-1H and 2A-2J, the slits F in the first sub-electrode portion P1 extend in the same direction as the first sub-electrode portion P1; the slits F in the second sub-electrode portion P2 extend in the same direction as the second sub-electrode portion P2; the slits F in the third sub-electrode portion P3 extend in the same direction as the third sub-electrode portion P3; and the slits F in the fourth sub-electrode portion P4 extend in the same direction as the fourth sub-electrode portion P4. This ensures that the fringe electric field of the pixel electrode 4 and the internal electric field of the pixel electrode 4 are aligned in the same direction, reducing or eliminating liquid crystal turbulence, improving dark fringes on the edge of the pixel electrode 4, and improving left-right viewing angle color deviation of the display panel.

[0207] In one possible embodiment, the length of the slit F in the direction perpendicular to the extension direction may be 2 μm to 4 μm. Specifically, the length of the slit F in the direction perpendicular to the extension direction may be 3 μm. In the embodiment of the present disclosure, in the array substrate provided based on the embodiment of the present disclosure, when the length of the slit F in the direction perpendicular to the extension direction is reduced to 3 μm, the dark lines almost disappear.

[0208] 1A to 1H , the angle formed by the extension direction of the slit F of the first sub-electrode portion P1 and the first direction X may be 40° to 50°, for example, 45°; the angle formed by the extension direction of the slit F of the second sub-electrode portion P2 and the first direction X may be 130° to 140°, for example, 135°; the angle formed by the extension direction of the slit F of the third sub-electrode portion P3 and the first direction X may be 130° to 140°, for example, 135°; the angle formed by the extension direction of the slit F of the fourth sub-electrode portion P4 and the first direction X may be 40° to 50°, for example, 45°.

[0209] Specifically, the angle formed by the liquid crystal alignment direction in the area where the first sub-electrode portion P1 is located and the first direction X can be 220° to 230°, for example, 225°; the angle formed by the liquid crystal alignment direction in the area where the second sub-electrode portion P2 is located and the first direction X can be 130° to 140°, for example, 135°; the angle formed by the liquid crystal alignment direction in the area where the third sub-electrode portion P3 is located and the first direction X can be 310° to 320°, for example, 315°; and the angle formed by the liquid crystal alignment direction in the area where the fourth sub-electrode portion P4 is located and the first direction X can be 40° to 50°, for example, 45°. By achieving four alignment directions in the area where a pixel electrode 4 is located, and combining them with the divided bright and dark areas, an alignment mode of eight domains in a sub-pixel can be formed when using the Super UV Photo Alignment (SUVA) technology.

[0210] In one possible embodiment, as shown in Figures 1A-1H and 2A-2J, the data line 3 includes: a first data portion 31 located on one side of the first sub-electrode portion P1 and extending in the same direction as the first sub-electrode P1; a second data portion 32 located on one side of the second sub-electrode portion P2 and extending in the same direction as the second sub-electrode P2; a third data portion 33 located on one side of the third sub-electrode portion P3 and extending in the same direction as the third sub-electrode P3; and a fourth data portion 34 located on one side of the fourth sub-electrode portion P4 and extending in the same direction as the fourth sub-electrode P4. In this way, the bend shape of the data line 3 is consistent with the bend shape of the pixel electrode 4, aligning the fringe electric field of the pixel electrode 4 with the internal electric field of the pixel electrode 4. This reduces or eliminates liquid crystal turbulence, improves dark fringes on the edge of the pixel electrode 4, and improves left-right viewing angle color deviation of the display panel.

[0211] In one possible implementation, referring to Figures 1A-1H and 2A-2J, the data line 3 further includes a fifth data portion 35 extending along the second direction Y and connecting the second data portion 32 and the third data portion 33. This design matches the gate line 2 passing through the center of the pixel electrode 4, facilitating the placement of a transistor in the region where the fifth data portion 35 is located.

[0212] In one possible embodiment, as shown in Figures 3A-3J , the first pixel electrode 41 and the second pixel electrode 42 both extend along a third direction Z; and the outer edge of the first pixel electrode 41 along the extension direction does not overlap with the outer edge of the second pixel electrode 42 along the extension direction. In the disclosed embodiment, the pixel electrode 4 only includes the first pixel electrode 41 and the second pixel electrode 42, both of which extend along the third direction Z. This simplifies the fabrication of the pixel electrode 4 and reduces the risk of short circuit defects on the array substrate due to the complex pattern of the pixel electrode 4.

[0213] In a possible implementation manner, the angle formed by the third direction Z and the first direction X is 0° to 90°; in a possible implementation manner, the angle formed by the third direction Z and the first direction X is 40° to 50°, for example, 45°.

[0214] In one possible embodiment, as shown in Figures 3A-3J , the data line 3 includes a sixth data portion 36 located on one side of the first pixel electrode 41 and a seventh data portion 37 located on one side of the second pixel electrode 42. The sixth data portion 36 extends in the same direction as the seventh data portion 37, and the extension line of the sixth data portion 36 does not overlap with the extension line of the seventh data portion 37. This ensures that the bend shape of the data line 3 aligns with the bend shape of the pixel electrode 4, aligning the directions of the fringe electric field of the pixel electrode 4 and the internal electric field of the pixel electrode 4. This reduces or eliminates liquid crystal turbulence, improves dark fringes on the edge of the pixel electrode 4, and improves color shift in the left-right viewing angle of the display panel.

[0215] In one possible implementation, as shown in Figures 3A to 3J , the data line 3 further includes an eighth data portion 38 extending along the second direction Y and connecting the sixth data portion 36 and the seventh data portion 37. This design matches the gate line 2 passing through the center of the pixel electrode 4, facilitating the placement of a transistor in the region where the eighth data portion 38 is located.

[0216] In one possible embodiment, as shown in Figures 3A-3J , the array substrate may be provided with only one fourth transistor T4 at each pixel electrode 4. The fourth transistor T4 may include: a gate TA, an active pattern 5, a first electrode TB, and a second electrode TC. The gate TA may be reused as the gate line 2, the first electrode TB may be reused as the data line 2, and the second electrode TC may include: a first fourth transistor portion T4C1, a second fourth transistor portion T4C2, and a third fourth transistor portion T4C3, sequentially distributed along the first direction X. The orthographic projection of the third fourth transistor portion T4C3 on the substrate 1 overlaps with the orthographic projection of the connecting portion 43 on the substrate 1. Thus, the connecting portion 43 is electrically connected to the third fourth transistor portion T4C3 via a first insulating layer via 910 penetrating the first insulating layer 91 and a second insulating layer via 920 penetrating the second insulating layer 92, thereby further achieving electrical connection between the pixel electrode 4 and the fourth transistor T4.

[0217] In a possible embodiment, referring to Figures 2A to 2J and Figures 3A to 3J, the first conductive layer 7 further includes a conductive layer hollow 70, and the non-hollow portion of the first conductive layer 7 includes a block electrode, a block electrode and a pixel electrode area portion, and the orthographic projection of the conductive layer hollow 70 on the substrate 1 has an overlapping area with the orthographic projection of the connecting portion 43 on the substrate 1. In this way, the connecting portion 43 is also electrically connected to the second portion T5C2 of the fifth transistor through the conductive layer hollow 70, thereby further realizing the electrical connection between the pixel electrode 4 and the fifth transistor T5.

[0218] In one possible implementation, referring to Figures 4A-4J and 5A-5J , the orthographic projection of the gate line 2 on the substrate 1 is located on one side of the orthographic projection of the pixel electrode 4 on the substrate 1. That is, in the embodiment of the present disclosure, the gate line 2 may not pass through the central area of ​​the pixel electrode 4, but may be located on one side of the pixel electrode 4.

[0219] In one possible implementation, referring to Figures 2A-2J, 3A-3J, 4A-4J, and 5A-5J, the array substrate further includes a first conductive layer 7 located on the side of the pixel electrode 4 facing the substrate 1. In the disclosed embodiment, for a display panel in a VA display mode in which the array substrate is provided with a pixel electrode layer and the opposing substrate is provided with a common electrode layer, the first conductive layer 7 is further provided on the side of the pixel electrode 4 facing the substrate 1. In addition to the vertical electric field formed by the pixel electrode and the common electrode within the array substrate, a lateral electric field is formed between the pixel electrode 4 and the first conductive layer 7. This can increase the deflection direction of the liquid crystal and improve the color shift problem of the display panel.

[0220] In a possible embodiment, for the array substrate structure shown in Figure 1A, a first conductive layer 7 can also be set between the layer where the data line 3 is located and the layer where the pixel electrode 4 is located, so that in addition to the vertical electric field formed by the pixel electrode and the common electrode in the array substrate, the pixel electrode 4 and the first conductive layer 7 will form a transverse electric field, thereby increasing the deflection direction of the liquid crystal and improving the color deviation problem of the display panel.

[0221] Specifically, the first conductive layer 7 can be located between the substrate 1 and the layer where the pixel electrode 4 is located. Specifically, the first conductive layer 7 can be loaded with the same signal as the common electrode layer of the opposite substrate. The first conductive layer 7 can be a transparent electrode layer, and the material of the first conductive layer 7 can be indium tin oxide.

[0222] In one possible embodiment, referring to Figures 4A-4J and 5A-5J, a fifth common trace 25 is provided on the same layer as the gate line 2; the first conductive layer 7 is electrically connected to the fifth common trace 25 via a via KD. In the disclosed embodiment, since the first conductive layer 7 is a large-area sheet structure and the material of the first conductive layer 7 is typically a metal oxide (e.g., indium tin oxide), while the material of the fifth common trace 25 is typically a metal with better conductivity than metal oxide, electrically connecting the first conductive layer 7 to the fifth common trace 25 can reduce the resistance of the first conductive layer 7.

[0223] In a possible embodiment, referring to Figures 2A-2J, 3A-3J, 4A-4J, and 5A-5J, the data line 3 may be located on the side of the gate line 2 facing away from the substrate 1, the first conductive layer 7 may be located on the side of the data line 3 facing away from the gate line 2, the pixel electrode 4 may be located on the side of the first conductive layer 7 facing away from the data line 3, a gate insulating layer may be provided between the layer where the gate line 2 is located and the layer where the data line 3 is located, an active layer may be provided between the gate insulating layer and the data line 3 (the active layer may include an active pattern 6, and the active layer material may be amorphous silicon, low-temperature polycrystalline silicon, metal oxide, or other materials, which are not limited here), a first insulating layer 91 may be provided between the data line 3 and the first conductive layer 7, and a second insulating layer 92 may be provided between the first conductive layer 7 and the pixel electrode 4.

[0224] In one possible embodiment, the via KD may penetrate each film layer between the fifth common trace 25 and the first conductive layer 7 to electrically connect the first conductive layer 7 to the fifth common trace 25. In one possible embodiment, the via KD may penetrate the gate insulating layer, the first insulating layer 91, and the second insulating layer 92.

[0225] In one possible embodiment, as shown in Figures 4A-4J and 5A-5J, the fifth common trace 25 has a first common protrusion 251 on the side facing the gate line 2; at least a portion of the orthographic projection of the first common protrusion 251 on the substrate 1 overlaps at least a portion of the orthographic projection of the via KD on the substrate. In the disclosed embodiment, the fifth common trace 25 has the first common protrusion 251 on the side facing the gate line 2 so that the fifth common trace 25 has sufficient area to achieve electrical connection with the first conductive layer 7 through the via KD.

[0226] In a possible implementation, referring to FIG. 4C and FIG. 5C , a length d1 of the first common protrusion 251 in the second direction Y is greater than a length d2 of the fifth common trace 25 in the second direction Y.

[0227] In one possible embodiment, as shown in FIG4C and FIG5C , the gate line 2 has a first recess 201 on the side facing the fifth common line 25, which is opposite to the first common protrusion 251. This matches the design of the first common protrusion 251 on the fifth common line 25, thereby preventing the first common protrusion 251 from contacting the gate line 2.

[0228] In one possible embodiment, as shown in FIG. 4C and FIG. 5C , a fifth overlapping portion PD5 is provided on one side of the pixel electrode 4; a second notch 202 is provided on the side of the gate line 2 facing the fifth common trace 25; and the orthographic projection of the second notch 202 on the substrate 1 covers the orthographic projection of the fifth overlapping portion PD5 on the substrate 1. This prevents the gate line 2 and the fifth overlapping portion PD5 from overlapping, thereby preventing the generation of coupling capacitance between the two, which would increase the load on the gate line 2 and affect signal transmission on the gate line 2.

[0229] In one possible embodiment, referring to FIG. 4C and FIG. 5C , the array substrate may be provided with only one fifth transistor T5 at each pixel electrode 4. The fifth transistor T5 may include: a gate TA, an active pattern 5, a first electrode TB, and a second electrode TC; wherein the second electrode TC may include: a first portion T5C1 of the fifth transistor and a second portion T5C2 of the fifth transistor distributed in sequence along the first direction X. The orthographic projection of the second portion T5C2 of the fifth transistor on the substrate 1 overlaps with the orthographic projection of the fifth overlapping portion PD5 on the substrate 1. In this way, the fifth overlapping portion PD5 is electrically connected to the second portion T5C2 of the fifth transistor via a first insulating layer via 910 penetrating the first insulating layer 91 and a second insulating layer via 920 penetrating the second insulating layer 92, thereby further realizing electrical connection between the pixel electrode 4 and the fifth transistor T5.

[0230] In a possible embodiment, referring to Figures 4A to 4J and Figures 5A to 5J, the first conductive layer 7 further includes a conductive layer hollow 70, and the orthographic projection of the conductive layer hollow 70 on the substrate 1 has an overlapping area with the orthographic projection of the fifth overlapping portion PD5 on the substrate 1. In this way, the fifth overlapping portion PD5 is also electrically connected to the second portion T5C2 of the fifth transistor through the conductive layer hollow 70, thereby further realizing the electrical connection between the pixel electrode 4 and the fifth transistor T5.

[0231] In one possible embodiment, as shown in Figures 4A-4J , the pixel electrode 4 includes: a first sub-electrode portion P1, a second sub-electrode portion P2, a third sub-electrode portion P3, and a fourth sub-electrode portion P4, sequentially distributed along the second direction Y; the first sub-electrode portion P1 extends in a direction different from that of the second sub-electrode portion P2; and the third sub-electrode portion extends in a direction different from that of the fourth sub-electrode portion. This allows the pixel electrode 4 to match the bend of the data line 3, aligning the fringe electric field of the pixel electrode 4 with the internal electric field of the pixel electrode 4, reducing or eliminating liquid crystal turbulence, improving dark fringes on the edges of the pixel electrode 4, and improving left-right viewing angle color deviation of the display panel.

[0232] In one possible embodiment, referring to Figures 4A to 4J , the extension direction of the first sub-electrode portion is the same as the extension direction of the fourth sub-electrode portion P3; the extension direction of the second sub-electrode portion P4 is the same as the extension direction of the third sub-electrode portion P3. Specifically, for example, referring to Figures 4A to 4J , the angle formed by the extension direction of the first sub-electrode portion P1 and the first direction X can be 40° to 50°, for example, 45°; the angle formed by the extension direction of the second sub-electrode portion P2 and the first direction X can be 130° to 140°, for example, 135°; the angle formed by the extension direction of the third sub-electrode portion P3 and the first direction X can be 40° to 50°, for example, 45°; and the angle formed by the extension direction of the fourth sub-electrode portion P4 and the first direction X can be 130° to 140°, for example, 135°.

[0233] As shown in Figures 4A-4J , the slits F in the first sub-electrode section P1 extend in the same direction as the first sub-electrode section P1; the slits F in the second sub-electrode section P2 extend in the same direction as the second sub-electrode section P2; the slits F in the third sub-electrode section P3 extend in the same direction as the third sub-electrode section P3; and the slits F in the fourth sub-electrode section P4 extend in the same direction as the fourth sub-electrode section P4. This aligns the fringe electric field of pixel electrode 4 with the internal electric field of pixel electrode 4, reducing or eliminating liquid crystal turbulence, improving dark fringes on the edge of pixel electrode 4, and improving left-right viewing angle color shift in the display panel.

[0234] In one possible embodiment, the length of the slit F in the direction perpendicular to the extension direction may be 2 μm to 4 μm. Specifically, the length of the slit F in the direction perpendicular to the extension direction may be 3 μm. In the embodiment of the present disclosure, in the array substrate provided based on the embodiment of the present disclosure, when the length of the slit F in the direction perpendicular to the extension direction is reduced to 3 μm, the dark lines almost disappear.

[0235] Specifically, referring to Figures 4A to 4J, the angle formed by the extension direction of the slit F of the first sub-electrode portion P1 and the first direction X can be 40° to 50°, for example, 45°; the angle formed by the extension direction of the slit F of the second sub-electrode portion P2 and the first direction X can be 130° to 140°, for example, 135°; the angle formed by the extension direction of the slit F of the third sub-electrode portion P3 and the first direction X can be 40° to 50°, for example, 45°; the angle formed by the extension direction of the slit F of the fourth sub-electrode portion P4 and the first direction X can be 130° to 140°, for example, 135°.

[0236] In one possible embodiment, as shown in Figures 4A-4J , the data line 3 includes: a first data portion 31 located on one side of the first sub-electrode portion P1 and extending in the same direction as the first sub-electrode portion; a second data portion 32 located on one side of the second sub-electrode portion P2 and extending in the same direction as the second sub-electrode portion P2; a third data portion 33 located on one side of the third sub-electrode portion P3 and extending in the same direction as the third sub-electrode portion P3; and a fourth data portion 34 located on one side of the fourth sub-electrode portion P4 and extending in the same direction as the fourth sub-electrode portion P4; the second data portion 32 is directly connected to the third data portion 33. In this way, the bending shape of the data line 3 is consistent with the bending shape of the pixel electrode 4, aligning the directions of the fringe electric field of the pixel electrode 4 and the internal electric field of the pixel electrode 4. This reduces or eliminates liquid crystal turbulence, improves dark fringes on the edge of the pixel electrode 4, and improves left-right viewing angle color deviation of the display panel.

[0237] In one possible embodiment, as shown in Figures 5A-5J , the pixel electrode 4 includes: a fifth sub-electrode portion P5, a sixth sub-electrode portion P6, and a seventh sub-electrode portion P7, sequentially distributed along the second direction Y; the fifth sub-electrode portion P5 extends in the same direction as the seventh sub-electrode portion P7; the sixth sub-electrode portion P6 extends in a different direction than the fifth sub-electrode portion P5; the extension length b1 of the sixth sub-electrode portion P6 is greater than the extension length b2 of the fifth sub-electrode portion P5 and greater than the extension length b3 of the seventh sub-electrode portion P7. The extension length b2 of the fifth sub-electrode portion P5 can be equal to the extension length b3 of the seventh sub-electrode portion P7. In one possible embodiment, the extension length b1 of the sixth sub-electrode portion P6 can be 1.5 to 3 times the extension length b2 of the fifth sub-electrode portion P5; in another possible embodiment, the extension length b1 of the sixth sub-electrode portion P6 can be twice the extension length b2 of the fifth sub-electrode portion P5.

[0238] In a possible embodiment, referring to Figures 5A to 5J, the angle formed by the extension direction of the fifth sub-electrode portion P5 and the first direction X may be 40° to 50°, for example, 45°; the angle formed by the extension direction of the sixth sub-electrode portion P6 and the first direction X may be 130° to 140°, for example, 135°; the angle formed by the extension direction of the seventh sub-electrode portion P7 and the first direction X may be 40° to 50°, for example, 45°.

[0239] As shown in Figures 5A-5J , the slits F in the fifth sub-electrode section P5 extend in the same direction as the fifth sub-electrode section P5; the slits F in the sixth sub-electrode section P6 extend in the same direction as the sixth sub-electrode section P6; and the slits F in the seventh sub-electrode section P7 extend in the same direction as the seventh sub-electrode section P7. This aligns the fringe electric field of pixel electrode 4 with the internal electric field of pixel electrode 4, reducing or eliminating liquid crystal turbulence, improving dark fringes on the edges of pixel electrode 4, and improving left-right viewing angle color shift in the display panel.

[0240] In one possible embodiment, the length of the slit F in the direction perpendicular to the extension direction may be 2 μm to 4 μm. Specifically, the length of the slit F in the direction perpendicular to the extension direction may be 3 μm. In the embodiment of the present disclosure, in the array substrate provided based on the embodiment of the present disclosure, when the length of the slit F in the direction perpendicular to the extension direction is reduced to 3 μm, the dark lines almost disappear.

[0241] Specifically, referring to Figures 5A to 5J, the angle formed by the extension direction of the slit F of the fifth sub-electrode portion P5 and the first direction X can be 40° to 50°, for example, it can be 45°; the angle formed by the extension direction of the slit F of the sixth sub-electrode portion P6 and the first direction X can be 130° to 140°, for example, it can be 135°; the angle formed by the extension direction of the slit F of the seventh sub-electrode portion P7 and the first direction X can be 40° to 50°, for example, it can be 45°.

[0242] In one possible embodiment, as shown in Figures 5A to 5J, the data line includes: a ninth data portion 39 located on one side of the fifth sub-electrode portion P5 and extending in the same direction as the fifth sub-electrode portion P5; a tenth data portion 310 located on one side of the sixth sub-electrode portion P6 and extending in the same direction as the sixth sub-electrode portion P6; and an eleventh data portion 311 located on one side of the seventh sub-electrode portion P7 and extending in the same direction as the seventh sub-electrode portion P7. In this way, the bending shape of the data line 3 is consistent with the bending shape of the pixel electrode 4, so that the fringe electric field of the pixel electrode 4 and the internal electric field of the pixel electrode 4 are in the same direction, reducing or eliminating liquid crystal disorder, improving the dark lines on the edge of the pixel electrode 4, and improving the left-right viewing angle color deviation of the display panel.

[0243] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes an array substrate as provided in the embodiment of the present disclosure, and also includes an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate includes a common electrode layer.

[0244] In one possible embodiment, as shown in conjunction with Figures 1H, 2J, 3J, 4J, and 5J, the display panel may further be provided with a black matrix 8, and the orthographic projection of the black matrix 8 on the substrate 1 may cover the orthographic projection of the gate line 2 on the substrate 1, and cover the orthographic projection of the data line 3 on the substrate 1. Specifically, the opposing substrate may include an opposing substrate 90, and the black matrix 8 may be located between the opposing substrate 90 and the common electrode layer (not shown in Figure 10).

[0245] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0246] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0247] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0248] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, in, include: substrate; A plurality of gate lines are located on one side of the substrate, and the plurality of gate lines extend along a first direction; A plurality of data lines, wherein the main body direction of the plurality of data lines extends along the second direction, and the orthographic projection of the data lines on the substrate is a bent shape; A plurality of pixel electrodes, wherein the orthographic projections of the pixel electrodes on the substrate are located between the orthographic projections of adjacent data lines on the substrate; The pixel electrode comprises a plurality of slits, and an extending direction of the slits in an orthographic projection of the substrate is consistent with an extending direction of an orthographic projection of an adjacent data line on the substrate.

2. The array substrate according to claim 1, in, The orthographic projection of the gate line on the substrate passes through the central area of ​​the orthographic projection of the pixel electrode on the substrate; The pixel electrode has a first gap in the area where the gate line is located; the pixel electrode includes: a first pixel electrode located on one side of the gate line, a second pixel electrode located on the other side of the gate line, and a connecting portion connecting at least part of the first pixel electrode and at least part of the second pixel electrode.

3. The array substrate according to claim 2, in, The array substrate further comprises: a plurality of transistors; the pixel electrodes are electrically connected to the data lines via the plurality of transistors; The first pixel electrode includes: a first sub-pixel electrode and a second sub-pixel electrode distributed along the second direction; the second pixel electrode includes: a third sub-pixel electrode and a fourth sub-pixel electrode distributed along the second direction; wherein the second sub-pixel electrode is located at a side of the first sub-pixel electrode away from the electrically connected data line, and the fourth sub-pixel electrode is located at a side of the third sub-pixel electrode away from the electrically connected data line; One of the first sub-pixel electrode and the second sub-pixel electrode is electrically connected to one of the third sub-pixel electrode and the fourth sub-pixel electrode through the connection portion.

4. The array substrate according to claim 3, in, The first sub-pixel electrode is electrically connected to the fourth sub-pixel electrode through the connecting portion at the layer where the pixel electrode is located; the second sub-pixel electrode and the third sub-pixel electrode are independent of each other at the layer where the pixel electrode is located.

5. The array substrate according to claim 4, in, The array substrate further comprises: a first common wiring located at one side of the gate line and extending along the first direction; the plurality of transistors comprises: a first transistor, a second transistor, and a third transistor; The control electrode of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the connecting portion; The control electrode of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second sub-pixel electrode and the third sub-pixel electrode; The control electrode of the third transistor is electrically connected to the gate line, the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is electrically connected to the first common wiring.

6. The array substrate according to claim 5, in, The second electrode of the first transistor includes: a first transistor first portion extending along the first direction; The array substrate further includes: a first overlapping portion connected to the connecting portion, wherein an orthographic projection of the first overlapping portion on the substrate and an orthographic projection of the first portion of the first transistor on the substrate have an overlapping area.

7. The array substrate according to claim 5 or 6, in, The connecting portion includes: a first connecting portion extending along the first direction, a second connecting portion, and a third connecting portion extending along the second direction; One end of the first connection portion is electrically connected to the first sub-pixel electrode, the other end of the first connection portion is electrically connected to one end of the third connection portion; the other end of the third connection portion is electrically connected to one end of the second connection portion; the other end of the second connection portion is electrically connected to the fourth sub-pixel electrode; The first overlapping portion is electrically connected to the first connecting portion and is away from a side of the first sub-pixel electrode to which it is connected.

8. The array substrate according to claim 7, in, A second gap is formed between the first connecting portion and the first sub-pixel electrode connected thereto, and a third gap is formed between the second connecting portion and the fourth sub-pixel electrode electrically connected thereto.

9. The array substrate according to claim 7 or 8, in, A length of the first overlapping portion in the second direction is greater than a length of the first connecting portion in the second direction.

10. The array substrate according to any one of claims 5 to 9, in, The second electrode of the second transistor includes: a second transistor first portion extending along the first direction, and a second transistor second portion extending from the second transistor first portion along the second direction; The array substrate further includes: a first transition portion extending along the first direction, a second transition portion extending along the second direction, and a second overlap portion; one end of the first transition portion is electrically connected to the second sub-pixel electrode, and the other end is electrically connected to one end of the second transition portion; the other end of the second transition portion is electrically connected to the second overlap portion; the orthographic projection of the second transistor second portion on the substrate has an overlapping area with the orthographic projection of the second overlap portion on the substrate; The array substrate also includes: a third transition portion along the first direction and a third overlap portion; one end of the third transition portion is electrically connected to the third sub-pixel electrode, and the other end is electrically connected to the third overlap portion; the orthographic projection of the first part of the second transistor on the substrate has an overlapping area with the orthographic projection of the third overlap portion on the substrate.

11. The array substrate according to claim 10, in, A fourth gap is formed between the first transition portion and the second sub-pixel electrode, and a fifth gap is formed between the third transition portion and the third sub-pixel electrode.

12. The array substrate according to claim 10 or 11, in, The length of the second overlapping portion in the first direction is greater than the length of the second transition portion in the first direction; A length of the third overlapping portion in the second direction is greater than a length of the third transition portion in the second direction.

13. The array substrate according to any one of claims 5 to 12, in, The second electrode of the third transistor includes: a third transistor first portion extending along the second direction, and a third transistor second portion extending from the third transistor first portion along the first direction; The array substrate further includes: a fourth bridging portion; the first common wiring includes: a first common wiring main portion, and a first common bridging portion connected to one side of the first common wiring main portion; The orthographic projection of the second portion of the third transistor on the substrate has an overlapping area with the orthographic projection of the fourth overlapping portion on the substrate; the orthographic projection of the first common overlapping portion on the substrate has an overlapping area with the orthographic projection of the fourth overlapping portion on the substrate.

14. The array substrate according to claim 13, in, The fourth overlap portion has a fourth overlap portion outer edge along the first direction, and the second overlap portion has a second overlap portion outer edge extending along the first direction; An extension line of the outer edge of the fourth overlapping portion coincides with an extension line of the outer edge of the second overlapping portion.

15. The array substrate according to any one of claims 6 to 14, in, The first overlapping portion has a first overlapping portion outer edge extending along the second direction, and the third overlapping portion has a third overlapping portion outer edge extending along the second direction; An extension line of the outer edge of the first overlapping portion coincides with an extension line of the outer edge of the third overlapping portion.

16. The array substrate according to any one of claims 5 to 15, in, The array substrate further comprises: a second common routing line group electrically connected to the first common routing line and extending to a side away from the gate line, the second common routing line group comprising: two second common routing lines; the orthographic projection of the data line on the substrate and the gap between the two second common routing lines of the same second common routing line group have an overlapping area on the orthographic projection of the substrate; The shape of the orthographic projection of the second common line on the substrate is a bend, and the bend shape of the orthographic projection of the second common line on the substrate is consistent with the bend shape of the orthographic projection of the data line on the substrate.

17. The array substrate according to any one of claims 5 to 16, in, The array substrate further includes: a third common wiring located at the other side of the gate line and extending along the first direction, and a fourth common wiring group connected to the third common wiring and extending away from the gate line; The third common routing line is disconnected at a position where it crosses the data line; the fourth common routing line group includes: two fourth common routing lines; the orthographic projection of the data line on the substrate and the gap between the two fourth common routing lines of the same fourth common routing line group have an overlapping area on the orthographic projection of the substrate; The shape of the orthographic projection of the fourth common line on the substrate is a bend, and the bend shape of the orthographic projection of the fourth common line on the substrate is consistent with the bend shape of the orthographic projection of the data line on the substrate.

18. The array substrate according to claim 2, in, The first pixel electrode is an integrated structure, and the second pixel electrode is an integrated structure.

19. The array substrate according to claim 18, in, One end of the first pixel electrode away from the gate line is an opening; and one end of the second pixel electrode away from the gate line is an opening.

20. The array substrate according to claim 18 or 19, in, The connection portion has an orthographic projection shape on the substrate that is a rectangle.

21. The array substrate according to any one of claims 18 to 20, in, The gate line has a gate line hollowing, and the gate line hollowing has an orthographic projection on the substrate, covering at least a portion of the orthographic projection of the connecting portion on the substrate.

22. The array substrate according to any one of claims 2 to 21, in, The first pixel electrode comprises: a first sub-electrode portion distributed along the second direction, and a second sub-electrode portion, wherein an extension direction of the first sub-electrode portion is different from an extension direction of the second sub-electrode portion; The second pixel electrode includes: a third sub-electrode portion distributed along the second direction, and a fourth sub-electrode portion; an extension direction of the third sub-electrode portion is different from an extension direction of the fourth sub-electrode portion.

23. The array substrate according to claim 22, in, An extending direction of the first sub-electrode portion is the same as an extending direction of the fourth sub-electrode portion; and an extending direction of the second sub-electrode portion is the same as an extending direction of the third sub-electrode portion.

24. The array substrate according to claim 22, in, An extending direction of the first sub-electrode portion is the same as an extending direction of the third sub-electrode portion; and an extending direction of the second sub-electrode portion is the same as an extending direction of the fourth sub-electrode portion.

25. The array substrate according to any one of claims 22 to 24, in, An extending direction of the slit in the first sub-electrode portion is the same as an extending direction of the first sub-electrode portion; An extending direction of the slit in the second sub-electrode portion is the same as an extending direction of the second sub-electrode portion; An extending direction of the slit in the third sub-electrode portion is the same as an extending direction of the third sub-electrode portion; An extending direction of the slit in the fourth sub-electrode portion is the same as an extending direction of the fourth sub-electrode portion.

26. The array substrate according to any one of claims 22 to 25, in, The data line includes: a first data portion located on one side of the first sub-electrode portion and extending in the same direction as the first sub-electrode, a second data portion located on one side of the second sub-electrode portion and extending in the same direction as the second sub-electrode, a third data portion located on one side of the third sub-electrode portion and extending in the same direction as the third sub-electrode, and a fourth data portion located on one side of the fourth sub-electrode portion and extending in the same direction as the fourth sub-electrode.

27. The array substrate according to claim 26, in, The data line further includes a fifth data portion extending along the second direction and connecting the second data portion and the third data portion.

28. The array substrate according to any one of claims 18 to 21, in, The first pixel electrode and the second pixel electrode both extend along a third direction; and an outer edge of the first pixel electrode along the extending direction does not overlap with an outer edge of the second pixel electrode along the extending direction.

29. The array substrate according to claim 28, in, The data line includes: a sixth data portion located at one side of the first pixel electrode, and a seventh data portion located at one side of the second pixel electrode; An extension direction of the sixth data portion is the same as an extension direction of the seventh data portion; and an extension line of the sixth data portion does not overlap with an extension line of the seventh data portion.

30. The array substrate according to claim 29, in, The data line further includes an eighth data portion extending along the second direction and connecting the sixth data portion and the seventh data portion.

31. The array substrate according to claim 1, in, The orthographic projection of the gate line on the substrate is located on one side of the orthographic projection of the pixel electrode on the substrate.

32. The array substrate according to claim 31, in, The array substrate further includes: a first conductive layer located on the side of the pixel electrode facing the substrate, and a fifth common wiring in the same layer as the gate line; the first conductive layer is electrically connected to the fifth common wiring through a via hole.

33. The array substrate according to claim 32, in, The fifth common wiring has a first common protrusion on a side facing the gate line; at least a portion of the first common protrusion in the orthographic projection of the substrate overlaps with at least a portion of the via in the orthographic projection of the substrate.

34. The array substrate according to claim 33, in, The gate line has a first recess on a side facing the fifth common wiring, which is opposite to the first common protrusion.

35. The array substrate according to claim 34, in, One side of the pixel electrode has a fifth overlapping portion; The gate line has the second notch on a side facing the fifth common wiring; the orthographic projection of the second notch on the substrate covers the orthographic projection of the fifth overlapping portion on the substrate.

36. The array substrate according to any one of claims 31 to 35, in, The pixel electrode comprises: a first sub-electrode portion, a second sub-electrode portion, a third sub-electrode portion, and a fourth sub-electrode portion sequentially distributed along the second direction; An extending direction of the first sub-electrode portion is different from an extending direction of the second sub-electrode portion; and an extending direction of the third sub-electrode portion is different from an extending direction of the fourth sub-electrode portion.

37. The array substrate according to claim 36, in, An extending direction of the first sub-electrode portion is the same as an extending direction of the fourth sub-electrode portion; and an extending direction of the second sub-electrode portion is the same as an extending direction of the third sub-electrode portion.

38. The array substrate according to claim 36 or 37, in, The data line includes: a first data portion located at one side of the first sub-electrode portion and extending in the same direction as the first sub-electrode portion, a second data portion located at one side of the second sub-electrode portion and extending in the same direction as the second sub-electrode portion, a third data portion located at one side of the third sub-electrode portion and extending in the same direction as the third sub-electrode portion, and a fourth data portion located at one side of the fourth sub-electrode portion and extending in the same direction as the fourth sub-electrode portion; the second data portion is directly connected to the third data portion.

39. The array substrate according to any one of claims 31 to 35, in, The pixel electrode comprises: a fifth sub-electrode portion, a sixth sub-electrode portion, and a seventh sub-electrode portion sequentially distributed along the second direction; an extending direction of the fifth sub-electrode portion is the same as an extending direction of the seventh sub-electrode portion; an extending direction of the sixth sub-electrode portion is different from an extending direction of the fifth sub-electrode portion; An extension length of the sixth sub-electrode portion is greater than an extension length of the fifth sub-electrode portion, and greater than an extension length of the seventh sub-electrode portion.

40. The array substrate according to claim 39, in, The data line includes: a ninth data portion located at one side of the fifth sub-electrode portion and extending in the same direction as the fifth sub-electrode portion, a tenth data portion located at one side of the sixth sub-electrode portion and extending in the same direction as the sixth sub-electrode portion, and an eleventh data portion located at one side of the seventh sub-electrode portion and extending in the same direction as the seventh sub-electrode portion.

41. A display panel, in, It comprises the array substrate as described in any one of claims 1 to 40, and also comprises an opposite substrate arranged opposite to the array substrate, wherein the opposite substrate comprises a common electrode layer.

42. A display device, in, Comprising a display panel as claimed in claim 41.

Images