Display panel and manufacturing method therefor, and display device

Abstract

The present invention provides a display panel and a manufacturing method therefor, and a display device. The display panel comprises a substrate, a first area and a second area which are located on the substrate, and the display panel further comprises a plurality of pixels. A plurality of first gate lines are comprised in the first area, a plurality of second gate lines are comprised in the second area, and the number of pixels connected to the first gate lines is less than the number of pixels connected to the second gate lines. Each first gate line comprises a first part arranged in an active display area and a second part arranged in a non-display area outside the active display area, and the first part and the second part are electrically connected to each other. The display panel further comprises a compensation structure, the compensation structure comprises a first electrode plate, and the orthographic projection of the first electrode plate on the substrate and the orthographic projection of the second part on the substrate at least partially overlap.

Description

Display panel, manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, to a display panel and a manufacturing method thereof, and a display device including the display panel. Background Art

[0002] With the advancement of science and technology, custom designs for special-shaped displays are becoming increasingly common. In panels with special-shaped display areas, the number of pixels per row is significantly reduced compared to normal areas. This results in significant differences in load between normal and special-shaped areas, or between adjacent pixel rows, which can cause display problems.

[0003] For display screens with special-shaped areas, such as the "bangs" screen, there are fewer pixels in the "bangs" area than in normal areas, and the load difference is large, which will cause display abnormalities.

[0004] Summary of the Invention

[0005] In view of the above problems, the present disclosure provides a display panel, a method for manufacturing the same, and a display device including the display panel.

[0006] An embodiment of the present disclosure provides a display panel, which includes a substrate, and a first area and a second area located on the substrate. The display panel also includes a plurality of pixels, wherein the first area includes a plurality of first gate lines, and the second area includes a plurality of second gate lines, the number of pixels connected by the first gate lines is less than the number of pixels connected by the second gate lines, the first gate line includes a first portion arranged in an effective display area and a second portion arranged in a non-display area outside the effective display area, the first portion and the second portion are electrically connected to each other, and the display panel also includes a compensation structure, the compensation structure including a first electrode plate, the first electrode plate and the orthographic projection of the second portion on the substrate at least partially overlapping.

[0007] According to an embodiment of the present disclosure, the display panel includes a gate line layer, a first insulating layer, a source / drain layer, a second insulating layer, and a conductive layer stacked sequentially, the first portion is disposed in the gate line layer, and the second portion is disposed in the source / drain layer.

[0008] According to an embodiment of the present disclosure, the first gate line also includes a third portion arranged in the conductive layer, the third portion is connected to the first portion arranged in the gate line layer via a through hole passing through the second insulating layer and the first insulating layer, and the third portion is connected to the second portion arranged in the source and drain layer via a through hole passing through the second insulating layer.

[0009] According to an embodiment of the present disclosure, the compensation structure includes a first outer ring electrode arranged in the conductive layer, the first outer ring electrode is arranged in a non-display area outside the effective display area of ​​the display panel, the first electrode plate includes the first outer ring electrode, and the first outer ring electrode and the second part arranged in the source and drain layer have at least partial overlap in their positive projection on the substrate, the first outer ring electrode and the third part arranged in the conductive layer are disconnected from each other, and the first outer ring electrode and the electrode in the conductive layer in the effective display area are disconnected from each other.

[0010] According to an embodiment of the present disclosure, the compensation structure also includes a second outer ring electrode arranged in the gate line layer, the second outer ring electrode is arranged in a non-display area outside the effective display area of ​​the display panel, and the second outer ring electrode and the second part arranged in the source and drain layer at least partially overlap with the positive projection on the substrate, and the second outer ring electrode is connected to the first outer ring electrode via a through hole passing through the second insulating layer and the first insulating layer.

[0011] According to an embodiment of the present disclosure, the compensation structure also includes a first compensation unit arranged in the source and drain layer, and the second part arranged in the source and drain layer is a gate line fan-out line, the first compensation unit is formed between two adjacent gate line fan-out lines and is connected to one of the gate line fan-out lines, and the first outer ring electrode and the first compensation unit arranged in the source and drain layer at least partially overlap in their positive projection on the substrate.

[0012] According to an embodiment of the present disclosure, the compensation structure also includes a third outer ring electrode arranged in the gate line layer, and the third outer ring electrode is arranged in a non-display area outside the effective display area of ​​the display panel. The third outer ring electrode at least partially overlaps with the positive projection of the first compensation unit arranged in the source and drain layer on the substrate, and the third outer ring electrode is connected to the first outer ring electrode via a through hole passing through the second insulating layer and the first insulating layer.

[0013] According to an embodiment of the present disclosure, the first compensation unit and the third outer ring electrode have a mesh shape, and the third outer ring electrode overlaps with an orthographic projection of the first compensation unit on the substrate.

[0014] According to an embodiment of the present disclosure, the display panel further includes a dummy spacer, which is arranged between adjacent second portions and disposed in the gate line layer and / or the source / drain layer.

[0015] According to an embodiment of the present disclosure, the display panel includes a gate line layer, a first insulating layer, a source / drain layer, a second insulating layer, and a conductive layer stacked sequentially, the first gate line and the second gate line are formed in the gate line layer, and the compensation structure includes a second compensation unit, which is formed between two adjacent first gate lines and connected to one of the first gate lines.

[0016] According to an embodiment of the present disclosure, the second compensation unit includes a first sub-compensation unit arranged in the gate line layer, the first sub-compensation unit is connected to the first gate line in the gate line layer, and the first sub-compensation unit at least partially overlaps with the positive projection of the conductive layer on the substrate.

[0017] According to an embodiment of the present disclosure, the first sub-compensation unit includes multiple first sub-compensation units, and the overlapping area between at least one first sub-compensation unit among the multiple first sub-compensation units and the orthographic projection of the conductive layer on the substrate is different from the overlapping area between other first sub-compensation units among the multiple first sub-compensation units and the orthographic projection of the conductive layer on the substrate.

[0018] According to an embodiment of the present disclosure, the second compensation unit further includes a second sub-compensation unit disposed in the source / drain layer, and orthographic projections of the first sub-compensation unit and the second sub-compensation unit on the substrate at least partially overlap.

[0019] According to an embodiment of the present disclosure, the first sub-compensation unit includes a plurality of first sub-compensation units, the second sub-compensation unit includes a plurality of second sub-compensation units, and the overlapping area of ​​the orthographic projections of at least one first sub-compensation unit among the plurality of first sub-compensation units and at least one second sub-compensation unit among the plurality of second sub-compensation units on the substrate is different from the overlapping area of ​​the orthographic projections of other first sub-compensation units among the plurality of first sub-compensation units and other second sub-compensation units among the plurality of second sub-compensation units on the substrate.

[0020] According to an embodiment of the present disclosure, the second sub-compensation unit is connected to the conductive layer via a through-hole passing through the second insulating layer.

[0021] According to an embodiment of the present disclosure, the first sub-compensation unit includes a plurality of first sub-compensation units, and the first gate line includes a plurality of first gate lines, and the number of first sub-compensation units connected to at least one of the plurality of first gate lines is different from the number of first sub-compensation units connected to other first gate lines of the plurality of first gate lines.

[0022] According to an embodiment of the present disclosure, the display panel includes a gate line layer, a first insulating layer, a source / drain layer, a second insulating layer, and a conductive layer stacked in sequence, the first gate line and the second gate line are formed in the gate line layer, and a data line is formed in the source / drain layer, the compensation structure includes a data line extension portion arranged in the source / drain layer, the data line extension portion extends from the data line to a non-display area of ​​the display panel, and at least partially overlaps with the orthographic projection of the second portion arranged in the gate line layer on the substrate.

[0023] According to an embodiment of the present disclosure, the line width of the data line extension portion is greater than the line width of the data line.

[0024] An embodiment of the present disclosure also provides a method for manufacturing a display panel, which is used to manufacture a display panel according to each embodiment of the present disclosure. The method includes: preparing a compensation structure, the compensation structure including a first electrode plate, and the first electrode plate and the orthographic projection of the second part on the substrate at least partially overlap.

[0025] An embodiment of the present disclosure further provides a display device, including the display panel according to each embodiment of the present disclosure.

[0026] According to the display panel of each embodiment of the present disclosure, by providing a compensation structure in the irregular region, the capacitance on each gate line in the irregular region is compensated, so that the load on each gate line in the irregular region is substantially the same as the load on each gate line in the normal region. While ensuring the display effect, the display panel's display space is saved, the display panel's border is narrow, and the display panel can also have a high screen-to-body ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed exemplary embodiments with reference to the accompanying drawings, in which:

[0028] FIG1 schematically shows a display panel including a special-shaped area;

[0029] FIG2 shows a schematic diagram of the layout of a display panel according to an embodiment of the present disclosure;

[0030] FIG3 shows a wiring diagram of a switching unit in a display panel according to an embodiment of the present disclosure;

[0031] FIG4 shows a cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0032] FIG5 is a schematic diagram showing an overlap capacitor formed in a display panel according to an embodiment of the present disclosure;

[0033] FIG6 is a schematic diagram showing a transfer unit formed in a conductive layer in a display panel according to an embodiment of the present disclosure;

[0034] FIG7 shows another schematic diagram of the layout of a display panel according to an embodiment of the present disclosure;

[0035] FIG8 shows another schematic diagram of forming overlap capacitance in a display panel according to an embodiment of the present disclosure;

[0036] FIG9 is a schematic diagram showing an outer ring electrode formed in a gate line layer in a display panel according to an embodiment of the present disclosure;

[0037] FIG10 is a schematic diagram showing a comparison of a display panel before and after compensation according to an embodiment of the present disclosure;

[0038] FIG11 shows another schematic diagram of the layout of a display panel according to an embodiment of the present disclosure;

[0039] FIG12 is a schematic diagram showing a first compensation unit formed in a source / drain layer of a display panel according to an embodiment of the present disclosure;

[0040] FIG13 shows another schematic diagram of the layout of a display panel according to an embodiment of the present disclosure;

[0041] FIG14 is a schematic diagram showing a display panel according to an embodiment of the present disclosure in which a first compensation unit is formed in a source / drain layer and an outer ring electrode is formed in a gate line layer;

[0042] FIG15 shows another schematic diagram of the layout of a display panel according to an embodiment of the present disclosure;

[0043] 16A and 16B are schematic diagrams illustrating a second compensation unit in a display panel according to an embodiment of the present disclosure;

[0044] FIG17 shows another schematic diagram of the layout of a display panel according to an embodiment of the present disclosure;

[0045] FIG18 is a schematic diagram showing a comparison of a display panel before and after compensation according to an embodiment of the present disclosure;

[0046] FIG19 shows a flow chart of a method for manufacturing a display panel according to an embodiment of the present disclosure; and

[0047] FIG20 shows a block diagram of a display device according to the present disclosure. DETAILED DESCRIPTION

[0048] To enable those skilled in the art to better understand the technical solution of the present disclosure, the display panel and its manufacturing method, as well as a display device including the display panel provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0049] Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art.

[0050] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0051] As used herein, the term "and / or" includes any and all combinations of at least one of the associated listed items.

[0052] The terms used herein are used only to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, they specify the presence of the features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of at least one other feature, whole, step, operation, element, component, and / or group thereof.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0054] FIG1 schematically shows a display panel including a special-shaped area. Specifically, FIG1 shows a “bangs” screen (i.e., a display screen with a U-shaped groove). In the “bangs” area (i.e., the U-shaped groove position), the length of the gate line is affected by the U-shaped groove and will increase, resulting in an increase in resistance R. However, since there are no pixels in the “bangs” area, the overlap of the gate line and the data line is reduced, and the coupling capacitance C is reduced. Therefore, the load R*C of each gate line in the “bangs” area is reduced. Of course, the display panel can include special-shaped areas of other shapes. It should be appreciated that the U-shaped groove shown in FIG1 is only an embodiment, and the special-shaped area can also include a blind hole formed in the display screen, and display pixels are formed around the blind hole.

[0055] For mobile devices, the display screen has a higher resolution, that is, a higher pixel density unit (Pixels Per Inch, PPI), and the touch and display driver integration (Touch and Display Driver Integration, TDDI), so there are many gate lines and the charging time of each gate line is short. At the same time, the touch time must be subtracted to make the charging time of each gate line even shorter.

[0056] Assuming that the load of each gate line in the irregular area is R1*C1, and the load of each gate line in the normal area is R2*C2, the voltage required for the highest grayscale is AV. When R2*C2 in the normal area is too large, the integrated circuit (IC) is insufficiently charged to the normal area or is on the verge of a critical value, the charging time of each row of gate lines is t, and the maximum voltage that can be charged is BV, B<A. Therefore, after time t, the pixel voltage in the normal area cannot drive the liquid crystal to fully deflect, and the displayed grayscale is not the maximum grayscale; while in the irregular area, because the load R1*C1<R2*C2, the signal delay time is short, and after time t, the pixel can be charged to the maximum voltage AV and can reach the maximum grayscale. Visually, it can be clearly seen that the picture in the normal area is darker, while the picture in the irregular area on both sides of the U-shaped groove is brighter, resulting in uneven picture display.

[0057] Usually, load compensation is performed on the gate lines in the special-shaped area where the U-shaped groove is located. However, since display panels often have narrow bezel requirements, the space available for load compensation is limited, and the compensated load often cannot meet the requirements. The difference between the compensated load and the load in the normal area is still large, and the problem of uneven picture quality will also occur.

[0058] The present disclosure designs a compensation structure to ensure that the delay time caused by the compensated load is close to the delay time in the normal area, and at the same time achieves a narrow frame and a high screen-to-body ratio.

[0059] Referring to FIG1 , an embodiment of the present disclosure provides a display panel including a substrate (not shown), and a first region 10 (i.e., a profiled region) and a second region 20 (i.e., a normal region) located on the substrate. The first region 10 includes a plurality of first gate lines, and the second region 20 includes a plurality of second gate lines. Due to the presence of the profile, the number of pixels connected to the first gate lines is less than the number of pixels connected to the second gate lines. The display panel according to an embodiment of the present disclosure includes a compensation structure for compensating for the capacitance on each first gate line in the first region 10.

[0060] According to an embodiment of the present disclosure, the capacitance on each first gate line in the first region 10 may be compensated at position A, position B, and / or position C shown in FIG. 1 .

[0061] Figure 2 shows a layout diagram of the display panel near position A according to an embodiment of the present disclosure, Figure 3 shows a wiring diagram of the adapter unit in the display panel according to an embodiment of the present disclosure, and Figure 4 shows a cross-sectional view of the adapter unit in the display panel according to an embodiment of the present disclosure.

[0062] As shown in Figures 2 and 3, the display panel may include a plurality of pixels, and the first gate line includes a first portion 110 disposed in an active display area (AA) and a second portion 120 disposed in a non-display area outside the AA area, wherein the first portion 110 and the second portion 120 are electrically connected to each other. The compensation structure of the display panel includes a first electrode plate, which at least partially overlaps with an orthographic projection of the second portion 120 of the first gate line on the substrate.

[0063] FIG2 shows the cutting line of the display panel, which includes the array substrate cutting line and the color film substrate cutting line. When making the display panel, a U-shaped groove for placing a sensor (for example, a camera) can be made by cutting the substrate. Because the dielectric layer (such as PVX) is very brittle, it is easy to crack when cutting, which will cause water vapor to enter the position of the metal layer along the cracks and cause metal corrosion. To prevent this from happening, when making the display panel, the edge 111 of the dielectric layer will be retracted so that there is a certain distance between the edge 111 of the dielectric layer and the cutting line, and the distance is related to the cutting accuracy. In order to avoid the influence of the external environment of the display panel on the interior of the display panel, a ground line (GND) 112 is also provided within the cutting line of the display panel. In some embodiments, the ground line (GND) 112 is provided on the side of the edge 111 of the dielectric layer away from the cutting line of the display panel. In some embodiments, the ground line (GND) 112 is provided between the edge 111 of the dielectric layer and the second part 120 of the first gate line.

[0064] In some embodiments, the second portion 120 of the first gate line is formed as a gate line fan-out line to be arranged around the U-shaped groove. The second portion 120 of the first gate line is formed in the non-display area outside the AA area, and unlike the first portion 110 formed in the AA area, no pixel is directly connected to the second portion 120. The first gate line also includes a third portion 130 (hereinafter also referred to as a "switch unit"), and each gate line fan-out line is connected to the first portion 110 of the first gate line (i.e., the portion connected to the pixel in the AA area) via each switching unit.

[0065] As shown in FIG3 , the first portion 110 of the first gate line is connected to each pixel via a thin film transistor (TFT) 150 in the AA region. When the signal on the first gate line turns on the TFT 150 , the data signal on the data line 160 is applied to the pixel electrode 170 via the TFT 150 .

[0066] FIG4 shows a cross-sectional view of the transfer unit shown in FIG3 . As shown in FIG4 , the display panel according to an embodiment of the present disclosure includes a gate line (Gate) layer 100, a gate insulation (GI) layer 200, a source and drain (SD) layer 300, a dielectric (PVX) layer 400, and a conductive (ITO) layer 500 stacked in sequence. The first portion 110 of the first gate line located in the Gate layer 100 can be transferred to the second portion 120 of the first gate line provided in the SD layer 300. That is, the first portion 110 of the first gate line is provided in the Gate layer 100, and the second portion 120 of the first gate line (or the gate line fan-out line) is provided in the SD layer 300, thereby reducing the distance between the first gate line and the ITO layer 500.

[0067] Before the above-mentioned switching is performed, when an overlap capacitance is formed between the first gate line and the ITO layer 500, the dielectric layer therebetween includes the GI layer 200 and the PVX layer 400. FIG5 shows a cross-sectional view taken in a direction perpendicular to the gate line fan-out line (i.e., the second portion 120 of the first gate line). Referring to FIG5, after the above-mentioned switching is performed, the first gate line is switched to the SD layer 300. When an overlap capacitance is formed between the first gate line and the ITO layer 500, the dielectric layer therebetween includes the PVX layer 400 and does not include the GI layer 200. That is, the distance between the first gate line and the ITO layer 500 is reduced, thereby increasing the overlap capacitance, i.e., greater compensation is performed on the capacitance on each first gate line.

[0068] As shown in Figure 4, the ITO layer 500 can be used to form a switching unit (i.e., the third portion 130 of the first gate line), which is connected to the first portion 110 of the first gate line located in the Gate layer 100 via a through-hole passing through the PVX layer 400 and the GI layer 200, and is connected to the gate line fan-out line (i.e., the second portion 120 of the first gate line) located in the SD layer via a through-hole passing through the PVX layer 400, so as to switch the first portion 110 of the first gate line located in the Gate layer to the gate line fan-out line (i.e., the second portion 120 of the first gate line) in the SD layer. The switching unit (i.e., the third portion 130 of the first gate line) can be formed near the A position and the B position shown in Figure 1.

[0069] A compensation structure is provided in the display panel according to an embodiment of the present disclosure, and the switching unit is used to switch the gate line provided in the Gate layer 100 to the gate line fan-out line provided in the SD layer 300, so as to reduce the distance between the gate line (or the gate line fan-out line) and the ITO layer 500, thereby increasing the overlapping capacitance to compensate for the capacitance on each gate line.

[0070] At positions A and B in the U-shaped groove area shown in Figure 1, the gate line width is relatively small due to the narrow frame limitation. Compared with the normal area, the gate line is longer, so the resistance on the gate line is usually equal to or greater than the resistance on the gate line in the normal area. Therefore, the resistance of the gate line in the special-shaped area does not usually need to be compensated. As shown in Figure 2, at the positions on both sides of the U-shaped groove area (i.e., positions A and B shown in Figure 1), the gate line located at the Gate layer 100 is transferred to the gate line fan-out line of the SD layer 300. The ITO layer 500 forms an overlapping capacitor with all the gate line fan-out lines formed in the SD layer 300. The capacitance compensation value of each gate line is related to the length of the gate line fan-out line. In the special-shaped area, the length of the gate line fan-out line becomes longer, which means that the number of pixels corresponding to the gate line decreases, so the capacitance that needs to be compensated increases. On the other hand, the length of the gate line fan-out line also means that the overlapping area with the ITO layer 500 increases, thereby increasing the capacitance compensation value that can be obtained, so there is no need to specifically calculate the compensation capacitance corresponding to each gate line.

[0071] 2 , dummy spacers 140 can be placed between adjacent gate fan-out lines to reduce the step difference at the gate fan-out lines and improve the flatness to make the cell thickness uniform. The dummy spacers 140 can be placed in the Gate layer 100 and / or the SD layer 300 .

[0072] FIG. 6 is a schematic diagram showing a switching unit (ie, the third portion 130 of the first gate line) formed in the ITO layer 500 in a display panel according to an embodiment of the present disclosure.

[0073] Referring to FIG6 , an ITO layer 500 can be used to form a transfer unit, and the material used to form the transfer unit is separated from the other materials of the ITO layer 500. As shown in FIG6 , the ITO layer 500 can form a common (COM) electrode (AA_C) and / or a touch (Sensor) electrode (AA_S) in the AA area of ​​the display panel, and form a first outer ring electrode 510 in the non-display area outside the AA area. According to an embodiment of the present disclosure, the first electrode plate of the compensation structure can include the first outer ring electrode 510 in the ITO layer 500.

[0074] In the context of the present disclosure, the "outer ring electrode" refers to an electrode formed in the non-display area outside the AA area, relative to the COM or Sensor electrode located in the inner ring formed in the AA area. As shown in Figure 6, the material of the ITO layer 500 located in the AA area and the material of the ITO layer 500 in the non-display area outside the AA area are disconnected from each other, and the distance of the disconnection depends on the process exposure capability of the ITO layer 500. The material of the ITO layer used to form the transfer unit is located in the non-display area outside the AA area, and the formed transfer unit (i.e., the third portion 130 of the first gate line) is separated from the first outer ring electrode 510. In other words, the first outer ring electrode 510 and the COM or Sensor electrode (AA_C / AA_S) are independent of each other, and the first outer ring electrode 510 and the transfer unit are also independent of each other.

[0075] FIG. 7 shows a schematic layout diagram of a display panel near position C according to an embodiment of the present disclosure.

[0076] As shown in FIG7 , the compensation structure may further include a second outer ring electrode 520 formed on the gate layer 100. After the gate line is transferred from the gate layer 100 to the gate line fan-out line of the SD layer 300, the second outer ring electrode 520 may be formed on the gate layer 100 to form an overlapping capacitor with the gate line fan-out line formed on the SD layer 300 to further compensate for the capacitance on the first gate line.

[0077] FIG. 8 is a schematic diagram showing the formation of overlap capacitance in the display panel shown in FIG. 7 .

[0078] As shown in Figure 8, an overlapping capacitor is formed between the gate line fan-out line formed in the SD layer 300 and the ITO layer 500, and the dielectric layer therebetween includes a PVX layer 400; in addition, an overlapping capacitor is formed between the gate line fan-out line formed in the SD layer 300 and the second outer ring electrode 520 formed in the Gate layer 100, and the dielectric layer therebetween includes a GI layer 200, thereby further compensating for the capacitance on each first gate line, thereby increasing the capacitance on the first gate line.

[0079] FIG9 is a schematic diagram showing a second outer ring electrode 520 formed in the gate layer 100 of a display panel according to an embodiment of the present disclosure. Specifically, FIG9 shows a layout design diagram at position D shown in FIG7 .

[0080] As shown in Figure 9, the second outer ring electrode 520 formed in the Gate layer 100 can be connected to the first outer ring electrode 510 formed in the ITO layer 500 through the PVX hole 450 (see Figure 6). In addition, Figure 9 shows that the second outer ring electrode 520 formed in the Gate layer 100 overlaps with the gate line fan-out line (i.e., the second part 120 of the first gate line) formed in the SD layer 300. It should be noted that this layout design needs to ensure the process accuracy (overlay) between the SD layer 300 and the Gate layer 100. However, the second outer ring electrode 520 formed in the Gate layer 100 is not limited to the formation method shown in the figure, but can have a different formation method. For example, similar to the first outer ring electrode 510 formed in the ITO layer 500, the second outer ring electrode 520 in the Gate layer 100 can be formed as a whole.

[0081] It should be noted that the first outer ring electrode 510 formed on the ITO layer 500 and the COM or sensor electrode (AA_C / AA_S) in the AA area are independent of each other (i.e., disconnected and insulated from each other). However, to prevent display or touch problems caused by capacitive coupling between the electrodes in the AA area and the first outer ring electrode 510 due to different signals, the signal of the first outer ring electrode 510 can be synchronized with the signal of the electrodes in the AA area. That is, when the AA area is in the display state, the signal applied to the electrodes in the AA area and the first outer ring electrode 510 is the COM signal; when the AA area is in the touch state, the signal applied to the electrodes in the AA area and the first outer ring electrode 510 is the touch pulse signal.

[0082] A compensation structure is provided in the display panel according to an embodiment of the present disclosure, and the compensation structure includes a first outer ring electrode 510 formed in the ITO layer 500 and a second outer ring electrode 520 formed in the Gate layer 100. The switching unit is used to switch the gate line provided in the Gate layer 100 to the gate line fan-out line provided in the SD layer 300, so as to reduce the distance between the gate line (or the gate line fan-out line) and the ITO layer 500. After the gate line of the Gate layer 100 is switched to the gate line fan-out line of the SD layer 300 through the switching unit, a double-layer capacitor can be formed through the second outer ring electrode 520 formed in the Gate layer 100, so that the compensation capacitor can more easily meet the requirements, and the design is simple and easy to operate.

[0083] FIG. 10 is a schematic diagram showing a comparison of a display panel before and after compensation according to an embodiment of the present disclosure.

[0084] See Figure 10, where the ordinate represents the percentages before and after compensation, and the abscissa represents the number of compensated gate lines in the irregularly shaped area. Before compensation, the capacitance at the U-groove position is 30% to 50% of the capacitance at the normal position, the resistance at the U-groove position is 120% to 130% of the resistance at the normal position, and the load R*C at the U-groove position is 40% to 60% of the load R*C at the normal position. After compensation, the capacitance at the U-groove position is 90% to 100% of the capacitance at the normal position, the resistance at the U-groove position remains the same as before compensation, and the load R*C at the U-groove position is 110% to 130% of the load R*C at the normal position.

[0085] According to an embodiment of the present disclosure, if the capacitance compensation on the gate line still cannot meet the requirements after compensation at position C, compensation can be performed at positions A and B by increasing the gate line area.

[0086] 11 shows another schematic layout diagram of a display panel near position A according to an embodiment of the present disclosure. FIG. 12 shows a schematic diagram of forming a first compensation unit 310 in the SD layer 300 of the display panel according to an embodiment of the present disclosure.

[0087] According to an embodiment of the present disclosure, the compensation structure may further include a first compensation unit 310 formed in the SD layer 300. Compared to the embodiment shown in FIG2 , in the display panels shown in FIG11 and FIG12 , a first compensation unit 310 is formed between two adjacent gate line fan-out lines (i.e., the second portion 120 of the first gate line), and the formed first compensation unit 310 is connected to one of the gate line fan-out lines. In the embodiment shown in FIG11 , by adding the first compensation unit 310 connected to the gate line fan-out line, the overlapping area between the gate line fan-out line and the ITO layer 500 can be increased, thereby increasing the overlapping capacitance formed between the first gate line and the ITO layer to compensate for the capacitance on the first gate line.

[0088] It should be understood that although the first compensation unit 310 is shown as having a mesh shape in Figures 11 and 12, the shape of the first compensation unit 310 is not limited to the style shown in the figures, but can have various patterns. If the first compensation unit 310 is located in the sealant area, the pattern of the first compensation unit 310 needs to ensure an appropriate aperture ratio to ensure that sufficient ultraviolet (UV) light can pass through to cure the sealant.

[0089] Figure 13 shows another layout schematic diagram of the display panel near position A according to an embodiment of the present disclosure, and Figure 14 shows a schematic diagram of forming a first compensation unit 310 in the SD layer 300 and forming a third outer ring electrode 530 in the Gate layer 100 in the display panel according to an embodiment of the present disclosure.

[0090] According to an embodiment of the present disclosure, the compensation structure may further include a third outer ring electrode 530 in the gate layer 100 corresponding to the first compensation unit 310. Compared to the embodiment shown in Figures 11 and 12, in the display panel shown in Figures 13 and 14, the third outer ring electrode 530 is formed in the gate layer 100 at a position corresponding to the first compensation unit 310 in the SD layer 300 and is connected to the first outer ring electrode 510 formed in the ITO layer 500 through the PVX hole 450. Therefore, overlap capacitance is formed not only between the gate line fan-out line in the SD layer 300 and the first outer ring electrode 510 formed in the ITO layer 500, but also between the gate line fan-out line in the SD layer 300 and the third outer ring electrode 530 in the gate layer 100. Thus, by forming the third outer ring electrode 530 in the gate layer 100 at a position corresponding to the first compensation unit 310, a double-layer capacitor can be formed to compensate for the capacitance on the first gate line.

[0091] Similar to the first compensation unit 310 described with reference to Figures 11 and 12, according to the embodiment of the present disclosure, the specific pattern of the third outer ring electrode 530 formed in the Gate layer 100 is not limited, as long as an appropriate aperture ratio can be ensured to ensure that sufficient UV light can pass through to cure the frame glue.

[0092] The display panel according to the embodiment of the present disclosure has been described above with reference to Figures 2 to 14 . Specifically, by connecting the gate lines located in the Gate layer 100 to the gate line fan-out lines of the SD layer 300, the distance between the gate lines and the ITO layer 500 can be reduced, thereby compensating for the capacitance on the gate lines. However, the embodiment of the present disclosure is not limited thereto, and the capacitance on the gate lines can be compensated without connecting the gate lines of the Gate layer to the SD layer.

[0093] FIG15 shows another schematic layout diagram of a display panel according to an embodiment of the present disclosure near position A. Compared to the embodiment shown in FIG2 , in the display panel shown in FIG15 , no transfer unit is formed, and the first portion 110 of the first gate line and the second portion 120 ′ of the first gate line (i.e., the gate line fan-out line) are both formed in the Gate layer.

[0094] According to an embodiment of the present disclosure, the compensation structure may include a second compensation unit. As shown in FIG15 , a second compensation unit is formed between two adjacent first gate lines and connected to one of the first gate lines.

[0095] According to an embodiment of the present disclosure, the second compensation unit may include a first sub-compensation unit 105 formed in the Gate layer 100, wherein the first sub-compensation unit 105 is connected to the first gate line, and a capacitor is formed between the first sub-compensation unit 105 and the ITO layer 500 to compensate for the capacitance on the first gate line.

[0096] According to an embodiment of the present disclosure, the second compensation unit further includes a second sub-compensation unit 305 formed in the SD layer 300 , and a capacitor is formed between the first compensation unit 105 and the second sub-compensation unit 305 to compensate for the capacitance on the first gate line.

[0097] 16A and 16B are schematic diagrams illustrating a second compensation unit in a display panel according to an embodiment of the present disclosure.

[0098] 16A , a capacitor is formed between the first compensation sub-unit 105 of the Gate layer 100 and the ITO layer 500 , and the dielectric layers therebetween include the GI layer 200 and the PVX layer 400 . The ITO layer 500 can be connected to the SD layer 300 through the PVX hole 450 .

[0099] 16B , a capacitor is formed between the first compensation sub-unit 105 of the Gate layer 100 and the second compensation sub-unit 305 of the SD layer 300 , with the dielectric layer therebetween including the GI layer 200 . The second compensation sub-unit 305 of the SD layer 300 may be connected to the ITO layer 500 through the PVX hole 450 .

[0100] Due to the different thicknesses of the dielectric layers therebetween, in the case of the same area, the compensation capacitances provided by the compensation unit shown in FIG16A and the compensation unit shown in FIG16B are different, and the compensation capacitance provided by the compensation unit shown in FIG16A is smaller than the compensation capacitance provided by the compensation unit shown in FIG16B.

[0101] As shown in Figure 15, about different first gate lines, owing to the different sizes of the space that can be provided to the second compensation unit at A position or B position, therefore for the consistency of compensation, different types of compensation units are provided, as shown in Figure 16 A and Figure 16 B.If space is large and compensation is enough, space can be made up by arranging more compensation units shown in Figure 16 A.Can, according to actual needs, reasonably arrange the quantity of various compensation units, to obtain desired compensation capacitance.In addition, can also by adjusting the area of ​​the first sub-compensation unit 105 and / or the second sub-compensation unit 305, and / or by adjusting the thickness of the dielectric layer to obtain desired compensation capacitance.

[0102] As shown in FIG. 16A and FIG. 16B , in order to ensure an appropriate aperture ratio so as to ensure that sufficient UV light can pass through to cure the sealant, holes may be opened in the first sub-compensation unit 105 and / or the second sub-compensation unit 305 .

[0103] A compensation structure is provided in the display panel according to an embodiment of the present disclosure. The compensation structure includes a second compensation unit, and the second compensation unit includes a first sub-compensation unit 105 formed in the Gate layer 100 and / or a second sub-compensation unit 305 formed in the SD layer 300. A desired compensation capacitance can be obtained by adjusting the number of the first sub-compensation units 105 and / or the second sub-compensation units 305, the area of ​​the first sub-compensation units 105 and / or the second sub-compensation units 305, and the thickness of the dielectric layer, thereby providing different compensation capacitances for different first gate lines, so that the compensated load (i.e., the product of the compensated capacitance and the resistance) on each first gate line is consistent.

[0104] FIG. 17 shows another schematic layout diagram of a display panel near position C according to an embodiment of the present disclosure.

[0105] According to an embodiment of the present disclosure, the compensation structure may include a data line extension portion 360 formed in the SD layer 300. As shown in FIG17 , the data line disposed in the SD layer 300 may be extended beyond the AA region at position C shown in FIG1 to form the data line extension portion 360, thereby forming an overlap capacitor with the gate line fan-out line 120′ formed in the gate layer 100, with the dielectric layer therebetween including a GI layer (not shown in FIG17 ).

[0106] 17 , the data lines disposed in the SD layer 300 may include touch data lines and display data lines. Each touch data line and the three display data lines between two adjacent touch data lines extend beyond the AA region to form a data line extension portion 360 .

[0107] According to an embodiment of the present disclosure, the line width of the data line extension portion 360 can be widened to increase the overlapping area. In some embodiments, the line width of each data line extension portion 360 is larger than the line width of the data line in the corresponding AA area. For example, the data line extension portion 360 formed by extending the touch data line outside the AA area is larger than the line width of the touch data line.

[0108] A compensation structure is provided in the display panel according to an embodiment of the present disclosure. The compensation structure includes a data line extension portion 360 formed in the SD layer 300. By forming an overlapping capacitor between the data line extension portion 360 and the gate line fan-out line 120' of the gate layer 100, the capacitance on the first gate line can be compensated. Furthermore, the capacitance on the data line can also be compensated.

[0109] FIG. 18 is a schematic diagram showing a comparison of a display panel before and after compensation according to an embodiment of the present disclosure.

[0110] See Figure 18, where the ordinate represents the percentages before and after compensation, and the abscissa represents the number of compensated gate lines in the irregularly shaped area. Before compensation, the capacitance at the U-groove position is 40% to 60% of the capacitance at the normal position, the resistance at the U-groove position is 130% to 150% of the resistance at the normal position, and the load R*C at the U-groove position is 60% to 90% of the load R*C at the normal position. After compensation, the capacitance at the U-groove position is 70% to 80% of the capacitance at the normal position, the resistance at the U-groove position is 120% to 130% of the resistance at the normal position, and the load R*C at the U-groove position is 85% to 100% of the load R*C at the normal position.

[0111] It should be recognized that although Figure 17 only shows a compensation structure for compensating the capacitance on the first gate line at position C shown in Figure 1, the ITO layer 500 can also be formed to completely cover the gate lines (or gate line fan-out lines) at positions A and B shown in Figure 1 to increase the compensation capacitance.

[0112] An embodiment of the present disclosure provides a method for manufacturing a display panel, wherein the display panel includes a first area 10 (i.e., an irregular area) and a second area 20 (i.e., a normal area), and the number of pixels corresponding to each gate line in the first area 10 is less than the number of pixels corresponding to each gate line in the second area 20.

[0113] FIG. 19 shows a flow chart of a method for manufacturing a display panel according to an embodiment of the present disclosure.

[0114] As shown in FIG. 19 , the method includes step S100 . In step S100 , a compensation structure is prepared. The compensation structure includes a first electrode plate. The first electrode plate at least partially overlaps with an orthographic projection of the second portion on the substrate.

[0115] According to an embodiment of the present disclosure, the display panel includes a Gate layer, a GI layer, an SD layer, a PVX layer, and an ITO layer stacked sequentially, and the manufacturing method further includes: transferring the gate line located in the Gate layer to the SD layer.

[0116] According to an embodiment of the present disclosure, transferring the gate lines in the Gate layer to the SD layer includes: forming a transfer unit using an ITO layer to transfer the gate lines in the Gate layer to the gate line fan-out lines in the SD layer.

[0117] According to an embodiment of the present disclosure, the manufacturing method further includes: arranging dummy spacers between adjacent gate line fan-out lines, wherein the dummy spacers are provided in the Gate layer and / or the SD layer.

[0118] According to an embodiment of the present disclosure, the manufacturing method further includes: forming an outer ring electrode in the Gate layer, wherein the outer ring electrode in the Gate layer and the gate line fan-out line in the SD layer form an overlapping capacitor.

[0119] According to an embodiment of the present disclosure, the manufacturing method further includes: forming a first compensation unit between two adjacent gate fan-out lines in the SD layer, wherein the formed first compensation unit is connected to one of the gate fan-out lines.

[0120] According to an embodiment of the present disclosure, the manufacturing method further includes: forming an outer ring electrode in the Gate layer at a position corresponding to the first compensation unit in the SD layer, and connecting it to the ITO layer through a PVX hole.

[0121] According to an embodiment of the present disclosure, the manufacturing method further includes: forming a second compensation unit between two adjacent gate lines, and the formed second compensation unit is connected to one of the gate lines.

[0122] According to an embodiment of the present disclosure, forming a second compensation unit between two adjacent gate lines includes forming a first sub-compensation unit in the Gate layer, wherein the first sub-compensation unit is connected to the gate line and a capacitor is formed between the first sub-compensation unit and the ITO layer.

[0123] According to an embodiment of the present disclosure, forming the second compensation unit between two adjacent gate lines further includes forming a second sub-compensation unit in the SD layer, and forming a capacitor between the first sub-compensation unit and the second sub-compensation unit.

[0124] According to an embodiment of the present disclosure, the manufacturing method further includes: forming a data line extension portion in the SD layer to form an overlapping capacitor with a gate line fan-out line in the Gate layer.

[0125] According to the manufacturing method of the display panel provided in the embodiment of the present disclosure, the display panel provided in each embodiment of the present disclosure can be manufactured. The technical details can be referred to the embodiments described in combination with Figures 2 to 18, and will not be repeated here.

[0126] FIG20 shows a block diagram of a display device according to the present disclosure.

[0127] An embodiment of the present disclosure provides a display device including a display panel according to each embodiment of the present disclosure.

[0128] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some embodiments, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A display panel, comprising a substrate, and a first area and a second area located on the substrate, the display panel further comprising a plurality of pixels, in, The first region includes a plurality of first gate lines, the second region includes a plurality of second gate lines, the number of pixels connected to the first gate lines is less than the number of pixels connected to the second gate lines, the first gate lines include a first portion arranged in an effective display region and a second portion arranged in a non-display region outside the effective display region, the first portion and the second portion are electrically connected to each other, The display panel further includes a compensation structure including a first electrode plate, the first electrode plate at least partially overlapping an orthographic projection of the second portion on the substrate.

2. The display panel according to claim 1, wherein: The display panel includes a gate line layer, a first insulating layer, a source-drain layer, a second insulating layer and a conductive layer stacked in sequence. The first portion is disposed in the gate line layer, and the second portion is disposed in the source and drain layer.

3. The display panel according to claim 2, wherein: The first gate line further includes a third portion disposed in the conductive layer, The third portion is connected to the first portion disposed in the gate line layer via a through hole passing through the second insulating layer and the first insulating layer, and The third portion is connected to the second portion provided in the source-drain layer via a through hole penetrating the second insulating layer.

4. The display panel according to claim 3, wherein: The compensation structure includes a first outer ring electrode arranged in the conductive layer, the first outer ring electrode is arranged in a non-display area outside the effective display area of ​​the display panel, the first electrode plate includes the first outer ring electrode, and the first outer ring electrode and the orthographic projection of the second part arranged in the source and drain layer on the substrate at least partially overlap, The first outer ring electrode and the third portion disposed in the conductive layer are disconnected from each other, and The first outer ring electrode and the electrode in the conductive layer in the effective display area are disconnected from each other.

5. The display panel according to claim 4, wherein: The compensation structure further includes a second outer ring electrode disposed in the gate line layer, the second outer ring electrode being disposed in a non-display area outside the effective display area of ​​the display panel, and the second outer ring electrode at least partially overlaps with the orthographic projection of the second portion disposed in the source / drain layer on the substrate, The second outer ring electrode is connected to the first outer ring electrode via a through hole passing through the second insulating layer and the first insulating layer.

6. The display panel according to claim 4, wherein: The compensation structure further includes a first compensation unit arranged in the source-drain layer, and the second portion arranged in the source-drain layer is a gate line fan-out line, The first compensation unit is formed between two adjacent gate line fan-out lines and connected to one of the gate line fan-out lines. The first outer ring electrode at least partially overlaps with the orthographic projection of the first compensation unit on the substrate.

7. The display panel according to claim 6, wherein: The compensation structure further includes a third outer ring electrode arranged in the gate line layer, The third outer ring electrode is arranged in a non-display area outside the effective display area of ​​the display panel, The third outer ring electrode at least partially overlaps with the orthographic projection of the first compensation unit on the substrate, and The third outer ring electrode is connected to the first outer ring electrode via a through hole passing through the second insulating layer and the first insulating layer.

8. The display panel according to claim 7, wherein: The first compensation unit and the third outer ring electrode both have a mesh shape, and the third outer ring electrode overlaps with an orthographic projection of the first compensation unit on the substrate.

9. The display panel according to claim 2, further comprising a dummy spacer, The dummy spacer is arranged between adjacent second portions and is disposed on the gate line layer and / or the source / drain layer.

10. The display panel according to claim 1, wherein: The display panel comprises a gate line layer, a first insulating layer, a source-drain layer, a second insulating layer and a conductive layer stacked in sequence, wherein the first gate line and the second gate line are formed in the gate line layer. The compensation structure includes a second compensation unit, which is formed between two adjacent first gate lines and connected to one of the first gate lines.

11. The display panel according to claim 10, wherein: The second compensation unit includes a first sub-compensation unit disposed in the gate line layer, the first sub-compensation unit is connected to a first gate line in the gate line layer, and the first sub-compensation unit at least partially overlaps with an orthographic projection of the conductive layer on the substrate.

12. The display panel according to claim 11, wherein: The first sub-compensation unit includes multiple first sub-compensation units, and an overlapping area between at least one first sub-compensation unit among the multiple first sub-compensation units and the orthographic projection of the conductive layer on the substrate is different from an overlapping area between other first sub-compensation units among the multiple first sub-compensation units and the orthographic projection of the conductive layer on the substrate.

13. The display panel according to claim 11, wherein: The second compensation unit further includes a second sub-compensation unit disposed in the source-drain layer, and orthographic projections of the first sub-compensation unit and the second sub-compensation unit on the substrate at least partially overlap.

14. The display panel according to claim 13, wherein: The first sub-compensation unit includes a plurality of first sub-compensation units, the second sub-compensation unit includes a plurality of second sub-compensation units, and an overlapping area of ​​a positive projection of at least one first sub-compensation unit among the plurality of first sub-compensation units and at least one second sub-compensation unit among the plurality of second sub-compensation units on the substrate is different from an overlapping area of ​​a positive projection of other first sub-compensation units among the plurality of first sub-compensation units and other second sub-compensation units among the plurality of second sub-compensation units on the substrate.

15. The display panel according to claim 13, wherein: The second sub-compensation unit is connected to the conductive layer via a via penetrating the second insulating layer.

16. The display panel according to claim 11, wherein: The first sub-compensation unit includes a plurality of first sub-compensation units, and the first gate line includes a plurality of first gate lines, and the number of first sub-compensation units connected to at least one of the plurality of first gate lines is different from the number of first sub-compensation units connected to other first gate lines of the plurality of first gate lines.

17. The display panel according to claim 1, wherein: The display panel includes a gate line layer, a first insulating layer, a source-drain layer, a second insulating layer and a conductive layer stacked in sequence, the first gate line and the second gate line are formed in the gate line layer, and a data line is formed in the source-drain layer. The compensation structure includes a data line extension portion disposed in the source / drain layer, The data line extension portion extends from the data line to the non-display area of ​​the display panel and is aligned with the second portion disposed in the gate line layer on the positive projection portion of the substrate. The shadows at least partially overlap.

18. The display panel according to claim 17, wherein: The line width of the data line extension portion is greater than the line width of the data line.

19. A method for manufacturing a display panel, for manufacturing the display panel according to any one of claims 1 to 18, the method comprising: A compensation structure is prepared, the compensation structure comprising a first electrode plate, the first electrode plate at least partially overlapping an orthographic projection of the second portion on the substrate.

20. A display device comprising the display panel according to any one of claims 1 to 18.

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