Display panel and display device

Abstract

A display panel and a display device. The display panel comprises pixel circuits (20) and signal lines (30). Each pixel circuit (20) comprises a driving transistor (T3), a bias transistor (T8), and a gate initialization transistor (T5); each signal line (30) comprises a bias signal line (DVH) and a first reference signal line (Vref1); the bias transistor (T8) is electrically connected between at least one of a first electrode (p31) and a second electrode (p32) of the driving transistor (T3) and the bias signal line (DVH); and the gate initialization transistor (T5) is electrically connected between a gate (g3) of the driving transistor (T3) and the first reference signal line (Vref1). By configuring the bias signal line (DVH) to comprise a first sub-bias signal line (DVH1) and a second sub-bias signal line (DVH2) which extend in different directions and are electrically cross-connected, and the first reference signal line (Vref1) to comprise a first sub-reference signal line (Vref11) and a second sub-reference signal line (Vref12) which extend in different directions and are electrically cross-connected, the resistance of the bias signal line (DVH) and the resistance of the first reference signal line (Vref1) are reduced, and the power consumption of the bias signal line (DVH) and the power consumption of the first reference signal line (Vref1) are reduced, thereby improving the stability of signal transmission, and improving the display effects such as display uniformity.

Description

Display panel and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on August 31, 2023, with application number 202311131077.8 and invention name “Display Panel and Display Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] With the development of display technology, the demand for low-frequency, low-power display panels is becoming increasingly urgent. This requires that the signal lines transmitting signals to the pixel circuits in the display panel have low power consumption and stable transmission signals. Therefore, how to provide a new display panel design that reduces the power consumption of the signal lines transmitting signals to the pixel circuits and ensures stable signal transmission, thereby meeting the low-frequency and low-power requirements, is a technical problem that needs to be solved by those skilled in the art.

[0004] Summary of the Invention

[0005] To solve the above technical problems, the embodiments of the present application provide a display panel and a display device to reduce the power consumption of the signal line transmitting the signal to the pixel circuit and make the signal transmission of the signal line stable, thereby meeting the requirements of low frequency and low power consumption.

[0006] To achieve the above objectives, the present invention provides the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a display panel, comprising a substrate and a pixel circuit and a signal line located on one side of the substrate;

[0008] The pixel circuit includes a driving transistor, a bias transistor, and a gate initialization transistor, the signal line includes a bias signal line and a first reference signal line, the bias transistor is electrically connected between at least one of the first electrode and the second electrode of the driving transistor and the bias signal line, and the gate initialization transistor is electrically connected between the gate of the driving transistor and the first reference signal line;

[0009] The bias signal line includes a first sub-bias signal line extending along the first direction and arranged along the second direction, and a second sub-bias signal line extending along the second direction and arranged along the first direction, the first direction and the second direction intersect, and the first sub-bias signal line and the second sub-bias signal line are electrically connected;

[0010] The first reference signal line includes a first sub-reference signal line extending along the first direction and arranged along the second direction, and a second sub-reference signal line extending along the second direction and arranged along the first direction, the first sub-reference signal line and the second sub-reference signal line being electrically connected;

[0011] The bias signal line and the first reference signal line are insulated from each other.

[0012] In a second aspect, an embodiment of the present application provides a display device comprising the above-mentioned display panel.

[0013] Compared with the existing technology, the above technical solution has the following advantages:

[0014] The display panel provided in the embodiment of the present application forms a grid structure of bias signal lines by providing bias signal lines including a first sub-bias signal line extending along a first direction and arranged along a second direction, and a second sub-bias signal line extending along a second direction and arranged along the first direction, and the first sub-bias signal line and the second sub-bias signal line are electrically connected, thereby forming a grid structure of bias signal lines. This reduces the overall resistance of the bias signal lines, thereby reducing the power consumption of the bias signal lines, and improving the signal transmission stability of the bias signal lines, which is beneficial to improving display uniformity and other display effects of the display panel. Similarly, the first reference signal lines form a grid structure of first reference signal lines by providing first sub-reference signal lines extending along a first direction and arranged along a second direction, and a second sub-reference signal line extending along a second direction and arranged along the first direction, and the first sub-reference signal line and the second sub-reference signal line are electrically connected, thereby reducing the overall resistance of the first reference signal lines, thereby reducing the power consumption of the first reference signal lines, and improving the signal transmission stability of the first reference signal lines, which is beneficial to improving display uniformity and other display effects of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0016] FIG1 is a schematic cross-sectional view of a display panel according to an embodiment of the present application;

[0017] FIG2 is a partial top view of a display panel provided in an embodiment of the present application;

[0018] FIG3 is a schematic structural diagram of a pixel circuit in a display panel provided in an embodiment of the present application;

[0019] FIG4 is a schematic structural diagram of another pixel circuit in a display panel provided in an embodiment of the present application;

[0020] FIG4 a is a timing diagram of an implementation of a signal provided to the pixel circuit shown in FIG4 within a driving cycle provided by an embodiment of the present application;

[0021] FIG5 is a schematic diagram of a partial layout structure of a display panel provided in an embodiment of the present application;

[0022] FIG6 is a partial enlarged schematic diagram of the layout structure shown in FIG5 ;

[0023] FIG7 a is a schematic diagram of the layout structure of the active layer poly in the layout structure shown in FIG5 ;

[0024] FIG7 b is a schematic diagram of the layout structure of the metal layer M1 in the layout structure shown in FIG5 ;

[0025] FIG7 c is a schematic diagram of the layout structure of the metal layer MC in the layout structure shown in FIG5 ;

[0026] FIG7 d is a schematic diagram of the layout structure of the oxide layer IGZO in the layout structure shown in FIG5 ;

[0027] FIG7e is a schematic diagram of the layout structure of the metal layer MG in the layout structure shown in FIG5 ;

[0028] FIG7 f is a schematic diagram of the layout structure of the metal layer M2 in the layout structure shown in FIG5 ;

[0029] FIG8 is a schematic diagram of a partial layout structure of another display panel provided in an embodiment of the present application;

[0030] FIG9 a is a schematic diagram of the layout structure of the metal layer M3 in the layout structure shown in FIG8 ;

[0031] FIG9 b is a schematic diagram of the layout structure of the metal layer M4 in the layout structure shown in FIG8 ;

[0032] FIG9 c is a schematic diagram of the layout structure of the metal layer RE in the layout structure shown in FIG8 ;

[0033] FIG10 is a schematic diagram of a partial layout structure of another display panel provided in an embodiment of the present application;

[0034] FIG11a is a schematic diagram of the layout structure of the active layer poly in the layout structure shown in FIG10;

[0035] FIG11 b is a schematic diagram of the layout structure of the metal layer M1 in the layout structure shown in FIG10 ;

[0036] FIG11c is a schematic diagram of the layout structure of the metal layer MC in the layout structure shown in FIG10;

[0037] FIG11d is a schematic diagram of the layout structure of the oxide layer IGZO in the layout structure shown in FIG10;

[0038] FIG11e is a schematic diagram of the layout structure of the metal layer MG in the layout structure shown in FIG10;

[0039] FIG11f is a schematic diagram of the layout structure of the metal layer M2 in the layout structure shown in FIG10 ;

[0040] FIG12 is a schematic diagram of a partial layout structure of another display panel provided in an embodiment of the present application;

[0041] FIG13a is a schematic diagram of the layout structure of the active layer poly in the layout structure shown in FIG12;

[0042] FIG13 b is a schematic diagram of the layout structure of the metal layer M1 in the layout structure shown in FIG12 ;

[0043] FIG13c is a schematic diagram of the layout structure of the metal layer MC in the layout structure shown in FIG12;

[0044] FIG13 d is a schematic diagram of the layout structure of the oxide layer IGZO in the layout structure shown in FIG12 ;

[0045] FIG13e is a schematic diagram of the layout structure of the metal layer MG in the layout structure shown in FIG12;

[0046] FIG13f is a schematic diagram of the layout structure of the metal layer M2 in the layout structure shown in FIG12;

[0047] FIG14 is a schematic top view of another display panel provided in an embodiment of the present application;

[0048] FIG15 is a schematic diagram of a partial layout structure of a stack consisting of a metal layer M3, a metal layer M4, and a metal layer RE in a display panel provided in an embodiment of the present application;

[0049] FIG16 is a schematic diagram of a partial layout structure of a stack consisting of another metal layer M3, a metal layer M4, and a metal layer RE in a display panel provided in an embodiment of the present application;

[0050] FIG17 is a schematic top view of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0052] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0053] Secondly, this application is described in detail with reference to schematic diagrams. When describing the embodiments of this application, for ease of explanation, cross-sectional views of device structures may be partially enlarged and not to scale. Furthermore, these schematic diagrams are merely illustrative and should not limit the scope of protection of this application. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0054] FIG1 shows a schematic cross-sectional structure diagram of a display panel provided in an embodiment of the present application. As shown in FIG1 , the display panel includes a substrate 10 and a pixel circuit 20 and a signal line 30 located on one side of the substrate 10 , and also includes a light-emitting element 40 .

[0055] Figure 2 shows a partial top view schematic diagram of a display panel provided by an embodiment of the present application. As shown in Figure 2, in the display panel, the pixel circuit 20 includes a driving transistor T3, a bias transistor T8 and a gate initialization transistor T5, the signal line 30 includes a bias signal line DVH and a first reference signal line Vref1, the bias transistor T8 is electrically connected between at least one of the first electrode p31 and the second electrode p32 of the driving transistor T3 and the bias signal line DVH, and the gate initialization transistor T5 is electrically connected between the gate g3 of the driving transistor T3 and the first reference signal line Vref1.

[0056] It will be understood that the signal line 30 is configured to provide a voltage signal and / or a current signal to the pixel circuit 20; the pixel circuit 20 is configured to drive the light-emitting element 40 to emit light for display, and to control the brightness of the light-emitting element. For example, the display panel includes the pixel circuit 20 and the light-emitting element 40 arranged in an array. The pixel circuit 20 drives different light-emitting elements 40 to emit light and display according to the target brightness, so that the display panel displays the target image.

[0057] Specifically, as shown in FIG2 , the first electrode p81 of the bias transistor T8 is electrically connected to the bias signal line DVH, and the second electrode p82 of the bias transistor T8 is electrically connected to at least one of the first electrode p31 and the second electrode p32 of the drive transistor T3. That is, the second electrode p82 of the bias transistor T8 may be electrically connected only to the first electrode p31 of the drive transistor T3, or the second electrode p82 of the bias transistor T8 may be electrically connected only to the second electrode p32 of the drive transistor T3, or the second electrode p82 of the bias transistor T8 may be electrically connected to both the first electrode p31 and the second electrode p32 of the drive transistor T3. FIG2 only illustrates the case where the second electrode p82 of the bias transistor T8 is electrically connected to the first electrode p31 of the drive transistor T3.

[0058] When the bias transistor T8 is turned on, the bias transistor T8 can transmit the adjustment signal transmitted on the bias signal line DVH to the first electrode p31 and / or the second electrode p32 of the driving transistor T3, thereby biasing the first electrode p31 and / or the second electrode p32 of the driving transistor T3, improving the brightness of the first frame during image display, avoiding excessively low brightness in the first frame, and ensuring good consistency in the image display effect. In addition, before resetting the gate g3 of the driving transistor T3, by controlling the bias transistor T8 to be turned on, the bias voltage provided by the bias signal line DVH can be written to the first electrode p31 and / or the second electrode p32 of the driving transistor T3, refreshing the potential of the first electrode p31 and / or the second electrode p32 of the driving transistor T3, setting the device characteristics of the driving transistor T3 to a certain initial state, and eliminating the influence of the data signal written in the previous frame on the device characteristics of the driving transistor T3. After the data voltage is written to the driving transistor T3, the voltage of the first electrode p31 and / or the second electrode p32 of the driving transistor T3 will leak, especially under low-frequency driving, the leakage is more obvious, resulting in a large offset in the potential of the first electrode p31 and / or the second electrode p32 of the driving transistor T3. At this time, by controlling the bias transistor T8 to turn on and using the bias transistor T8 to write the bias voltage to the first electrode p31 and / or the second electrode p32 of the driving transistor T3, the bias state of the driving transistor T3 can be maintained consistent with the bias state when the data voltage is just written, thereby improving the stability of the working state of the driving transistor T3, improving low-frequency flicker, and thus improving the picture display effect of the display panel.

[0059] As shown in FIG2 , a first electrode p51 of the gate initialization transistor T5 is electrically connected to the first reference signal line Vref1, and a second electrode p52 of the gate initialization transistor T5 is electrically connected to the gate g3 of the driving transistor T3. When the gate initialization transistor T5 is turned on, the gate initialization transistor T5 can transmit the reference signal transmitted on the first reference signal line Vref1 to the gate g3 of the driving transistor T3, thereby initializing (also called resetting) the gate g3 of the driving transistor T3.

[0060] As shown in FIG2 , the bias signal line DVH includes a first sub-bias signal line DVH1 extending along a first direction X and arranged along a second direction Y, and a second sub-bias signal line DVH2 extending along the second direction Y and arranged along the first direction X. The first direction X and the second direction Y intersect, and the first sub-bias signal line DVH1 and the second sub-bias signal line DV2 are electrically connected.

[0061] Exemplarily, there may be multiple first sub-bias signal lines DVH1 and multiple second sub-bias signal lines DVH2, and the multiple first sub-bias signal lines DVH1 and the multiple second sub-bias signal lines DVH2 may intersect at multiple locations. Electrically connecting the first sub-bias signal lines DVH1 and the second sub-bias signal lines DVH2 includes: electrically connecting the first sub-bias signal lines DVH1 and the second sub-bias signal lines DVH2 at all of their intersections, as shown in FIG2 ; or electrically connecting the first sub-bias signal lines DVH1 and the second sub-bias signal lines DVH2 at some of their intersections. Specifically, each first sub-bias signal line DVH1 may be electrically connected to at least one second sub-bias signal line DVH2, and each second sub-bias signal line DVH2 may be electrically connected to at least one first sub-bias signal line DVH1.

[0062] As shown in FIG2 , the first reference signal line Vref1 includes a first sub-reference signal line Vref11 extending along the first direction X and arranged along the second direction Y, and a second sub-reference signal line Vref12 extending along the second direction Y and arranged along the first direction X. The first sub-reference signal line Vref11 and the second sub-reference signal line Vref12 are electrically connected.

[0063] Exemplarily, there may be multiple first sub-reference signal lines Vref11 and multiple second sub-reference signal lines Vref12, and the multiple first sub-reference signal lines Vref11 and the multiple second sub-reference signal lines Vref12 may intersect at multiple locations. Electrically connecting the first sub-reference signal line Vref11 and the second sub-reference signal line Vref12 includes: electrically connecting the first sub-reference signal line Vref11 and the second sub-reference signal line Vref12 at all intersections, as shown in FIG2 ; or electrically connecting the first sub-reference signal line Vref11 and the second sub-reference signal line Vref12 at some intersections. Specifically, each first sub-reference signal line Vref11 may be electrically connected to at least one second sub-reference signal line Vref12, and each second sub-reference signal line Vref12 may be electrically connected to at least one first sub-reference signal line Vref11.

[0064] In some embodiments, as shown in FIG2 , the first direction X is perpendicular to the second direction Y. For example, the first direction X is a row direction, and the second direction Y is a column direction. In other embodiments, the first direction X and the second direction Y may not be perpendicular, and may form an angle greater than 0 degrees and less than 90 degrees.

[0065] It can be understood that the bias signal line DVH and the first reference signal line Vref1 are insulated, that is, the first sub-bias signal line DVH1 in the bias signal line DVH is insulated from the first sub-reference signal line Vref1 and the second sub-reference signal line Vref2 in the first reference signal line Vref1, and the second sub-bias signal line DVH2 in the bias signal line DVH is also insulated from the first sub-reference signal line Vref1 and the second sub-reference signal line Vref2 in the first reference signal line Vref1; similarly, the first sub-reference signal line Vref11 in the first reference signal line Vref1 is insulated from the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 in the bias signal line DVH, and the second sub-reference signal line Vref12 in the first reference signal line Vref1 is also insulated from the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 in the bias signal line DVH.

[0066] It can be seen that the display panel provided in the embodiment of the present application forms a grid structure of bias signal lines DVH by providing the bias signal line DVH including a first sub-bias signal line DVH1 and a second sub-bias signal line DVH2 extending in different directions and electrically cross-connected, thereby reducing the overall resistance of the bias signal line DVH, thereby reducing the power consumption of the bias signal line DVH, and improving the signal transmission stability of the bias signal line DVH, which is beneficial to improving the display uniformity and other display effects of the display panel; similarly, by providing the first reference signal line Vref1 including a first sub-reference signal line Vref11 and a second sub-reference signal line Vref12 extending in different directions and electrically cross-connected, a grid structure of first reference signal lines Vref1 is also formed, thereby reducing the overall resistance of the first reference signal line Vref1, thereby reducing the power consumption of the first reference signal line Vref1, and improving the signal transmission stability of the first reference signal line Vref1, which is beneficial to improving the display uniformity and other display effects of the display panel.

[0067] For example, Figures 3 and 4 respectively show structural schematic diagrams of two pixel circuits 20 in the display panel provided in an embodiment of the present application. As shown in Figures 3 and 4, the pixel circuit 20 includes a first light-emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a compensation transistor T4, a gate initialization transistor T5, a second light-emitting control transistor T6, an anode initialization transistor T7, a bias transistor T8 and a storage capacitor Cst. The signal line 30 includes a scan signal line, a reference signal line, a power signal line and a data signal line DL. The scan signal line includes a first scan signal line S1, a second scan signal line S2, a third scan signal line SP*, a bias control signal line SP and a light-emitting control signal line EMIT; the reference signal line includes at least one of a first reference signal line Vref1 and a second reference signal line Vref2; and the power signal line includes a first power signal line PVDD and a second power signal line PVEE.

[0068] The first electrode of the first light emitting control transistor T1 is electrically connected to the first power signal line PVDD, the second electrode of the first light emitting control transistor T1 is electrically connected to the second node N2, and the gate of the first light emitting control transistor T2 is electrically connected to the light emitting control signal line EMIT;

[0069] A first electrode of the data writing transistor T2 is electrically connected to the data signal line DL, a second electrode of the data writing transistor T2 is electrically connected to the second node N2, and a gate of the data writing transistor T2 is electrically connected to the third scanning signal line SP*.

[0070] A first electrode of the driving transistor T3 is electrically connected to the second node N2, a second electrode of the driving transistor T3 is electrically connected to the third node N3, and a gate of the driving transistor T3 is electrically connected to the first node N1;

[0071] A first electrode of the compensation transistor T4 is electrically connected to the third node N3 , a second electrode of the compensation transistor T4 is electrically connected to the first node N1 , and a gate of the compensation transistor T4 is electrically connected to the second scan signal line S2 .

[0072] A first electrode of the gate initialization transistor T5 is electrically connected to the first reference signal line Vref1 , a second electrode of the gate initialization transistor T5 is electrically connected to the first node N1 , and a gate of the gate initialization transistor T5 is electrically connected to the first scan signal line S1 .

[0073] A first electrode of the second light emitting control transistor T6 is electrically connected to the third node N3, a second electrode of the second light emitting control transistor T6 is electrically connected to the sixth node N6, and a gate of the second light emitting control transistor T6 is electrically connected to the light emitting control signal line EMIT;

[0074] A first electrode of the anode initialization transistor T7 is electrically connected to the second reference signal line Vref2, a second electrode of the anode initialization transistor T7 is electrically connected to the sixth node N6, and a gate of the anode initialization transistor T7 is electrically connected to the bias control signal line SP;

[0075] A first electrode of the bias transistor T8 is electrically connected to the bias signal line DVH, a second electrode of the bias transistor T8 is electrically connected to the second node N2, and a gate of the bias transistor T8 is electrically connected to the bias control signal line SP;

[0076] The first plate of the storage capacitor Cst is electrically connected to the first node N1, and the second plate of the storage capacitor Cst is electrically connected to the first power signal line PVDD;

[0077] Thus, the pixel driving circuit 20 with an 8T1C structure is realized.

[0078] It can be understood that the first node N1, the second node N2, the third node N3 and the fourth node N4 may be virtually existing connection nodes or actually existing connection nodes.

[0079] It should be noted that the pixel circuit 20 shown in FIG3 and FIG4 is only an example. In actual applications, pixel circuits 20 with other circuit structures can be selected based on needs and are not limited to the 8T1C pixel circuits shown in FIG3 and FIG4.

[0080] It should also be noted that the first reference signal line Vref1 and the second reference signal line Vref2 can transmit the same reference signal, that is, a single reference signal can be used to reset nodes N1 and N6. Alternatively, the first reference signal line Vref1 and the second reference signal line Vref2 can transmit different reference signals, that is, the reset voltage of node N1 can be different from the reset voltage of node N6. This is not limited in this application and will be determined based on specific circumstances.

[0081] As shown in Figures 1, 3 and 4, each thin film transistor in the pixel circuit 20 can be a low-temperature polycrystalline silicon (LTPS) thin film transistor Qx. Specifically, the LTPS thin film transistor Qx includes an active layer b1, a gate g, a source electrode s1 and a drain electrode d1. It can also be an indium gallium zinc oxide (IGZO) thin film transistor Qy. Specifically, the IGZO thin film transistor Qy includes an oxide layer b2, a bottom gate dg, a top gate tg, a source electrode s2 and a drain electrode d2.

[0082] As shown in FIG. 3 and FIG. 4 , the compensation transistor T4 and the gate initialization transistor T5 may be dual-gate transistors to reduce leakage current of the transistors and improve the display effect of the display panel.

[0083] Optionally, as shown in Figures 1 and 3 , in the pixel circuit 20, the compensation transistor T4 and the gate initialization transistor T5 can be IGZO thin-film transistors having a dual-gate structure with a bottom gate dg and a top gate tg, and the other thin-film transistors can be LTPS thin-film transistors. Since the IGZO thin-film transistors have low leakage, the pixel circuit 20 can achieve low-frequency drive, that is, a low-frequency pixel circuit. In this case, all thin-film transistors in the pixel circuit 20 can be PMOS thin-film transistors, but this application does not limit this and the specific situation depends on the circumstances.

[0084] Alternatively, as shown in conjunction with FIG1 and FIG4 , each thin-film transistor in the pixel circuit 20 may also be an LTPS thin-film transistor. The compensation transistor T4 may include two sub-transistors T41 and T42 connected in series, thereby having a dual-gate structure. The junction of sub-transistors T41 and T42 forms the intermediate node N4 of the compensation transistor T4. Similarly, the gate initialization transistor T5 may include two sub-transistors T51 and T52 connected in series, thereby having a dual-gate structure. The junction of sub-transistors T51 and T52 forms the intermediate node N5 of the gate initialization transistor T5. In this case, the compensation transistor T4 and the gate initialization transistor T5 may be NMOS thin-film transistors, and the other thin-film transistors may be PMOS thin-film transistors. However, this is not limited in this application and will be determined based on specific circumstances.

[0085] FIG4a shows a timing diagram of an implementation method of a signal provided to the pixel circuit shown in FIG4 within a driving cycle provided by an embodiment of the present application. In combination with FIG4 and FIG4a, the compensation transistor T4 and the gate initialization transistor T5 are both NMOS thin film transistors, and the other transistors are all PMOS thin film transistors. The enable level can turn on the transistor, and the disable level can turn off (or cut off) the transistor. The enable level of the scanning signal VS1 provided by the first scanning signal line S1 and the scanning signal VS2 provided by the second scanning signal line S2 is a high level, and the disable level is a low level; the enable level of the scanning signal VSP* provided by the third scanning signal line SP*, the bias control signal VSP provided by the bias control signal line SP, and the light-emitting control signal VEMIT provided by the light-emitting control signal line EMIT are low levels, and the disable level is high.

[0086] Specifically, a driving cycle of the pixel circuit 10 in a low-frequency state is divided into a data writing phase P1 and a light-emitting holding phase P2. The data writing phase P1 is further divided into four periods t1-t4, wherein in period t1, the scanning signal VS2 is at an enable level, the compensation transistor T4 is turned on, and the bias control signal VSP is at an enable level, the anode initialization transistor T7 and the bias transistor T8 are turned on, and the bias voltage provided by the bias signal line DVH can be written into the first electrode and / or the second electrode of the driving transistor T3, and the potential of the first electrode and / or the second electrode of the driving transistor T3 is refreshed, so that the device characteristics of the driving transistor T3 are set to a certain initial state, eliminating the influence of the data signal written in the previous frame on the device characteristics of the driving transistor T3, and resetting the anode of the light-emitting element 40; in period t2, the scanning signal VS1 is at an enable level, the gate initialization transistor T5 is turned on, and the reference signal provided by the first reference signal line Vref1 can be transmitted to the gate of the driving transistor T3, resetting the gate of the driving transistor T3, and then The post-scan signal VS2 is at an enable level, the compensation transistor T4 is turned on, and the driving transistor T3 is diode-connected through the turned-on compensation transistor T4; in the t3 period, the scan signal VS2 is at an enable level, the compensation transistor T4 is turned on, and the scan signal VSP* is at an enable level, the data writing transistor T2 is turned on, so that the data signal transmitted by the data signal line DL is written to the gate of the driving transistor T2 (also called the threshold capture of the driving transistor T3); in the t4 stage, the bias control signal VSP is at an enable level, the anode initialization transistor T7 and the bias transistor T8 are turned on, and the bias transistor T8 is used to write a bias voltage to the first electrode and / or the second electrode of the driving transistor T3, so that the bias state of the driving transistor T3 can be maintained consistent with the bias state when the data voltage is just written, so as to improve the stability of the working state of the driving transistor T3, improve low-frequency flicker, and reset the anode of the light-emitting element 40. In the light-emission maintaining phase P2 , when the light-emission control signal VEMIT is at the enable level, the first light-emission control transistor T1 and the second light-emission control transistor T6 are turned on, and the driving transistor T3 drives the light-emitting element 40 to emit light.

[0087] As can be seen, the data write phase P1 includes a non-enable level phase of the light-emission control signal VEMIT. During the light-emission hold phase P2, the light-emission control signal VEMIT includes multiple non-enable level phases and multiple non-enable level phases. During the data write phase P1, the scan signal VS2 includes at least one enable level phase to transmit the data signal to the gate of the drive transistor T3. During the light-emission hold phase P2, the scan signal VS2 is at a low level, controlling the compensation transistor T4 to be turned off. It is understood that during the light-emission hold phase P2, the two enable level phases of VSP corresponding to one non-enable level phase of VEMIT in Figure 4 can be adjusted to one, and the duration of this enable level phase can be increased or decreased relative to the duration of one enable level phase of VSP during the data write phase P1. The frequency of the light-emission control signal VEMIT is greater than the frequency of the scan signal VS2.

[0088] In practice, when a display panel requires a different refresh rate, the duration of the light-maintaining phase P2 can be appropriately adjusted. When a high-frequency drive mode is required, the display panel can have only the data-writing phase P1, without the light-maintaining phase P2, in contrast to a low-frequency drive mode. This shortens the duration of the light-maintaining phase P2 as much as possible. For example, except for maintaining a non-enabled level for VEMIT adjacent to the data-writing phase P1, the remaining time period in the light-maintaining phase P2 can be discontinued, allowing the next data-writing phase P1 to be entered again.

[0089] It should be noted that Figure 1 is a schematic diagram of the film layer stacking structure of a display panel, showing the pixel circuit 20 including an LTPS thin-film transistor and an IGZO thin-film transistor as an example. It can be seen that the display panel includes a substrate 10, an active layer poly located on one side of the substrate 10, a multi-layer metal layer located on the side of the active layer poly away from the substrate 10, and an oxide layer IGZO, wherein the multi-layer metal layer includes a metal layer M1, a metal layer MC, a metal layer MG, a metal layer M2, a metal layer M3, a metal layer M4 and a metal layer RE arranged in a direction away from the substrate 10, and the oxide layer IGZO is located between the metal layer MC and the metal layer MG, and different metal layers, between the metal layer and the active layer, and between the metal layer and the oxide layer are all isolated by an insulating layer.

[0090] On this basis, FIG5 shows a schematic diagram of a partial layout structure of a display panel provided by an embodiment of the present application, including the layout structure of the active layer poly, metal layer M1, metal layer MC, metal layer MG, and metal layer M2. To clearly distinguish different pixel circuit regions, FIG5 uses horizontal and vertical dashed lines to represent the boundaries between adjacent pixel circuit regions along the first direction X and the second direction Y. It is understood that these boundaries are only for ease of explanation and do not serve as a limitation on the pixel circuit 20. Similar situations in other figures of the present application will not be repeated.

[0091] For clarity of the illustration, Figure 6 shows a partially enlarged schematic diagram of the layout structure shown in Figure 5, Figure 7a shows a schematic diagram of the layout structure of the active layer poly in the layout structure shown in Figure 5, Figure 7b shows a schematic diagram of the layout structure of the metal layer M1 in the layout structure shown in Figure 5, Figure 7c shows a schematic diagram of the layout structure of the metal layer MC in the layout structure shown in Figure 5, Figure 7d shows a schematic diagram of the layout structure of the oxide layer IGZO in the layout structure shown in Figure 5, Figure 7e shows a schematic diagram of the layout structure of the metal layer MG in the layout structure shown in Figure 5, and Figure 7f shows a schematic diagram of the layout structure of the metal layer M2 in the layout structure shown in Figure 5.

[0092] Figure 8 shows a schematic diagram of a partial layout structure of another display panel provided in an embodiment of the present application, including the layout structures of metal layers M3, M4, and RE. For clarity, Figure 9a shows a schematic diagram of the layout structure of metal layer M3 in the layout structure shown in Figure 8, Figure 9b shows a schematic diagram of the layout structure of metal layer M4 in the layout structure shown in Figure 8, and Figure 9c shows a schematic diagram of the layout structure of metal layer RE in the layout structure shown in Figure 8.

[0093] As shown in Figures 5 and 6, the pixel circuit 20 includes a driving transistor T3, a bias transistor T8, and a gate initialization transistor T5. The signal line 30 includes a bias signal line DVH and a first reference signal line Vref1, wherein the bias signal line DVH includes a first sub-bias signal line DVH1 and a second sub-bias signal line DVH2, the first sub-bias signal line DVH1 extends along the first direction X and is arranged along the second direction Y, and the second sub-bias signal line DVH2 extends along the second direction Y and is arranged along the first direction X; the first reference signal line Vref1 includes a first sub-reference signal line Vref11 and a second sub-reference signal line Vref12, the first sub-reference signal line Vref11 extends along the first direction X and is arranged along the second direction Y, and the second sub-reference signal line Vref12 extends along the second direction Y and is arranged along the first direction X.

[0094] Optionally, the first bias sub-line DVH1 and the second bias sub-line DVH2 can be arranged in different layers, that is, the signal lines extending in different directions are located in different metal layers, to reduce the difficulty of routing signal lines within the same metal layer. For example, as shown in Figures 5, 6, 7e, and 7f, the first bias sub-line DVH1 can be located in metal layer MG, and the second bias sub-line DVH2 can be located in metal layer M2. The first bias sub-line DVH1 and the second bias sub-line DVH2 can be electrically connected through a via between metal layer MG and metal layer M2.

[0095] Optionally, the first sub-reference signal line Vref11 and the second sub-reference signal line Vref12 are disposed in different layers, that is, signal lines extending in different directions are located in different metal layers, to reduce the difficulty of routing signal lines within the same metal layer. For example, as shown in conjunction with Figures 5, 6, 7e, and 7f, the first sub-reference signal line Vref11 can be located in metal layer MG, and the second sub-reference signal line Vref12 can be located in metal layer M2. The first sub-reference signal line Vref11 and the second sub-reference signal line Vref12 can be electrically connected via a via between metal layer MG and metal layer M2.

[0096] Optionally, the first sub-bias signal line DVH1 and the first sub-reference signal line Vref11 can be arranged in the same layer, that is, the signal lines extending in the same direction (first direction X) can be located in the same metal layer, reducing film layer occupancy and facilitating a lightweight and thin design of the display panel.

[0097] Specifically, as shown in Figure 1, the display panel includes a substrate 10 and a first metal layer MG, an oxide layer IGZO and a second metal layer M2 arranged in a direction away from the substrate 10; in combination with Figures 5, 6 and 7c-7e, the gate initialization transistor T5 can be an oxide thin film transistor, that is, an IGZO thin film transistor, and the gate initialization transistor T5 includes a first channel region p5, a first bottom gate bg5 located on the side of the first channel region p5 close to the substrate 10, and a first top gate tg5 located on the side of the first channel region p5 away from the substrate 10, the first channel region p5 is located in the oxide layer IGZO, the first bottom gate bg5 is located in the first metal layer MC, and the first top gate tg5 is located in the second metal layer MG.

[0098] 5 , 6 , and 7 c - 7 e , the signal line 30 further includes a first scanning signal line S1 extending along the first direction X. The first scanning signal line S1 includes a first sub-scanning signal line S11 and a second sub-scanning signal line S12 transmitting the same scanning signal. The first sub-scanning signal line S11 is located in the first metal layer MC and extends along the first direction X. The second sub-scanning signal line S12 is located in the second metal layer MG and extends along the first direction X. In a direction perpendicular to the plane of the substrate 10, the first sub-scanning signal line S11, the second sub-scanning signal line S12, and the first channel region p5 of the gate initialization transistor T5 overlap. Optionally, in a direction perpendicular to the plane of the substrate 10, the portion where the oxide layer IGZO overlaps with both the first sub-scanning signal line S11 and the second sub-scanning signal line S12 is the first channel region p5 of the gate initialization transistor T5, and the portion of the first sub-scanning signal line S11 facing the first channel region p5 of the gate initialization transistor T5 is the first bottom gate bg5 of the gate initialization transistor T5, so that the first bottom gate bg5 of the gate initialization transistor T5 is electrically connected to the first sub-scanning signal line S11; the portion of the first channel region p5 of the gate initialization transistor T5 facing the second sub-scanning signal line S12 is the first top gate tg5 of the initial transistor T5, so that the first top gate tg5 of the initial transistor T5 is electrically connected to the second sub-scanning signal line S12, so that the first top gate tg5 and the first bottom gate bg5 of the initial transistor T5 are both electrically connected to the first scan signal line S1 and receive the same scan signal.

[0099] As shown in Figures 5, 6, and 7d, gate initialization transistor T5 further includes a first electrode p51 and a second electrode p52 connected to the first channel region p5. As shown in Figures 5, 6, and 7d-7f, the first electrode p51 of gate initialization transistor T5 is electrically connected to the first sub-reference signal line Vref11 located on metal layer MG via a connection portion L3 located on metal layer M2 and a connection portion K3 located on metal layer MG. The first electrode p51 of gate initialization transistor T5 can also be electrically connected to the second sub-reference signal line Vref12 located on metal layer M2 via a connection portion L4 located on metal layer M2.

[0100] As shown in Figures 5, 6, and 7a, the driving transistor T3 includes a channel region p3 located in the active layer poly, and a first electrode p31 and a second electrode p32 connected to the channel region p3. As shown in Figures 5, 6, 7a, and 7b, the driving transistor T3 also includes a gate g3 located in the metal layer M1. In a direction perpendicular to the plane of the substrate 10, the gate g3 of the driving transistor T3 at least partially overlaps with the channel region p3 of the driving transistor T3. As shown in Figures 5, 6, 7b, 7d, and 7f, the gate g3 of the driving transistor T3 is electrically connected to the second electrode p52 of the gate initialization transistor T5 via a connection portion J1 located in the metal layer M2.

[0101] 5 , 6 and 7 b , the signal line 30 further includes a bias control signal line SP. The bias control signal line SP is located in the metal layer M1 and extends along the first direction X.

[0102] As shown in Figures 5, 6, and 7a, bias transistor T8 includes a channel region p8 located in the active layer poly, and a first electrode p81 and a second electrode p82 connected to the channel region p8. As shown in Figures 5, 6, 7a, and 7b, the channel region p8 of bias transistor T8 at least partially overlaps with the bias control signal line SP in a direction perpendicular to the plane of substrate 10. Optionally, the portion where the active layer poly overlaps with the bias control signal line SP in a direction perpendicular to the plane of substrate 10 constitutes the channel region p8 of bias transistor T8, and the portion where the bias control signal line SP overlaps with the channel region p8 of bias transistor T8 constitutes the gate g8 of bias transistor T8, electrically connecting the gate g8 of bias transistor T8 to the bias control signal line SP.

[0103] As shown in Figures 5, 6, 7a, 7e and 7f, the first electrode p81 of the bias transistor T8 is electrically connected to the first sub-bias signal line DVH1 located on the metal layer MG through the connection portion L1 located on the metal layer M2 and the connection portion K1 located on the metal layer MG, and the first electrode p81 of the bias transistor T8 can also be electrically connected to the second sub-bias signal line DVH2 located on the metal layer M2 through the connection portion L1 and the connection portion L2 located on the metal layer M2; the second electrode p82 of the bias transistor T8 is electrically connected to the first electrode p31 of the driving transistor T3 through the connection portion J2 located on the metal layer M2.

[0104] It can be seen that, in combination with Figures 5, 6 and 7e, the first sub-bias signal line DVH1 and the first sub-reference signal line Vref11 can both be located in the second metal layer MG, and the two are insulated to avoid signal crosstalk. At this time, the first sub-bias signal line DVH1 and the first sub-reference signal line Vref11 are both in the same layer as the first top gate tg5 of the gate initialization transistor T5. Therefore, the first sub-bias signal line DVH1 and the first sub-reference signal line Vref11 need to be insulated from the first top gate tg5 of the gate initialization transistor T5.

[0105] It should be noted that, for the convenience of description, this application divides the part of each transistor located in the active layer poly into regions, and also divides the part of each transistor located in the oxide layer IGZO into regions. For example, the driving transistor T3 is located at the first pole p31 and the second pole p32 of the active layer poly, and the gate initialization transistor T5 is located at the first pole p51 and the second pole p32 of the oxide layer IGZO. However, it can be understood that this regional division is not intended to limit specific areas. Different names and marks are given only to better explain and illustrate the embodiments of this application.

[0106] Optionally, in combination with Figures 5, 6 and 7e, the pixel circuits 20 are arranged in an array along the first direction X and the second direction Y, with the first direction X being the row direction, the number of rows of the pixel circuits 20 is N10, the number of first sub-bias signal lines DVH1 is N11, and the number of first sub-reference signal lines Vref11 is N12, wherein N11≤N10, N12≤N10, and N10, N11 and N12 are all positive integers, that is, with the number of rows N10 of the pixel circuits 20 as a reference, the number of first sub-bias signal lines DVH1 can be equal to or less than the number of rows N10 of the pixel circuits 20, and the number of first sub-reference signal lines Vref11 can also be equal to or less than the number of rows N10 of the pixel circuits 20.

[0107] In some embodiments, in combination with Figures 5, 6 and 7e, for a row of pixel circuits 20, both a first sub-bias signal line DVH1 and a first sub-reference signal line Vref11 can be set accordingly. At this time, N11=N12=N10. Such a setting is beneficial to increasing the number of first sub-bias signal lines DVH1 and first sub-reference signal lines Vref11, reducing the resistance of the bias signal line DVH and the first reference signal line Vref1, and thereby reducing the power consumption of the bias signal line DVH and the first reference signal line Vref1, and improving the signal transmission stability of the bias signal line DVH and the first reference signal line Vref1.

[0108] In some other embodiments, a first sub-bias signal line DVH1 may be correspondingly provided for a part of the row pixel circuits 20, and a first sub-reference signal line Vref11 may be correspondingly provided for another part of the row pixel circuits 20. At this time, N11 < N10, N12 < N10. With such a setting, to a certain extent, the layout density of the first sub-bias signal line DVH1 and the first sub-reference signal line Vref11 extending in the same direction (the first direction X) is reduced, the layout space of the pixel circuit 20 is reduced, the pixel density of the display panel is increased, and it is convenient to achieve a high-resolution and high-definition display.

[0109] Optionally, along the second direction Y, the first sub-bias signal line DVH1 and the first sub-reference signal line Vref11 are alternately arranged. At this time, N11 + N12 ≤ N10, so that the distribution uniformity of the first sub-bias signal line DVH1 and the distribution uniformity of the first sub-reference signal line Vref11 can be improved. Furthermore, the wiring uniformity in the film layer can be improved, which is beneficial to improving the overall signal consistency of the display panel.

[0110] Among them, the first sub-bias signal line DVH1 and the first sub-reference signal line Vref11 may be alternately arranged according to a certain quantity ratio. For example, a single first sub-bias signal line DVH1 and a single first sub-reference signal line Vref11 are alternately arranged in sequence, and the quantity ratio may be 1:1; or, two first sub-bias signal lines DVH1 and a single first sub-reference signal line Vref11 are alternately arranged in sequence, and the quantity ratio may be 2:1; or they are alternately arranged according to other quantity ratios. The present application does not limit this, and it depends on the specific situation.

[0111] It should be noted that in the present application, that a row of pixel circuits 20 corresponds to one signal line 30 means that a row of pixel circuits 20 and one signal line 30 at least partially overlap in the direction perpendicular to the plane of the substrate 10. For example, that a row of pixel circuits 10 corresponds to one first sub-bias signal line DVH1 and one first sub-reference signal line Vref11 means that a row of pixel circuits 20 and one first sub-bias signal line DVH1 at least partially overlap in the direction perpendicular to the plane of the substrate 10, and a row of pixel circuits 20 and one first sub-reference signal line Vref11 at least partially overlap in the direction perpendicular to the plane of the substrate 10, which will not be elaborated here.

[0112] As shown in FIG1 , the display panel further includes a light-emitting element 40, which includes an anode RE, a light-emitting layer (not shown), and a cathode (not shown) arranged in a direction away from the substrate 10. As shown in FIG3-6 , the pixel circuit 20 further includes an anode initialization transistor T7, which is electrically connected to the anode RE of the light-emitting element 40. The signal line 30 further includes a bias control signal line SP, which is electrically connected to the gate of the anode initialization transistor T7 and to the gate of the bias transistor T8.

[0113] As shown in Figures 5, 6, 7a and 7b, the anode initialization transistor T7 includes a channel region p7 located in the active layer poly, the bias transistor T8 includes a channel region p8 located in the active layer poly, and the bias control signal line SP can be located in the metal layer M1 and extend along the first direction X. In a direction perpendicular to the plane of the substrate 10, the bias control signal line SP at least partially overlaps with the channel region p7 of the anode initialization transistor T7 and at least partially overlaps with the channel region p8 of the bias transistor T8. Optionally, in a direction perpendicular to the plane of the substrate 10, the portion where the bias control signal line SP overlaps with the channel region p7 of the anode initialization transistor T7 is the gate g7 of the anode initialization transistor T7, so that the bias control signal line SP is electrically connected to the gate of the anode initialization transistor T7; the portion where the bias control signal line SP overlaps with the channel region p8 of the bias transistor T8 is the gate g8 of the bias transistor T8, so that the bias control signal line SP is electrically connected to the gate g8 of the bias transistor T8.

[0114] As shown in Figures 5, 6, and 7a, the anode initialization transistor T7 further includes a first electrode p71 and a second electrode p72 connected to the channel region p7. As shown in Figures 7a, 7f, 8, and 9a-9c, the second electrode p72 of the anode initialization transistor T7 is electrically connected to the anode RE of the light-emitting element via a connection portion J3 located in the metal layer M2, a connection portion J4 located in the metal layer M3, and a connection portion J5 located in the metal layer M4.

[0115] 5 , 6 , 7 b and 7 f , the bias control signal line SP extends along the first direction X and is arranged in a different layer from the first sub-bias signal line DVH1; optionally, the bias control signal line SP is located in the metal layer M1, and the first sub-bias signal line DVH1 is located in the metal layer MG; in a direction perpendicular to the plane of the substrate 10, the first sub-bias signal line DVH1 at least partially overlaps with the bias control signal line SP.

[0116] It should be noted that because the bias control signal line SP is located in the metal layer M1 and the first sub-bias signal line DVH1 is located in the metal layer MG, and the metal layer M1 and the metal layer MG are separated by at least the metal layer MC, the oxide layer IGZO, and multiple insulating layers, even in a direction perpendicular to the plane of the substrate 10, the first sub-bias signal line DVH1 and the bias control signal line SP at least partially overlap, and the coupling between the first sub-bias signal line DVH1 and the bias control signal line SP is also relatively small, so that the signal transmitted by the first sub-bias signal line DVH1 and the signal transmitted by the bias control signal line SP do not interfere with each other. In addition, such an arrangement can greatly reduce the arrangement density of the signal lines extending along the first direction X, which is beneficial for reducing the layout space of the pixel circuit 20, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition display.

[0117] As shown in Figures 3 to 6, the pixel circuit 20 also includes a first light-emitting control transistor T1 and a second light-emitting control transistor T6, and the signal line 30 also includes a first power signal line PVDD and a light-emitting control signal line EMIT. The first light-emitting control transistor T1 is electrically connected between the first power signal line PVDD and the first electrode of the driving transistor T3, the second light-emitting control transistor T6 is electrically connected between the second electrode of the driving transistor T3 and the light-emitting element 40, and the light-emitting control signal line EMIT is electrically connected to the gate of the first light-emitting control transistor T1 and to the gate of the second light-emitting control transistor T6.

[0118] 5 , 6 , 7 a and 7 b , the first light emission control transistor T1 includes a channel region p1 located in the active layer poly, the second light emission control transistor T6 includes a channel region p6 located in the active layer poly, the light emission control signal line EMIT may be located in the metal layer M1 and extend along the first direction X, and in a direction perpendicular to the plane of the substrate 10, the light emission control signal line EMIT at least partially overlaps with the channel region p1 of the first light emission control transistor T1 and at least partially overlaps with the channel region p6 of the second light emission control transistor T6. Optionally, in a direction perpendicular to the plane of the substrate 10, the portion where the light-emitting control signal line EMIT overlaps with the channel region p1 of the first light-emitting control transistor T1 is the gate g1 of the first light-emitting control transistor T1, so that the light-emitting control signal line EMIT is electrically connected to the gate g1 of the first light-emitting control transistor T1; the portion where the light-emitting control signal line EMIT overlaps with the channel region p6 of the second light-emitting control transistor T6 is the gate g6 of the second light-emitting control transistor T6, so that the light-emitting control signal line EMIT is electrically connected to the gate g6 of the second light-emitting control transistor T6.

[0119] 5 , 6 and 7 a , the first light emission control transistor T1 further includes a first electrode p11 and a second electrode p12 connected to the channel region p1 . The second electrode p12 of the first light emission control transistor T1 is directly electrically connected to the first electrode p31 of the driving transistor T3 in the active layer poly.

[0120] As shown in conjunction with Figures 5, 6, and 7a, the second light-emission control transistor T6 further includes a first electrode p61 and a second electrode p62 connected to the channel region p6. The first electrode p61 of the second light-emission control transistor T6 is directly electrically connected to the second electrode p32 of the driving transistor T3 in the active layer poly. The second electrode p62 of the second light-emission control transistor T6 is also directly electrically connected to the second electrode p72 of the anode initialization transistor T7 in the active layer poly. Furthermore, as shown in conjunction with Figures 7a, 7f, 8, and 9a-9c, the second electrode p62 of the second light-emission control transistor T6 and the second electrode p72 of the anode initialization transistor T7 are both electrically connected to the anode RE of the light-emitting element via a connection portion J3 located in the metal layer M2, a connection portion J4 located in the metal layer M3, and a connection portion J5 located in the metal layer M4.

[0121] 5 , 6 , 7 b and 7 f , the light-emitting control signal line EMIT extends along the first direction X and is provided in a different layer from the first sub-reference signal line Vref11; optionally, the light-emitting control signal line EMIT is located in the metal layer M1, and the first sub-reference signal line Vref11 is located in the metal layer MG; in a direction perpendicular to the plane of the substrate 10, the first sub-reference signal line Vref11 at least partially overlaps with the light-emitting control signal line EMIT.

[0122] It should be noted that, since the light-emitting control signal line EMIT is located in the metal layer M1 and the first sub-reference signal line Vref11 is located in the metal layer MG, and the metal layer M1 and the metal layer MG are separated by at least the metal layer MC, the oxide layer IGZO, and multiple insulating layers, even in a direction perpendicular to the plane of the substrate 10, the first sub-reference signal line Vref11 at least partially overlaps with the light-emitting control signal line EMIT, and the coupling between the first sub-reference signal line Vref11 and the light-emitting control signal line EMIT is also small, so that the signal transmitted by the first sub-reference signal line Vref11 and the signal transmitted by the light-emitting control signal line EMIT do not interfere with each other. In addition, such a configuration can greatly reduce the arrangement density of the signal lines extending along the first direction X, which is conducive to reducing the layout space of the pixel circuit 20, increasing the pixel density of the display panel, and achieving high-resolution and high-definition display.

[0123] Furthermore, optionally, the second sub-bias signal line DVH2 and the second sub-reference signal line Vref12 can also be arranged in the same layer. That is, the signal lines extending in the same direction (the first direction Y) can be located in the same metal layer, reducing the film layer occupation and facilitating the thinning design of the display panel. For example, as shown in FIGS. 5, 6, and 7f, both the second sub-bias signal line DVH2 and the second sub-reference signal line Vref12 can be located in the metal layer M2, and the two are insulated from each other to avoid signal crosstalk.

[0124] Similar to the first sub-bias signal line DVH1 and the first sub-reference signal line Vref11 that are insulated in the same layer, the pixel circuits 20 are arranged in an array along the first direction X and the second direction Y. Taking the second direction Y as the column direction, the number of columns of the pixel circuits 20 is N20, the number of the second sub-bias signal lines DVH2 is N21, and the number of the second sub-reference signal lines Vref12 is N22. Among them, N21≤N20, N22≤N10, and N20, N21, and N22 are all positive integers. That is, taking the number of columns N20 of the pixel circuits 20 as a reference, the number of the second sub-bias signal lines DVH2 can be equal to or less than the number of columns N20 of the pixel circuits 20, and the number of the second sub-reference signal lines Vref12 can also be equal to or less than the number of columns N20 of the pixel circuits 20.

[0125] In some embodiments, for one column of pixel circuits 20, one second sub-bias signal line DVH2 and one second sub-reference signal line Vref12 can be correspondingly provided. At this time, N21 = N22 = N20. Such a setting is beneficial to increasing the number of the second sub-bias signal line DVH2 and the second sub-reference signal line Vref12, reducing the resistance of the bias signal line DVH and the first reference signal line Vref1, thereby reducing the power consumption of the bias signal line DVH and the first reference signal line Vref1, and improving the signal transmission stability of the bias signal line DVH and the first reference signal line Vref1.

[0126] In some other embodiments, some columns of pixel circuits 20 can be correspondingly provided with the second sub-bias signal line DVH2, and some other columns of pixel circuits 20 can be correspondingly provided with the second sub-reference signal line Vref12. At this time, N21 < N20, N22 < N20. Such a setting reduces the arrangement density of the second sub-bias signal line DVH2 and the second sub-reference signal line Vref12 extending in the same direction (the second direction Y) to a certain extent, which is beneficial to reducing the layout space of the pixel circuits 20, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition displays.

[0127] Optionally, along the first direction X, the second sub-bias signal line DVH2 and the second sub-reference signal line Vref12 are alternately arranged. At this time, N21+N22≤N20, thereby improving the distribution uniformity of the second sub-bias signal line DVH2 and the distribution uniformity of the second sub-reference signal line Vref12, thereby improving the wiring uniformity within the film layer, which is beneficial to improving the overall signal consistency of the display panel.

[0128] Among them, the second sub-bias signal line DVH2 and the second sub-reference signal line Vref12 can be arranged alternately according to a certain quantity ratio; for example, a single second sub-bias signal line DVH2 and a single second sub-reference signal line Vref12 are arranged alternately in sequence, and the quantity ratio can be 1:1; or, two second sub-bias signal lines DVH2 and a single second sub-reference signal line Vref12 are arranged alternately in sequence, and the quantity ratio can be 2:1; or they are arranged alternately according to other quantity ratios, which are not limited in this application and depend on the specific circumstances.

[0129] It should be noted that, in the present application, when a column of pixel circuits 20 is provided with a corresponding signal line 30, it means that a column of pixel circuits 20 and a signal line 30 at least partially overlap in a direction perpendicular to the plane of the substrate 10. For example, when a column of pixel circuits 10 is provided with a second sub-bias signal line DVH2 and a second sub-reference signal line Vref12, it means that a column of pixel circuits 20 and a second sub-bias signal line DVH2 at least partially overlap in a direction perpendicular to the plane of the substrate 10, and a column of pixel circuits 20 and a second sub-reference signal line Vref12 at least partially overlap in a direction perpendicular to the plane of the substrate 10. Detailed description is omitted.

[0130] As shown in FIG1 , the display panel further includes a light-emitting element 40, which includes an anode RE, a light-emitting layer (not shown), and a cathode (not shown) disposed in a direction away from the substrate 10. As shown in FIG3-6 , the pixel circuit 20 further includes an anode initialization transistor T7, and the signal line 30 further includes a second reference signal line Vref2. The anode initialization transistor T7 is electrically connected between the second reference signal line Vref2 and the anode RE of the light-emitting element 40.

[0131] As shown in Figures 5 and 6 , the second reference signal line Vref2 includes a third sub-reference signal line Vref21 extending along the first direction X and aligned along the second direction Y, and a fourth sub-reference signal line Vref22 extending along the second direction Y and aligned along the first direction X. The third sub-reference signal line Vref21 and the fourth sub-reference signal line Vref22 are electrically connected, thereby forming a grid structure of second reference signal lines Vref2. This reduces the overall resistance of the second reference signal line Vref2, thereby reducing power consumption of the second reference signal line Vref2 and improving signal transmission stability of the second reference signal line Vref2, thereby enhancing display uniformity and other display effects of the display panel. The bias signal line DVH, the first reference signal line Vref1, and the second reference signal line Vref2 are insulated from each other to prevent signal crosstalk.

[0132] Optionally, the third sub-reference signal line Vref21 and the fourth sub-reference signal line Vref22 are disposed in different layers, that is, the signal lines extending in different directions are located in different metal layers, to reduce the difficulty of routing signal lines within the same metal layer. For example, as shown in Figures 5, 6, 7c, and 7f, the third sub-reference signal line Vref21 can be located in metal layer MC, and the fourth sub-reference signal line Vref22 can be located in metal layer M2. The third sub-reference signal line Vref21 and the fourth sub-reference signal line Vref22 can be electrically connected via a via between metal layer MC and metal layer M2.

[0133] Therefore, in some embodiments, the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 are arranged in different layers, the first sub-reference signal line Vref11 and the second sub-reference signal line Vref12 are arranged in different layers, and the third sub-reference signal line Vref21 and the fourth sub-reference signal line Vref22 are arranged in different layers, that is, the signal lines extending in different directions are located in different metal layers to reduce the difficulty of laying out the signal lines in the same metal layer.

[0134] Optionally, the second sub-bias signal line DVH2, the second sub-reference signal line Vref12 and the fourth sub-reference signal line Vref22 are arranged in the same layer, that is, the signal lines extending along the same direction (first direction X) can be located in the same metal layer, reducing the film layer occupancy and facilitating the lightweight design of the display panel.

[0135] Specifically, as shown in Figures 5, 6, 7c, 7e and 7f, the third sub-reference signal line Vref21 can be located in the metal layer MC, the first sub-bias signal line DVH1 and the first sub-reference signal line Vref11 can both be located in the metal layer MG, and the second sub-bias signal line DVH2, the second sub-reference signal line Vref12 and the fourth sub-reference signal line Vref22 can all be located in the metal layer M2.

[0136] Optionally, as shown in FIGS. 5, 6, and 7f, the pixel circuits 20 are arranged in an array along the first direction X and the second direction Y. Taking the second direction Y as the column direction, the number of columns of the pixel circuits 20 is N20, the number of the second sub-bias signal lines DVH2 is N21, the number of the second sub-reference signal lines Vref12 is N22, and the number of the fourth sub-reference signal lines Vref22 is N23. Among them, N21≤N20, N22≤N20, N23≤N20, and N20, N21, N22, and N23 are all positive integers. That is, taking the number of columns N20 of the pixel circuits 20 as a reference, the number of the second sub-bias signal lines DVH2, N21, can be equal to or less than the number of columns N20 of the pixel circuits 20, the number of the second sub-reference signal lines Vref12, N22, can be equal to or less than the number of columns N20 of the pixel circuits 20, and the number of the fourth sub-reference signal lines Vref22, N23, can also be equal to or less than the number of columns N20 of the pixel circuits 20.

[0137] In some embodiments, for one column of pixel circuits 20, one second sub-bias signal line DVH2, one second sub-reference signal line Vref12, and one fourth sub-reference signal line Vref22 can be correspondingly provided. At this time, N21 = N22 = N23 = N10. With such a setting, it is beneficial to increase the number of the second sub-bias signal line DVH2, the second sub-reference signal line Vref12, and the fourth sub-reference signal line Vref22, reduce the resistance of the bias signal line DVH, the first reference signal line Vref1, and the second reference signal line Vref2, and further reduce the power consumption of the bias signal line DVH, the first reference signal line Vref1, and the second reference signal line Vref2, and improve the signal transmission stability of the bias signal line DVH, the first reference signal line Vref1, and the second reference signal line Vref2.

[0138] In some other embodiments, as shown in FIGS. 5, 6, and 7f, it is also possible that the second sub-bias signal line DVH2 is correspondingly provided for some columns of pixel circuits 20, the second sub-reference signal line Vref12 is correspondingly provided for some other columns of pixel circuits 20, and the fourth sub-reference signal line Vref22 is correspondingly provided for some other columns of pixel circuits 20. At this time, N21 < N20, N22 < N20, N23 < N20. With such a setting, the arrangement density of the second sub-bias signal line DVH2, the second sub-reference signal line Vref12, and the fourth sub-reference signal line Vref22 extending along the same direction (the second direction Y) is reduced to a certain extent, which is beneficial to reducing the layout space of the pixel circuits 20, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition displays.

[0139] Optionally, N21 + N22 + N23 ≤ N20. In some embodiments, as shown in FIGS. 5, 6, and 7f, each column of pixel circuits 20 is correspondingly provided with one of the second sub-bias signal line DVH2, the second sub-reference signal line Vref12, and the fourth sub-reference signal line Vref22. That is to say, according to the types of these three signal lines, namely the second sub-bias signal line DVH2, the second sub-reference signal line Vref12, and the fourth sub-reference signal line Vref22, one column of pixel circuits 20 is correspondingly provided with the second sub-bias signal line DVH2, or is correspondingly provided with the second sub-reference signal line Vref12, or is correspondingly provided with the fourth sub-reference signal line Vref22. Then, N21 + N22 + N23 = N20. With such a setting, the distances between the second sub-bias signal line DVH2, the second sub-reference signal line Vref12, and the fourth sub-reference signal line Vref22 can be relatively increased, and the mutual influence between these three signal lines can be reduced.

[0140] In other embodiments, in some columns of pixel circuits 20, each column of pixel circuits 20 is correspondingly provided with one of the second sub-bias signal line DVH2, the second sub-reference signal line Vref12, and the fourth sub-reference signal line Vref22, and in some other columns of pixel circuits 20, they are not correspondingly provided with the second sub-bias signal line DVH2, the second sub-reference signal line Vref12, and the fourth sub-reference signal line Vref22, but can be used to arrange signal lines for transmitting other signals. At this time, N21 + N22 + N23 < N20. With such a setting, the requirement of arranging signal lines with different functions in a limited film layer can be兼顾.

[0141] It should be noted that there is a small error in the original text. "兼顾满足" should be "兼顾". The corrected translation is provided above.5, 6 and 7f, each column of pixel circuits 20 is correspondingly provided with one of the second sub-bias signal line DVH2, the second sub-reference signal line Vref12 and the fourth sub-reference signal line Vref22. On this basis, considering that the light-emitting element 40 includes a first color light-emitting element 41, a second color light-emitting element 42 and a third color light-emitting element 43, as shown in FIG9c, the anode RE41 of the first color light-emitting element 41 represents the first color light-emitting element 41, the anode RE42 of the second color light-emitting element 42 represents the second color light-emitting element 42, and the anode RE43 of the third color light-emitting element 43 represents the third color light-emitting element 43. It can be seen that in order to meet the display requirements, the first color light-emitting elements 41 are arranged along the second direction to form a plurality of columns, which are named the first light-emitting element column 401, and the second ... The elements 42 and the third color light-emitting elements 43 are alternately arranged along the second direction Y to form multiple columns, which are named second light-emitting element columns 402. In addition, the first light-emitting element columns 401 and the second light-emitting element columns 402 are alternately arranged along the first direction X. In two adjacent second light-emitting element columns 402 along the first direction X, the second color light-emitting elements 42 in one second light-emitting element column 402 and the third color light-emitting elements 43 in the other second light-emitting element column 402 correspond to each other along the first direction X, and the third color light-emitting elements 43 in one second light-emitting element column 402 and the second color light-emitting elements 42 in the other second light-emitting element column 402 correspond to each other along the first direction X. Therefore, the two first light-emitting element columns 401 and the two second light-emitting element columns 402 arranged adjacent to each other along the first direction X, totaling four columns of light-emitting elements, constitute a pixel repeating unit.

[0142] Correspondingly, in combination with Figure 5 and Figure 9c, in two adjacent columns of pixel circuits 20, one column of pixel circuits 20 corresponds to driving the first color light-emitting elements 41, that is, corresponding to driving the first light-emitting element column 401, and the other column of pixel circuits 20 corresponds to driving the second color light-emitting elements 42 and the third color light-emitting elements 43, that is, corresponding to driving the second light-emitting element column 402. Since the two columns of first light-emitting element columns 401 and the two columns of second light-emitting element columns 402 arranged adjacent to each other along the first direction X, a total of four columns of light-emitting elements constitute a pixel repeating unit, the four columns of pixel circuits 20 arranged adjacent to each other along the first direction X also constitute a pixel circuit repeating unit.

[0143] Then, for four adjacent columns of pixel circuits 20, three columns of pixel circuits 20 can be respectively set with the second sub-bias signal line DVH2, the second sub-reference signal line Vref12 and the fourth sub-reference signal line Vref22, and the remaining column of pixel circuits 20 can be respectively set with one of the second sub-bias signal line DVH2, the second sub-reference signal line Vref12 and the fourth sub-reference signal line Vref22. Thus, among the four adjacent columns of pixel circuits 20, two columns of pixel circuits 20 are respectively set with the same type of second sub-bias signal line DVH2, second sub-reference signal line Vref12 and fourth sub-reference signal line Vref22, and the other two columns of pixel circuits 20 are respectively set with the other two types of second sub-bias signal line DVH2, second sub-reference signal line Vref12 and fourth sub-reference signal line Vref22.

[0144] That is to say, according to the types of the three signal lines, namely the second sub-bias signal line DVH2, the second sub-reference signal line Vref12 and the fourth sub-reference signal line Vref22, in some embodiments, in combination with Figures 5, 6 and 7f, in the four adjacent columns of pixel circuits 20, two columns of pixel circuits 20 are correspondingly provided with the fourth sub-reference signal line Vref22, and in the other two columns of pixel circuits 20, one column of pixel circuits 20 is correspondingly provided with the second sub-bias signal line DVH2, and the other column of pixel circuits 20 is correspondingly provided with the second sub-reference signal line Vref12.

[0145] Figure 10 shows a schematic diagram of a partial layout structure of another display panel provided in an embodiment of the present application, including the layout structure of an active layer poly, a metal layer M1, a metal layer MC, a metal layer MG, and a metal layer M2. For clarity, Figure 11a shows a schematic diagram of the layout structure of the active layer poly in the layout structure shown in Figure 10, Figure 11b shows a schematic diagram of the layout structure of the metal layer M1 in the layout structure shown in Figure 10, Figure 11c shows a schematic diagram of the layout structure of the metal layer MC in the layout structure shown in Figure 10, Figure 11d shows a schematic diagram of the layout structure of the oxide layer IGZO in the layout structure shown in Figure 10, Figure 11e shows a schematic diagram of the layout structure of the metal layer MG in the layout structure shown in Figure 10, and Figure 11f shows a schematic diagram of the layout structure of the metal layer M2 in the layout structure shown in Figure 10.

[0146] It can be seen that the three signal lines, namely the second sub-bias signal line DVH2, the second sub-reference signal line Vref12 and the fourth sub-reference signal line Vref22, are distinguished. In other embodiments, as shown in combination with Figures 10 and 11f, in four adjacent columns of pixel circuits 20, two columns of pixel circuits 20 are correspondingly provided with the second sub-bias signal line DVH2, and in the other two columns of pixel circuits 20, one column of pixel circuits 20 is correspondingly provided with the second sub-reference signal line Vref12, and the other column of pixel circuits 20 is correspondingly provided with the fourth sub-reference signal line Vref22.

[0147] Figure 12 shows a schematic diagram of a partial layout structure of another display panel provided in an embodiment of the present application, including the layout structure of the active layer poly, metal layer M1, metal layer MC, metal layer MG, and metal layer M2. For clarity, Figure 13a shows a schematic diagram of the layout structure of the active layer poly in the layout structure shown in Figure 12, Figure 13b shows a schematic diagram of the layout structure of the metal layer M1 in the layout structure shown in Figure 12, Figure 13c shows a schematic diagram of the layout structure of the metal layer MC in the layout structure shown in Figure 12, Figure 13d shows a schematic diagram of the layout structure of the oxide layer IGZO in the layout structure shown in Figure 12, Figure 13e shows a schematic diagram of the layout structure of the metal layer MG in the layout structure shown in Figure 12, and Figure 13f shows a schematic diagram of the layout structure of the metal layer M2 in the layout structure shown in Figure 12.

[0148] It can be seen that the three signal lines, namely the second sub-bias signal line DVH2, the second sub-reference signal line Vref12 and the fourth sub-reference signal line Vref22, are distinguished. In some further embodiments, as shown in combination with Figures 10 and 11f, in four adjacent columns of pixel circuits 20, two columns of pixel circuits 20 are correspondingly provided with the second sub-reference signal line Vref12, and in the other two columns of pixel circuits 20, one column of pixel circuits 20 is correspondingly provided with the second sub-bias signal line DVH2, and the other column of pixel circuits 20 is correspondingly provided with the fourth sub-reference signal line Vref22.

[0149] Further optionally, among the four adjacent columns of pixel circuits 20, two columns of pixel circuits 20 corresponding to the same type of the second sub-bias signal line DVH2, the second sub-reference signal line Vref12, and the fourth sub-reference signal line Vref22 are arranged in alternate columns, then two columns of pixel circuits 20 corresponding to the other two types of the second sub-bias signal line DVH2, the second sub-reference signal line Vref12, and the fourth sub-reference signal line Vref22 must also be arranged in alternate columns.

[0150] In some embodiments, in combination with Figures 5, 6 and 7f, among the four adjacent columns of pixel circuits 20, two columns of pixel circuits 20 are correspondingly provided with the fourth sub-reference signal line Vref22, and the other two columns of pixel circuits 20 are respectively correspondingly provided with the second sub-bias signal line DVH2 and the second sub-reference signal line Vref12. Moreover, the two columns of pixel circuits 20 corresponding to the fourth sub-reference signal line Vref22 are arranged in alternate columns. Therefore, the two columns of pixel circuits 20 corresponding to the second sub-bias signal line DVH2 and the second sub-reference signal line Vref12 must also be arranged in alternate columns.

[0151] In other embodiments, as shown in Figures 10 and 11f, among the four adjacent columns of pixel circuits 20, two columns of pixel circuits 20 are correspondingly provided with the second sub-bias signal line DVH2, and the other two columns of pixel circuits 20 are respectively correspondingly provided with the second sub-reference signal line Vref12 and the fourth sub-reference signal line Vref22. Moreover, the two columns of pixel circuits 20 corresponding to the second sub-bias signal line DVH2 are arranged in alternate columns. Therefore, the two columns of pixel circuits 20 corresponding to the second sub-reference signal line Vref12 and the fourth sub-reference signal line Vref22 must also be arranged in alternate columns.

[0152] In some further embodiments, in combination with Figures 12 and 13f, among the four adjacent columns of pixel circuits 20, two columns of pixel circuits 20 are correspondingly provided with the second sub-reference signal line Vref12, and the other two columns of pixel circuits 20 are respectively correspondingly provided with the second sub-bias signal line DVH2 and the fourth sub-reference signal line Vref22. Moreover, the two columns of pixel circuits 20 corresponding to the second sub-reference signal line Vref12 are arranged in alternate columns. Therefore, the two columns of pixel circuits 20 corresponding to the second sub-bias signal line DVH2 and the fourth sub-reference signal line Vref22 must also be arranged in alternate columns.

[0153] Further optionally, in four adjacent columns of pixel circuits 20 , two columns of pixel circuits 20 correspondingly provided with the same second sub-bias signal line DVH2 , second sub-reference signal line Vref12 and fourth sub-reference signal line Vref22 drive the first color light emitting element 41 .

[0154] As known above, four columns of light-emitting elements, namely, two columns of first light-emitting elements 401 and two columns of second light-emitting elements 402 arranged adjacent to each other along the first direction X, constitute a pixel repeating unit. Moreover, in a pixel repeating unit, the two columns of first light-emitting elements 401 (including the first color light-emitting elements 41 arranged along the second direction Y) are arranged identically. Therefore, in four adjacent columns of pixel circuits 20, two columns of pixel circuits 20 correspondingly provided with the same second sub-bias signal line DVH2, second sub-reference signal line Vref12, and fourth sub-reference signal line Vref22 drive the first color light-emitting elements 41. This allows the layout design of the pixel columns constituted by the first color light-emitting elements 41 and the pixel circuits 20 driving the first color light-emitting elements 41 to be identical, greatly reducing the difficulty of layout design.

[0155] Specifically, in some embodiments, in combination with Figures 5, 6 and 7f, among the four adjacent columns of pixel circuits 20, the two columns of pixel circuits 20 corresponding to the fourth sub-reference signal line Vref22 drive the first color light-emitting element 41, and the two columns of pixel circuits 20 corresponding to the second sub-bias signal line DVH2 and the second sub-reference signal line Vref12 drive the second color light-emitting element 42 and the third color light-emitting element 43.

[0156] In other embodiments, as shown in Figures 10 and 11f, among the four adjacent columns of pixel circuits 20, the two columns of pixel circuits 20 corresponding to the second sub-bias signal line DVH2 drive the first color light-emitting element 41, and the two columns of pixel circuits 20 corresponding to the second sub-reference signal line Vref12 and the fourth sub-reference signal line Vref22 drive the second color light-emitting element 42 and the third color light-emitting element 43.

[0157] In some further embodiments, in combination with Figures 12 and 12f, among the four adjacent columns of pixel circuits 20, the two columns of pixel circuits 20 corresponding to the second sub-reference signal line Vref12 drive the first color light-emitting element 41, and the two columns of pixel circuits 20 corresponding to the second sub-bias signal line DVH2 and the fourth sub-reference signal line Vref22 drive the second color light-emitting element 42 and the third color light-emitting element 43.

[0158] Optionally, the first color light emitting element 41 is a green light emitting element, the second color light emitting element 42 is a red light emitting element, and the third color light emitting element 43 is a blue light emitting element.

[0159] In the above embodiments, with the number of columns N20 of the pixel circuit 20 as a reference, the number N21 of the second sub-bias signal lines DVH2 can be equal to or less than the number N20 of the columns of the pixel circuit 20, the number N22 of the second sub-reference signal lines Vref12 can be equal to or less than the number N20 of the columns of the pixel circuit 20, and the number N23 of the fourth sub-reference signal lines Vref22 can also be equal to or less than the number N20 of the columns of the pixel circuit 20. Furthermore, in order to ensure that each pixel circuit 10 is electrically connected to the bias signal line DVH, the first reference signal line Vref1, and the second reference signal line Vref2, an optional 5 , 6 , and 7 e , as well as FIG10 and FIG11 e , and FIG12 and FIG12 e , each row of pixel circuits 20 is correspondingly provided with a first sub-bias signal line DVH1, a first sub-reference signal line Vref11, and a third sub-reference signal line Vref21. That is, with the number N10 of rows of pixel circuits 20 as a reference, the number N11 of the first sub-bias signal lines DVH1, the number N12 of the first sub-reference signal lines Vref11, and the number N13 of the third sub-reference signal lines Vref21 satisfy: N11=N12=N13=N10.

[0160] On this basis, the following describes how the sub-bias signal lines extending in different directions in the bias signal line DVH are electrically connected, and how they are electrically connected to the corresponding thin film transistors in the pixel circuit 20 .

[0161] In combination with Figures 5, 6, 7a, 7e and 7f, in combination with Figures 10, 11a, 11e and 11f, and in combination with Figures 12, 12a, 12e and 12f, the display panel further includes a plurality of first connection portions L1 arrayed along the first direction X and the second direction Y, the first connection portion L1 extending along the first direction X, and the first connection portion L1 and the first sub-bias signal line DVH1 are arranged in different layers; optionally, the first connection portion L1 is located in the metal layer M2, and the first sub-bias signal line DVH1 is located in the metal layer MG; the first sub-bias signal line DVH1 is electrically connected to the bias transistor T8 through the first connection portion L1, specifically, the first sub-bias signal line DVH1 located in the metal layer MG is electrically connected to the first electrode p81 of the bias transistor T8 through the connection portion K1 located in the metal layer MG, the first connection portion L1 located in the metal layer M2, and the connection portion K2 located in the active layer poly.

[0162] As shown in Figures 5, 6, 7a, 7e and 7f, the second sub-bias signal line DVH2 may further include a second connection portion L2 extending along the first direction X, the second connection portion L2 being electrically connected to the first connection portion L2 in the same layer, that is, the second connection portion L2 and the first connection portion L2 may both be located in the metal layer M2 and electrically connected to each other; the second sub-bias signal line DVH2 is electrically connected to the bias transistor T8 through the second connection portion L2 and the first connection portion L1 located in the metal layer M2, and the connection portion K2 located in the active layer poly. At the same time, the second sub-bias signal line DVH2 located in the metal layer M2 is electrically connected to the first sub-bias signal line DVH1 located in the metal layer MG through the second connection portion L2 located in the metal layer M2 and the connection portion K1 located in the metal layer MG.

[0163] In combination with Figures 10, 11a, 11e and 11f, and in combination with Figures 12, 13a, 13e and 13f, the second sub-bias signal line DVH2 located in the metal layer M2 can also be electrically connected to the first sub-bias signal line DVH1 located in the metal layer MG at a position where they overlap in a direction perpendicular to the plane of the substrate 10, and the second sub-bias signal line DVH2 located in the metal layer M2 can also be electrically connected to the first electrode p81 of the bias transistor T8 through the first connection portion L1 located in the metal layer M2 and the connection portion K2 located in the active layer poly.

[0164] The following describes how the sub-reference signal lines extending in different directions in the first reference signal line Vref1 are electrically connected, and how they are electrically connected to the corresponding thin film transistors in the pixel circuit 20 .

[0165] In combination with Figures 5, 6, 7d-7f, Figures 10, 11d-11f, and Figures 12, 12d-12f, the display panel also includes a plurality of third connection portions L3 arranged in an array along the first direction X and the second direction Y, the third connection portion L3 extends along the second direction Y, and the third connection portion L3 and the first sub-reference signal line Vref11 are arranged in a different layer; optionally, the third connection portion L2 is located in the metal layer M2, and the first sub-reference signal line Vref11 is located in the metal layer MG; the first sub-reference signal line Vref11 is electrically connected to the gate initialization transistor T5 through the third connection portion L3. Specifically, the first sub-reference signal line Vref11 located in the metal layer MG is electrically connected to the first electrode p51 of the gate initialization transistor T5 through the connection portion K3 located in the metal layer MG and the third connection portion L3 located in the metal layer M2.

[0166] In combination with Figures 5, 6, 7d-7f, Figures 10, 11d-11f, and Figures 12, 12d-12f, the second sub-reference signal line Vref12 also includes a fourth connection portion L4 extending along the first direction X, and the fourth connection portion L4 and the third connection portion L3 are electrically connected in the same layer, that is, the fourth connection portion L4 and the third connection portion L3 can both be located in the metal layer M2 and electrically connected to each other; the second sub-reference signal line Vref12 is electrically connected to the anode initialization transistor T5 through the fourth connection portion L4. Specifically, the second sub-reference signal line Vref12 located in the metal layer M2 is electrically connected to the first electrode p51 of the gate initialization transistor T5 through the fourth connection portion L4 located in the metal layer M2. At the same time, the second sub-reference signal line Vref12 located in the metal layer M2 is electrically connected to the first sub-reference signal line Vref11 located in the metal layer MG through the fourth connection portion L4 and the third connection portion L3 located in the metal layer M2 and the connection portion K3 located in the metal layer MG.

[0167] The following describes how the sub-reference signal lines extending in different directions in the second reference signal line Vref2 are electrically connected, and how they are electrically connected to the corresponding thin film transistors in the pixel circuit 20 .

[0168] In conjunction with Figures 5, 6, 7a, 7c, and 7f, in conjunction with Figures 10, 11a, 11c, and 11f, and in conjunction with Figures 12, 12a, 12c, and 12f, in a direction perpendicular to the plane of the substrate 10, the third sub-reference signal line Vref21 and the fourth sub-reference signal line Vref22 are electrically connected at a position where the two overlap. Specifically, the third sub-reference signal line Vref21 located in the metal layer MC and the fourth sub-reference signal line Vref22 located in the metal layer M2 are electrically connected at a position where the two overlap through a connection portion J located in the metal layer M2. 6 is electrically connected to the connection portion K4 located on the metal layer MC, and the third sub-reference signal line Vref21 located in the metal layer MC is electrically connected to the first electrode p71 of the anode initialization transistor T7 through the connection portion K4 located on the metal layer MC, the connection portion J6 and the connection portion J7 located on the metal layer M2, and the connection portion K5 located on the active layer poly. At the same time, the fourth sub-reference signal line Vref22 located in the metal layer M2 is also electrically connected to the first electrode p71 of the anode initialization transistor T7 through the connection portion J7 located on the metal layer M2 and the connection portion K5 located on the active layer poly.

[0169] It should be noted that the only difference between the three layout structures in Figures 5, 10, and 12 is that the second sub-bias signal line DVH2, the second sub-reference signal line Vref12, and the fourth sub-reference signal line Vref22 extending along the second direction Y are arranged in a different order along the first direction X, and the corresponding signal line connection methods are adaptively adjusted. The following description will continue with the layout structure shown in Figure 5 as an example. Of course, each embodiment is also applicable to the layout structures shown in Figures 10 and 12, and will not be repeated here.

[0170] 3-6 and 8 , the pixel circuit 20 further includes a first light emitting control transistor T1 , the signal line 30 further includes a first power signal line PVDD, and the first light emitting control transistor T1 is electrically connected between the first power signal line PVDD and the first electrode of the driving transistor T3 .

[0171] 5 , 6 , 7 a and 7 b , the first light-emitting control transistor T1 includes a channel region p1 located in the active layer poly, and a first electrode p11 and a second electrode p12 connected to the channel region p1. The second electrode p12 of the first light-emitting control transistor T1 is directly electrically connected to the first electrode p31 of the driving transistor T3 in the active layer poly.

[0172] As shown in Figures 8, 9a, and 9b, the first power signal line PVDD includes a first sub-power signal line PVDD1 extending along a first direction X and arranged along a second direction Y, and a second sub-power signal line PVDD2 extending along the second direction Y and arranged along the first direction X. The first sub-power signal line PVDD1 and the second sub-power signal line PVDD2 are electrically connected, thereby forming a grid structure of the first power signal line PVDD. This reduces the overall resistance of the first power signal line PVDD, thereby reducing power consumption of the first power signal line PVDD and improving signal transmission stability of the first power signal line PVDD, thereby enhancing display uniformity and other display effects of the display panel. In this case, the bias signal line DVH, the first reference signal line Vref1, the second reference signal line Vref2, and the first power signal line PVDD are insulated from each other to prevent signal crosstalk.

[0173] Optionally, the first sub-power signal line PVDD1 and the second sub-power signal line PVDD2 are disposed in different layers, that is, signal lines extending in different directions are located in different metal layers, to reduce the difficulty of routing signal lines within the same metal layer. For example, as shown in Figures 8, 9a, and 9b, the first sub-power signal line PVDD1 is located in metal layer M3, and the second sub-power signal line PVDD2 is located in metal layer M4. The first sub-power signal line PVDD1 and the second sub-power signal line PVDD2 can be electrically connected through a via between metal layer M3 and metal layer M4.

[0174] Therefore, in some embodiments, the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 are arranged in different layers, the first sub-reference signal line Vref11 and the second sub-reference signal line Vref12 are arranged in different layers, the third sub-reference signal line Vref21 and the fourth sub-reference signal line Vref22 are arranged in different layers, and the first sub-power signal line PVDD1 and the second sub-power signal line PVDD2 are arranged in different layers, that is, the signal lines extending in different directions are located in different metal layers to reduce the difficulty of laying out the signal lines in the same metal layer.

[0175] Optionally, as shown in Figure 1, the display panel includes a substrate 10 and a first metal layer MC, a second metal layer MG, a third metal layer M2, a fourth metal layer M3 and a fifth metal layer M5 arranged in a direction away from the substrate 10; as shown in Figure 7c, the third sub-reference signal line Vref21 is located in the first metal layer MC; as shown in Figure 7e, the first sub-bias signal line DVH1 and the first sub-reference signal line Vref11 are located in the second metal layer MG; as shown in Figure 7f, the second sub-bias signal line DVH2, the second sub-reference signal line Vref12 and the fourth sub-reference signal line Vref22 are located in the third metal layer M2; as shown in Figure 9a, the first sub-power signal line PVDD1 is located in the fourth metal layer M3; as shown in Figure 9b, the second sub-power signal line PVDD2 is located in the fifth metal layer M4.

[0176] As shown in FIG9 a , the first sub-power signal line PVDD1 includes a first sub-segment D1 and a second sub-segment D2 alternately connected along a first direction X. The width of the second sub-segment D2 along the second direction Y is greater than the width of the first sub-segment D1 along the second direction Y, and the sum of the lengths of adjacent first sub-segments D1 and second sub-segments D2 along the first direction X is greater than the length of the pixel circuit 20 along the first direction X.

[0177] It should be noted that the first sub-power signal line PVDD1 is actually an entire signal line extending along the first direction X, but its width and shape are different at different positions in the first direction X. In this application, for the convenience of description, the first sub-power signal line PVDD1 is divided into a first sub-segment D1 and a second sub-segment D2, which does not serve as a limitation of the first sub-power signal line PVDD1.

[0178] As shown in Figures 8, 9a and 9b, the first sub-segment D1 and the second sub-segment D2 are electrically connected to the second sub-power signal line PVDD2 at the position where the two are connected. Specifically, the first sub-segment D1 and the second sub-segment D2 located in the metal layer M3 are electrically connected to the second sub-power signal line PVDD2 located in the metal layer M4 at the position where the two are connected through the connection portion J8 located in the metal layer M3 and the connection portion J9 located in the metal layer M4.

[0179] 8 and 9 a , the first sub-power signal line PVDD1 further includes a fifth connection portion L5 extending along the second direction Y. The fifth connection portion L5 is electrically connected to the same layer as the first sub-segment D1. That is, the fifth connection portion L5 may also be located in the metal layer M3 and connected to the same layer as the first sub-segment D1. In combination with Figures 5, 6, 7a, 7c, 7f, 8 and 9a, the fifth connection portion L5 is electrically connected to the first electrode p11 of the first light-emitting control transistor T1 through the connection portion J10 located in the metal layer M2, the connection portion K6 located in the metal layer MC and the connection portion K7 located in the active layer poly; and, in combination with Figures 5, 6, 7a-7c, 7f, 8 and 9a, the fifth connection portion L5 is electrically connected to one electrode plate Cst2 (located in the metal layer MC) of the storage capacitor Cst through the connection portion J10 located in the metal layer M2 and the connection portion K6 located in the metal layer MC. The other electrode plate Cst of the storage capacitor Cst is located in the metal layer M1 and also serves as the gate g3 of the driving transistor T3.

[0180] As shown in Figures 8 and 9b, the second sub-power signal line PVDD2 includes a third sub-segment D3 and a fourth sub-segment D4 alternately connected along the second direction Y. The width of the fourth sub-segment D4 along the first direction X is greater than the width of the third sub-segment D3 along the first direction X. Two adjacent fourth sub-segments D4 are connected by two third sub-segments D3 symmetrically arranged along the second direction Y, and the length of adjacent third sub-segments D3 and fourth sub-segments D4 along the second direction Y is greater than or equal to the length of the pixel circuit 20 along the second direction Y.

[0181] As shown in Figures 8 and 9b, the signal line 30 also includes a data signal line DL extending along the second direction Y. Optionally, with the width of the data signal line DL along the first direction X as a reference, the width of the fourth sub-segment D4 along the first direction X may be greater than twice the width of the data signal line DL along the first direction X, and the width of the third sub-segment D3 along the first direction X may be less than twice the width of the data signal line DL along the first direction X.

[0182] It should be noted that the second sub-power signal line PVDD2 is actually an entire signal line extending along the second direction Y, but its width and shape are different at different positions in the second direction Y. In this application, for the convenience of description, the second sub-power signal line PVDD2 is divided into a third sub-segment D3 and a fourth sub-segment D4, which does not serve as a limitation of the second sub-power signal line PVDD2.

[0183] As shown in Figures 8, 9a, and 9b, the second subsegment D2 and the fourth subsegment D4 at least partially overlap in a direction perpendicular to the plane of the substrate 10. Since the second subsegment D2 is the subsegment of the first sub-power signal line PVDD1 with a greater width along the second direction Y, and the fourth subsegment D4 is the subsegment of the second sub-power signal line PVDD2 with a greater width along the first direction X, the second subsegment D2 and the fourth subsegment D4 are at least partially overlapped in a direction perpendicular to the plane of the substrate 10. This allows the wider areas of the first sub-power signal line PVDD1 and the second sub-power signal line PVDD2 to overlap, thereby reducing the light-blocking area and increasing light transmittance, thereby enhancing the display quality of the display panel.

[0184] As shown in FIG. 3 to FIG. 6 , the pixel circuit 20 further includes a compensation transistor T4 , which is electrically connected between the gate electrode of the driving transistor T3 and the second electrode of the driving transistor T3 .

[0185] Optionally, the compensation transistor T4 can be an oxide thin film transistor, that is, an IGZO thin film transistor. As shown in Figures 5, 6 and 7b to 7f, the compensation transistor T4 includes a channel region p4 located in the oxide layer IGZO, and a first electrode p41 and a second electrode p42 connected to the channel region p4. The first electrode p41 of the compensation transistor T4 is electrically connected to the second electrode p32 of the driving transistor T3 through the connection portion K8 located in the metal layer M2 and the connection portion K9 located in the active layer poly in sequence. The second electrode p42 of the compensation transistor T4 is directly electrically connected to the second electrode p52 of the gate initialization transistor T5 in the oxide layer IGZO, and is electrically connected to the gate g3 of the driving transistor T3 through the connection portion J1 located in the metal layer M2 and through a via hole in a plate Cst2 of the storage capacitor Cst located in the metal layer MC.

[0186] 5 , 6 , and 7 c - 7 e , the signal line 30 further includes a second scanning signal line S2 extending along the first direction X. The second scanning signal line S2 includes a third sub-scanning signal line S21 and a fourth sub-scanning signal line S22 that transmit the same scanning signal. The third sub-scanning signal line S21 is located in the metal layer MC and extends along the first direction X. The fourth sub-scanning signal line S22 is located in the metal layer MG and extends along the first direction X. In a direction perpendicular to the plane of the substrate 10, the third sub-scanning signal line S21, the fourth sub-scanning signal line S22, and the channel region p4 of the compensation transistor T4 overlap. Optionally, in a direction perpendicular to the plane of the substrate 10, the portion of the oxide layer IGZO overlapping with the third sub-scanning signal line S21 and the fourth sub-scanning signal line S22 is the channel region p4 of the compensation transistor T4, and the portion of the third sub-scanning signal line S21 facing the channel region p4 of the compensation transistor T4 is the bottom gate bg4 of the compensation transistor T4, so that the bottom gate bg4 of the compensation transistor T4 is electrically connected to the third sub-scanning signal line S21; the portion of the fourth sub-scanning signal line S22 facing the channel region p4 of the compensation transistor T4 is the top gate tg4 of the compensation transistor T4, so that the top gate tg4 of the compensation transistor T4 is electrically connected to the fourth sub-scanning signal line S22, so that the top gate tg4 and the bottom gate bg4 of the compensation transistor T4 are both electrically connected to the second scan signal line S2 and receive the same scan signal.

[0187] As shown in Figures 5, 6, 7d, 8, and 9a-9b, in a direction perpendicular to the plane of the substrate 10, the overlapping region of the second subsegment D2 and the fourth subsegment D4 covers the compensation transistor T4 and the gate initialization transistor T5. This configuration allows the second subsegment D2 and the fourth subsegment D4 to block external light in a direction perpendicular to the plane of the substrate 10, preventing external light from reaching the compensation transistor T4 and the gate initialization transistor T5 and affecting their performance. In particular, when the compensation transistor T4 and the gate initialization transistor T5 are IGZO thin-film transistors, the stability of the performance of the compensation transistor T4 and the gate initialization transistor T5 can be improved.

[0188] 5 , 6 , and 7 b to 7 f , the pixel circuit further includes a sixth connection portion J1, which is electrically connected between the gate initialization transistor T5 and the gate g3 of the driving transistor T3, and is also electrically connected between the compensation transistor T4 and the gate g3 of the driving transistor T3. Specifically, the second electrode p42 of the compensation transistor T4 and the second electrode p52 of the gate initialization transistor T5 are both electrically connected to the gate g3 of the driving transistor T3 through the sixth connection portion J1 located in the metal layer M2 and through a via in a plate Cst2 of the storage capacitor Cst located in the metal layer MC. It can be seen from the structural schematic diagrams of the pixel circuit 20 shown in FIG. 3 and FIG. 4 that the sixth connection portion J1 corresponds to the first node N1.

[0189] 5 , 6 , 7 f , 8 , and 9 a - 9 b , in a direction perpendicular to the plane of the substrate 10 , both the first sub-power signal line PVDD1 and the second sub-power signal line PVDD2 cover the sixth connection portion J1 to maintain the stability of the potential of the first node N1, that is, to maintain the stability of the potential of the gate g3 of the driving transistor T3, which is beneficial to improving the display effect of the display panel.

[0190] As shown in Figures 8 and 9b, the pixel circuits 20 are arranged in an array along the first direction X and the second direction Y, and the signal lines 30 also include data signal lines DL extending along the second direction Y. A column of pixel circuits 20 is electrically connected to one data signal line DL; optionally, the data signal line DL can be located in the metal layer M4.

[0191] FIG14 is a schematic top view of another display panel provided in an embodiment of the present application. As shown in FIG14 , the display panel further includes a display area AA and a non-display area NA at least partially surrounding the display area AA. The non-display area NA includes a fan-out area FA located on one side of the display area AA along the second direction Y. The fan-out area FA includes a plurality of fan-out traces W1.

[0192] The display area AA includes a first display area AA1 and a second display area AA2 located on at least one side of the first display area AA1 along a first direction X. The first display area AA1 and the second display area AA2 each include a plurality of data signal lines DL. The data signal lines DL are electrically connected to the fan-out lines W1. The data signal lines DL in the second display area AA2 are electrically connected to the fan-out lines W1 via connecting lines V1.

[0193] The connecting line V1 is located in the display area AA and includes a first connecting line segment V11 extending along the first direction X and a second connecting line segment V12 extending along the second direction Y. The second connecting line segment V12 is electrically connected to the fan-out line W1, and the first connecting line segment V11 is electrically connected to the data signal line DL in the second display area AA2.

[0194] As shown in Figure 14, the data signal lines DL in the first display area AA1 extend directly to the fan-out area FA and are electrically connected to the fan-out traces W1 in the fan-out area FA. The data signal lines DL in the second display area AA2 are electrically connected to the fan-out traces W1 in the fan-out area FA via the connecting traces V1 located in the display area AA. Specifically, the data signal lines DL in the second display area AA2 are first electrically connected to the fan-out traces W1 in the fan-out area FA via a first connecting trace segment V11 extending along a first direction X, and then via a second connecting trace segment V12 extending along a second direction Y. This arrangement implements a design in which some fan-out traces are arranged in the display area (Fanout in AA, FIAA). This eliminates the need to route the fan-out traces W1 near the lower left and / or lower right borders of the display panel, facilitating a narrow border of the display panel. In particular, the width of the lower border of the display panel can be significantly reduced, facilitating a full-screen design.

[0195] It should be noted that in FIG14 , the number of data signal lines DL in the first display area AA1 and the second display area AA2 is for illustration only and does not represent the actual number of data signal lines DL. Similarly, the number of fan-out traces W1 in the fan-out area FA is for illustration only and does not represent the actual number of fan-out traces W1.

[0196] As shown in FIG14 , the first display area AA1 is located in the middle area of ​​the display panel, and the second display area AA2 is located on at least one side of the first display area AA1 along the first direction X, that is, on one side or both sides of the first display area AA1 along the first direction X. FIG15 is merely an example in which the second display area AA2 is provided on both sides of the first display area AA1.

[0197] As shown in FIG14 , the display panel further includes a pin area PA, which is bound and connected to the control chip. In actual application, the pin area PA will be folded back to the non-light-emitting surface of the display panel to reduce the width of the lower frame of the display panel.

[0198] It should also be noted that, as shown in FIG14 , the overlapping relationship between the first connecting line segment V11 and the data signal line DL along the first direction X does not mean that the two are electrically connected. In fact, the first connecting line segment V11 extending along the first direction X cannot be electrically connected to the data signal line DL along the first direction X. Therefore, the first connecting line segment V11 extending along the first direction X and the data signal line DL extending along the second direction Y need to be arranged in different layers.

[0199] Figure 15 shows a schematic diagram of the layout structure of the dotted box U1 portion in Figure 14, specifically a schematic diagram of the layout structure of the stack composed of the metal layer M3, the metal layer M4 and the metal layer RE. It can be seen that for a data signal line DL in the second display area AA2, the data signal line DL is electrically connected to the first connecting trace V11 extending along the first direction X.

[0200] Figure 16 shows a schematic diagram of the layout structure of the dotted box U2 portion in Figure 14, specifically a schematic diagram of the layout structure of the stack consisting of the metal layer M3, the metal layer M4 and the metal layer RE. It can be seen that the first connecting trace V11 extending along the first direction X is electrically connected to the second connecting trace V12 extending along the second direction Y, and will eventually be electrically connected to the fan-out trace W1 in the fan-out area FA.

[0201] In fact, considering the etching uniformity and the uniformity of the reflection effect of the display panel, as shown in Figures 8 and 9a-9b, a first connecting trace FIAA1 extending along the first direction X is provided between two adjacent rows of pixel circuits 10, and as shown in Figures 15 and 16, at least part of the first connecting trace FIAA1 includes a first connecting line segment V11.

[0202] Moreover, as shown in FIG8 and FIG9a-FIG9b, at least one second connecting trace FIAA2 extending along the second direction Y is provided between two adjacent columns of pixel circuits 10. FIG8 and FIG9a-FIG9b illustrate a situation where two second connecting traces FIAA2 extending along the second direction Y are provided between two adjacent columns of pixel circuits 10, and as shown in FIG15 and FIG16, at least part of the second connecting trace FIAA2 includes a second connecting line segment V12.

[0203] Optionally, as shown in Figures 8 and 9a-9b, the first connecting trace FIAA1 can be insulated and set in the same layer as the first power signal line PVDD1, both located in the metal layer M3. In this case, the first connecting line segment V11 is insulated and set in the same layer as the first power signal line PVDD1.

[0204] Optionally, as shown in conjunction with Figures 8 and 9a-9b, the second connecting trace FIAA2 can be insulated and arranged on the same layer as the second power signal line PVDD2, and both can be located in the metal layer M4. In this case, the second connecting trace segment is insulated and arranged on the same layer as the second sub-power signal line PVDD2. Furthermore, because the data signal line DL, the second power signal line PVDD2, and the second connecting trace FIAA2 all extend along the second direction Y, the data signal line DL, the second power signal line PVDD2, and the second connecting trace FIAA2 can be arranged on the same layer and insulated from each other.

[0205] The first connecting trace FIAA1 and the first power signal line PVDD1 are insulated on the same layer, and the second connecting trace FIAA2, the second power signal line PVDD2 and the data signal line DL are insulated from each other on the same layer, so that the signal lines extending in the same direction can be located in the same metal layer, reducing the film layer occupancy and facilitating the lightweight and thin design of the display panel.

[0206] In other embodiments of the present application, the first connecting trace FIAA1 and the first power signal line PVDD1 may also be located in the metal layer M4, in which case the first connecting line segment V11 is also located in the metal layer M4; the second connecting trace FIAA2, the second power signal line PVDD2 and the data signal line DL may also be located in the metal layer M3, in which case the second connecting line segment V12 is also located in the metal layer M3.

[0207] It can be understood that the first connecting line FIAA1 including the first connecting line segment V11 is not entirely used to transmit data signals, but only the first connecting line segment V11 is used to transmit data signals. Similarly, the second connecting line FIAA2 including the second connecting line segment V12 is not entirely used to transmit data signals, but only the second connecting line segment V12 is used to transmit data signals. Therefore, as shown in Figures 15 and 16, the display panel also includes a plurality of first auxiliary line segments V13 extending along the first direction X and a plurality of second auxiliary line segments V14 extending along the second direction Y; the first auxiliary line segment V13 is on the same layer as the first connecting line segment V11, and is insulated from the first connecting line segment V11 and the first sub-power signal line PVDD1; the second auxiliary line segment V14 is on the same layer as the second connecting line segment V12, and is insulated from the second connecting line segment V12 and the second sub-power line PVDD2.

[0208] That is to say, the first auxiliary line segment V13 in the first connecting trace FIAA1 is not used to transmit data signals, and the first auxiliary line segment V13 is on the same layer as the first connecting line segment V11 and the first sub-power signal line PVDD1, and is insulated from the first connecting line segment V11 and the first sub-power signal line PVDD1.

[0209] Similarly, the second auxiliary line segment V14 in the second connecting line FIAA2 is not used to transmit data signals, and the second auxiliary line segment V14 is on the same layer as the second connecting line segment V12 and the second sub-power line PVDD2, and is insulated from the first connecting line segment V11 and the second sub-power line PVDD2.

[0210] As shown in Figures 15 and 16, for the first connecting line FIAA1 including the first connecting line segment V11 and the first auxiliary line segment V13, there is a first gap P1 between the first auxiliary line segment V13 and the first connecting line segment V11, so that the first auxiliary line segment V13 is insulated from the first connecting line segment V11 to prevent signal crosstalk between the first connecting line segment V11 used to transmit data signals and the first auxiliary line segment V13 not used to transmit data signals.

[0211] Similarly, as shown in Figures 15 and 16, for the second connecting line FIAA2 including the second connecting line segment V12 and the second auxiliary line segment V14, there is a second gap P2 between the second auxiliary line segment V14 and the second connecting line segment V12, so that the second auxiliary line segment V14 is insulated from the second connecting line segment V12, thereby preventing signal crosstalk between the second connecting line segment V12 used to transmit data signals and the second auxiliary line segment V14 that is not used to transmit data signals.

[0212] As shown in Figures 1, 8, and 9c, the light-emitting element 40 includes an anode RE, a light-emitting layer (not shown), and a cathode (not shown) disposed in a direction away from the substrate 10. As shown in Figures 15 and 16, the anode RE covers the first gap P1 and the second gap P2 in a direction perpendicular to the plane of the substrate 10.

[0213] That is to say, the first gap P1 (i.e., the broken line position) in the first connecting line FIAA1 extending along the first direction X is blocked by the anode RE of the light-emitting element 40 in the direction perpendicular to the plane where the substrate 10 is located, and the second gap P2 (i.e., the broken line position) in the second connecting line FIAA2 extending along the second direction Y is also blocked by the anode RE of the light-emitting element 40 in the direction perpendicular to the plane where the substrate 10 is located. Since metal can reflect light but is not transparent, the display panel is uniform in appearance and the reflection effect of light is also relatively uniform, thereby avoiding the visual display unevenness phenomenon at the broken line position and other positions in the display panel in the dark state and the display state, thereby improving the display uniformity of the display panel.

[0214] It should be noted that, along the direction perpendicular to the plane of the substrate 10, the anode RE covers the first gap P1 and the second gap P2, which means that the orthographic projections of the first gap P1 and the second gap P2 on the plane of the substrate 10 are within the orthographic projection range of the anode RE on the plane of the substrate 10.

[0215] It is understood that the first auxiliary line segment V13 in the first connecting trace FIAA1 that is not used for transmitting data signals may also include the entire first connecting trace FIAA1 that is not used for transmitting data signals. Similarly, the second auxiliary line segment V14 in the second connecting trace FIAA2 that is not used for transmitting data signals may also include the entire second connecting trace FIAA2 that is not used for transmitting data signals. Figures 8 and 9a-9b are both illustrated using the entire first connecting trace FIAA1 that is not used for transmitting data signals and the entire second connecting trace FIAA2 that is not used for transmitting data signals.

[0216] As shown in conjunction with Figures 15 and 16 , in a direction perpendicular to the plane of the substrate 10, the first connecting line segment V11 extending along the first direction X and the second connecting line segment V12 extending along the second direction Y can be electrically connected at their overlapping locations through a via between the metal layer M3 and the metal layer M4. Similarly, the first auxiliary line segment V13 extending along the first direction X and the second auxiliary line segment V14 extending along the second direction Y can also be electrically connected at their overlapping locations through a via between the metal layer M3 and the metal layer M4. Specifically, as shown in conjunction with Figures 8 and 9a-9b , the first auxiliary line segment V13 extending along the first direction X is electrically connected to the second auxiliary line segment V14 extending along the second direction Y via a connecting portion E1 located on the metal layer M3 and a connecting portion E2 located on the metal layer M4, and the connecting portion E1 of the metal layer M3 and the connecting portion E2 located on the metal layer M4 are electrically connected via a via between the metal layer M3 and the metal layer M4.

[0217] 5 , 6 , 7 a , 7 f , 8 and 9 a - 9 b , the data signal line DL located in the metal layer M4 is electrically connected to the first electrode p21 of the data write transistor T2 via the connection portion E3 located in the metal layer M4, the connection portion E4 located in the metal layer M3, the connection portion E5 located in the metal layer M2 and the connection portion E6 located in the active layer poly in sequence.

[0218] As shown in Figures 8 and 9a-9b, the first auxiliary line segments V13 extend along the first direction X and are arranged along the second direction Y. The second auxiliary line segments V14 extend along the second direction Y and are arranged along the first direction X. Thus, the first auxiliary line segments V13 and the second auxiliary line segments V14 also form a grid structure. Optionally, both the first auxiliary line segments V13 and the second auxiliary line segments V14 are connected to a fixed potential.

[0219] For the first auxiliary line segments V13, all first auxiliary line segments V13 can be connected to the first power signal line PVDD in parallel with the first power signal line PVDD, thereby reducing the voltage drop on the first power signal line PVDD; or all first auxiliary line segments V13 can be connected to the second power signal line PVEE in parallel with the second power signal line PVEE, thereby reducing the voltage drop on the second power signal line PVEE; or, some first auxiliary line segments V13 can be connected to the first power signal line PVDD, while some can be connected to the second power signal line PVEE, so that multiple first auxiliary line segments V13 are connected in parallel with the first power voltage line PVDD and the second power voltage line PVEE in a certain proportion, thereby reducing the voltage drop on the first power voltage line PVDD and the second power voltage line PVEE. The above configurations can achieve the purpose of improving the display uniformity of the display panel and reducing power consumption.

[0220] Similarly, for the second auxiliary line segments V14, all second auxiliary line segments V14 can be connected to the first power signal line PVDD in parallel with the first power signal line PVDD, thereby reducing the voltage drop on the first power signal line PVDD; or all second auxiliary line segments V14 can be connected to the second power signal line PVEE in parallel with the second power signal line PVEE, thereby reducing the voltage drop on the second power signal line PVEE; or, some second auxiliary line segments V14 can be connected to the first power signal line PVDD, while some second auxiliary line segments V14 can be connected to the second power signal line PVEE, so that multiple second auxiliary line segments V14 are connected in parallel with the first power voltage line PVDD and the second power voltage line PVEE in a certain proportion, thereby reducing the voltage drop on the first power voltage line PVDD and the second power voltage line PVEE. The above configurations can achieve the purpose of improving the display uniformity of the display panel and reducing power consumption.

[0221] It should be noted that fixed potential means that the potential is fixed within a certain time period or under a certain working state (such as a certain working brightness), and the fixed potential can have different potential values ​​in different time periods or different working states (such as different working brightness).

[0222] It should also be noted that in the present application, the signal line providing a fixed potential is not limited to the first power signal line PVDD and the second power signal line PVEE, but can also be the first reference signal line Vref1, the second reference signal line Vref2, etc., depending on the specific situation.

[0223] The present application also provides a display device, as shown in Figure 17. The display device 100 includes a display panel 200 provided by any of the above embodiments. Since the display panel 200 has been described in detail in the above embodiments, it will not be repeated here.

[0224] The display device 100 can be any electronic device with a display function, such as a touch screen display, a mobile phone, a tablet computer, a notebook computer, an e-reader, or a television.

[0225] The various parts in this manual are described in a combination of parallel and progressive manners. Each part focuses on the differences from other parts, and the same or similar parts between the various parts can be referenced to each other.

[0226] With respect to the above description of the disclosed embodiments, the features described in the various embodiments in this specification may be interchanged or combined with one another to enable those skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: It includes a substrate and a pixel circuit and a signal line located on one side of the substrate; The pixel circuit includes a driving transistor, a bias transistor and a gate initialization transistor, the signal line includes a bias signal line and a first reference signal line, the bias transistor is electrically connected between at least one of a first electrode and a second electrode of the driving transistor and the bias signal line, and the gate initialization transistor is electrically connected between a gate of the driving transistor and the first reference signal line; The bias signal line includes a first sub-bias signal line extending along a first direction and arranged along a second direction, and a second sub-bias signal line extending along the second direction and arranged along the first direction, the first direction and the second direction intersect, and the first sub-bias signal line and the second sub-bias signal line are electrically connected; The first reference signal line includes a first sub-reference signal line extending along a first direction and arranged along a second direction, and a second sub-reference signal line extending along the second direction and arranged along the first direction, the first sub-reference signal line and the second sub-reference signal line being electrically connected; The bias signal line and the first reference signal line are insulated from each other.

2. The display panel according to claim 1, characterized in that: The first sub-bias signal line and the second sub-bias signal line are arranged in different layers, and the first sub-reference signal line and the second sub-reference signal line are arranged in different layers.

3. The display panel according to claim 2, characterized in that: The first sub-bias signal line and the first sub-reference signal line are arranged in the same layer.

4. The display panel according to claim 3, characterized in that: The pixel circuits are arranged in an array along the first direction and the second direction; The number of rows of the pixel circuit is N10, the number of the first sub-bias signal lines is N11, and the number of the first sub-reference signal lines is N12, wherein N11≤N10, N12≤N10, and N10, N11 and N12 are all positive integers.

5. The display panel according to claim 3, characterized in that: The display panel further comprises a light emitting element, wherein the light emitting element comprises an anode, a light emitting layer and a cathode arranged in a direction away from the substrate; The pixel circuit further comprises an anode initialization transistor, wherein the anode initialization transistor is electrically connected to the anode of the light emitting element; The signal line further includes a bias control signal line, the bias control signal line is electrically connected to the gate of the anode initialization transistor and to the gate of the bias transistor; The bias control signal line extends along the first direction and is arranged in a different layer from the first sub-bias signal line; In a direction perpendicular to a plane where the substrate is located, the first sub-bias signal line at least partially overlaps with the bias control signal line.

6. The display panel according to claim 3, characterized in that: The pixel circuit further includes a first light emission control transistor and a second light emission control transistor, the signal line further includes a first power signal line and a light emission control signal line, and the display panel further includes a light emitting element; The first light emission control transistor is electrically connected between the first power signal line and the first electrode of the driving transistor, the second light emission control transistor is electrically connected between the second electrode of the driving transistor and the light emitting element, and the light emission control signal line is electrically connected to the gate of the first light emission control transistor and to the gate of the second light emission control transistor; The light emitting control signal line extends along the first direction and is arranged in a different layer from the first sub-reference signal line; In a direction perpendicular to the plane where the substrate is located, the first sub-reference signal line at least partially overlaps with the light-emitting control signal line.

7. The display panel according to claim 3, characterized in that: The display panel includes a substrate and a first metal layer, an oxide layer, and a second metal layer arranged in a direction away from the substrate; The gate initialization transistor is an oxide thin film transistor, comprising a first channel region, a first bottom gate located on a side of the first channel region close to the substrate, and a first top gate located on a side of the first channel region away from the substrate, the first channel region being located in the oxide layer, the first bottom gate being located in the first metal layer, and the first top gate being located in the second metal layer; The first sub-bias signal line and the first sub-reference signal line are both located in the second metal layer, and the first sub-bias signal line and the first sub-reference signal line are both connected to the first top gate Insulation settings.

8. The display panel according to claim 3, characterized in that: The second sub-bias signal line and the second sub-reference signal line are arranged in the same layer.

9. The display panel according to claim 8, characterized in that: The pixel circuits are arranged in an array along the first direction and the second direction; The number of columns of the pixel circuit is N20, the number of the second sub-bias signal lines is N21, and the number of the second sub-reference signal lines is N22, wherein N21≤N20, N22≤N10, and N20, N21 and N22 are all positive integers.

10. The display panel according to claim 1, characterized in that: The display panel further comprises a light emitting element, wherein the light emitting element comprises an anode, a light emitting layer and a cathode arranged in a direction away from the substrate; The pixel circuit further includes an anode initialization transistor, the signal line further includes a second reference signal line, and the anode initialization transistor is electrically connected between the second reference signal line and the anode of the light emitting element; The second reference signal line includes a third sub-reference signal line extending along the first direction and arranged along the second direction, and a fourth sub-reference signal line extending along the second direction and arranged along the first direction, and the third sub-reference signal line and the fourth sub-reference signal line are electrically connected; The bias signal line, the first reference signal line, and the second reference signal line are insulated from each other.

11. The display panel according to claim 10, characterized in that: The first sub-bias signal line and the second sub-bias signal line are arranged in different layers, the first sub-reference signal line and the second sub-reference signal line are arranged in different layers, and the third sub-reference signal line and the fourth sub-reference signal line are arranged in different layers.

12. The display panel according to claim 11, characterized in that: The second sub-bias signal line, the second sub-reference signal line and the fourth sub-reference signal line are arranged in the same layer.

13. The display panel according to claim 12, characterized in that: The pixel circuits are arranged in an array along the first direction and the second direction; The number of columns of the pixel circuit is N20, the number of the second sub-bias signal lines is N21, The number of the second sub-reference signal lines is N22, and the number of the fourth sub-reference signal lines is N23, wherein N21≤N20, N22≤N20, N23≤N20, and N20, N21, N22 and N23 are all positive integers.

14. The display panel according to claim 13, characterized in that: N21+N22+N23≤N20.

15. The display panel according to claim 13, characterized in that: Each column of the pixel circuits is correspondingly provided with one of the second sub-bias signal line, the second sub-reference signal line and the fourth sub-reference signal line.

16. The display panel according to claim 15, characterized in that: Among the four adjacent columns of pixel circuits, two columns of pixel circuits are correspondingly provided with the same one of the second sub-bias signal line, the second sub-reference signal line and the fourth sub-reference signal line, and the other two columns of pixel circuits are correspondingly provided with the other two of the second sub-bias signal line, the second sub-reference signal line and the fourth sub-reference signal line.

17. The display panel according to claim 16, characterized in that: In the four adjacent columns of pixel circuits, two columns of pixel circuits corresponding to the same type of the second sub-bias signal line, the second sub-reference signal line and the fourth sub-reference signal line are arranged in alternate columns.

18. The display panel according to claim 17, characterized in that: The light-emitting elements include a first color light-emitting element, a second color light-emitting element and a third color light-emitting element; In two adjacent columns of pixel circuits, the pixel circuits in one column drive the first color light emitting elements correspondingly, and the pixel circuits in the other column drive the second color light emitting elements and the third color light emitting elements correspondingly; Among the four adjacent columns of pixel circuits, two columns of pixel circuits corresponding to the same type of the second sub-bias signal line, the second sub-reference signal line and the fourth sub-reference signal line drive the first color light emitting elements.

19. The display panel according to claim 13, characterized in that: Each row of the pixel circuits is correspondingly provided with one of the first sub-bias signal lines, one of the first sub-reference signal lines, and one of the third sub-reference signal lines.

20. The display panel according to claim 19, characterized in that: The display panel further includes a plurality of first connection portions arranged in an array along the first direction and the second direction, the first connection portions extending along the first direction, and the first connection portions and the first sub-bias signal lines are arranged in different layers; The first sub-bias signal line is electrically connected to the bias transistor through the first connection portion.

21. The display panel according to claim 20, characterized in that: The second sub-bias signal line further includes a second connection portion extending along the first direction, the second connection portion being electrically connected to the first connection portion in the same layer; the second sub-bias signal line is electrically connected to the bias transistor via the second connection portion and the first connection portion.

22. The display panel according to claim 19, characterized in that: The display panel further includes a plurality of third connection portions arranged in an array along the first direction and the second direction, the third connection portions extending along the second direction, and the third connection portions and the first sub-reference signal line are disposed in a different layer; The first sub-reference signal line is electrically connected to the gate initialization transistor through the third connection portion.

23. The display panel according to claim 22, characterized in that: The second sub-reference signal line further includes a fourth connection portion extending along the first direction, the fourth connection portion and the third connection portion being electrically connected in the same layer; the second sub-reference signal line is electrically connected to the anode initialization transistor through the fourth connection portion.

24. The display panel according to claim 19, characterized in that: In a direction perpendicular to the plane where the substrate is located, the third sub-reference signal line and the fourth sub-reference signal line are electrically connected at a position where the two overlap.

25. The display panel according to claim 10, characterized in that: The pixel circuit further includes a first light emission control transistor, the signal line further includes a first power signal line, and the first light emission control transistor is electrically connected between the first power signal line and the first electrode of the driving transistor; The first power signal line includes a first sub-power signal line extending along the first direction and arranged along the second direction, and a second sub-power signal line extending along the second direction and arranged along the first direction, and the first sub-power signal line and the second sub-power signal line are electrically connected; The bias signal line, the first reference signal line, the second reference signal line, and the first power signal line are insulated from each other.

26. The display panel according to claim 25, characterized in that: The first sub-bias signal line and the second sub-bias signal line are arranged in different layers, the first sub-reference signal line and the second sub-reference signal line are arranged in different layers, the third sub-reference signal line and the fourth sub-reference signal line are arranged in different layers, and the first sub-power signal line and the second sub-power signal line are arranged in different layers.

27. The display panel according to claim 26, characterized in that: The display panel includes a substrate and a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer arranged in a direction away from the substrate; The third sub-reference signal line is located in the first metal layer; The first sub-bias signal line and the first sub-reference signal line are located in the second metal layer; The second sub-bias signal line, the second sub-reference signal line and the fourth sub-reference signal line are located in the third metal layer; The first sub-power signal line is located in the fourth metal layer; The second sub-power signal line is located in the fifth metal layer.

28. The display panel according to claim 26, characterized in that: The first sub-power signal line includes a first sub-segment and a second sub-segment alternately connected along the first direction, the width of the second sub-segment along the second direction is greater than the width of the first sub-segment along the second direction, and the sum of the lengths of the adjacent first sub-segment and the second sub-segment along the first direction is greater than the length of the pixel circuit along the first direction; The first sub-segment and the second sub-segment are electrically connected to the second sub-power signal line at a position where the first sub-segment and the second sub-segment are connected.

29. The display panel according to claim 28, characterized in that: The first sub-power signal line further includes a fifth connection portion extending along the second direction, wherein the fifth connection portion is electrically connected to the first sub-segment in the same layer and is electrically connected to the first light emission control transistor.

30. The display panel according to claim 28, characterized in that The second sub-power signal line includes a third sub-segment and a fourth sub-segment alternately connected along the second direction, the width of the fourth sub-segment along the first direction is greater than the width of the third sub-segment along the first direction, two adjacent fourth sub-segments are connected by two third sub-segments symmetrically arranged along the second direction, and the length of adjacent third sub-segments and fourth sub-segments along the second direction is greater than or equal to the length of the pixel circuit along the second direction; In a direction perpendicular to a plane where the substrate is located, the second subsegment at least partially overlaps with the fourth subsegment.

31. The display panel according to claim 30, characterized in that: The pixel circuit further includes a compensation transistor electrically connected between the gate electrode of the driving transistor and the second electrode of the driving transistor; In a direction perpendicular to the plane where the substrate is located, an area where the second sub-segment overlaps with the fourth sub-segment covers the compensation transistor and the gate initialization transistor.

32. The display panel according to claim 26, characterized in that: The pixel circuit further includes a sixth connection portion, the sixth connection portion being electrically connected between the gate initialization transistor and the gate of the driving transistor; In a direction perpendicular to the plane where the substrate is located, both the first sub-power signal line and the second sub-power signal line cover the sixth connecting portion.

33. The display panel according to claim 26, characterized in that: The pixel circuits are arranged in an array along the first direction and the second direction, the signal lines further include data signal lines extending along the second direction, and a column of the pixel circuits is electrically connected to one of the data signal lines; The display panel further includes a display area and a non-display area at least partially surrounding the display area, the non-display area includes a fan-out area located at one side of the display area along the second direction, and the fan-out area includes a plurality of fan-out wirings; The display area includes a first display area and a second display area located at least on one side of the first display area along the first direction, the first display area and the second display area each include a plurality of data signal lines, the data signal lines are electrically connected to the fan-out wiring, wherein the data signal lines in the second display area are electrically connected to the fan-out wiring via a connecting wiring; The connecting line is located in the display area and includes a first connecting line segment extending along the first direction and a second connecting line segment extending along the second direction, the second connecting line segment is electrically connected to the fan-out line, and the first connecting line segment is electrically connected to the data signal line in the second display area.

34. The display panel according to claim 33, characterized in that: The first connecting line segment and the first sub-power signal line are insulated and arranged in the same layer, and the second connecting line segment and the second sub-power signal line are insulated and arranged in the same layer.

35. The display panel according to claim 34, characterized in that: The display panel also includes a plurality of first auxiliary line segments extending along the first direction and a plurality of second auxiliary line segments extending along the second direction; the first auxiliary line segments are in the same layer as the first connecting line segments, and are insulated from the first connecting line segments and the first sub-power signal lines; the second auxiliary line segments are in the same layer as the second connecting line segments, and are insulated from the second connecting line segments and the second sub-power lines.

36. The display panel according to claim 35, characterized in that: There is a first gap between the first auxiliary line segment and the first connecting line segment, and there is a second gap between the second auxiliary line segment and the second connecting line segment; Along a direction perpendicular to a plane where the substrate is located, the anode covers the first gap and the second gap.

37. The display panel according to claim 35, characterized in that: The first auxiliary line segment and the second auxiliary line segment are both connected to a fixed potential.

38. A display device, characterized in that: A display panel comprising any one of claims 1-37.

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