Display substrate and display device

Abstract

The present application provides a display substrate and a display device. The display substrate comprises a base substrate, a first conductive layer, a second conductive layer and a shielding layer; the first conductive layer has a first signal pattern, the second conductive layer has a second signal pattern, the first conductive layer and the second conductive layer are different layers, and the orthographic projection of the first signal pattern on the base substrate and the orthographic projection of the second signal pattern on the base substrate have an overlapping area; the shielding layer is located between the first conductive layer and the second conductive layer, and the shielding layer, the first conductive layer and the second conductive layer are insulated from each other; the shielding layer comprises at least two stacked sub-shielding film layers, each sub-shielding film layer is provided with a hollowed-out area and a shielding area, the portion where the orthographic projection of the hollowed-out area of one sub-shielding film layer on the base substrate overlap the orthographic projection of the shielding area of the other sub-shielding film layer on the base substrate is a first overlapping area, and the first overlapping area at least partially coincides with the overlapping area. According to the display substrate and the display device of the present application, crosstalk between different signals can be reduced, and the product quality is improved.

Description

Display substrate and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No.: 202311120193.X filed in China on August 31, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0004] In related technologies, there are many circuits arranged inside the display panel, and different signals are applied to some of the circuits. However, there may be overlaps. The existence of these overlapping areas will cause crosstalk between different signals, thus affecting product quality.

[0005] Summary of the Invention

[0006] The embodiments of the present disclosure provide a display substrate and a display device, which can reduce crosstalk between different signals and improve product quality.

[0007] The technical solutions provided by the embodiments of the present disclosure are as follows:

[0008] According to a first aspect of the present disclosure, there is provided a display substrate, comprising:

[0009] substrate;

[0010] a first conductive layer located on the base substrate, wherein the first conductive layer has a first signal pattern;

[0011] a second conductive layer located on the base substrate, wherein the first conductive layer and the second conductive layer are provided in different layers, and the second conductive layer has a second signal pattern, wherein orthographic projections of the first signal pattern and the second signal pattern on the base substrate have an overlapping area; and

[0012] A shielding layer is located on the base substrate, the shielding layer is located between the first conductive layer and the second conductive layer, and the shielding layer, the first conductive layer and the second conductive layer are insulated from each other by an insulating layer; wherein,

[0013] The shielding layer includes at least two stacked sub-shielding film layers, each of the sub-shielding film layers is provided with a hollow area and a shielding area, and the part where the orthographic projection of the hollow area of ​​one sub-shielding film layer on the base substrate overlaps with the orthographic projection of the shielding area of ​​another sub-shielding film layer on the base substrate is a first overlapping area, and the first overlapping area at least partially overlaps with the overlapping area.

[0014] Exemplarily, different electrical signals may be applied to the first signal pattern and the second signal pattern respectively.

[0015] Exemplarily, the display substrate has a display area and a peripheral area located outside the display area, and a driving integrated circuit is provided in the peripheral area on the binding side of the display substrate;

[0016] The display substrate comprises:

[0017] a plurality of touch leads extending from the display area, the plurality of touch leads being located in the peripheral area and connected to the driver integrated circuit; and

[0018] A plurality of data line leads extending from the display area, the data line leads being located in the peripheral area and connected to the driver integrated circuit; wherein,

[0019] At least part of the touch leads overlap with part of the data line leads in their orthographic projections on the base substrate, the first signal pattern includes one of the overlapping touch leads and the data line leads, and the second signal pattern includes the other of the overlapping touch leads and the data line leads.

[0020] Exemplarily, on the binding side, the peripheral area includes a non-bending area, a bending area, and a binding area, the non-bending area is adjacent to the display area, and the bending area is located between the binding area and the non-bending area; wherein,

[0021] A plurality of data line leads extend from the non-bending area through the bending area to the binding area, and the lead portion of at least some of the data line leads extending into the binding area extends along a first direction and is connected to the driver integrated circuit;

[0022] A plurality of touch leads extend from the non-bending area through the bending area to the binding area, and the lead portion of at least part of the touch leads extending into the binding area is bent along a second direction intersecting the first direction to form a winding segment, and the end of the winding segment extends along the first direction to the driver integrated circuit; wherein the winding segment intersects with the data line lead corresponding to its position, and the orthographic projection of the shielding layer on the base substrate at least covers the orthographic projection of the winding segment on the base substrate.

[0023] Exemplarily, the display substrate further includes:

[0024] A plurality of gate lines and a plurality of data lines, wherein the plurality of gate lines intersect the plurality of data lines, and the data line leads are led out from the data lines to the peripheral area;

[0025] a plurality of rows of first electrode chains, wherein the first electrode chains and the gate lines extend in the same direction;

[0026] a plurality of columns of second electrode chains, wherein the second electrode chains and the data lines extend in the same direction;

[0027] The plurality of touch leads include: a plurality of first touch leads extending from a plurality of rows of the first electrode chains, and a plurality of second touch leads extending from a plurality of columns of the second electrode chains.

[0028] Exemplarily, the peripheral region further includes a first side and a second side opposite to each other in the extending direction of the gate lines;

[0029] The plurality of touch leads are divided into a first group of touch leads and a second group of touch leads;

[0030] The first group of touch leads includes a plurality of first touch leads extending from a first side of the first electrode chain, and a plurality of second touch leads close to the first side;

[0031] The second group of touch leads includes a plurality of first touch leads extending from the second side of the first electrode chain and a plurality of second touch leads close to the second side;

[0032] Each touch lead in the second group of touch leads is bent toward the first group of touch leads after extending from the non-bending area through the bending area to the binding area to form the winding segment.

[0033] Exemplarily, the same signal is connected to each sub-shielding film layer.

[0034] Exemplarily, the display substrate further includes:

[0035] The source-drain metal layer has a pattern including a source and a drain of a thin film transistor, and at least one of a data line; at least one sub-shielding film layer is in the same layer and made of the same material as the source-drain metal layer.

[0036] Exemplarily, the display substrate further includes: an electrode layer, the pattern of the electrode layer includes an anode, and at least one sub-shielding film layer is in the same layer and made of the same material as the electrode layer.

[0037] Exemplarily, the display substrate further includes:

[0038] At least two touch metal layers, the patterns of the at least two touch metal layers at least include patterns of touch electrodes; wherein at least one sub-shielding film layer and at least one touch metal layer are in the same layer and made of the same material.

[0039] Exemplarily, the hollow area on each of the sub-shielding film layers includes an opening array, and the opening array includes a plurality of openings distributed in an array, wherein the opening array on one of the sub-shielding film layers is staggered along the row direction or the column direction relative to the opening array on the other sub-shielding film layer, so that the hollow area on one of the sub-shielding film layers and the shielding area of ​​the other sub-shielding film layer at least partially overlap with each other in their orthographic projection on the base substrate; and / or

[0040] The hollow area on each sub-shielding film layer includes a plurality of strip openings arranged at intervals, wherein one of the sub-shielding film layers is staggered relative to the strip openings on another sub-shielding film layer in a direction perpendicular to the strip openings, so that the hollow area on one of the sub-shielding film layers and the shielding area on the other sub-shielding film layer at least partially overlap in their orthographic projection on the base substrate.

[0041] According to a second aspect of the present disclosure, a display device is provided, comprising the display substrate as described above.

[0042] The beneficial effects brought about by the embodiments of the present disclosure are as follows:

[0043] In the display substrate and display device provided by the embodiments of the present disclosure, there is an overlapping area between the first signal pattern and the second signal pattern in the display substrate, and a shielding layer is provided between the two to reduce signal crosstalk. However, since the first signal pattern and the second signal pattern are in different layers and are insulated, there is an insulating layer between the two, and the insulating layer can be made of organic or inorganic materials. In order to facilitate the discharge of gas in the process of the organic insulating layer, the shielding layer located above the organic insulating layer needs to be provided with a hollow area, and the hollow area serves as an exhaust hole. If the shielding layer is provided with only one layer, there will still be a certain degree of signal crosstalk between the first signal pattern and the second signal pattern in the hollow area, and due to the presence of the hollow area, the space will also be limited when arranging the signal patterns. Therefore, in the above scheme, the shielding layer is provided as at least two layers of sub-shielding film layers, and the part where the orthographic projection of the hollow area on at least one sub-shielding film layer overlaps with the shielding area of ​​another sub-shielding film layer on the base substrate is the first overlapping area, and the first overlapping area at least partially overlaps with the overlapping area. That is to say, the hollow areas of at least two layers of sub-shielding film layers compensate each other at least in the overlapping area of ​​the first signal pattern and the second signal pattern, so that the entire shielding layer forms a complete shielding surface at least in the overlapping area, which can effectively avoid crosstalk between different signals on the first signal pattern and the second signal pattern, and improve product quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] FIG1A is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure, wherein the display function layer is not shown;

[0045] FIG1B is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure, wherein the touch layer is not shown;

[0046] FIG2 is an enlarged view of the wiring of the touch lead and the data line lead at a local position O in FIG1A and FIG1B ;

[0047] FIG3 shows an enlarged view of the pattern of the first sub-shielding film layer at a local position O in FIG1A and FIG1B;

[0048] FIG4 shows an enlarged view of the pattern of the second sub-shielding film layer at a local position O in FIG1A and FIG1B;

[0049] FIG5 is a schematic structural diagram showing a case where only one first sub-shielding film layer is provided at a local position O in FIG1A;

[0050] FIG6 shows a cross-sectional view taken along line AA′ in FIG5 ;

[0051] FIG7 shows a cross-sectional view taken along line BB′ in FIG5 ;

[0052] FIG8 is a schematic diagram showing a stacking pattern of data line leads, touch leads, a first sub-shielding film layer and a second sub-shielding film layer at a local position O in FIG1A and FIG1B;

[0053] FIG9 shows a cross-sectional view taken along line AA′ in FIG8 ;

[0054] FIG10 shows a cross-sectional view taken along line BB' in FIG8;

[0055] FIG11 shows a cross-sectional view taken along line CC' in FIG8 ;

[0056] FIG12 is a schematic diagram showing a pattern of the first sub-shielding film layer in another embodiment;

[0057] FIG13 is a schematic diagram showing a pattern of the second sub-shielding film layer in another embodiment;

[0058] FIG14 is a schematic diagram showing a pattern stacking of the first sub-shielding film layer and the second sub-shielding film layer in another embodiment;

[0059] FIG15 is a schematic diagram showing a pattern of the first sub-shielding film layer in another embodiment;

[0060] FIG16 is a schematic diagram showing a pattern of the second sub-shielding film layer in another embodiment;

[0061] FIG17 is a schematic diagram showing a pattern stacking diagram of the first sub-shielding film layer and the second sub-shielding film layer in another embodiment;

[0062] FIG18 is a schematic circuit diagram showing a pixel circuit structure of a sub-LTPS mode in a display panel provided in one embodiment of the present disclosure;

[0063] FIG19 is a schematic diagram of the circuit structure of the LTPO mode sub-pixel driving circuit in the display substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0064] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0065] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0066] With the continuous development of display technology, touch display devices are being used more and more widely. Touch display devices integrate a touch panel and a display panel. When using a touch display device, users can directly input or control operations through touch, making the application of touch display devices more convenient.

[0067] TSP (Touch Sensor Panel) can use FMLOC (Flexible Multi Layer On Cell) process to design the touch structure. The FMLOC process refers to the production of a metal grid electrode layer on the packaging substrate of the display panel (PNL) for touch control, eliminating the need for an external TSP and achieving a thinning effect.

[0068] Due to the requirements of basic functions or detection functions, peripheral routing is inevitably required in the peripheral area of ​​the display panel, such as peripheral display routing (BP routing), peripheral touch routing (TP routing), and screen crack detection routing (PCD routing). Among them, the peripheral touch routing is used to implement the touch function, the peripheral display routing is used to implement the display function, and the screen crack detection routing is used to implement edge fracture or hole area fracture detection functions.

[0069] A variety of peripheral signal lines are arranged around the periphery of the FMLOC display panel. There are overlapping areas between some signal lines to which different electrical signals are applied, resulting in signal crosstalk and affecting the quality of the display product.

[0070] In order to solve the above problems, the embodiments of the present disclosure provide a display substrate and a display device, which can reduce the signal crosstalk problem and improve the quality of display products.

[0071] As shown in FIG. 1A , FIG. 1B , FIG. 2 to FIG. 3 , and FIG. 8 , an embodiment of the present disclosure provides a display substrate, including:

[0072] Base substrate 100;

[0073] A first conductive layer located on the base substrate 100 , wherein the first conductive layer has a first signal pattern 201 ;

[0074] a second conductive layer located on the base substrate 100 , wherein the first conductive layer and the second conductive layer are provided in different layers, and the second conductive layer has a second signal pattern 301 , and orthographic projections of the first signal pattern 201 and the second signal pattern 301 on the base substrate 100 have an overlapping area S1 ; and

[0075] a shielding layer 400 located on the base substrate 100, wherein the shielding layer 400 is located between the first conductive layer and the second conductive layer in a direction perpendicular to the base substrate 100, and the shielding layer 400, the first conductive layer, and the second conductive layer are insulated from each other by an insulating layer 500;

[0076] In which, the shielding layer 400 includes at least two stacked sub-shielding film layers 401, each of the sub-shielding film layers 401 is provided with a hollow area 400A and a shielding area 400B, and the part where the hollow area 400A of one layer of the sub-shielding film layer 401 and the shielding area 400B of another layer of the sub-shielding film layer 401 overlap on the base substrate 100 is a first overlapping area S2, and the first overlapping area S2 at least partially overlaps with the overlapping area S1.

[0077] In the above solution, the first signal pattern 201 and the second signal pattern 301 in the display substrate have an overlapping region S1. Therefore, a shielding layer 400 is provided between them to reduce signal crosstalk. However, since the first signal pattern 201 and the second signal pattern 301 are separate and insulated layers, an insulating layer 500 is located between them. The insulating layer 500 can be made of either organic or inorganic materials. To facilitate gas discharge during the manufacturing process of the organic insulating layer 500, a hollow region 400A is provided in the shielding layer 400 above the organic insulating layer 500. This hollow region 400A serves as a vent.

[0078] If only one layer of shielding layer 400 is provided, there will still be a certain degree of signal crosstalk between the first signal pattern 201 and the second signal pattern 301 at the hollow area 400A, and due to the presence of the hollow area 400A, the space for arranging the signal patterns will also be limited. Therefore, in the above scheme, the shielding layer 400 is provided with at least two layers of sub-shielding film layers 401, and the portion where the hollow area 400A on one sub-shielding film layer 401 overlaps with the shielding area 400B of another sub-shielding film layer 401 on the base substrate 100 is the first overlapping area S2, and the first overlapping area S2 at least partially overlaps with the overlapping area S1. Overlapping area S1

[0079] That is to say, the hollow areas 400A of at least two layers of sub-shielding film layers 401 compensate each other at least in the overlapping area S1 of the first signal pattern 201 and the second signal pattern 301, so that the entire shielding layer 400 forms a complete shielding surface at least in the overlapping area S1, which can effectively avoid crosstalk between different signals on the first signal pattern 201 and the second signal pattern 301, thereby improving product quality.

[0080] 1A and 1B , the display substrate has a display area AA and a peripheral area B located outside the display area AA. The first signal pattern 201 and the second signal pattern 301 can be signal patterns provided in the peripheral area B or in the display area AA.

[0081] Furthermore, different electrical signals can be applied to the first signal pattern 201 and the second signal pattern 301. The signal patterns of the first signal pattern 201 and the second signal pattern 301 can be signal trace patterns or electrode patterns. Furthermore, the display substrate provided in the embodiments of the present disclosure can be applied to a touch display substrate, but is not limited thereto.

[0082] The display substrate provided in the embodiment of the present disclosure is described in more detail below by taking the display substrate provided in the embodiment of the present disclosure as a touch display substrate as an example.

[0083] Touch screens can be categorized into four main types based on their operating principles and the medium used to transmit information: resistive, capacitive, infrared, and surface acoustic wave. Resistive and capacitive touch screens are widely used, with projected capacitive being the most widely used due to its multi-touch capabilities. However, their main drawbacks are high cost and thickness. Low cost and thinness are the new trends in the touch screen industry. To achieve thinner and lighter touch panels, research into integrating touch panels with liquid crystal display (LCD) panels is gaining popularity. In-cell touch solutions, where the touch panel is embedded within the LCD panel, are attracting significant attention.

[0084] There are three types of in-cell touch technologies: resistive, capacitive, and optical. Capacitive solutions include self-capacitive touch and mutual-capacitive touch. In the self-capacitive touch method, the transparent conductive layer used as the common electrode (Vcom) on the display substrate is divided into several blocks as touch electrodes. One end of the touch signal line (Tx line) is connected to the touch electrode through a via, and the other end is connected to the driver integrated circuit. When a finger touches the display substrate, it will cause the capacitance value of the touch electrode at the corresponding position to fluctuate. The driver integrated circuit can determine the position of the touch point by detecting the fluctuation of the capacitance value, thereby realizing the touch function.

[0085] FIC (Full In Cell Touch) touchscreens integrate both touch electrodes and touch signal lines within the display substrate. This allows the touch electrodes and touch signal lines used to implement the touch function to be integrated within the LCD panel when the LCD panel is manufactured using this display substrate, thus achieving an embedded touch structure for the LCD touchscreen display panel. Full In Cell Touch LCD touchscreen panels integrate touch and display functions, enabling seamless, one-stop production and offering advantages such as integration, lightweight design, low cost, low power consumption, high image quality, and the ability to implement multiple touch modes (i.e., Multi-Touch).

[0086] The display substrates provided in some embodiments of the present disclosure can be applied to OLED display substrates, and their touch functions may include, but are not limited to, self-capacitive touch or mutual-capacitive touch. The touch layer in the display substrates provided in embodiments of the present disclosure can be a flexible multi-layer on-screen touch structure (FMLOC) or a flexible single-layer on-screen touch structure (FSLOC). The specific structure is not further described here.

[0087] In some exemplary embodiments of the present disclosure, the display substrate may include a display function layer and a touch layer. The display function layer is used to implement the display function and may include multiple sub-pixels. The sub-pixels include coupled pixel drive circuits and light-emitting elements. The pixel drive circuit is used to provide drive signals to the light-emitting elements to drive the light-emitting elements to emit light, thereby implementing the display function of the display substrate. The display function layer will be described in more detail below. The touch layer includes multiple touch electrodes distributed in an array and touch signal lines connected to the touch electrodes. The touch layer will be described in more detail below.

[0088] As shown in FIG1A , the display substrate includes a bonding side BA, on which a driver integrated circuit (IC) 600, ie, a flexible printed circuit (FPC), is disposed. The display function layer and the touch control layer are both connected to the driver integrated circuit 600.

[0089] Specifically, as shown in Figures 1A and 1B, the peripheral area B includes a non-bending area BA1, a bending area BA2, and a bonding area BA3. The non-bending area BA1 is adjacent to the display area AA, and the bending area BA2 is located between the bonding area BA3 and the non-bending area BA1. The bonding area BA3 is bonded to a driver integrated circuit 600. The driver integrated circuit 600 may include a first driver integrated circuit 601 and a second driver integrated circuit 602.

[0090] As shown in FIG1B , the pixel driving circuit in the display function layer of the display substrate includes a plurality of gate lines 210 and a plurality of data lines 220 located within the display area AA. The plurality of gate lines 210 and the plurality of data lines 220 intersect with each other to define a plurality of sub-pixels P. Each sub-pixel P may be provided with at least one thin film transistor and at least one light-emitting element. The pixel driving circuit also includes a plurality of gate line leads and a plurality of data line leads located in the peripheral area. The gate line leads are led from the gate lines 210 and connected to the gate driving circuit 230 located in the peripheral area B; the data line leads are led from the data lines and connected to the first driver integrated circuit 601.

[0091] Exemplarily, as shown in FIG1B , a plurality of sub-pixels P are provided in the display area AA, and the plurality of sub-pixels P can be arranged in an array, for example, in the form of multiple rows, including a first row of sub-pixels P1, a second row of sub-pixels P2, ..., an nth row of sub-pixels Pn.

[0092] As shown in FIG1B , a plurality of data lines DATA1, DATA2, ..., DATAk are located in the display area and extend along a first direction Y. The plurality of data lines DATA1, DATA2, ..., DATAk are electrically connected to the plurality of sub-pixels P. For example, in FIG1B , the data line DATA1 is connected to the first column of sub-pixels P, the data line DATA2 is connected to the second column of sub-pixels P, and so on, the data line DATAk is connected to the kth column of sub-pixels.

[0093] A plurality of gate lines Gate1, Gate2, ..., Gaten are located in the display area 10 and extend along the second direction X. The first direction Y intersects the second direction X. The plurality of gate lines Gate1, Gate2, ..., Gaten are electrically connected to the plurality of sub-pixels P. For example, gate line Gate1 is connected to the first row of sub-pixels P1, gate line Gate2 is connected to the second row of sub-pixels P2, and so on, gate line Gaten is connected to the nth row of sub-pixels Pn.

[0094] The gate drive circuit 230 is located in the peripheral area B, and the gate drive circuit 230 is connected to a plurality of gate lines Gate1, Gate2, ..., Gaten. For example, in Figure 1B, the gate drive circuit 230 includes a plurality of shift registers GOA0, GOA1, ..., GOAn in a multi-stage cascade, that is, the output end of the first shift register GOAi of the i-th stage is connected to the reset end of the first shift register GOA(i+1) of the i+1-th stage. The first shift register GOA1 of the first stage is connected to the gate line Gate1 to provide a gate drive signal to the first row of sub-pixels P1, the second-stage first shift register GOA2 is connected to the gate line Gate2 to provide a gate drive signal to the second row of sub-pixels P2, and so on. In Figure 1B, the gate drive signal generated by the i-th stage shift register GOAi for the i-th row of sub-pixels Pi is also used as the reset signal RST(i+1) for the i+1-th row of sub-pixels P(i+1). For example, the gate drive signal for the sub-pixel P0 in the 0th row generated by the first shift register GOA0 of the 0th level is also used as the reset signal RST1 for the sub-pixel P1 in the 1st row, and the gate drive signal for the sub-pixel P1 in the 1st row generated by the first shift register GOA1 of the 1st level is also used as the reset signal RST2 for the sub-pixel P2 in the 2nd row, and so on.

[0095] As shown in FIG1B , the display substrate may further include a plurality of emission control lines EM1, EM2, ..., EMn and an emission control driving circuit 240. The plurality of emission control lines EM1, EM2, ..., EMn pass through the display area AA and extend along the second direction X. The plurality of emission control lines EM1, EM2, ..., EMn are electrically connected to a plurality of sub-pixels P. For example, in FIG1B , the emission control line EM1 is electrically connected to the first row of sub-pixels P1, the emission control line EM2 is electrically connected to the second row of sub-pixels P2, and so on.

[0096] The light-emitting control driving circuit 240 is located in the peripheral area B and on a side of the gate driving circuit 230 away from the display area AA. In FIG1B , the light-emitting control driving circuit 240 includes a plurality of cascaded stages of second shift registers EOA0, EOA1, ..., EOAm, wherein the second shift register EOA0 of the 0th stage is connected to the light-emitting control lines EM1 and EM2 to provide light-emitting control signals to the first row of sub-pixels P1 and the second row of sub-pixels P2, respectively. The second shift register EOA1 of the 1st stage is connected to the light-emitting control lines EM3 ​​and EM4 to provide light-emitting control signals to the third row of sub-pixels P3 and the fourth row of sub-pixels P4, respectively.

[0097] A second start voltage signal line ESTV, a third clock signal line ECK, and a fourth clock signal line ECB may also be arranged in the peripheral area B. The light-emission control driving circuit 240 is also electrically connected to the second start voltage signal line ESTV, the third clock signal line ECK, and the fourth clock signal line ECB to generate light-emission control signals under their control. For example, the second shift register EOA0 of the 0th stage in the light-emission control driving circuit 240 is electrically connected to the second start voltage signal line ESTV, the third clock signal line ECK, and the fourth clock signal line ECB to generate light-emission control signals for sub-pixels P1 in the first row and sub-pixels P2 in the second row under the control of the second start voltage signal line ESTV, the third clock signal line ECK, and the fourth clock signal line ECB. Similarly, the second shift register EOA1 of the 1st stage in the light-emission control driving circuit 240 is electrically connected to the third clock signal line ECK and the fourth clock signal line ECB to generate light-emission control signals for sub-pixels P2 in the second row and sub-pixels P3 in the third row under the control of the third clock signal line ECK and the fourth clock signal line ECB.

[0098] As shown in Figure 1A, the touch layer in the display substrate may include: multiple touch electrodes 320 located in the display area AA, and multiple touch leads 310 located in the peripheral area B, wherein the touch electrodes 320 are used to realize the touch function, and the multiple touch leads 310 are led out from the display area AA, and the touch leads 310 are used to connect the touch electrodes 320 and the second driving integrated circuit 602 to transmit touch signals.

[0099] The multiple touch electrodes 320 may include first touch electrodes 321 and second touch electrodes 322. Exemplarily, the touch layer may be composed of two intersecting metal wire channels, namely, a Tx channel and an Rx channel. The Tx channel is composed of multiple rows of first electrode chains, each row of the first electrode chain including multiple first touch electrodes 321 arranged in sequence and connected. The Rx channel is composed of multiple columns of second electrode chains, each column of the second electrode chain including multiple second touch electrodes 322 arranged in sequence and connected. Whether a touch has occurred is determined by detecting the change in mutual capacitance ΔCm between the two channels before and after contact.

[0100] The multiple touch leads 310 include: multiple first touch leads 311 connected to multiple rows of the first electrode chains, and multiple second touch leads 312 connected to multiple columns of the second electrode chains, wherein the first electrode chains extend in the same direction as the gate lines 210, and the second electrode chains extend in the same direction as the data lines 220.

[0101] At least part of the touch lead 310 overlaps with part of the data line lead 221 in its orthographic projection on the base substrate 100, the first signal pattern 201 includes one of the overlapping touch lead 310 and the data line lead 221, and the second signal pattern 301 includes the other of the overlapping touch lead 310 and the data line lead 221.

[0102] In the above solution, the shielding layer 400 is disposed between the data line lead 221 and the touch lead 310 in the peripheral area B to shield signal interference in the overlapping area S1 of the data line lead 221 and the touch lead 310 .

[0103] It should be understood that in other embodiments not shown, the display substrate may further include gate line leads, electrical test leads or screen crack detection leads extending from the display area AA, and the first conductive pattern and the second conductive pattern may be any two overlapping ones of the gate line leads, the electrical test leads, the touch leads 310, the data line leads 221 and the screen crack detection leads.

[0104] In some exemplary embodiments of the present disclosure, as shown in Figures 1A and 1B, on the binding side BA, the plurality of data line leads 221 and the plurality of touch leads 310 extend from the non-bending area BA1 through the bending area BA2 to the binding area BA3 and are connected to the driver integrated circuit 600. The display substrate also includes an opposite side BB opposite to the binding side BA, and a first side BC and a second side BD opposite to each other in the extending direction of the gate line 210. Taking the orientation of the display substrate in a usage scenario as an example, the binding side BA is the bottom side, the opposite side BB is the top side, and the first side BC and the second side BD are the left and right sides.

[0105] As shown in Figure 1A, some touch leads 310 can be extended from the first side BC and the second side BD of the display area AA of the display substrate, that is, from the left and right sides of the display substrate. The multiple touch leads 310 can be divided into a first group of touch leads 310A and a second group of touch leads 310B. The first group of touch leads 310A includes a plurality of first touch leads 311 extending from the first side BC of the first electrode chain and a plurality of second touch leads 312 proximate to the first side BC. The second group of touch leads 310B includes a plurality of first touch leads 311 extending from the second side BD of the first electrode chain and a plurality of second touch leads 312 proximate to the second side BD.

[0106] Since the first group of touch leads 310A is close to the first side BC and the second group of touch leads 310B is close to the second side BD, if the first group of touch leads 310A and the second group of touch leads 310B are distributed on the first side BC and the second side BD of the display substrate, since the first group of touch leads 310A and the second group of touch leads 310B are separated by a large distance, the driver integrated circuit 600 needs to have sufficient wiring width when designing.

[0107] In order to reduce the wiring width of the driver integrated circuit 600, in some exemplary embodiments of the present disclosure, as shown in FIG1A and FIG1B , at least a portion of the data line lead 221 extends from the non-bending area BA1 through the bending area BA2 to the binding area BA3, and the lead portion of the data line lead 221 extending into the binding area BA3 extends along the first direction Y and is connected to the driver integrated circuit 600;

[0108] At least a portion of the touch lead 310 extends from the non-bending area BA1 through the bending area BA2 into the binding area BA3. The portion of the touch lead 310 extending into the binding area BA3 is bent along a second direction X that intersects the first direction Y to form a winding segment 310a. The end of the winding segment 310a extends along the first direction Y to the driver integrated circuit 600. Specifically, the winding segment 310a is connected to the second driver integrated circuit 602. As shown in FIG. 2 , the winding segment 310a intersects the data line lead 221 at its corresponding position to form the overlapping area S1.

[0109] In the above scheme, at least part of the touch leads 310 are designed to be wound after extending to the binding area BA3. In this way, the touch leads 310 can be wound according to the actual wiring space to make the touch leads 310 led out from the first side BC and the second side BD as close to each other as possible, so as to reduce the wiring width of the driver integrated circuit 600.

[0110] In some exemplary embodiments of the present disclosure, as shown in FIG. 5 to FIG. 8 , the orthographic projection of the shielding layer 400 on the base substrate 100 at least covers the orthographic projection of the winding segment 310 a on the base substrate 100 .

[0111] Of course, it is understandable that, in other embodiments, the shielding layer 400 may also only cover the overlapping region S1 between the winding segment 310 a and the data line lead 221 .

[0112] In addition, in some exemplary embodiments of the present disclosure, as shown in Figure 1A, the first group of touch leads 310A includes a plurality of first touch leads 311 led out from the first side BC of the first electrode chain, and a plurality of second touch leads 312 close to the first side BC; the second group of touch leads 310B includes a plurality of first touch leads 311 led out from the second side BD of the first electrode chain, and a plurality of second touch leads 312 close to the second side BD; wherein, each touch lead 310 in the second group of touch leads 310B is bent toward the direction close to the first group of touch leads 310A after extending from the non-bending area BA1 through the bending area BA2 to the binding area BA3 to form the winding segment 310a.

[0113] In this way, one of the two groups of touch leads 310 located on opposite sides of the display area AA is routed toward the other group of touch leads 310, thereby bringing the two groups of touch leads 310 closer together. In other embodiments, the two groups of touch leads 310 may be routed toward each other.

[0114] In some exemplary embodiments of the present disclosure, each sub-shielding film layer 401 is connected to the same signal. For example, each sub-shielding film layer 401 is grounded (GND). This prevents signal crosstalk. The sub-shielding film layer 401 can be made of metal.

[0115] In some exemplary embodiments of the present disclosure, the display substrate may include a source / drain metal layer (SD), wherein the pattern of the source / drain metal layer includes at least one of the source and drain electrodes of the thin film transistor and the data line 220. The at least one sub-shielding film layer 401 is formed on the same layer and made of the same material as the source / drain metal layer. In this way, the at least one sub-shielding film layer 401 can be formed through a single patterning process when forming at least one of the source electrode, drain electrode, and data line 220 pattern on the source / drain metal layer.

[0116] Figure 5 is a schematic diagram showing the structure of the touch lead 310, the data line lead 221 and a sub-shielding film layer. Figure 6 is a cross-sectional view taken along line AA' in Figure 5; and Figure 7 is a cross-sectional view taken along line BB' in Figure 5.

[0117] 5 to 7 , the film layer stack structure of the peripheral region B of the display substrate on the bonding side BA may exemplarily include a first gate metal layer Gate1, an interlayer insulating layer ILD, a second gate metal layer Gate2, a first planarization layer PLN1, a source / drain metal layer SD, a second planarization layer PLN2, and a first metal layer TM stacked on the base substrate 100. One of the sub-shielding film layers is a first sub-shielding film layer 401, which is made of a source / drain metal layer material.

[0118] In some embodiments, the display substrate may include a single source / drain metal layer, namely, a first source / drain metal layer (SD1 layer), or may include multiple source / drain metal layers, namely, a second source / drain metal layer (SD2 layer). One of the sub-shielding film layers is the first sub-shielding film layer 401, and another sub-shielding film layer is the second sub-shielding film layer 402. The first sub-shielding film layer 401 may be formed from the same material as any source / drain metal layer, and the second sub-shielding film layer 402 may be formed from the same material as another source / drain metal layer. For example, referring to Figures 6, 9, and 10, the first sub-shielding film layer 401 is formed from the second source / drain metal layer SD2, and the second sub-shielding film layer 402 is formed from the first source / drain metal layer SD1.

[0119] It should be noted that the source / drain metal layer is a stacked structure of multiple film layers including a metallic conductive material. The sub-shielding film layer 401 is formed in the same layer and material as the source / drain metal layer. Specifically, the sub-shielding film layer 401 is formed in the same layer and material as the metal film layer in the source / drain metal layer. That is, at least one layer of the sub-shielding film layer 401 can be formed through the same patterning process as the metal film layer in the source / drain metal layer.

[0120] In other embodiments, the display substrate may further include an electrode layer, wherein the pattern of the electrode layer includes an anode, and the at least one sub-shielding film layer 401 is formed in the same layer and made of the same material as the electrode layer. In this way, the at least one sub-shielding film layer 401 can be formed through the same patterning process as the pattern of the anode on the electrode layer.

[0121] In other embodiments, the display substrate further includes at least two touch metal layers, and the patterns of the at least two touch metal layers include at least the pattern of the touch electrode 320. The at least one sub-shielding film layer 401 is formed in the same layer and made of the same material as the at least one touch metal layer. This allows the at least one sub-shielding film layer 401 to be formed through the same patterning process as the touch electrode 320 and other patterns.

[0122] It should be understood that each sub-shielding film layer 401 of the shielding layer 400 may be formed in the same layer and with the same material as other metal layers on the display substrate, or may be formed using a separate patterning process.

[0123] Furthermore, in some embodiments of the present disclosure, the hollowed-out area 400A on each of the sub-shielding film layers 401 includes an opening array, wherein the opening array includes a plurality of openings distributed in an array, and the opening array on one of the sub-shielding film layers 401 is staggered along the row direction or the column direction relative to the opening array on the other sub-shielding film layer 401. In other words, the openings on one of the sub-shielding film layers 401 are arranged directly opposite the shielding area 400B on the other sub-shielding film layer 401. In this way, the orthographic projections of the hollowed-out area 400A on one of the sub-shielding film layers 401 and the shielding area 400B of the other sub-shielding film layer 401 on the base substrate 100 at least partially overlap.

[0124] The shape of the openings can be various regular or irregular shapes such as circle, rectangle, triangle, polygon, etc. The shapes of the openings on each sub-shielding film layer 401 can be the same or different.

[0125] 3, 4, and 12 to 17, in some exemplary embodiments, one of the sub-shielding film layers is designated as a first sub-shielding film layer 401, and the other sub-shielding film layer is designated as a second sub-shielding film layer 402. In the opening array of each sub-shielding film layer, two adjacent rows of openings are staggered to form a wall-like opening arrangement structure. The openings on the two sub-shielding film layers have the same shape, and the openings on the first sub-shielding film layer 401 are staggered with the openings on the second sub-shielding film layer 402 so that they can compensate for each other and achieve a full-surface shielding effect.

[0126] Taking Figures 12 to 17 as an example, in some exemplary embodiments, the hollowed-out area 400A on the first sub-shielding film layer 401 includes multiple openings in regular or irregular shapes such as circles, triangles, quadrilaterals, and polygons, while the shielding area 400B has a shape corresponding to the area outside the hollowed-out area 400A. The hollowed-out area 400A on the second sub-shielding film layer 402 is constructed to have the same shape as the shielding area 400B on the first sub-shielding film layer, while the shielding area 400B is constructed to have the same shape as the hollowed-out area 400A on the first sub-shielding film layer 401. In this way, the two sub-shielding film layers 401 are stacked to compensate for each other's openings, achieving a full-surface shielding effect.

[0127] In other embodiments of the present disclosure, as shown in Figures 13 and 14, the hollow area 400A on each sub-shielding film layer 401 includes a plurality of strip openings arranged at intervals, and one of the sub-shielding film layers 401 is staggered relative to the strip openings on another sub-shielding film layer 401 in a direction perpendicular to the strip openings, so that the hollow area 400A on one of the sub-shielding film layers 401 and the shielding area 400B of the other sub-shielding film layer 401 at least partially overlap with each other in their orthographic projection on the base substrate 100.

[0128] The sub-pixel driving circuit in the display substrate provided in the embodiment of the present disclosure can adopt LTPS and LTPO modes. FIG18 shows a schematic diagram of the circuit structure of a sub-pixel driving circuit in the LTPS mode in the display substrate provided in the embodiment of the present disclosure. Of course, it is understood that the circuit structure of the sub-pixel driving circuit on the display substrate is not limited to this. The sub-pixel driving circuit in the LTPS mode shown in FIG18 is used as an example to illustrate the sub-pixel driving circuit.

[0129] As shown in FIG18 , the pixel driving circuit adopts the LTPS mode.

[0130] The pixel driving circuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst.

[0131] The display substrate includes a power line VDD, a data line DA, a gate line GA, a light emitting control line EM, a first reset line RE1, a second reset line RE2, a first initialization signal line Vinit1, and a second initialization signal line Vinit2.

[0132] The gate of the first transistor T1 is coupled to the corresponding first reset line RE1, the first electrode of the first transistor T1 is coupled to the corresponding first initialization signal line Vinit1, and the second electrode of the first transistor T1 is coupled to the gate of the third transistor T3 (i.e., the first node N1). The gate of the third transistor T3 also serves as the first plate of the storage capacitor Cst, and the second plate of the storage capacitor Cst is coupled to the power line VDD.

[0133] The gate of the second transistor T2 is coupled to the corresponding gate line GA, the first electrode of the second transistor T2 is coupled to the second electrode (i.e., the second node N2) of the third transistor T3 (i.e., the driving transistor), and the second electrode of the second transistor T2 is coupled to the gate of the third transistor T3.

[0134] A gate of the fourth transistor T4 is coupled to the corresponding gate line GA, a first electrode of the fourth transistor T4 is coupled to the corresponding data line DA, and a second electrode of the fourth transistor T4 is coupled to the first electrode of the third transistor T3 (ie, the third node N3).

[0135] A gate of the fifth transistor T5 is coupled to the corresponding light emitting control line EM, a first electrode of the fifth transistor T5 is coupled to the power line VDD, and a second electrode of the fifth transistor T5 is coupled to the first electrode of the third transistor T3.

[0136] The gate of the sixth transistor T6 is coupled to the corresponding light emitting control line EM, the first electrode of the sixth transistor T6 is coupled to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is coupled to the anode of the light emitting element LD (ie, the fourth node N4).

[0137] The gate of the seventh transistor T7 is coupled to the second reset line RE2, the first electrode of the seventh transistor T7 is coupled to the second initialization signal line Vinit2, the second electrode of the seventh transistor T7 is coupled to the anode of the light emitting element LD, and the cathode of the light emitting element LD receives the negative power signal VSS.

[0138] When the pixel driving circuit of the above structure is in operation, each working cycle includes a first reset period P1, a writing compensation period P2, a second reset period P3 and a light emitting period P4.

[0139] In the first reset period P1, the reset signal input by the first reset line RE1 is at an effective level, the first transistor T1 is turned on, and the first initialization signal transmitted by the first initialization signal line Vinit1 is input to the gate of the third transistor T3, so that the gate-source voltage Vgs maintained on the third transistor T3 in the previous frame is cleared, thereby resetting the gate of the third transistor T3.

[0140] During the write compensation period P2, the reset signal is at an inactive level, the first transistor T1 is turned off, the gate scan signal input by the gate line GA is at an active level, the second transistor T2 and the fourth transistor T4 are controlled to be turned on, the data line DA writes the data signal, and transmits it to the first electrode of the third transistor T3 through the fourth transistor T4. At the same time, the second transistor T2 and the fourth transistor T4 are turned on, so that the third transistor T3 forms a diode structure. Therefore, the threshold voltage of the third transistor T3 is compensated by the cooperation of the second transistor T2, the third transistor T3 and the fourth transistor T4. When the compensation time is long enough, the gate potential of the third transistor T3 can be controlled to eventually reach Vdata+Vth, where Vdata represents the data signal voltage value and Vth represents the threshold voltage of the third transistor T3.

[0141] In the second reset period P3, the gate scan signal is at a non-valid level, the second transistor T2 and the fourth transistor T4 are both turned off, the reset signal input by the second reset line RE2 (which can be optionally the first reset line coupled to the adjacent next row of pixel driving circuits) is at a valid level, and the seventh transistor T7 is controlled to be turned on, and the initialization signal input by the second initialization signal line Vinit2 is input to the anode of the light-emitting element LD, so as to control the light-emitting element LD not to emit light.

[0142] During the light-emitting period P4, the light-emitting control signal written into the light-emitting control line EM is at an effective level, controlling the fifth transistor T5 and the sixth transistor T6 to be turned on, so that the power signal transmitted by the power line VDD is input to the first electrode of the third transistor T3. At the same time, since the gate of the third transistor T3 is maintained at Vdata+Vth, the third transistor T3 is turned on, and the gate-source voltage corresponding to the third transistor T3 is Vdata+Vth-Vdd, where Vdd is the voltage value corresponding to the power signal. The leakage current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element LD, driving the corresponding light-emitting element LD to emit light.

[0143] As shown in FIG19 , the pixel driving circuit adopts the LTPO mode.

[0144] As shown in FIG19 , the pixel driving circuit includes a first transistor T1, an organic light emitting diode O1, a driving transistor T0, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, a fifth transistor T5, and a sixth transistor T6;

[0145] The gate of the first transistor T1 is electrically connected to the first node N1, the source of the first transistor T1 is electrically connected to the first initial voltage line, and the drain of the first transistor T1 is electrically connected to the anode of the organic light emitting diode O1;

[0146] The gate of the driving transistor T0 is electrically connected to the first node N1;

[0147] The gate of the second transistor T2 is electrically connected to the light emitting control line E1, the source of the second transistor T2 is electrically connected to the drain of the driving transistor T0, and the drain of the second transistor T0 is electrically connected to the anode of the organic light emitting diode O1;

[0148] The gate of the third transistor T3 is electrically connected to the scan line GA, the source of the third transistor T3 is electrically connected to the data line DA, and the drain of the third transistor T3 is electrically connected to the source of the driving transistor T0;

[0149] The gate of the fourth transistor T4 is electrically connected to the scan line GA, the source of the fourth transistor T4 is electrically connected to the gate of the driving transistor T0, and the drain of the fourth transistor T4 is electrically connected to the drain of the driving transistor T0;

[0150] The first plate of the first capacitor C1 is electrically connected to the gate of the driving transistor T0, and the second plate of the first capacitor C1 is electrically connected to the high voltage line VDD;

[0151] The gate of the fifth transistor T5 is electrically connected to the reset control line R1, the source of the fifth transistor T5 is electrically connected to the second initial voltage line, and the drain of the fifth transistor T5 is electrically connected to the gate of the driving transistor T0;

[0152] The gate of the sixth transistor T6 is electrically connected to the light emitting control line E1, the source of the sixth transistor T6 is electrically connected to the high voltage line VDD, and the drain of the sixth transistor T6 is electrically connected to the source of the driving transistor T0; the cathode of the organic light emitting diode O1 is electrically connected to the low voltage line VSS.

[0153] In at least one embodiment, T1 and T5 are N-type transistors, and T2, T3, T4, T6, and T0 are P-type transistors.

[0154] In at least one embodiment, T1 and T5 can both be oxide transistors, and T2, T3, T4, T6 and T0 can all be LTPS (low-temperature polysilicon) transistors. In this case, the pixel circuit shown in Figure 19 is an LTPO (low-temperature polysilicon transistor and oxide transistor) circuit.

[0155] In addition, the present disclosure also provides a display device including the display substrate provided in the present disclosure. Obviously, the display device provided in the present disclosure can also bring about the beneficial effects brought about by the display substrate provided in the present disclosure, which will not be described in detail here.

[0156] In addition, the present disclosure also provides a method for manufacturing a display substrate, which is used to manufacture the display substrate provided by the present disclosure. The method includes the following steps:

[0157] Step S01: providing a base substrate 100;

[0158] Step S02: forming a first conductive layer, a second conductive layer and a shielding layer 400 on the base substrate 100, wherein the first conductive layer has a first signal pattern 201, the second conductive layer has a second signal pattern 301, and the orthographic projections of the first signal pattern 201 and the second signal pattern 301 on the base substrate 100 have an overlapping area S1; the shielding layer 400 is located between the first conductive layer and the second conductive layer, and the shielding layer 400, the first conductive layer and the second conductive layer are insulated from each other by an insulating layer 500; the shielding layer 400 includes at least two stacked sub-shielding film layers 401, each layer of the sub-shielding film layer 401 is provided with a hollow area 400A and a shielding area 400B, and the hollow area 400A of at least one layer of the sub-shielding film layer 401 and the orthographic projections of the shielding area 400B of the other layer of the sub-shielding film layer 401 on the base substrate 100 overlap at least in the overlapping area S1.

[0159] In the above solution, the first signal pattern 201 and the second signal pattern 301 in the display substrate can each be applied with different signals, and an overlapping region S1 exists between them. Therefore, a shielding layer 400 is provided between them to reduce signal crosstalk. However, since the first signal pattern 201 and the second signal pattern 301 are separate and insulated layers, an insulating layer 500 is located between them. The insulating layer 500 can be made of either organic or inorganic materials. To facilitate gas discharge during the manufacturing process of the organic insulating layer 500, a hollow region 400A is provided in the shielding layer 400 above the organic insulating layer 500. This hollow region 400A serves as a vent.

[0160] If only one shielding layer 400 is provided, there will still be a certain degree of signal crosstalk between the first signal pattern 201 and the second signal pattern 301 at the hollow area 400A. Furthermore, the presence of the hollow area 400A will also limit the space available for arranging the signal patterns. Therefore, in the above solution, the shielding layer 400 is provided with at least two sub-shielding film layers 401, and the orthographic projections of the hollow area 400A on at least one sub-shielding film layer 401 and the shielding area 400B of the other sub-shielding film layer 401 on the base substrate 100 overlap at least in the overlapping region S1.

[0161] That is to say, the hollow areas 400A of at least two layers of sub-shielding film layers 401 compensate each other at least in the overlapping area S1 of the first signal pattern 201 and the second signal pattern 301, so that the entire shielding layer 400 forms a complete shielding surface at least in the overlapping area S1, which can effectively avoid crosstalk between different signals on the first signal pattern 201 and the second signal pattern 301, thereby improving product quality.

[0162] In some exemplary embodiments of the present disclosure, the display substrate further includes a source / drain metal layer; and the above step S02 specifically includes:

[0163] Step S021, forming the source-drain metal layer on the base substrate 100, and patterning the source-drain metal layer using the same composition process to form at least one of the source, drain and data line 220 of the thin film transistor, and at least one layer of the sub-shielding film layer 401.

[0164] In this way, no additional process steps are required.

[0165] Specifically, in step S021, the source / drain metal layer is a multi-layer structure including a metal film layer, wherein when forming the pattern of the metal film layer in the source / drain metal layer, at least one layer of the sub-shielding film layer 401 is formed simultaneously using the same patterning process.

[0166] In addition, in some exemplary embodiments of the present disclosure, the display substrate further includes an electrode layer; and the above step S02 specifically includes:

[0167] Step S021 ′: forming a third conductive layer on the base substrate 100 , and patterning the third conductive layer using the same patterning process to form an anode layer and at least one sub-shielding film layer 401 .

[0168] In addition, in some exemplary embodiments of the present disclosure, the display substrate further includes a touch electrode 320; the above step S02 specifically includes:

[0169] In step S021 ″, at least two metal layers are formed on the base substrate 100 , and at least one of the metal layers is patterned using the same patterning process to form a pattern of the touch electrode 320 and at least one sub-shielding film layer 401 .

[0170] There are a few points to note:

[0171] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0172] (2) For the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are exaggerated or reduced, i.e., these drawings are not drawn to scale. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or intervening elements may be present.

[0173] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0174] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, characterized in that: include: substrate substrate; A first conductive layer located on the base substrate, wherein the first conductive layer has a first signal pattern; a second conductive layer located on the base substrate, wherein the first conductive layer and the second conductive layer are arranged in different layers, the second conductive layer has a second signal pattern, and the orthographic projections of the first signal pattern and the second signal pattern on the base substrate have an overlapping area; and A shielding layer is located on the base substrate, the shielding layer is located between the first conductive layer and the second conductive layer, and the shielding layer, the first conductive layer and the second conductive layer are insulated from each other by an insulating layer; wherein, The shielding layer includes at least two stacked sub-shielding film layers, each of the sub-shielding film layers is provided with a hollow area and a shielding area, and the part where the orthographic projection of the hollow area of ​​one sub-shielding film layer on the base substrate overlaps with the orthographic projection of the shielding area of ​​another sub-shielding film layer on the base substrate is a first overlapping area, and the first overlapping area at least partially overlaps with the overlapping area.

2. The display substrate according to claim 1, characterized in that: Different electrical signals may be applied to the first signal pattern and the second signal pattern respectively.

3. The display substrate according to claim 1, characterized in that: The display substrate comprises a display area and a peripheral area located outside the display area, and a driving integrated circuit is arranged in the peripheral area on the binding side of the display substrate; The display substrate comprises: A plurality of touch control leads extending from the display area, wherein the plurality of touch control leads are located in the peripheral area and connected to the driving integrated circuit; and A plurality of data line leads extending from the display area, the data line leads being located in the peripheral area and connected to the drive integrated circuit; wherein, At least part of the touch leads overlaps with part of the data line leads in orthographic projection on the substrate, the first signal pattern includes one of the overlapping touch leads and the data line leads, and the second signal pattern includes the other of the overlapping touch leads and the data line leads. One.

4. The display substrate according to claim 3, characterized in that: On the binding side, the peripheral area includes a non-bending area, a bending area and a binding area, the non-bending area is adjacent to the display area, and the bending area is located between the binding area and the non-bending area; wherein, At least part of the data line leads extend from the non-bending area through the bending area to the binding area, and the lead portion of at least part of the data line leads extending into the binding area extends along a first direction and is connected to the driving integrated circuit; At least part of the touch leads extend from the non-bending area through the bending area to the binding area, and the lead portion of at least part of the touch leads extending to the binding area is bent along a second direction intersecting the first direction to form a winding segment, and an end of the winding segment extends along the first direction to the driver integrated circuit; The winding segment and the data line lead corresponding to the position thereof cross to form the overlapping area, and the orthographic projection of the shielding layer on the base substrate at least covers the orthographic projection of the winding segment on the base substrate.

5. The display substrate according to claim 4, characterized in that: The display substrate further comprises: A plurality of gate lines and a plurality of data lines are located in the display area, the plurality of gate lines intersect with the plurality of data lines, and the data line leads are led out from the data lines to the peripheral area; A plurality of rows of first electrode chains and a plurality of columns of second electrode chains are located in the display area, wherein the first electrode chains and the gate lines extend in the same direction, and the second electrode chains and the data lines extend in the same direction; The plurality of touch leads include: a plurality of first touch leads connected to a plurality of rows of the first electrode chains, and a plurality of second touch leads connected to a plurality of columns of the second electrode chains.

6. The display substrate according to claim 5, characterized in that: The peripheral region further includes a first side and a second side opposite to each other in the extending direction of the gate lines; The plurality of touch leads are divided into a first group of touch leads and a second group of touch leads; The first group of touch leads includes a plurality of first touch leads extending from a first side of the first electrode chain, and a plurality of second touch leads close to the first side; The second group of touch leads includes a plurality of first touch leads extending from the second side of the first electrode chain, and a plurality of second touch leads close to the second side; Wherein, each touch lead in the second group of touch leads passes through the non-bending area. The bending area extends to the binding area and then bends toward the direction close to the first group of touch leads to form the winding segment.

7. The display substrate according to claim 1, characterized in that: The same signal is connected to each sub-shielding film layer.

8. The display substrate according to claim 1, characterized in that: The display substrate further comprises: The source-drain metal layer has a pattern including a source and a drain of a thin film transistor, and at least one of a data line; at least one sub-shielding film layer is in the same layer and made of the same material as the source-drain metal layer.

9. The display substrate according to claim 1, characterized in that: The display substrate further comprises: an electrode layer, the pattern of the electrode layer comprises an anode, and at least one layer of the sub-shielding film layer is in the same layer and made of the same material as the electrode layer.

10. The display substrate according to claim 1, characterized in that: The display substrate further comprises: At least two touch metal layers, the patterns of the at least two touch metal layers at least include the patterns of touch electrodes; wherein at least one of the sub-shielding film layers is in the same layer and made of the same material as the at least one touch metal layer.

11. The display substrate according to claim 1, characterized in that: The hollow area on each of the sub-shielding film layers includes an opening array, and the opening array includes a plurality of openings distributed in an array, wherein the opening array on one of the sub-shielding film layers is staggered along the row direction or the column direction relative to the opening array on the other sub-shielding film layer, so that the hollow area on one of the sub-shielding film layers and the shielding area of ​​the other sub-shielding film layer at least partially overlap with the orthographic projection on the substrate; and / or The hollow area on each of the sub-shielding film layers includes a plurality of strip openings arranged at intervals, wherein one of the sub-shielding film layers is staggered relative to the strip openings on another sub-shielding film layer in a direction perpendicular to the strip openings, so that the hollow area on one of the sub-shielding film layers at least partially overlaps with the orthographic projection of the shielding area on the other sub-shielding film layer on the base substrate.

12. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 11.

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