Data selection device for SRAM array, and storage system and system-on-chip

Abstract

Embodiments of the present application provide a data selection device for an SRAM array, and a storage system and a system-on-chip. The data selection device comprises: a multiplexer array comprising a plurality of multiplexers; and a D flip-flop array comprising a plurality of D flip-flops, wherein the D flip-flop array is arranged in the multiplexer array; the multiplexer array has an input end connected to an output end of the SRAM array, and an output end connected to a bus; the multiplexer array is used for selecting output paths for outputting storage data in the SRAM array; and the D flip-flops arranged on the output paths are used for cutting off time sequence paths of the output paths.

Description

Data selection device for SRAM array, storage system and system-level chip

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 1, 2023, with application number 202311118068.5 and application name “Data selection device, storage system and system-level chip for SRAM array”. Technical Field

[0002] The present application relates to the field of data storage, and in particular to a data selection device, a storage system, and a system-on-chip for a static random-access memory (SRAM) array.

[0003] Background of the Invention

[0004] Static random-access memory (SRAM) is a commonly used storage device in chip design. Due to limitations in SRAM manufacturing processes, the capacity of a single SRAM block is typically limited. System-on-chip (SOC) designs have a high demand for SRAM, often using multiple SRAM banks to achieve large storage capacities. However, because the SRAM output data is far from the control logic and requires long traces, this results in timing delays in the output data, complicating back-end timing closure.

[0005] Currently, front-end designs typically connect D-type flip-flops directly to each SRAM data output port to eliminate the timing delay of the output data. However, this approach requires the deployment of a large number of D-type flip-flops, resulting in high resource costs and hindering the streamlining of hardware architectures.

[0006] Summary of the Invention

[0007] Embodiments of the present application provide a data selection device for an SRAM array, a storage system, and a system-on-chip.

[0008] In one aspect, an embodiment of the present application provides a data selection device for a static random access memory (SRAM) array, comprising:

[0009] a multiplexer array comprising a plurality of multiplexers;

[0010] A D flip-flop array, comprising a plurality of D flip-flops;

[0011] in,

[0012] The D flip-flop array is arranged inside the multiplexer array;

[0013] The input end of the multiplexer array is connected to the output end of the SRAM array;

[0014] The output end of the multiplexer array is connected to a bus;

[0015] The multiplexer array is used to select an output path in the SRAM array for outputting stored data;

[0016] The D flip-flop arranged on the output path is used to cut off the timing path of the output path.

[0017] On the other hand, an embodiment of the present application further provides a storage system, including:

[0018] A static random access memory (SRAM) array, wherein the SRAM array comprises a plurality of SRAM groups, and each SRAM group comprises a plurality of SRAMs;

[0019] a multiplexer array comprising a plurality of multiplexers;

[0020] A D flip-flop array, comprising a plurality of D flip-flops;

[0021] in,

[0022] The D flip-flop array is arranged inside the multiplexer array;

[0023] The input terminal of each multiplexer is connected to the output terminal of the corresponding SRAM group;

[0024] The output end of the multiplexer array is connected to a bus;

[0025] The multiplexer array is used to select an output path in the SRAM array for outputting stored data;

[0026] The D flip-flop arranged on the output path is used to cut off the timing path of the output path.

[0027] On the other hand, an embodiment of the present application further provides a system-on-chip, including the data selection device of the SRAM array as described above, or the storage system as described above.

[0028] BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a diagram showing an exemplary structure of an SRAM array.

[0030] FIG. 2 is an exemplary structural diagram of a data selection device of an SRAM array according to an embodiment of the present application.

[0031] FIG. 3 is an exemplary structural diagram of an SRAM array and a multiplexer array according to an embodiment of the present application.

[0032] FIG. 4 is an exemplary schematic diagram of arranging a D flip-flop array in a multiplexer array according to an embodiment of the present application.

[0033] Implementation Method

[0034] In order to make the objectives, technical solutions and advantages of this application clearer, this application is further described in detail below with reference to the accompanying drawings.

[0035] For the sake of brevity and intuitiveness in description, the solution of the present application is explained below by describing several representative implementation methods. A large number of details in the implementation methods are only used to help understand the solution of the present application. However, it is obvious that the technical solution of the present application may not be limited to these details when implemented. In order to avoid unnecessarily blurring the solution of the present application, some implementation methods are not described in detail, but only a framework is given. Hereinafter, "including" means "including but not limited to", and "according to..." means "at least according to..., but not limited to only according to...". Due to the language habits of Chinese, when the number of a component is not specifically specified below, it means that the component can be one or more, or can be understood as at least one.

[0036] An SRAM array typically includes multiple SRAM groups, each of which contains multiple SRAMs. Figure 1 shows an exemplary structure of an SRAM array. As shown in Figure 1, the SRAM array includes N SRAM groups, namely SRAM Group 0, SRAM Group 1, SRAM Group 2, and SRAM Group (N-1). Each SRAM group contains n SRAMs, namely SRAM 0, SRAM 1, SRAM 2, and SRAM n-1. Therefore, the SRAM array contains a total of n*N SRAMs.

[0037] When the bus performs a read operation on the SRAM array, it selects the data from one of the SRAM groups for output. In the prior art, a D-type flip-flop is directly connected to the data output port of each SRAM group to cut off the timing path for data transmission in that SRAM group, thereby facilitating timing closure. Therefore, the SRAM array requires a total of at least N D-type flip-flops.

[0038] In an embodiment of the present application, a multiplexer (MUX) is used to select data from multiple input data and forward it, and the MUX is combined with a D flip-flop to implement a method of eliminating the timing delay of SRAM output data by using a D flip-flop array inside the MUX array. This method can solve the timing convergence problem while reducing the resource requirements for the D flip-flop.

[0039] FIG. 2 is an exemplary structural diagram of a data selection device for an SRAM array according to an embodiment of the present application.

[0040] In Figure 2, the data selection device of the SRAM array includes:

[0041] a multiplexer array comprising a plurality of multiplexers;

[0042] A D flip-flop array, comprising a plurality of D flip-flops;

[0043] in,

[0044] The D flip-flop array is arranged inside the multiplexer array;

[0045] The input end of the multiplexer array is connected to the output end of the SRAM array;

[0046] The output of the multiplexer array is connected to the bus;

[0047] a multiplexer array for selecting an output path for outputting stored data in the SRAM array;

[0048] The D flip-flop arranged on the output path is used to cut off the timing path of the output path.

[0049] The data selection device using the above-mentioned SRAM array can improve timing delay based on the coordinated cooperation of the multiplexer array and the D flip-flop array, save D flip-flop resources, and simplify the hardware structure.

[0050] Each MUX in the MUX array can select an output path from multiple output channels of the SRAM array. When the bus performs a read operation on the SRAM array, the MUX array selects the output data of an SRAM group in the SRAM array and outputs it to the bus through the output terminal of the MUX array.

[0051] The D flip-flop is an information storage device with a memory function and two stable states. It is the basic logic unit of many sequential circuits. When a trigger edge arrives, the D flip-flop stores the value of its input, and this value is independent of the currently stored value. Between two valid pulse edges, the D flip-flop's input jumps do not affect the value stored in the D flip-flop. Based on these characteristics, the D flip-flop can be used to truncate the timing path of data transmission, thereby facilitating chip timing closure.

[0052] In the embodiments of the present application, by placing the D flip-flop array inside the MUX array, rather than directly connecting the data output port of each SRAM group to the D flip-flops, the number of D flip-flops deployed can be significantly reduced. Furthermore, the D flip-flops combined with the multiplexing function of the MUX can truncate the timing path of each output path to the bus, thereby ensuring timing convergence.

[0053] In one embodiment, the multiple MUXs in the MUX array are multi-stage MUXs; the multiple D flip-flops in the D flip-flop array are arranged in parallel at the same position between multiplexers in adjacent stages of the MUX array. Considering that the timing delay characteristics of each output path are generally the same or similar, arranging the multiple D flip-flops in parallel at the same position between multiplexers in adjacent stages can reduce the layout difficulty.

[0054] In one embodiment, the multiple MUXs in the MUX array are multi-stage MUXs, and the multiple D flip-flops in the D flip-flop array are arranged in parallel at different positions in the MUX array. Considering that the timing delay characteristics of various output paths may vary (for example, the transmission path lengths of various output paths may vary), it is necessary to arrange the multiple D flip-flops in parallel at different positions in the MUX array to truncate the timing path of each output path.

[0055] In one embodiment, the multiple MUXs in the MUX array are multi-stage MUXs; the D flip-flop array includes a first part and a second part; wherein,

[0056] The first part is arranged in parallel at the same position between the multiplexers of adjacent stages in the MUX array;

[0057] The second part is arranged in parallel at different positions in the MUX array.

[0058] Here, for output paths with the same timing delay characteristics, the first part is arranged in parallel at the same position between adjacent multiplexers, thereby not only cutting off the timing paths of these output paths with the same timing delay characteristics but also reducing the difficulty of arrangement.

[0059] In addition, for output paths with different timing delay characteristics, the second part is arranged in parallel at different positions in the MUX array, so that the timing paths of the output paths with different timing delay characteristics can be cut off.

[0060] In one embodiment, in each output path from the output end of the SRAM array to the bus, a first timing delay along the output path to the first D flip-flop is less than a predetermined timing delay threshold, and a difference between the first timing delay and the timing delay threshold is less than a predetermined difference threshold.

[0061] Here, the layout position of the first D flip-flop satisfies:

[0062] (1) The first timing delay reaching the first D flip-flop is less than a predetermined timing delay threshold;

[0063] (2) The difference between the first timing delay reaching the first D flip-flop and the timing delay threshold is less than a predetermined difference threshold.

[0064] The timing delay threshold value may be a fixed value or an adjustable value.

[0065] Similarly, the difference threshold value may be a fixed value or an adjustable value.

[0066] Preferably, the timing delay threshold is determined based on the maximum operating frequency of the SRAM array. For example, assuming that the maximum operating frequency of the SRAM array is 250 MHz, the timing delay threshold may be 1 / 250 MHz = 4 nanoseconds (ns).

[0067] Therefore, this arrangement for the first D flip-flop not only ensures timing closure for the first D flip-flop, but also ensures that the first D flip-flop is placed as far away from the output of the SRAM array as possible, thereby minimizing the number of deployed D flip-flops. For example, a timing delay measurement tool (such as the static timing analysis tool Prime Time) can be used to measure the timing delay for the first D flip-flop.

[0068] In one embodiment, in each output path from the output end of the SRAM array to the bus, a second timing delay between any two closest D flip-flops along the output path is less than a predetermined timing delay threshold, and a difference between the second timing delay and the timing delay threshold is less than a predetermined difference threshold.

[0069] Here, the placement of any two closest D flip-flops satisfies:

[0070] (1) The second timing delay between any two closest D flip-flops is less than a predetermined timing delay threshold;

[0071] (2) The difference between the second timing delay of any two closest D flip-flops and the timing delay threshold is smaller than the predetermined difference threshold.

[0072] The timing delay threshold value may be a fixed value or an adjustable value.

[0073] Similarly, the difference threshold value may be a fixed value or an adjustable value.

[0074] Preferably, the timing delay threshold is determined based on the maximum operating frequency of the SRAM array. For example, assuming that the maximum operating frequency of the SRAM array is 250 MHz, the timing delay threshold may be 1 / 250 MHz = 4 nanoseconds (ns).

[0075] Therefore, timing closure can be guaranteed while also ensuring that the distance between any two closest D flip-flops is as far as possible, thereby minimizing the number of D flip-flops deployed. For example, a timing delay measurement tool (such as the static timing analysis tool Prime Time) can be used to measure the timing delay between any two closest D flip-flops.

[0076] The present application also provides a storage system, including:

[0077] SRAM array, the SRAM array contains multiple SRAM groups, and each SRAM group contains multiple SRAMs;

[0078] MUX array, including multiple multiplexers;

[0079] A D flip-flop array, comprising a plurality of D flip-flops;

[0080] in,

[0081] The D flip-flop array is arranged inside the MUX array;

[0082] The input of each MUX is connected to the output of the corresponding SRAM group;

[0083] The output end of the MUX array is connected to the bus;

[0084] A MUX array is used to select an output path in the SRAM array for outputting stored data;

[0085] The D flip-flop arranged on the output path is used to cut off the timing path of the output path.

[0086] In one embodiment, the MUX array includes multiple stages of MUXs; multiple D flip-flops arranged in parallel at the same position between adjacent stages of MUXs in the MUX array; or multiple D flip-flops arranged in parallel at different positions in the MUX array.

[0087] In one embodiment, the MUX array includes multiple levels of multiplexers; the D flip-flop array includes a first part and a second part; wherein the first part is arranged in parallel at the same position between MUXs of adjacent levels in the MUX array; and the second part is arranged in parallel at different positions in the MUX array.

[0088] In one embodiment, in each output path from the output end of the SRAM array to the bus, a first timing delay along the output path to the first D flip-flop is less than a predetermined timing delay threshold, and a difference between the first timing delay and the timing delay threshold is less than a predetermined difference threshold.

[0089] In one embodiment, in each output path from the output end of the SRAM array to the bus, a second timing delay between any two closest D flip-flops along the output path is less than a predetermined timing delay threshold, and a difference between the second timing delay and the timing delay threshold is less than a predetermined difference threshold.

[0090] FIG3 is an exemplary structural diagram of an SRAM array and a MUX array according to an embodiment of the present application.

[0091] In FIG3 , the SRAM array includes N SRAM groups, namely SRAM group 0, SRAM group 1, SRAM group 2, SRAM group 3, ..., SRAM group (N-1).

[0092] The MUX array contains (M+1) stages, namely the first-stage MUX at position 2 (MUX_L0_0, MUX_L0_1, MUX_L0_2, MUX_L0_3…MUX_L0_(N / 2-1)), the second-stage MUX at position 4 (MUX_L1_0, MUX_L1_1…MUX_L1_(N / 4-1)), the third-stage MUX at position 6 (MUX_L2_0, MUX_L2_1…MUX_L1_(N / 8-1)), and so on.

[0093] In this embodiment, each MUX in the MUX array is implemented as a two-choose-one MUX, that is, it has two data inputs and one data output. The two data inputs of the MUX in the first stage are connected to the corresponding two SRAM groups in the SRAM array, the data outputs of the intermediate MUXs are connected to the data inputs of the next stage MUX, and the data output of the last stage MUX is connected to the bus.

[0094] You can use a timing delay measurement tool (such as Prime Time) to measure the timing delay parameters of each path in the output path from the SRAM bank to each MUX level and then to the bus. Then, identify the rightmost position in the output path that meets the timing delay threshold (that is, as close to the bus as possible) and insert a D flip-flop at this location. The advantage is that the resource cost of inserting a D flip-flop at this location is minimal.

[0095] If the timing delay of the right path after the D flip-flop is inserted still does not meet the timing delay threshold, further D flip-flops may be inserted into the right path.

[0096] The specific insertion methods of D flip-flops can include:

[0097] (1) Multiple D flip-flops can be inserted in parallel at positions such as position 3 (i.e., between the MUX stage at position 2 and the MUX stage at position 4, where the MUX stage at position 2 and the MUX stage at position 4 are adjacent stages), position 5 (i.e., between the MUX stage at position 4 and the MUX stage at position 6, where the MUX stage at position 4 and the MUX stage at position 6 are adjacent stages), and position 7 (i.e., between the MUX stage at position 6 and the MUX stage at position 8, where the MUX stage at position 6 and the MUX stage at position 8 are adjacent stages). Since the D flip-flops correspond to the MUXs in the previous adjacent stage, the number of D flip-flops is equal to the number of MUXs in the previous adjacent stage. These inserted D flip-flops together form a D flip-flop array.

[0098] Assuming that the D flip-flop resources required to be inserted at position 1 are A bits as in the prior art, when a two-choice MUX is used according to the embodiment of the present application, the D flip-flop inserted at position 3 requires A / 2 bits, the D flip-flop inserted at position 5 requires A / 4 bits, and the D flip-flop inserted at position 7 requires A / 8 bits. It can be seen that the embodiment of the present application significantly reduces the D flip-flop resources.

[0099] (2) A D flip-flop can be inserted at any position in the MUX array.

[0100] At this time, the following needs to be met:

[0101] ① In each output path from the output end of the SRAM array to the bus, the timing delay along the output path to the first D flip-flop is less than a predetermined timing delay threshold, and the difference between the timing delay and the timing delay threshold is less than a predetermined difference threshold;

[0102] ② In each output path from the output of the SRAM array to the bus, the timing delay between any two closest D flip-flops is less than the timing delay threshold, and the difference between this timing delay and the timing delay threshold is less than a predetermined difference threshold. D flip-flops inserted in this manner can be perfectly matched to the conditions of each output channel.

[0103] When the timing delay of the output channel is large, more D flip-flops may be inserted into the output channel; when the timing delay of the output channel is small, fewer D flip-flops may be inserted into the output channel.

[0104] The following describes another embodiment of the present application using a storage system as an example. For a 5MB storage system, assume that the storage capacity of an SRAM is 4098 (depth) * 128 (bit width) = 64 (KB). Every four SRAMs form an SRAM group, and the total capacity of the SRAM group is 4098 * 128 * 4 = 256 (KB).

[0105] FIG. 4 is an exemplary schematic diagram of arranging a D flip-flop array in a MUX array according to an embodiment of the present application.

[0106] In FIG4 , the MUXs in the MUX array are all implemented as two-or-one MUXs, that is, each MUX has two data input terminals and one data output terminal.

[0107] The MUX array consists of five stages: the first-stage MUX (MUX_L0_0, MUX_L0_1, MUX_L0_2, MUX_L0_3, ..., MUX_L0_9), the second-stage MUX (MUX_L1_0, MUX_L1_1, ..., MUX_L1_4), the third-stage MUX (MUX_L2_0, MUX_L2_1), the fourth-stage MUX (MUX_L3_0), and the fifth-stage MUX (MUX_L4_0). The output of MUX_L4_0 is connected to the bus.

[0108] Between the second-stage MUX (MUX_L1_0, MUX_L1_1, ..., MUX_L1_4) and the third-stage MUX (MUX_L3_0), five D flip-flops are arranged in parallel to form a D flip-flop array. Compared to the prior art approach of inserting D flip-flops for each SRAM group (requiring a total of 20*128*4 = 10240 bits), the total resource of the D flip-flop array in Figure 4 is 20*128*4 / 4 = 2560 bits. Therefore, the embodiment of the present application not only solves the timing problem but also reduces resource consumption.

[0109] In Figure 4, a two-choose-one MUX is used as an example to illustrate the MUX array. In addition, the MUX can also be implemented as a three-choose-one MUX, a four-choose-one MUX, or an eight-choose-one MUX, etc., and the embodiments of the present application are not limited to this.

[0110] When the number of input terminals of a MUX is greater (ie, when N in the N-to-one MUX is greater), the number of MUXs in the MUX array can be reduced, thereby reducing costs.

[0111] Moreover, the MUXs used in the MUX array can be implemented as MUXs of the same type (for example, all are four-to-one MUXs), or can be implemented as MUXs of different types (for example, one part uses a four-to-one MUX, the other part uses an eight-to-one MUX, and so on). The implementation methods of the present application are not limited to this.

[0112] The data selection device and storage system of the SRAM array can be applied to a system-on-chip. The embodiment of the present application also provides a system-on-chip, comprising the storage system or the data selection device of the SRAM array as described above.

[0113] The above is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A data selection device for a static random access memory (SRAM) array, comprising: a multiplexer array comprising a plurality of multiplexers; A D flip-flop array, comprising a plurality of D flip-flops; in, The D flip-flop array is arranged inside the multiplexer array; The input end of the multiplexer array is connected to the output end of the SRAM array; The output end of the multiplexer array is connected to a bus; The multiplexer array is used to select an output path in the SRAM array for outputting stored data; The D flip-flop arranged on the output path is used to cut off the timing path of the output path.

2. The device according to claim 1, wherein: The multiple multiplexers are multiple-stage multiplexers; the multiple D flip-flops are arranged in parallel at the same position between the multiplexers of adjacent stages; or, The multiple D flip-flops are arranged in parallel at different positions in the multiplexer array.

3. The device according to claim 1, wherein: The multiple multiplexers are multi-stage multiplexers; The D flip-flop array includes a first part and a second part, wherein: The first part is arranged in parallel at the same position between the multiplexers of adjacent stages; The second parts are arranged in parallel at different positions in the multiplexer array.

4. The device according to claim 1, wherein: In each output path from the output end of the SRAM array to the bus, the first timing delay along the output path to the first D flip-flop is less than a predetermined timing delay threshold value, and the difference between the first timing delay and the timing delay threshold value is less than a predetermined difference threshold value.

5. The device according to claim 1, wherein: In each output path from the output end of the SRAM array to the bus, the second timing delay between any two closest D flip-flops along the output path is less than a predetermined timing delay threshold value, and the difference between the second timing delay and the timing delay threshold value is less than a predetermined difference threshold value.

6. A storage system comprising: A static random access memory (SRAM) array, wherein the SRAM array comprises a plurality of SRAM groups, and each SRAM group comprises a plurality of SRAMs; a multiplexer array comprising a plurality of multiplexers; A D flip-flop array, comprising a plurality of D flip-flops; in, The D flip-flop array is arranged inside the multiplexer array; The input terminal of each multiplexer is connected to the output terminal of the corresponding SRAM group; The output end of the multiplexer array is connected to a bus; The multiplexer array is used to select an output path in the SRAM array for outputting stored data; The D flip-flop arranged on the output path is used to cut off the timing path of the output path.

7. The storage system according to claim 6, wherein: The multiple multiplexers are multiple-stage multiplexers; the multiple D flip-flops are arranged in parallel at the same position between the multiplexers of adjacent stages; or, The multiple D flip-flops are arranged in parallel at different positions in the multiplexer array.

8. The storage system according to claim 7, wherein: The multiple multiplexers are multi-stage multiplexers; The D flip-flop array includes a first part and a second part, wherein: The first part is arranged in parallel at the same position between the multiplexers of adjacent stages; The second parts are arranged in parallel at different positions in the multiplexer array.

9. The storage system according to claim 6, wherein: In each output path from the output end of the SRAM array to the bus, the first timing delay along the output path to the first D flip-flop is less than a predetermined timing delay threshold value, and the difference between the first timing delay and the timing delay threshold value is less than a predetermined difference threshold value.

10. The storage system according to claim 6, wherein: In each output path from the output end of the SRAM array to the bus, the second timing delay between any two closest D flip-flops along the output path is less than a predetermined timing delay threshold value, and the difference between the second timing delay and the timing delay threshold value is less than a predetermined difference threshold value.

11. A system-level chip, comprising the data selection device of the SRAM array according to any one of claims 1 to 5, or the storage system according to any one of claims 6 to 10.

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