Display panel and display device

Abstract

A display panel and a display device. A peripheral region (WA) of the display panel is provided with binding portions (PA). The display panel comprises sub-pixels (P) and data lines (DAL), and each sub-pixel (P) comprising a pixel circuit (PC) and a light-emitting device (LD). Multiple data lines (DAL) are connected to multiple binding portions (PA) by means of multiple fan-out lines (FL) located in the peripheral region (WA). The multiple fan-out lines (FL) are divided into multiple line groups, and different line groups are connected to different binding portions (PA). The distance between two adjacent binding portions (PA) is greater than the distance between two adjacent line groups. One of the line groups connected to two adjacent binding portions (PA) is a first line group (FG1), and the other line group is a second line group (FG2). The first through n-th fan-out lines (FL) belong to the first line group (FG1), and the (n+1)-th fan-out line (FL) belongs to the second line group (FG2). The first through (n-x)-th fan-out lines (FL) in the first line group (FG1) are first-type fan-out lines (F1), and the (n-x+1)-th through n-th fan-out lines (FL) are second-type fan-out lines (F2). The distance (L1) of at least part of a region between the (n-x)-th fan-out line (FL) and the (n-x+1)-th fan-out line (FL) is greater than the minimum distance (L2) between two adjacent fan-out lines (FL) among the first-type fan-out lines (F1).

Description

Display panel and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202311090804.0, filed on August 25, 2023, entitled “Display Panel and Display Device,” and the entire contents of this Chinese patent application are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] Currently, display panels using light-emitting diodes (LEDs) as light-emitting devices are widely used. To control the brightness of the light-emitting devices, data signals are transmitted via data lines. However, existing display panels may exhibit display anomalies such as dark lines. This problem is particularly pronounced on large-scale display panels, such as televisions.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0006] Summary of the Invention

[0007] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a display panel and a display device that can reduce the risk of display anomalies such as dark lines.

[0008] According to one aspect of the present disclosure, there is provided a display panel comprising a display area and a peripheral area outside the display area; the peripheral area comprising a plurality of binding portions spaced apart along a first direction;

[0009] The display panel includes a plurality of sub-pixels and a plurality of data lines, the plurality of sub-pixels are located in the display area, at least one of the plurality of sub-pixels includes a pixel circuit and a light-emitting device, the pixel circuit is configured to drive the light-emitting device to emit light, the plurality of data lines extend along a second direction and are spaced apart along the first direction, and the first direction and the second direction intersect; the plurality of data lines are connected to the plurality of sub-pixels; the plurality of data lines are connected to the plurality of binding portions via a plurality of fan-out lines located in the peripheral area; the plurality of fan-out lines are divided into a plurality of line groups, each of the plurality of line groups is connected to a different binding portion; the spacing between two adjacent binding portions is greater than the spacing between two adjacent line groups;

[0010] One of the line groups connected by two adjacent binding portions is a first line group, and the other is a second line group; counting from the first line group to the second line group in the first direction, the 1st to nth fan-out lines are located in the first line group, and the n+1th fan-out line is located in the second line group; the 1st to nxth fan-out lines in the first line group are first-type fan-out lines, and the n-x+1th to nth fan-out lines are second-type fan-out lines; the distance between at least a portion of the nxth fan-out line and the n-x+1th fan-out line is greater than the minimum distance between two adjacent fan-out lines in the first type of fan-out lines.

[0011] In an exemplary embodiment of the present disclosure, a plurality of the second-type fan-out lines have a bending portion, and the bending portion includes a first bending portion and a second bending portion, and the first bending portion and the second bending portion have different bending directions.

[0012] In an exemplary embodiment of the present disclosure, the resistance of the (n+1)th fan-out line is greater than the resistance of the (n)th fan-out line; at least one of the resistance difference between two adjacent second-type fan-out lines, the resistance difference between the (nx)th and (n-x+1)th fan-out lines, and the resistance difference between the (n)th and (n+1)th fan-out lines is greater than the resistance difference between two adjacent first-type fan-out lines and is less than a resistance threshold, 30Ω≥the resistance threshold>0; 1<x<n.

[0013] In an exemplary embodiment of the present disclosure, the resistance of the fan-out line satisfies the following relationship:

[0014] (|ΔR1|+|ΔR2|) / x=(Rn+1-Rn-x) / x≤y;

[0015] ΔR1 is the resistance difference between the nxth and nth fan-out lines, ΔR2 is the resistance difference between the nth and n+1th fan-out lines; Rn-x is the resistance of the nxth fan-out line, Rn+1 is the resistance of the n+1th fan-out line; y is the resistance threshold.

[0016] In an exemplary embodiment of the present disclosure, the fan-out lines from n-x+1 to n-x+i have the first bending portion bent toward the first type of fan-out line, and the fan-out lines from n-x+j to n have the second bending portion bent toward the second line group; 1<i≤j<x.

[0017] In an exemplary embodiment of the present disclosure, the binding portion connected by the first wire group is a first binding portion, and the binding portion connected by the second wire group is a second binding portion; a straight line located between the first binding portion and the second binding portion and having the same distance from the first binding portion and the second binding portion in the first direction is a midline between the first binding portion and the second binding portion;

[0018] The bending portions of at least a portion of the fan-out lines from the n-x+jth to the nth extend to a side of a midline between the first binding portion and the second binding portion close to the second binding portion.

[0019] In an exemplary embodiment of the present disclosure, the bending portion bends along a folding line trajectory or a curved trajectory.

[0020] In an exemplary embodiment of the present disclosure, the fan-out line includes a lead-out section, a transition section, and a binding section, the lead-out section is connected to the data line, the binding section is connected to the binding portion, and the transition section connects the lead-out section and the binding section; the lead-out section and the binding section both extend along the second direction;

[0021] A transition section of the second type of fan-out line includes at least one bending portion, and the bending portion includes a first connecting section, an intermediate section, and a second connecting section. The first connecting section connects the lead-out section and the intermediate section, and the second connecting section connects the intermediate section and the binding section. The intermediate section extends along the second direction, and the lead-out section connected to it is staggered in the second direction.

[0022] In an exemplary embodiment of the present disclosure, the middle sections of each of the second-type fan-out lines are spaced apart along the first direction, and part of the middle sections are located on a side of a midline between the first binding portion and the second binding portion close to the second binding portion.

[0023] In an exemplary embodiment of the present disclosure, the middle segment of any one of the fan-out lines from n-x+1 to n-x+i is located on the side of the lead-out segment to which it is connected close to the first binding portion; the middle segment of any one of the fan-out lines from n-x+j to n is located on the side of the lead-out segment to which it is connected close to the second binding portion, i≤j<x.

[0024] In an exemplary embodiment of the present disclosure, the lengths of the lead-out segments of the fan-out lines from the n-x+1th to the n-x+ith gradually decrease; the lengths of the first connection segments of the fan-out lines from the n-x+1th to the n-x+ith gradually decrease; and the lengths of the first connection segments of the fan-out lines from the n-x+jth to the nth gradually increase.

[0025] In an exemplary embodiment of the present disclosure, a distance between two adjacent middle segments is greater than a distance between two adjacent lead-out segments.

[0026] In an exemplary embodiment of the present disclosure, a length of the middle segment in the second direction is smaller than a length of the lead-out segment in the second direction.

[0027] In an exemplary embodiment of the present disclosure, 20Ω≥the resistance threshold>0.

[0028] In an exemplary embodiment of the present disclosure, i<j.

[0029] In an exemplary embodiment of the present disclosure, the display panel includes a substrate and a semiconductor layer, a first gate layer, a second gate layer, a first source-drain layer, and a second source-drain layer sequentially distributed in a direction away from the substrate;

[0030] The data line is located in at least one of the first source-drain layer and the second source-drain layer; the fan-out line is located in at least one of the first gate layer, the second gate layer, the first source-drain layer and the second source-drain layer.

[0031] According to one aspect of the present disclosure, there is provided a display device, including:

[0032] The display panel according to any one of the above items;

[0033] a flexible circuit board connected to the binding portion;

[0034] A control circuit board is connected to the flexible circuit board.

[0035] The present invention discloses a driving backplane, a display panel, and a display device. Since the number of binding parts is far less than the number of data lines, multiple fan-out lines are gathered as a line group and connected to one binding part. The number of data lines cannot be evenly divided by each binding part, and since other wiring lines in the peripheral area limit the wiring space, it is difficult to evenly distribute the binding parts, so that the nth and n+1th fan-out lines are connected to different binding parts, and the length difference is large. When the line width and material are consistent, the resistance difference is large, resulting in a large difference in voltage drop when the two transmit signals, resulting in differences in brightness of the light-emitting devices controlled by the corresponding data lines. This difference is reflected on the screen as dark lines and other abnormalities.

[0036] If both the length and resistance of the (n+1)th fan-out line are greater than those of the (n)th fan-out line, x fan-out lines connected to the first binding portion can be selected as second-category fan-out lines, with the remaining fan-out lines remaining as first-category fan-out lines. By increasing the length of the second-category fan-out lines, the spacing between the first-category fan-out lines increases, bringing the second-category fan-out lines closer to the (n+1)th fan-out line. This allows the distance between at least a portion of the (nx)th fan-out line and the (n-x+1)th fan-out line to be greater than the minimum distance between two adjacent fan-out lines of the first-category fan-out line, thereby reducing the resistance difference between the (n)th and (n+1)th fan-out lines. This reduces the voltage drop difference between adjacent fan-out lines, improving or eliminating display anomalies such as dark lines.

[0037] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0039] FIG1 is a schematic diagram of a display area and a peripheral area of ​​a display panel according to an embodiment of the present disclosure.

[0040] FIG2 is a schematic cross-sectional view of an embodiment of a display panel according to the present disclosure.

[0041] FIG3 is a schematic top view of an embodiment of a display panel according to the present disclosure.

[0042] FIG4 is a partial schematic diagram of FIG3 .

[0043] FIG5 is a partial schematic diagram of FIG4 .

[0044] FIG6 is a partial schematic diagram of an embodiment of a display panel disclosed herein.

[0045] FIG. 7 is a partial schematic diagram of an embodiment of a display panel disclosed herein.

[0046] FIG8 is a partial schematic diagram of an embodiment of a display panel disclosed herein.

[0047] FIG9 is a schematic diagram of an embodiment of a display device disclosed herein. DETAILED DESCRIPTION

[0048] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0049] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0050] The first direction X and the second direction Y herein are merely two intersecting directions. For example, they may be perpendicular to each other. In the drawings of this disclosure, the first direction X is the horizontal direction, and the second direction Y is the vertical direction perpendicular to the horizontal direction. However, the first and second directions of this disclosure are not limited to this. Furthermore, those skilled in the art will appreciate that if the display panel is rotated, the actual orientations of the first direction X and the second direction Y may change accordingly, but the intersecting relationship remains unchanged.

[0051] As shown in Figures 1 and 2, an embodiment of the present disclosure provides a display panel, which may include a driving backplane BP and a plurality of light-emitting devices LD. The light-emitting devices LD may be arranged on one side of the driving backplane BP. The driving backplane BP may drive the light-emitting devices LD to emit light to display images.

[0052] The driving backplane BP can be divided into at least a display area AA and a peripheral area WA. The light-emitting device LD can be located in the display area AA. The peripheral area WA can be a continuous or discontinuous annular region surrounding the display area AA. The shape of the peripheral area WA is not particularly limited herein. For example, if the driving backplane BP has a rectangular outline and the boundary of the display area AA is also rectangular, the peripheral area WA can be a rectangular ring. Of course, the driving backplane BP, the display area AA, and the peripheral area WA can also have other shapes.

[0053] It should be noted that the boundary of the display area AA coincides with the inner boundary of the peripheral area WA, and the boundary is a boundary divided according to function, and is not limited to a physical boundary.

[0054] The peripheral area WA has multiple bonding portions PA, for example, two or three, and the bonding portions PA can be spaced apart along the first direction X and arranged along a straight line. For example, if the boundary of the display area AA is rectangular, the bonding portions PA can be spaced apart along a long side of the rectangle. Furthermore, each bonding portion PA can have multiple bonding pads spaced apart along the first direction X.

[0055] The binding portion PA can be connected to the flexible circuit board via a pad, and the flexible circuit board can be connected to the control circuit board. This allows the display panel and the control circuit board to be connected via the flexible circuit board, and the control circuit board controls the driving backplane BP to drive the light-emitting devices LD to display an image. Different binding portions PA can be connected to the control circuit board via the same flexible circuit board, or alternatively, different flexible circuit boards can be used to connect the display panel and the control circuit board.

[0056] As shown in Figure 1, based on the pixel circuit PC and the light-emitting device LD, the display panel may include multiple pixels, each pixel P may include multiple sub-pixels P with different luminous colors, each sub-pixel P may include a pixel circuit PC and a light-emitting device LD connected thereto, and the pixel circuit PC is configured to drive the light-emitting device LD to emit light.

[0057] The following is a detailed description of the structure of the driver backplane BP:

[0058] The driving backplane BP may include a driving circuit for driving each light-emitting device LD to emit light independently. The driving circuit may include a pixel circuit PC and a peripheral circuit, wherein the number of pixel circuits PC is multiple, and at least part of the pixel circuits PC are arranged in the display area AA. Of course, part of the pixel circuit PC may be located in the peripheral area WA as a virtual pixel circuit.

[0059] Each pixel circuit PC may include multiple transistors and storage capacitors. The pixel circuit PC may be a 3T1C, 7T1C, or other pixel circuit. nTmC indicates that a pixel circuit PC includes n transistors (represented by the letter "T") and m capacitors (represented by the letter "C"). The pixel circuits may be arranged in a plurality of rows and columns along a first direction X and a second direction Y, where the first direction X may be defined as a row direction and the second direction Y may be defined as a column direction. A pixel circuit may be connected to one light-emitting device LD. Of course, a pixel circuit PC may also be connected to multiple light-emitting devices LD.

[0060] As shown in Figures 1 and 3, the peripheral circuits of the driver backplane BP may include gate drive circuits, light-emitting control circuits, and other circuits for scanning pixel circuits PC. The gate drive circuits and light-emitting control circuits may be connected to the binding portion PA via drive traces. Simultaneously, the driver backplane BP may also include a plurality of data lines DAL extending along the second direction Y and distributed along the first direction X. A data line DAL may be connected to a column of pixel circuits PC and used to transmit a data signal that can control the brightness of the light-emitting device LD to the pixel circuit PC. Of course, a data line DAL may also be connected to multiple columns of pixel circuits PC, or a data line DAL may be connected to multiple pixel circuits PC that are not in the same column. The distribution of the pixel circuits PC connected to the data line DAL is not particularly limited herein.

[0061] The data lines DAL are located in the display area AA and extend toward the peripheral area WA. They can be connected to the bonding portion PA via fan-out lines FL located in the peripheral area WA. Each data line DAL can be connected to a pad on the bonding portion PA via each fan-out line FL. The fan-out lines FL and the data lines DAL connected thereto can be an integrated structure or independent interconnected structures, as long as they can transmit data signals. Furthermore, the pixel circuits PC are evenly distributed in the first direction X, and the data lines DAL can be evenly spaced, i.e., the spacing between any two adjacent data lines DAL is equal.

[0062] The number of bonding sections PA is far smaller than the number of data lines DAL, allowing multiple fan-out lines FL to be aggregated and connected to a single bonding section PA as a line group. Specifically, the fan-out lines FL can be divided into multiple line groups, with each line group comprising multiple fan-out lines FL. The fan-out lines FL in the same line group are connected to the same bonding section PA. The spacing between two adjacent bonding sections PA is greater than the spacing between two adjacent fan-out lines FL, and greater than the spacing between two adjacent line groups. The spacing between two adjacent bonding sections PA can be defined as the distance between the closest pads in the two bonding sections PA, and the spacing between two adjacent line groups can be defined as the minimum distance between the two closest fan-out lines FL in the two adjacent line groups.

[0063] Different fan-out lines FL connected to the same binding portion PA may have different lengths. Given the same material and line width, fan-out lines FL of different lengths exhibit resistance differences. Furthermore, the number of data lines DAL is not necessarily evenly distributed across the binding portions PA. Different binding portions PA may connect to different numbers of fan-out lines FL and data lines DAL. Furthermore, due to the limited wiring space of other traces and peripheral circuits in the peripheral area WA, it is difficult for the binding portions PA to distribute the fan-out lines uniformly. This results in significant differences in length and, consequently, in resistance, between some fan-out lines FL. Consequently, this leads to significant differences in voltage drop during signal transmission between the two fan-out lines. This results in differences in brightness of the light-emitting devices LD controlled by the corresponding data lines DAL. This difference is reflected in the image as anomalies such as dark lines.

[0064] In some embodiments of the present disclosure, one of the wire groups connected by two adjacent binding portions PA is designated as the first wire group, and the other as the second wire group. Counting from the first wire group to the second wire group in a first direction X, the 1st to nth fan-out wires are located in the first wire group, and the n+1th fan-out wire is located in the second wire group. This allows the nth and n+1th fan-out wires to be connected to different binding portions and have significantly different lengths. When the wire width and material are consistent, the resistance difference can be significant, reaching over 1000Ω, for example, 1483.9Ω. This excessive voltage drop difference can result in anomalies such as dark lines.

[0065] As shown in Figures 3-5, to address the aforementioned issues, the present disclosure proposes dividing the first line group FG1 into a first type of fan-out lines F1 and a second type of fan-out lines F2, with the second type of fan-out lines F2 located between the first type of fan-out lines F1 and the second type of fan-out lines FG2. The first type of fan-out lines F1 includes the 1st to nxth fan-out lines FL, while the second type of fan-out lines F2 has x fan-out lines FL and includes the n-x+1th to n-th fan-out lines FL. The distance between the nxth fan-out line FL in the first type of fan-out lines F1 and the n-x+1th fan-out line FL in the second type of fan-out lines F2 is greater than the minimum distance between two adjacent fan-out lines FL in the first type of fan-out lines F1, thereby extending the length of the fan-out lines FL in the second type of fan-out lines F2. For example, in FIG4 , the distance L1 between the nx-th fan-out line FL and the n-x+1-th fan-out line FL in the second type of fan-out line F2 is greater than the minimum distance L2 between two adjacent fan-out lines FL in the first type of fan-out line F1.

[0066] Furthermore, by bending at least some of the fan-out lines FL in the second type of fan-out lines F2, the resistance is increased by increasing the length, thereby reducing the resistance difference between the fan-out lines FL with a large resistance difference. At the same time, by bending multiple fan-out lines FL, the resistance difference is shared, avoiding the situation where the length difference between the nth and n+1th fan-out lines FL decreases, resulting in a reduced resistance difference, while the length difference between the n-1th and nth fan-out lines FL increases, resulting in an excessively large resistance difference. In other words, while eliminating the dark lines of the sub-pixels connected to the data lines DAL connected to the nth and n+1th fan-out lines FL, dark lines are avoided in the sub-pixels connected to the data lines DAL connected to the nth and n-1th fan-out lines FL. In other words, by sharing the resistance difference through multiple second type fan-out lines F2, it is ensured that the resistance difference between any two adjacent fan-out lines FL is not too large, rather than only ensuring that the resistance difference between the nth and n+1th fan-out lines FL is not too large. The following is a detailed description of this solution:

[0067] The resistance difference can be increased by selecting the x fan-out lines FL closest to the second line group FG2 from the first line group FG1. Specifically, based on the counting method described above, for example, the resistance of the n+1th fan-out line FL is greater than the resistance of the nth fan-out line FL. In the first line group FG1, the 1st to nxth fan-out lines FL can be defined as first-type fan-out lines F1, and the n-x+1th to nth fan-out lines FL can be defined as second-type fan-out lines F2, where n is the number of fan-out lines FL in the first line group FG1, satisfying 1<x<n. The length of the n+1th fan-out line FL is greater than that of the nth fan-out line FL. At the same time, multiple second-type fan-out lines F2 can be provided with a bend WP, ​​that is, at least two second-type fan-out lines F2 can be provided with a bend WP, ​​thereby extending the length of the second-type fan-out line F2, increasing the resistance and making it closer to the length of the (n+1)th fan-out line FL, thereby reducing the resistance difference. By adjusting the length of the bend WP (the length along the extension trajectory of the fan-out line FL), at least one of the resistance difference between two adjacent second-type fan-out lines F2, the resistance difference between the nxth and (n-x+1)th fan-out lines FL, and the resistance difference between the nth and (n+1)th fan-out lines FL can be made greater than the resistance difference between two adjacent first-type fan-out lines F1 and less than the resistance threshold; 1<x<n, for example, the resistance difference between two adjacent second-type fan-out lines F2, the resistance difference between the nxth and (n-x+1)th fan-out lines FL, and the resistance difference between the nth and (n+1)th fan-out lines FL are all greater than the resistance difference between two adjacent first-type fan-out lines F1 and less than the resistance threshold.

[0068] Based on the above solution, when the resistance difference is less than the resistance threshold, by increasing the resistance difference between adjacent fan-out lines FL in the plurality of second-type fan-out lines F2, any two adjacent fan-out lines FL will not have an excessively large resistance difference. This can also be understood as using the small resistance difference of the plurality of second-type fan-out lines F2 to "share" the large resistance difference between the nth and (n+1)th fan-out lines FL. This reduces the voltage drop difference between adjacent fan-out lines FL, improving or eliminating display anomalies such as dark lines.

[0069] The specific value of x depends on the resistance of the fan-out line FL of the different driving backplanes BP. In some embodiments of the present disclosure, the resistance of the fan-out line FL satisfies the following relationship:

[0070] (|ΔR1|+|ΔR2|) / x=(Rn+1-Rn-x) / x≤y;

[0071] ΔR1 is the resistance difference between the nxth and nth fan-out lines FL, ΔR2 is the resistance difference between the nth and n+1th fan-out lines FL; Rn-x is the resistance of the nxth fan-out line FL, Rn+1 is the resistance of the n+1th fan-out line FL; y is the resistance threshold.

[0072] After testing and analysis, it can be concluded that when 30Ω ≥ resistance threshold y > 0, display anomalies such as dark lines can be avoided. Since the lengths of different fan-out lines FL are difficult to be completely equal, y is usually not equal to 0, but this situation is not ruled out. In some embodiments, in order to minimize the dark line phenomenon, the value of y can be less than or equal to 20Ω, so as to reduce the resistance difference while meeting the required fan-out line FL routing length. For example, ΔR1 = 721.7Ω, ΔR2 = 1483.9Ω, and x = 160 can be assumed. In this case, (|ΔR1| + |ΔR2|) / x = 13.8Ω < 20Ω, so x can be 160. Of course, other values ​​can also be taken, but in addition to meeting the above resistance difference requirements, wiring space limitations and the impact of process and cost should also be considered. No special restrictions are made on the specific values ​​here.

[0073] When the width and material of the fan-out line FL are the same, the length and resistance are proportional. Therefore, when calculating x, the length of the fan-out line FL can be directly used for calculation.

[0074] The structure of the bent portion WP of the fan-out line FL is exemplarily described below:

[0075] As shown in Figures 3 to 5, the second type of fan-out line F2 needs to reduce the resistance difference with the n+1th fan-out line FL while avoiding too large a resistance difference with the nxth fan-out line FL, and is limited by the wiring space. For the second type of fan-out line F2 with a bending portion WP, it has a bending portion WP that bends in different directions, a part of which can be bent toward the second line group FG2, and the bending portion WP is the first bending portion WP1, and a part of it can be bent toward the first type of fan-out line F1, and the bending portion WP is the second bending portion WP2, which meets the above requirements.

[0076] For example:

[0077] In some embodiments of the present disclosure, the fan-out lines (n-x+1) through (n-x+i) have first bends WP1 that bend toward the first-type fan-out line F1, and the fan-out lines (n-x+j) through (n) have second bends WP2 that bend toward the second line group FG2. 1<i≤j<x, for example, i=6, j=8, while the fan-out line (n-x+7) may not have a bend WP. Of course, i=j=6, 7, 8, and so on, with no particular limitation imposed herein. Furthermore, i<j can be set, meaning that more fan-out lines FL increase in length by bending toward the second line group FG2 than by bending toward the first-type fan-out line F1. This is primarily because the second-type fan-out lines F2 and the first-type fan-out lines F1, both in the first line group FG1, are closer together, resulting in a smaller space between them, while the space between them and the second line group FG2 is larger.

[0078] As shown in Figures 3-5, in some embodiments of the present disclosure, the binding portion PA connected to the first wire group FG1 is the first binding portion, and the binding portion PA connected to the second wire group FG2 is the second binding portion. A straight line located between the first binding portion and the second binding portion and at the same distance from the first binding portion and the second binding portion in the first direction X is the centerline S of the first and second binding portions. To ensure that the bent portion WP meets the required length and resistance, the bent portion WP of at least a portion of the fan-out lines FL from n-x+j to n can be extended to the side of the centerline S of the first and second binding portions closer to the second binding portion, fully utilizing the space between the first and second binding portions.

[0079] The following is an exemplary description of the trajectory of the fan-out line FL and the bend WP:

[0080] As shown in Figures 4 and 5, for a fan-out line FL having a bending portion WP, it may have one or more bending portions WP, and the specific number depends on the increased length and resistance. As shown in Figure 6, the same fan-out line FL has one bending portion WP, and as shown in Figure 7, the same fan-out line FL may have two bending portions WP.

[0081] The extension path of the bend WP can be a broken line, formed by connecting multiple straight line segments in sequence, with adjacent segments forming angles. Alternatively, as shown in Figure 6, the extension path of the bend WP can be a curved line, such as an arc, parabola, or other curve. Furthermore, the extension path of the bend WP can also be formed by connecting broken lines or curves, as long as the bend WP increases the length and resistance of the fan-out line FL.

[0082] As shown in FIG5 , in some embodiments of the present disclosure, any fan-out line FL may include a lead-out segment FL1 , a transition segment FL2 , and a binding segment FL3 , wherein:

[0083] Both the lead-out section FL1 and the binding section FL3 extend along the second direction Y. The lead-out section FL1 is connected to the data line DAL, or it can be an integral structure with the data line DAL. The binding section FL3 is connected to the pads of the binding portion PA in a one-to-one correspondence. The transition section FL2 can connect the lead-out section FL1 and the binding section FL3. The transition section FL2 of the first type of fan-out line F1 can extend along a straight line, and the extension direction of the transition section FL2 of different fan-out lines FL is different. There can be multiple transition sections FL2 with a certain angle between the first direction X and the second direction Y, and the angle can be different for different transition sections FL2. In addition, there can also be transition sections FL2 extending along the second direction Y. The second type of fan-out line F2 with a bend portion WP does not extend along a straight line.

[0084] Furthermore, the binding segments FL3 of each fan-out line FL can be spaced and evenly spaced along the first direction X. Of course, the spacing of the binding segments FL3 is not specifically limited herein, and the spacing between adjacent binding segments FL3 may not be unique. The lengths of each binding segment FL3 in the second direction Y can be identical. Simultaneously, the lead-out segments FL1 of each fan-out line FL can be spaced and evenly spaced along the first direction X, matching the evenly spaced distribution of the data lines DAL. The lead-out segments FL1 of each first-type fan-out line F1 can have the same length in the second direction Y.

[0085] In some embodiments of the present disclosure, a transition section FL2 of a second-type fan-out line F2 includes at least one bend WP. Taking a bend WP as an example, the bend WP includes a first connecting section FL21, a middle section FL22, and a second connecting section FL23, wherein:

[0086] The first connecting segment FL21 connects the lead segment FL1 and the middle segment FL22, and the second connecting segment FL23 connects the middle segment FL22 and the binding segment FL3. The middle segment FL22, serving as the top of the bent portion WP, can be a line segment extending along the second direction Y. The lead segment FL1 connected to the middle segment FL22 is staggered in the second direction Y. The distance between the middle segment FL22 and the lead segment FL1 connected to the middle segment FL22 in the first direction X is the height of the bent portion WP. Of course, the middle segment FL22 can also be a line segment forming a certain angle with the first direction X and the second direction Y, or a curve.

[0087] As shown in Figure 4, the distance L1 between the second connecting segment FL23 of the nx-th fan-out line FL and the second connecting segment FL23 of the n-x+1-th fan-out line FL is greater than the distance L2 between the transition segments FL2 of two adjacent fan-out lines FL in the first type of fan-out line F1, that is, the minimum distance between two adjacent fan-out lines FL in the first type of fan-out line F1; it should be noted that the minimum distance between two adjacent fan-out lines FL in the first type of fan-out line F1 is not limited to the distance between the transition segments FL2, but can also be the distance between the lead-out segments FL1 and the distance between the binding segments FL3. Of course, the three can also be equal or equal in pairs.

[0088] Furthermore, as shown in FIG5 , the middle segments FL22 of each second-type fan-out line F2 may be spaced apart along the first direction X to form a row of middle segments FL22. To ensure that at least a portion of the bent portion WP of the (n-x+j) to n-th fan-out lines FL extends to the side of the midline between the first and second binding portions close to the second binding portion, a portion of the middle segments FL22, i.e., the middle segments FL22 of the (n-x+j) to n-th fan-out lines FL, may be located on the side of the midline S between the first and second binding portions close to the second binding portion, thereby limiting the range of the bent portion WP.

[0089] Furthermore, the spacing between two adjacent middle segments FL22 is greater than the spacing between two adjacent lead segments FL1. This prevents the tops of the bent portions WP from being too densely packed, preventing short circuits and reducing manufacturing complexity. Furthermore, the length of the middle segment FL22 in the second direction Y can be smaller than that of the lead segment FL1. The length of the middle segment FL22 is also smaller than the lengths of the first connecting segment FL21 and the second connecting segment FL23 of the fan-out line FL in which it resides.

[0090] As shown in FIG5 , in order to achieve that the fan-out lines (n-x+1) through (n-x+i) have a bend portion WP that bends toward the first type of fan-out line F1, and the fan-out lines (n-x+j) through (n) have a bend portion WP that bends toward the second line group FG2, in some embodiments of the present disclosure, the middle segment FL22 of any one of the fan-out lines (n-x+1) through (n-x+i) can be located on the side of the lead-out segment FL1 to which it is connected that is close to the first binding portion, so that the first connecting segment FL21 and the second connecting segment FL23 connected thereto extend toward the first binding portion, thereby bending the bend portion WP toward the first binding portion. Simultaneously, the middle segment FL22 of any one of the fan-out lines (n-x+j) through (n) can be located on the side of the lead-out segment FL1 to which it is connected that is close to the second binding portion, so that the first connecting segment FL21 and the second connecting segment FL23 connected thereto extend toward the second binding portion, thereby bending the bend portion WP toward the second binding portion.

[0091] In some embodiments, the lead segments FL1 of the first-type fan-out lines F1 can have equal lengths in the second direction Y. However, to facilitate connection with the middle segment FL22, the lead segments FL1 of the second-type fan-out lines F2 can extend to different lengths in the second direction Y, such that the lead segments FL1 of the second-type fan-out lines F2 are no less long in the second direction Y than the lead segments FL1 of the first-type fan-out lines F1. Specifically, the lengths of the lead segments FL1 of the (n-x+1)th to (n)th fan-out lines FL can be gradually reduced toward the second line group FG2, such that the length of the lead segment FL1 of the n-th fan-out line FL is less than the length of the lead segment FL1 of the (n-1)th fan-out line FL. Furthermore, the lengths of these lead segments FL1 can be reduced according to an arithmetic progression to avoid significant changes in length difference, thereby ensuring that the resistance difference does not change suddenly but remains substantially consistent.

[0092] As shown in FIG5 , in accordance with the length and arrangement of the above-mentioned middle segment FL22 , the length of the first connection segment FL21 of the n-x+1th to n-x+ith fan-out lines FL may gradually decrease, and the length of the first connection segment FL21 of the n-x+jth to nth fan-out lines FL may gradually increase.

[0093] In some embodiments of the present disclosure, as shown in FIG7 , the bending portion WP of the n-x+jth to nth fan-out lines FL may have multiple bending portions WP. The extension trajectory of the bending portion WP may refer to the extension trajectory above and will not be described in detail here.

[0094] In some embodiments of the present disclosure, as shown in Figure 8, the bending portion WP of the n-x+j to n-th fan-out line FL may also not include the above-mentioned middle segment FL22, but is connected by the first connecting segment FL21 and the second connecting segment FL23 to form two sides of a triangle, that is, the first connecting segment FL21 and the second connecting segment FL23 extend along a broken line trajectory with a certain angle.

[0095] The following is a detailed description of each film layer of the driver backplane BP:

[0096] As shown in FIG2 , the driving backplane BP may include a substrate and a semiconductor layer SE, a first gate layer GA1, a second gate layer GA2, a first source / drain layer SD1, and a second source / drain layer SD2 sequentially distributed in a direction away from the substrate, wherein:

[0097] The active portion of the transistor in the pixel circuit can be located in the semiconductor layer SE, the transistor gate can be located in the first gate layer GA1, and the two plates of the capacitor can be located in the first gate layer GA1 and the second gate layer GA2, respectively. The pattern of the first source and drain layer SD1 can be used to connect at least some of the transistors and capacitors. Furthermore, the data line DAL can be located in at least one of the first source and drain layer SD1 and the second source and drain layer SD2.

[0098] In addition, the driving backplane BP may also include a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer dielectric layer ILD, a first planarizing layer PLN1, and a second planarizing layer PLN2. The first gate insulating layer GI1 may cover the semiconductor layer SE, and the first gate layer GA1 may be disposed on the surface of the first gate insulating layer GI1 away from the substrate SU. The second gate insulating layer GI2 covers the first gate layer GA1, and the second gate layer GA2 is disposed on the surface of the second gate insulating layer GI2 away from the substrate SU. The interlayer dielectric layer ILD covers the second gate layer GA2. The first source and drain layer SD may be disposed on the surface of the interlayer dielectric layer ILD away from the substrate SU, and the first planarizing layer PLN1 covers the first source and drain layer SD1. Alternatively, a passivation layer may cover the first source and drain layer SD1, and the first planarizing layer PLN1 may cover the passivation layer. The second source and drain layer SD2 is disposed on the surface of the first planarizing layer PLN1 away from the substrate SU, and the second planarizing layer PLN2 covers the second source and drain layer SD2. The first electrode ANO of the light-emitting device LD is disposed on the surface of the second planarizing layer PLN2 away from the substrate SU.

[0099] The data line DAL is located on at least one of the first source / drain layer SD1 and the second source / drain layer SD2. For example, the data line DAL is located on the second source / drain layer SD2. Meanwhile, the fan-out line FL may be located on at least one of the first gate layer GA1, the second gate layer GA2, the first source / drain layer SD1, and the second source / drain layer SD2. For example, the fan-out line FL may be located on the second gate layer GA2 and connected to the data line DAL via a via. A pad may be located on the first gate layer GA1 and connected to the fan-out line FL via a via.

[0100] It should be noted that the relative positions of the first and second line groups mentioned above are only exemplary. As shown in Figures 3 to 5, the first line group FG1 can be located on the left side of the second line group FG2; as shown in Figure 4, the second line group FG2 can also be located on the right side of the first line group FG1; for example, for three binding parts PA, the fan-out line FL is divided into three line groups, the middle line group is the second line group FG2, and the line groups on both sides are the first line group FG1. The two first line groups FG1 are divided into first-type fan-out lines F1 and second-type fan-out lines F2, and the two first line groups FG1 can be symmetrically arranged about the second line group FG2.

[0101] Of course, in other embodiments of the present disclosure, for the three wire groups described above, the left wire group can be the first wire group FG1, and the middle wire group can be the second wire group FG2 of the left wire group. Simultaneously, the middle wire group can be the first wire group FG1 of the right wire group, and the right wire group can be the second wire group FG2 of the middle wire group. The specific configuration depends on the resistance relationship of the fan-out lines FL, as long as the resistance and length relationship described above are met.

[0102] The present disclosure further provides a display panel, which may include the driving backplane BP of any of the above embodiments and a plurality of light-emitting devices LD, wherein:

[0103] The structure of the driving backplane BP in any of the above items has been described in the above embodiments and will not be described in detail here.

[0104] As shown in FIG2 , each light-emitting device LD may be disposed on one side of the driving backplane BP and arrayed within the display area AA. For example, the light-emitting device LD may be disposed on a surface of the second planar layer PLN2 away from the substrate SU and connected to the pixel circuit. The light-emitting device LD may be an OLED (organic light-emitting diode), a QLED (quantum dot light-emitting diode), a Micro LED, or a Mini LED, and may include a first electrode ANO, a second electrode CAT, and a light-emitting layer EL located between the second electrode CAT, wherein:

[0105] The first electrode ANO can be provided on the surface of the second planar layer PLN2 away from the substrate SU. The light-emitting layer EL may include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer stacked in a direction away from the driving backplane BP. Each light-emitting device LD may share the second electrode CAT. That is, the second electrode CAT may be a continuous, whole-layer structure, and the second electrode CAT may extend to the peripheral area WA. The first electrodes ANO are distributed in an array to ensure that each light-emitting device LD can emit light independently. In addition, in order to limit the light-emitting range of the light-emitting device LD and prevent crosstalk, a pixel definition layer PDL may be provided on the surface where the first electrode ANO is provided. The pixel definition layer PDL may be provided with an opening that exposes each first electrode ANO. The light-emitting layer EL is stacked with the first electrode ANO within the opening.

[0106] Each light-emitting device LD may share at least a common light-emitting material layer, so that each light-emitting device LD emits the same color. In this case, to achieve color display, a color filter layer may be provided on the side of the light-emitting device LD away from the substrate SU. Color display is achieved through the filter portions of the color filter layer corresponding to each light-emitting device LD. Of course, the light-emitting material layers of each light-emitting device LD may also be independent, so that the light-emitting device LD can directly emit monochromatic light, and different light-emitting devices LD can emit different colors, thereby achieving color display.

[0107] In addition, the display panel of the present disclosure may further include an encapsulation layer TFE covering the light-emitting device LD, and the encapsulation layer TFE may include a first inorganic layer CVD1, an organic layer IJP and a second inorganic layer CVD2, wherein the first inorganic layer CVD1 may cover each light-emitting device LD and extend to the peripheral area WA, and at least expose the binding portion PA, the organic layer IJP is arranged on the surface of the first inorganic layer CVD1 away from the driving backplane BP, and extends to the peripheral area WA, the organic layer IJP is located on the inner side of the boundary of the first inorganic layer CVD1, and the second inorganic layer CVD2 covers the organic layer IJP and the first inorganic layer CVD1 not covered by the organic layer IJP. The specific structure will not be described in detail here.

[0108] The present disclosure further provides a display device, as shown in FIG9 , which may include a display panel 01 according to any of the aforementioned embodiments, a flexible circuit board 02, and a control circuit board 03. The display panel 01 is a display panel according to any of the aforementioned embodiments. Its specific structure and beneficial effects can be found in the embodiments of the display panel and its driving backplane BP described above, and will not be further described here.

[0109] The control circuit board 03 can be connected to the binding part PA through the flexible circuit board 02, thereby controlling the display panel 01 to display an image, wherein the flexible circuit board 02 can be connected to the solder pads of the binding part PA, so that it can be connected to each data line DAL through at least part of the solder pads and the fan-out lines FL connected thereto. At the same time, each flexible circuit board 02 can be bent to the backlight side of the display panel 01, that is, the side of the driving backplane BP away from the light-emitting device LD, and the control circuit board 03 can also be arranged on the side of the driving backplane BP away from the light-emitting device LD.

[0110] There can be multiple flexible circuit boards 02, each connected to a binding portion PA in a one-to-one correspondence. Each flexible circuit board 02 can also be connected to a control circuit board 03. Of course, there can be only one flexible circuit board 02, and it can also be connected to each binding portion PA. The connection method between the flexible circuit boards 02 and the binding portion PA is not specifically limited.

[0111] The display device disclosed herein may be a mobile phone, a tablet computer, a television, or other electronic device with a display function, which will not be listed here one by one.

[0112] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, comprising a display area and a peripheral area outside the display area; the peripheral area having a plurality of binding portions spaced apart along a first direction; The display panel comprises a plurality of sub-pixels and a plurality of data lines, the plurality of sub-pixels are located in the display area, at least one of the plurality of sub-pixels comprises a pixel circuit and a light-emitting device, the pixel circuit is configured to drive the light-emitting device to emit light, the plurality of data lines extend along a second direction, and are spaced apart along the first direction, and the first direction and the second direction intersect; the plurality of data lines are connected to the plurality of sub-pixels; the plurality of data lines are connected to the plurality of binding portions through a plurality of fan-out lines located in the peripheral area; the plurality of fan-out lines are divided into a plurality of line groups, each of the plurality of line groups is connected to a different binding portion; the spacing between two adjacent binding portions is greater than the spacing between two adjacent line groups; One of the line groups connected by two adjacent binding parts is a first line group, and the other is a second line group; counting from the first line group to the second line group in the first direction, the 1st to the nth fan-out lines are located in the first line group, and the n+1th fan-out line is located in the second line group; the 1st to the nxth fan-out lines in the first line group are first-type fan-out lines, and the n-x+1th to the nth fan-out lines are second-type fan-out lines; the distance between the nxth fan-out line and the n-x+1th fan-out line in at least a partial area is greater than the minimum distance between two adjacent fan-out lines in the first type of fan-out lines.

2. The display panel according to claim 1, wherein: A plurality of the second-type fan-out lines have a bending portion, and the bending portion includes a first bending portion and a second bending portion, and the first bending portion and the second bending portion have different bending directions.

3. The display panel according to claim 2, wherein: The resistance of the n+1th fan-out line is greater than the resistance of the nth fan-out line; at least one of the resistance difference between two adjacent second-type fan-out lines, the resistance difference between the nxth and n-x+1th fan-out lines, and the resistance difference between the nth and n+1th fan-out lines is greater than the resistance difference between two adjacent first-type fan-out lines and is less than a resistance threshold, 30Ω≥the resistance threshold>0; 1<x<n.

4. The display panel according to claim 3, wherein: The resistance of the fan-out line satisfies the following relationship: (|ΔR1|+|ΔR2|) / x=(Rn+1-Rn-x) / x≤y; ΔR1 is the resistance difference between the nxth and nth fan-out lines, ΔR2 is the resistance difference between the nth and n+1th fan-out lines. Rn-x is the resistance difference of the nx-th fan-out line, Rn+1 is the resistance of the n+1-th fan-out line; and y is the resistance threshold.

5. The display panel according to claim 3, wherein: The fan-out lines from n-x+1 to n-x+i have the first bending portions bent toward the first type of fan-out lines, and the fan-out lines from n-x+j to n have the second bending portions bent toward the second line group; 1<i≤j<x.

6. The display panel according to claim 5, wherein: The binding part connected by the first wire group is the first binding part, and the binding part connected by the second wire group is the second binding part; a straight line located between the first binding part and the second binding part and having the same distance from the first binding part and the second binding part in the first direction is the midline of the first binding part and the second binding part; The bending portions of at least a portion of the fan-out lines from the n-x+jth to the nth extend to a side of a midline between the first binding portion and the second binding portion close to the second binding portion.

7. The display panel according to claim 6, wherein: The bending portion bends along a fold line track or a curved track.

8. The display panel according to claim 7, wherein: The fan-out line comprises a lead-out section, a transition section and a binding section, the lead-out section is connected to the data line, the binding section is connected to the binding portion, and the transition section connects the lead-out section and the binding section; the lead-out section and the binding section both extend along the second direction; A transition section of the second type of fan-out line includes at least one bending portion, and the bending portion includes a first connecting section, an intermediate section and a second connecting section, the first connecting section connects the lead-out section and the intermediate section, and the second connecting section connects the intermediate section and the binding section; the intermediate section extends along the second direction, and the lead-out section connected to it is staggered in the second direction.

9. The display panel according to claim 8, wherein: The middle sections of the second-type fan-out lines are spaced apart along the first direction, and part of the middle sections are located on a side of a midline between the first binding portion and the second binding portion close to the second binding portion.

10. The display panel according to claim 9, wherein: The middle section of any one of the fan-out lines from n-x+1 to n-x+i is located on the side of the lead-out section connected to it close to the first binding part; the middle section of any one of the fan-out lines from n-x+j to n is located on the side of the lead-out section connected to it close to the second binding part, i≤j<x.

11. The display panel according to claim 10, wherein: The lengths of the lead-out segments from the n-x+1th to the n-th fan-out lines gradually decrease; the lengths of the first connection segments from the n-x+1th to the n-x+ith fan-out lines gradually decrease; and the lengths of the first connection segments from the n-x+jth to the n-th fan-out lines gradually increase.

12. The display panel according to claim 9, wherein: The distance between two adjacent middle sections is greater than the distance between two adjacent lead-out sections.

13. The display panel according to claim 8, wherein: A length of the middle section in the second direction is smaller than a length of the lead-out section in the second direction.

14. The display panel according to claim 3, wherein: 20Ω≥the resistance threshold>0.

15. The display panel according to claim 5, wherein: i<j.

16. The display panel according to claim 3, wherein: The display panel comprises a substrate, and a semiconductor layer, a first gate layer, a second gate layer, a first source-drain layer, and a second source-drain layer sequentially distributed in a direction away from the substrate; The data line is located in at least one of the first source-drain layer and the second source-drain layer; the fan-out line is located in at least one of the first gate layer, the second gate layer, the first source-drain layer and the second source-drain layer.

17. A display device, comprising: The display panel according to any one of claims 1 to 16; A flexible circuit board connected to the binding portion; A control circuit board is connected to the flexible circuit board.

Images