TPM communication method, TPM, single board, and device

Abstract

A TPM communication method, a TPM, a single board, and a device, applied to the technical field of computers. The TPM comprises: a TPM logic module, a receiving buffer, a TPM register, and a processor. The TPM register is a storage space obtained by dividing a memory of the TPM. The method comprises: the TPM logic module receives a TPM register write command sent by a host, and stores the payload of the write command to the receiving buffer, wherein the payload of the TPM register write command is part or all of the content forming TPM command data; when data in the receiving buffer reaches a first data volume threshold, the processor transfers the data in the receiving buffer to the TPM register; and when all the content of the TPM command data has been stored in the TPM register, the processor executes the TPM command data. In this way, the problem in the related art of high TPM hardware costs caused by using a hardware-only solution for TPM communication can be solved.

Description

TPM communication method, TPM, board, and device

[0001] This application claims priority to Chinese patent application number 202311096737.3, filed on August 28, 2023, entitled “TPM communication method, TPM, board and device,” the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of computer technology, and in particular to a TPM communication method, a TPM, a single board, and a device. Background Art

[0003] A Trusted Platform Module (TPM) is an independent security chip that securely stores information used to authenticate devices, such as computers, mobile phones, and communications equipment. This information can include passwords, certificates, encryption keys, and more. As a passive device, the TPM doesn't actively perform operations. The device's central processing unit (CPU) acts as the host to communicate with the TPM, sending TPM command data to the TPM. The TPM then executes the tasks indicated by the TPM command data and returns the task response data to the host.

[0004] Currently, the module used in TPM to communicate with the host is implemented purely by hardware, which increases the overall hardware cost of TPM.

[0005] Summary of the Invention

[0006] This disclosure provides a TPM communication method, TPM, board, and device, which can solve the problem in related technologies where the module used to communicate with the host in the TPM is implemented purely in hardware, resulting in high TPM hardware costs. The technical solution is as follows:

[0007] In a first aspect, a communication method for a TPM is provided. The TPM includes a TPM logic module, a receive buffer, a TPM register, and a processor. The TPM register is a storage space divided in a memory of the TPM. The method includes:

[0008] The TPM logic module receives a TPM register write command sent by the host and stores the payload of the TPM register write command in a receive buffer, where the payload of the TPM register write command is part or all of the contents of the TPM command data. When the data stored in the receive buffer reaches a first data volume threshold, the processor transfers the data stored in the receive buffer to the TPM register. When the TPM register has stored the entire contents of the TPM command data, the processor executes the task indicated by the TPM command data.

[0009] In the technical solution provided by this disclosure, the TPM registers required to store complete TPM command data are simulated in software (i.e., a storage space is allocated in the TPM memory, which is externally visible as the TPM registers). The newly added receive buffer does not need to be able to store complete TPM command data, but only needs to be able to store the payload of a TPM register write command. In actual implementation, the payload of a TPM register write command is only a portion of the TPM command data. Thus, although the receive buffer is implemented in hardware, the required chip area is smaller than that required for hardware-implemented TPM registers in related technologies, effectively saving hardware costs. For example, a TPM register needs to be able to store at least 1 kilobyte of data, while the receive buffer only needs to be able to store 128 bytes of data. In hardware implementation, the hardware cost required to implement the receive buffer is much smaller than that required to implement the TPM register.

[0010] In a possible implementation, the TPM further includes a sending buffer, and the method further includes:

[0011] The processor stores the task response data in the TPM register, then transfers the response data stored in the TPM register to the send buffer. The TPM logic module sends the response data stored in the send buffer to the host.

[0012] In the technical solution provided by this disclosure, a transmit buffer is also introduced into the TPM. The amount of data required to be stored in the transmit buffer is similar to that required to be stored in the receive buffer. For example, both the transmit buffer and the receive buffer can store only 128 bytes of data. This allows the total amount of data that the transmit and receive buffers can store to be much smaller than that required by the TPM registers, resulting in significantly lower hardware costs.

[0013] In one possible implementation, the process of the processor storing the task response data in the TPM register may include:

[0014] The processor reads data that is no larger than the remaining storage space of the sending buffer from the response data stored in the TPM register, and transfers the data to the sending buffer. The TPM logic module receives the TPM register read command sent by the host. The TPM register read command carries information indicating the amount of data to be read. Then, the TPM logic module sends the response data of the amount of data to be read stored in the sending buffer to the host. In addition, the TPM logic module monitors the amount of data stored in the sending buffer, and when the amount of stored data is less than a second data amount threshold, it sends a first interrupt signal to the processor. In response to the first interrupt signal, the processor reads data that is no larger than the remaining storage space of the sending buffer from the response data stored in the TPM register, and transfers the data to the sending buffer.

[0015] In the technical solution provided by this disclosure, the command header of a TPM register read command includes a read data amount field. The value in this field indicates the amount of data to be read, indicating the host's desired read amount. If the send buffer has limited storage space and may not be able to store the complete response data, the processor can transfer the response data to the send buffer in batches.

[0016] In one possible implementation, before the TPM logic module receives the TPM register write command sent by the host, the method further includes:

[0017] The TPM logic module configures the value of the burst count field in the status register to the remaining storage space size of the receive buffer.

[0018] In the solution provided by the present disclosure, the value of the burst count field in the status register can be dynamically adjusted by the TPM logic module. The value of the burst count field is provided to the host. In the scenario where the TPM receives command data, the value of this field is used to indicate how much data the TPM can receive without backpressure on the host. In order to ensure that the data sent by the host can be received by the TPM without backpressure on the host, the TPM logic module can configure the value of this field to the remaining storage space size of the receive buffer in the scenario where the TPM receives command data. In this way, the amount of data of the payload carried in the TPM register write command sent by the host to the TPM can be less than or equal to the remaining storage space size of the receive buffer. Therefore, the TPM logic module can return a high-level signal at the same time as receiving the command header of the TPM register write command (when the command header is received), so that the host can send the payload of the TPM register write command to the TPM without waiting. In this way, the TPM communication method provided by the present disclosure can meet the zero-latency requirements of the TCG PC Client Platform TPM Profile (PTP) specification.

[0019] In one possible implementation, after the processor executes the task indicated by the TPM command data, the method further includes:

[0020] The TPM logic module configures the value of the burst count field in the status register to be the amount of data stored in the send buffer.

[0021] In the solution provided by this disclosure, when the TPM sends data (i.e., when the host reads the response data of a task from the TPM), the value of the burst count field indicates how much data the TPM can send to the host without backpressure. To ensure that the amount of data stored in the send buffer is not less than the amount of data the host wants to read, when the TPM sends data, the TPM logic module configures the value of the burst count field to the amount of data stored in the send buffer. This allows the host to read the response data it wants without waiting.

[0022] In one possible implementation, the processor transfers the data stored in the receive buffer to the TPM register, which may be triggered by the TPM logic module and processed as follows:

[0023] The TPM logic module determines that the data stored in the receive buffer reaches a first data volume threshold and sends a second interrupt message to the processor. In response to the second interrupt message, the processor transfers the data stored in the receive buffer to the TPM register.

[0024] In a second aspect, a TPM is provided, the TPM comprising a TPM logic module, a receive buffer, a TPM register, and a processor, wherein the TPM register is a storage space divided in a memory of the TPM, wherein:

[0025] The TPM logic module is configured to receive a TPM register write command sent by a host and store a payload of the TPM register write command in the receive buffer, wherein the payload of the TPM register write command is part or all of the content constituting the TPM command data;

[0026] When the data stored in the receiving buffer reaches a first data amount threshold, the processor is configured to transfer the data stored in the receiving buffer to the TPM register;

[0027] When all the contents of the TPM command data have been stored in the TPM register, the processor is further configured to execute the task indicated by the TPM command data.

[0028] In one possible implementation, the TPM further includes a sending buffer, and the processor is further configured to store the response data of the task in the TPM register, and transfer the response data stored in the TPM register to the sending buffer;

[0029] The TPM logic module is further configured to send the response data stored in the sending buffer to the host.

[0030] In a possible implementation, the processor is configured to read data no larger than the remaining storage space of the sending buffer from the response data stored in the TPM register, and transfer the data to the sending buffer;

[0031] The TPM logic module is configured to receive a TPM register read command sent by the host, wherein the TPM register read command carries indication information of the amount of data to be read;

[0032] Sending the response data of the amount of data to be read stored in the sending buffer to the host;

[0033] The TPM logic module is further configured to determine that the data stored in the sending buffer is less than a second data amount threshold, and send a first interrupt signal to the processor;

[0034] In response to the first interrupt signal, the processor is further configured to read data no larger than the remaining storage space of the sending buffer from the response data stored in the TPM register, and transfer the data to the sending buffer.

[0035] In a possible implementation, before the TPM logic module receives the TPM register write command sent by the host, the TPM logic module is further configured to configure the value of the burst count field in the status register as the remaining storage space size of the receive buffer.

[0036] In a possible implementation, after the processor executes the task indicated by the TPM command data, the TPM logic module is further configured to configure the value of the burst count field in the status register to the amount of data stored in the send buffer.

[0037] In a possible implementation, the TPM logic module is further configured to determine that the data stored in the receiving buffer reaches a first data amount threshold, and send a second interrupt message to the processor;

[0038] In response to the second interrupt message, the processor is configured to transfer the data stored in the receiving buffer to the TPM register.

[0039] In a third aspect, a single board is provided, comprising a processor and a trusted platform module TPM, wherein the processor is used to send register read and write commands to the TPM, and the TPM is used to execute the TPM communication method as described in the first aspect above.

[0040] In a fourth aspect, a device is provided, comprising a CPU and a TPM, wherein the CPU is configured to send a TPM register write command to the TPM, and the TPM is configured to execute the TPM communication method as described in the first aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] FIG1 is a schematic structural diagram of a single board provided in an embodiment of the present disclosure;

[0042] FIG2 is a schematic diagram of the structure of a TPM provided by an embodiment of the present disclosure;

[0043] FIG3 is a schematic diagram of the structure of a TPM provided by an embodiment of the present disclosure;

[0044] FIG4 is a schematic diagram of the structure of a TPM provided by an embodiment of the present disclosure;

[0045] FIG5 is a flow chart of a TPM communication method provided by an embodiment of the present disclosure;

[0046] FIG6 is a schematic structural diagram of a device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0048] The present disclosure provides a TPM communication method that can be applied to a TPM. A TPM can be a standalone chip deployed in a device, such as a computer, mobile phone, or communication device. FIG1 shows a single board of a device, which has a service CPU and a TPM deployed on it. The service CPU acts as a host and communicates with the TPM via a serial peripheral interface (SPI).

[0049] Communication between the host and the TPM generally involves two steps. One step involves the host sending TPM command data to the TPM via SPI. The TPM then writes the received command data into a TPM register and executes the task indicated by the command data. The other step involves the TPM executing the task indicated by the command data, generating a response data, writing the response data into the TPM register, and returning it to the host via SPI.

[0050] In related technologies, there are generally two solutions for implementing the above communication process:

[0051] Related technologies 1. Pure hardware implementation

[0052] As shown in Figure 2, in a pure hardware implementation, the TPM register and TPM logic module are both hardware modules. The following is a brief description of the TPM communication process in a pure hardware implementation:

[0053] Step 21: The host application (Application, app) calls the Trusted Software Stack (TSS), and calls the TPM driver in the operating system (OS) through the TSS. The TPM driver generates TPM command data in the TSS and sends the TPM command data to the SPI master module (SPI master).

[0054] Step 22: The SPI master carries the TPM command data in at least one TPM register write command according to the size of the TPM command data, and sends the at least one TPM register write command to the SPI slave module (SPI slave) in the TPM in sequence.

[0055] Step 23: The SPI slave receives the TPM register write command and forwards the TPM register write command to the TPM Logic Module.

[0056] Step 24: The TPM Logic Module parses the TPM register write command and writes the payload of the TPM register write command into the TPM register. The TPM register acts as a data buffer (data FIFO) to store TPM command data and task response data.

[0057] Step 25: When the TPM Logic Module determines that all the contents of the TPM command data have been written into the TPM register, it reports an interrupt to the interrupt handle module.

[0058] Step 26: The Interrupt handle module wakes up the TPM task (TASK) module to execute the task indicated by the TPM command data.

[0059] Step 27: After the TPM TASK module completes the task, it writes the task response data into the TPM register and notifies the TPM Logic Module that the task processing is complete.

[0060] Step 28: The host sends a TPM register read command to the TPM to read the task response data. The TPM Logic Module sends the task response data to the host via the SPI slave.

[0061] In this related art, the TPM register is implemented in hardware. Typically, the TPM register needs to be able to store at least 1 kilobyte of data. If the TPM needs to support the asymmetric encryption algorithm (RSA4096), the TPM register needs to be able to store 4 kilobytes of data. This hardware-implemented TPM register occupies a larger area on the chip, resulting in higher hardware costs.

[0062] Related Technology 2: Pure Software Implementation

[0063] Refer to Figure 3. In the pure software implementation solution, the communication library module (Communicate Lib) is a software module, and the TPM register is implemented by software simulation. Communicate Lib replaces the TPM Logic Module in the pure hardware implementation to implement the relevant functions of the TPM Logic Module. The software simulation implements the TPM register by dividing a storage space in the TPM memory as the TPM register. This storage space is the TPM register for the host. The TPM command data sent by the host and the response data of the task will be stored in this storage space. Among them, Random Access Memory can be Random Access Memory (RAM). The following is a brief introduction to the TPM communication process under the pure software implementation solution:

[0064] Step 31: The host app calls the TSS, and calls the TPM driver in the OS through the TSS. The TPM driver generates TPM command data in the TSS and sends the TPM command data to the SPI master.

[0065] Step 32: The SPI master carries the TPM command data in at least one TPM register write command according to the size of the TPM command data, and sends the at least one TPM register write command to the SPI slave in the TPM in sequence.

[0066] Step 33: After receiving the TPM register write command, the SPI slave reports an interrupt to the Interrupt handle module.

[0067] Step 34: The Interrupt handle module notifies Communicate Lib, and Communicate Lib writes the payload of the TPM register write command into the TPM register.

[0068] Step 35: When Communicate Lib determines that all the contents of the TPM command data have been written into the TPM register, it wakes up the TPM TASK module to execute the task indicated by the TPM command data.

[0069] Step 36: After TPM TASK completes the task, it writes the task response data into the TPM register and notifies Communicate Lib that the task processing is complete.

[0070] Step 37: The host sends a TPM register read command to the TPM to read the task's response data. Communicate Lib sends the task's response data to the host via the SPI slave.

[0071] In this related technology 2, the communication between the TPM and the host does not meet the zero-latency requirement of the TCG PC Client Platform TPM Profile (PTP) specification. The PTP specification stipulates that the host needs to be able to read the data returned by the TPM at the same time as it sends the last byte of the command header of the register read / write command to the TPM. However, for related technology 2, the command header needs to be sent from the SPI slave to Communicate Lib first. After Communicate Lib receives the complete command header, it needs to parse it and return the corresponding data to the host after parsing. Therefore, related technology 2 cannot meet the zero-latency requirement specified by PTP.

[0072] The present disclosure provides a communication method for a TPM. Referring to FIG4 , the TPM includes an SPI slave, a TPM Logic Module, a TPM register, a receive buffer (rxFIFO), and a transmit buffer (txFIFO). The TPM Logic Module, the rxFIFO, and the txFIFO are hardware modules, and the TPM register is implemented by software simulation. Furthermore, the TPM may further include software modules: a TPM TASK module, an Interrupt handle module, and a Communicate Lib module. The Interrupt handle module and the Communicate Lib module may be configured in the TPM's OS. These software modules are run by the TPM's processor. Of course, the software modules mentioned here are merely exemplary divisions based on execution functions. These modules may be divided into more or fewer software modules. The specific division of software modules is not limited in the embodiments of the present disclosure.

[0073] The communication method of the TPM provided by the embodiment of the present disclosure is described below in conjunction with the TPM shown in Figure 4. Referring to Figure 5, the communication method provided by the embodiment of the present disclosure may include the following processing flow:

[0074] Step 401: The application program running on the host sends TPM command data to the SPI master.

[0075] In practice, when a host application needs to instruct the TPM to perform a task, it can call the TSS, which in turn calls the TPM driver. The TPM driver then generates corresponding TPM command data in the TSS. The TPM command data is used to instruct the TPM to perform the corresponding task. For example, when the TPM needs to be initialized, the TPM command data generated by the host is initialization command data, which is used to instruct the TPM to perform the initialization task.

[0076] After generating the TPM command data, the TPM driver sends the TPM command data to the SPI master.

[0077] Step 402: The SPI master sends a TPM register write command to the SPI slave module (SPI slave).

[0078] In practice, the host and TPM communicate via SPI. The SPI protocol, which complies with the PTP specification, specifies the maximum payload size for a single transmission. Furthermore, the TPM's status register contains a burst count field. This field indicates how much data the TPM can receive without backpressure from the host when receiving TPM command data, and how much data the TPM can send to the host without backpressure when sending task response data.

[0079] Therefore, the SPI master needs to obtain the value of the burst count field in the Status Register. Then, based on the maximum payload size specified by the SPI for a single transmission and the value of the burst count field, it determines whether the TPM command data needs to be segmented.

[0080] If the amount of TPM command data is greater than the maximum amount of payload for a single transmission specified by SPI, or the amount of TPM command data is greater than the value of the burst count field, data segments are segmented starting from the first byte of the TPM command data, and the SPI command header is encapsulated in the data segments to obtain TPM register write commands. The TPM register write command is used to instruct the TPM to write the payload to the specified register. When segmenting the data segments, the size of the segmented data segments can be MIN (the amount of unsent TPM command data, the maximum amount of payload for a single transmission specified by SPI, and the amount of data indicated by the value of the burst count field), where MIN() represents taking the minimum value of the elements in the brackets. For example, if the amount of unsent TPM command data is 128 bytes, the maximum amount of payload for a single transmission specified by SPI is 64 bytes, and the value of the burst count field is 128, the segmented data segments can be 64 bytes.

[0081] If the amount of TPM command data is less than or equal to the maximum amount of payload data for a single transmission specified by SPI, and the amount of TPM command data is less than or equal to the value of the burst count field, the TPM command data is encapsulated with an SPI command header to obtain a TPM register write command.

[0082] After generating a TPM register write command, the SPI master sends the command to the SPI slave. During the process of sending the TPM register write command to the SPI slave, if the SPI master receives a low-level signal from the TPM after sending the command header, it indicates that the TPM is not ready to receive the TPM register write command, and the SPI master temporarily does not send the payload in the TPM register write command. If the SPI master receives a high-level signal from the TPM, it indicates that the TPM is ready to receive the TPM register write command, and the SPI master continues to send the payload in the TPM register write command.

[0083] In addition, if the payload in the TPM register write command is a data fragment of the TPM command data, after the current TPM register write command is sent, the SPI master continues to split and encapsulate the unsent TPM command data according to the above segmentation rules, generates the corresponding TPM register write command, and sends it to the TPM.

[0084] Step 403: The SPI slave sends a TPM register write command to the TPM Logic Module.

[0085] In implementation, whenever the SPI slave receives data sent by the SPI master, it immediately forwards the received data to the TPM Logic Module.

[0086] Step 404: The TPM Logic Module stores the payload of the TPM register write command into the rxFIFO.

[0087] In implementation, the TPM Logic Module detects whether the remaining storage space in the rxFIFO is sufficient to store the payload in the TPM register write command. If so, the payload in the TPM register write command is stored in the rxFIFO. If the remaining storage space in the rxFIFO is insufficient to store the payload in the TPM register write command, the host is backpressured.

[0088] Specifically, after receiving the command header of a TPM register write command from the SPI slave, the TPM Logic Module parses the command header and determines that the currently received TPM register write command is a TPM register write command based on the read / write identification field in the command header. It also determines the amount of data to be written (i.e., the amount of data in the payload of the TPM register write command) based on the read / write data amount field in the command header. The TPM Logic Module then determines whether the amount of data to be written is less than or equal to the remaining storage space in the rxFIFO.

[0089] If the amount of data to be written is less than or equal to the remaining storage space in the rxFIFO, the SPI slave returns a high signal to the SPI master, instructing the SPI master to send the payload of the TPM register write command. Upon receiving this high signal, the SPI master sends the payload of the TPM register write command to the SPI slave. The SPI slave sends the received payload of the TPM register write command to the TPM Logic Module. The TPM Logic Module stores the payload of the TPM register write command in the rxFIFO.

[0090] If the amount of data to be written is determined to be greater than the remaining storage space in the rxFIFO, the host is back-pressured. Back-pressure on the host can be handled by returning a low-level signal to the SPI master via the SPI slave. Upon receiving this low-level signal, the SPI master temporarily suspends sending the payload of the TPM register write command to the SPI slave. The TPM Logic Module stops back-pressure on the host until it detects that the remaining storage space in the rxFIFO is greater than or equal to the amount of data to be written. It then returns a high-level signal to the SPI master via the SPI slave, instructing the SPI master to send the payload of the TPM register write command. Upon receiving this high-level signal, the SPI master sends the payload of the TPM register write command to the SPI slave. The SPI slave sends the received payload of the TPM register write command to the TPM Logic Module. The TPM Logic Module stores the payload of the TPM register write command in the rxFIFO.

[0091] In one possible implementation, to ensure that the payload of the TPM register write command sent by the host can be stored in the rxFIFO without generating back pressure, in the disclosed embodiment, the TPM Logic Module can also configure the value of the burst count field in the Status Register based on the TPM's current mode (receive data mode or send data mode). The following first describes the value of the burst count field configured by the TPM Logic Module in receive data mode:

[0092] Before sending command data to the TPM, the host first notifies the TPM. Upon receiving the notification, the Communicate Lib configures the TPM Logic Module to receive data mode. The TPM Logic Module then checks the remaining storage space in the rxFIFO and sets the burst count field in the Status Register to a value that indicates the remaining storage space in the rxFIFO. For example, if the remaining storage space in the rxFIFO is 128 bytes, the burst count field can be set to 128.

[0093] Step 405: When the amount of data in the rxFIFO reaches a first data amount threshold, the TPM Logic Module reports a first interrupt signal to the Interrupt handle module.

[0094] In implementation, each time the TPM Logic Module stores the payload of the TPM register write command into the rxFIFO, it detects the amount of data stored in the rxFIFO, and sends a first interrupt signal to the Interrupt handle module if the amount of data stored in the rxFIFO is greater than a first data amount threshold.

[0095] The first data volume threshold may be dynamically configured by Communicate Lib. The configuration of the first data volume threshold is described below:

[0096] Before the host sends command data to the TPM, it will first notify the TPM. Accordingly, after the TPM receives the notification, Communicate Lib can initialize the first data volume threshold to the command header length of the TPM command data, for example, 10 bytes. After receiving the command header of the TPM command data and transferring the command header of the TPM command data to the TPM Register, Communicate Lib uses the command header to determine the total data volume of the TPM command data and calculate the remaining data volume of the TPM command data that the TPM has not yet received. Furthermore, the first data volume threshold is configured as: MIN (remaining data volume of the TPM command data, default threshold). The default threshold can be pre-configured according to the actual storage space of the rxFIFO. Exemplarily, the default threshold can be half of the total storage space of the rxFIFO. For example, when the total storage space of the rxFIFO is 128 bytes, the default threshold can be configured as 64 bytes.

[0097] Step 406: The Interrupt handle module sends a first data transfer notification to Communicate Lib.

[0098] In implementation, after receiving the first interrupt signal, the Interrupt handle module sends a first data transfer notification to Communicate Lib through the interrupt handling function. The first data transfer notification is used to instruct Communicate Lib to transfer the data stored in the rxFIFO to the TPM Register.

[0099] Step 407: Communicate Lib transfers the data in the rxFIFO to the TPM Register.

[0100] In implementation, after receiving the first data transfer notification, Communicate Lib transfers the data stored in the rxFIFO to the TPM Register.

[0101] Step 408: After Communicate Lib determines that the TPM command data has been received, it sends a wake-up message to the TPM TASK module.

[0102] In practice, the TPM command data header includes a data size indication field. Communicate Lib can read the value of this data size indication field and detect whether the amount of TPM command data stored in the TPM Register has reached the amount indicated by this data size indication field. If the amount of TPM command data stored in the TPM Register has reached the amount indicated by this data size indication field, Communicate Lib determines that the TPM command data has been received and sends a wake-up message to the TPM Task module.

[0103] Step 409: The TPM TASK module executes the task indicated by the command data and generates task response data.

[0104] In practice, upon receiving a wake-up message, the TPM TASK module retrieves the TPM command data stored in the TPM register, parses the TPM command data, executes the task indicated by the TPM command data, and generates task response data after the task is completed. For example, if the TPM command data is initialization command data, the TPM TASK module executes the initialization task, and the corresponding task response data is initialization result data.

[0105] Step 410: The TPM TASK module stores the task response data in the TPM register and returns a task completion message to Communicate Lib.

[0106] In practice, after executing the task indicated by the TPM command data, the TPM TASK module generates task response data, stores the task response data in the TPM register, and returns a task completion message to Communicate Lib.

[0107] Step 411: Communicate Lib transfers the response data of the task to the txFIFO.

[0108] In practice, after receiving a task completion message, Communicate Lib transfers the task response data to the txFIFO. Because the amount of response data may exceed the storage space of the txFIFO, Communicate Lib can transfer the response data to the txFIFO in multiple batches.

[0109] If the task response data is transferred only once, after the transfer is completed, the value of the Burst Count field in the status register is set to the amount of data currently stored in the txFIFO, and the value of the available data (dataAvail) field in the Status Register is set to 1. After all task data is read by the host, the dataAvail field in the status register is set to 0. The value of the dataAvail field is used to indicate that the host can read the task response data from the TPM.

[0110] If the response data of the task is transferred multiple times, after the first transfer is completed, the value of the Burst Count field in the status register is set to the amount of data currently stored in the txFIFO, and the available data (dataAvail) field in the status register is set to 1. After all task data is read by the HOST, the value of the dataAvail field in the status register is set to 0.

[0111] Step 412: The SPI master sends a TPM register read command to the SPI slave.

[0112] In implementation, when the host detects that the value of the dataAvail field in the TPM's Status Register is 1, it generates a register read command and sends it to the SPI slave via the SPI master. The amount of data to be read, as indicated by the read data amount field in the command header of the register read command, is the amount indicated by the value of the Burst Count field.

[0113] Step 413: The SPI slave sends a TPM register read command to the TPM Logic Module.

[0114] In implementation, after receiving the TPM register read command, the SPI slave sends the TPM register read command to the TPM Logic Module.

[0115] Step 414: The TPM Logic Module sends the task response data stored in the txFIFO to the SPI slave.

[0116] In practice, in order to ensure that the amount of data that the host wants to read when reading the response data of the task is exactly the amount of data stored in the txFIFO, in the embodiment of the present disclosure, the TPM Logic Module can configure the value of the burst count field in the Status Register. Specifically, after the task is completed, Communicate Lib configures the TPM Logic Module to send data mode, and then the TPM Logic Module detects the amount of data stored in the txFIFO and configures the value of the burst count field in the Status Register to a value indicating the amount of data stored in the txFIFO. For example, if the amount of data stored in the txFIFO is 64 bytes, the value of the burst count field can be set to 64.

[0117] Based on the above configuration, the TPM Logic Module reads the read data amount field in the command header of the TPM register read command and determines that the amount of data to be read is the same as the amount of data stored in the txFIFO. Therefore, there is no need to backpressure the host and the data stored in the txFIFO is directly returned to the SPI slave.

[0118] In addition, each time after completing a read operation on the txFIFO, the TPM Logic Module detects the amount of data stored in the txFIFI, and when it determines that the amount of data stored in the txFIFO is less than the second data amount threshold, it sends a second interrupt signal to the Interrupt handle module. After receiving the second interrupt signal, the Interrupt handle module sends a data supplement notification to Communicate Lib through the interrupt processing function. After receiving the data supplement notification, Communicate Lib reads part or all of the response data of the task stored in the TPM Register that has not yet been transferred and transfers it to the txFIFO. The specific amount of data read and transferred can be MIN (the remaining amount of response data that has not yet been transferred, the remaining storage space size of the txFIFO).

[0119] The second data volume threshold can be dynamically configured by Communicate Lib. The configuration of the second threshold is described below:

[0120] If the response data of the above task only needs to be transferred once, then after the transfer is completed, or while transferring, the second data volume threshold is configured to be less than or equal to the total data volume of the response data. For example, the second data volume threshold can be configured to be 0.

[0121] If the task result data needs to be transferred multiple times, after the first transfer is completed, or at the same time as the first transfer, the second data volume threshold is configured as a default threshold. Exemplarily, the default threshold can be half of the total storage space of the txFIFO. For example, when the total storage space of the txFIFO is 128 bytes, the default threshold can be configured as 64 bytes. After the last transfer is completed, or at the same time as the last transfer, the second data volume threshold is configured to a value less than or equal to the amount of data transferred this time. Exemplarily, the second data volume threshold can be configured as 0.

[0122] Step 415: The SPI slave sends the task response data to the SPI master.

[0123] In the solution provided by the embodiment of the present disclosure, the TPM Register that needs to store the complete TPM command data is implemented by software simulation without the need for additional hardware implementation, and the newly introduced rxFIFO does not need to be able to store the complete TPM command data, but only needs to be able to store the payload of a TPM register write command. In actual implementation, the payload of a TPM register write command is only a part of the TPM command data. In this way, although the rxFIFO is implemented by hardware, the required chip area is smaller than the chip area required by the TPM Register in the related art, which can effectively save hardware costs. In addition, in the solution provided by the embodiment of the present disclosure, the TPM Logic Module is implemented by hardware. Through cooperation with the rxFIFO, it can return data (i.e., a high-level signal in the embodiment) when receiving the command header of the TPM register write command, so that the host can continue to send the payload of the TPM register write command without waiting, meeting the zero-latency requirement of the PTP specification.

[0124] The present disclosure also provides a device 100. As shown in FIG6 , device 100 includes a bus 102, a processor 104, a memory 106, a communication interface 108, and a TPM 110. Processor 104, memory 106, and communication interface 108 communicate with each other via bus 102. Computing device 100 may be a server or a terminal device. It should be understood that the present disclosure does not limit the number of processors and memories in device 100.

[0125] Bus 102 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, among others. Buses may be classified as address buses, data buses, control buses, and the like. For ease of illustration, FIG6 shows only one bus line, but this does not imply a single bus or type of bus. Bus 102 may include a path for transmitting information between various components of device 100 (e.g., memory 106, processor 104, and communication interface 108).

[0126] The processor 104 may include any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP). The processor 104 may serve as the host in the above embodiment.

[0127] The memory 106 may include volatile memory, such as random access memory (RAM). The memory 106 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0128] The memory 106 stores executable codes, and the processor 104 executes the executable codes to implement relevant functions.

[0129] The communication interface 108 uses a transceiver module such as, but not limited to, a network interface card or a transceiver to implement communication between the device 100 and other devices or a communication network.

[0130] TPM 110 may be the TPM mentioned in the above embodiment, and communication between TPM 110 and processor 104 is via SPI.

[0131] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the protection scope of the technical solutions of the embodiments of the present application.

Claims

1. A communication method of a trusted platform module TPM, characterized in that: The TPM includes a TPM logic module, a receiving buffer, a TPM register and a processor, wherein the TPM register is a storage space divided in the memory of the TPM, and the method includes: The TPM logic module receives a TPM register write command sent by a host, and stores a payload of the TPM register write command in the receiving buffer, wherein the payload of the TPM register write command is part or all of the contents constituting the TPM command data; When the data stored in the receiving buffer reaches a first data amount threshold, the processor transfers the data stored in the receiving buffer to the TPM register; When all the contents of the TPM command data have been stored in the TPM register, the processor executes the task indicated by the TPM command data.

2. The method according to claim 1, characterized in that The TPM further includes a sending buffer, and the method further includes: The processor stores the response data of the task in the TPM register; The processor transfers the response data stored in the TPM register to the sending buffer; The TPM logic module sends the response data stored in the sending buffer to the host.

3. The method according to claim 2, characterized in that The processor stores the response data of the task in the TPM register, including: The processor reads data no larger than the remaining storage space of the sending buffer from the response data stored in the TPM register, and transfers the data to the sending buffer; The TPM logic module sends the response data stored in the sending buffer to the host, including: The TPM logic module receives a TPM register read command sent by the host, wherein the TPM register read command carries indication information of the amount of data to be read; The TPM logic module sends the response data of the amount of data to be read stored in the sending buffer to the host; The method further comprises: The TPM logic module determines that the data stored in the sending buffer is less than a second data amount threshold, and sends a first interrupt signal to the processor; In response to the first interrupt signal, the processor reads data no larger than the remaining storage space of the sending buffer from the remaining data of the response data stored in the TPM register, and transfers the data to the sending buffer.

4. The method according to any one of claims 1 to 3, characterized in that Before the TPM logic module receives the TPM register write command sent by the host, the method further includes: The TPM logic module configures the value of the burst count field in the status register as the remaining storage space size of the receiving buffer.

5. The method according to any one of claims 1 to 4, characterized in that After the processor executes the task indicated by the TPM command data, the method further includes: The TPM logic module configures the value of the burst count field in the status register to be the data volume of the data stored in the sending buffer.

6. The method according to any one of claims 1 to 5, characterized in that When the data stored in the receiving buffer reaches a first data amount threshold, the processor transfers the data stored in the receiving buffer to the TPM register, including: The TPM logic module determines that the data stored in the receiving buffer reaches a first data volume threshold, and sends a second interrupt message to the processor; In response to the second interrupt message, the processor transfers the data stored in the receiving buffer to the TPM register.

7. A trusted platform module TPM, characterized in that: The TPM includes a TPM logic module, a receiving buffer, a TPM register and a processor, wherein the TPM register is a storage space divided in the memory of the TPM, wherein: The TPM logic module is used to receive a TPM register write command sent by a host, and store a payload of the TPM register write command in the receiving buffer, wherein the payload of the TPM register write command is part or all of the content constituting the TPM command data; When the data stored in the receiving buffer reaches a first data amount threshold, the processor is used to transfer the data stored in the receiving buffer to the TPM register; When all the contents of the TPM command data have been stored in the TPM register, the processor is further configured to execute the task indicated by the TPM command data.

8. The TPM according to claim 7, characterized in that: The TPM further includes a sending buffer, and the processor is further configured to store the response data of the task in the TPM register, and transfer the response data stored in the TPM register to the sending buffer; The TPM logic module is further configured to send the response data stored in the sending buffer to the host.

9. The TPM according to claim 8, characterized in that: The processor is configured to read data that is no larger than the remaining storage space of the sending buffer from the response data stored in the TPM register, and transfer the data to the sending buffer; The TPM logic module is used for the TPM logic module to receive a TPM register read command sent by the host, wherein the TPM register read command carries indication information of the amount of data to be read; Sending the response data of the amount of data to be read stored in the sending buffer to the host; The TPM logic module is further configured to determine that the data stored in the sending buffer is less than a second data amount threshold, and send a first interrupt signal to the processor; In response to the first interrupt signal, the processor is further configured to read data no larger than the remaining storage space of the sending buffer from the remaining data of the response data stored in the TPM register, and transfer the data to the sending buffer.

10. The TPM according to any one of claims 7 to 9, characterized in that: Before the TPM logic module receives the TPM register write command sent by the host, the TPM logic module is further configured to configure the value of the burst count field in the status register as the remaining storage space size of the receiving buffer.

11. The TPM according to any one of claims 7 to 10, characterized in that: After the processor executes the task indicated by the TPM command data, the TPM logic module is further configured to configure the value of the burst count field in the status register to the data amount of the data stored in the sending buffer.

12. The TPM according to any one of claims 7 to 11, characterized in that: The TPM logic module is further configured to determine that the data stored in the receiving buffer reaches a first data volume threshold, and send a second interrupt message to the processor; In response to the second interrupt message, the processor is configured to transfer the data stored in the receiving buffer to the TPM register.

13. A single board, characterized in that: The single board includes a central processing unit (CPU) and a trusted platform module (TPM), wherein the CPU is used to send a register write command to the TPM, and the TPM is used to execute the trusted platform module (TPM) communication method according to any one of claims 1 to 6.

14. A device, characterized in that The device comprises a central processing unit (CPU) and a trusted platform module (TPM), wherein the CPU is used to send a TPM register write command to the TPM, and the TPM is used to execute the trusted platform module (TPM) communication method according to any one of claims 1 to 6.

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