Manufacturing method for semiconductor structure, and semiconductor structure

Abstract

A manufacturing method for a semiconductor structure, and a semiconductor structure. The manufacturing method for a semiconductor structure comprises: providing a bonding layer (20) on a side of a carrier board (10); providing one or more electrical elements (30) on the side of the bonding layer (20) facing away from the carrier board (10), at least one electrical element (30) comprising a body (302) and a soldering end (301) protruding from the body, the soldering end (301) facing the carrier board (10), and the soldering end (301) at least partially entering the bonding layer (20); forming a plastic encapsulating layer (40) on the bonding layer (20), the plastic encapsulating layer (40) at least encapsulating side surfaces of the electrical element (30); removing the carrier board (10) and the bonding layer (20), such that the part of the soldering end (301) entering the bonding layer (20) is exposed; and forming a redistribution layer (82) on the side of the electrical element (30) provided with the soldering end (301), the redistribution layer (82) being electrically connected to the soldering end (301).

Description

Semiconductor structure manufacturing method and semiconductor structure CROSS-REFERENCE TO RELATED APPLICATIONS

[0000] This application claims the priority of the Chinese patent application filed with the China Patent Office on August 29, 2023, with application number 202311102294.4 and invention name “Manufacturing method of semiconductor structure and semiconductor structure”, all contents of which are incorporated by reference in this application. Technical Field The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art In common semiconductor packaging processes, such as system-level packaging processes, electrical components such as chips and passive devices can be arranged horizontally at intervals. When the solder ends of the electrical components are protruding, the semiconductor packaging process may include the following processes: first, a rewiring layer is prepared on a silicon substrate; then, the electrical components are mounted on the rewiring layer, with the solder ends of the electrical components facing the rewiring layer; then, the solder ends of the electrical components are connected to the rewiring layer; then, a plastic layer is formed to encapsulate the rewiring layer and the electrical components; and finally, a grinding process is used to remove the silicon substrate. In the above-mentioned semiconductor packaging technology, the silicon substrate is consumed and cannot be reused, resulting in a high cost of the semiconductor packaging process. Summary of the invention Embodiments of the present application provide a method for manufacturing a semiconductor structure and a semiconductor structure. The first aspect of the embodiment of the present application provides a method for manufacturing a semiconductor structure. The manufacturing method includes: providing an adhesive layer on one side of a carrier; placing one or more electrical components on the side of the adhesive layer away from the carrier, at least one of the electrical components includes a body and a soldering end protruding from the body, the soldering end faces the carrier and at least part of the soldering end enters the adhesive layer; forming a plastic encapsulation layer on the adhesive layer, the plastic encapsulation layer at least encapsulating the side of the electrical component; removing the carrier and the adhesive layer, exposing the part of the soldering end entering the adhesive layer; forming a rewiring layer on the side of the electrical component where the soldering end is provided, the rewiring layer being electrically connected to the soldering end. In one embodiment, a ratio of the thickness of the bonding layer to the thickness of the portion of the welding end entering the bonding layer is greater than or equal to 2. In one embodiment, the method further comprises: forming a conductive structure on the surface exposed by the welding terminal, wherein the orthographic projection of the conductive structure on the plane where the surface of the plastic sealing layer away from the welding terminal is located covers the orthographic projection of the portion of the welding terminal exposed by the plastic sealing layer on the plane, and the material of the conductive structure is different from the material of the welding terminal; The redistribution layer is at least partially located on a side of the conductive structure away from the electrical component and is electrically connected to the conductive structure. In one embodiment, the method further includes: setting flux on the surface exposed by the welding end; forming the conductive structure on the surface of the portion of the plastic sealing layer exposed by the welding end, including: setting a conductive film on the side of the electrical component where the flux is provided, the conductive film covering the flux; welding the conductive film and the welding end together; and graphing the conductive film to obtain the conductive structure. In one embodiment, the conductive structures correspond to the soldering terminals one by one, and an orthographic projection area of ​​the conductive structures on the plane is larger than an orthographic projection area of ​​a corresponding portion of the soldering terminal exposed from the plastic encapsulation layer on the plane. In one embodiment, before welding the conductive film and the welding end together, the method for manufacturing the semiconductor structure further comprises: using a vacuum adsorption method to make the conductive film adhere to the soldering flux on the surface of the welding end. In one embodiment, the thickness of the conductive film is in the range of 10 μm to 35 μm. In one embodiment, the material of the conductive structure is the same as that of the redistribution layer. In one embodiment, the one or more electrical components include a first chip, the first chip includes a first pad, the first pad faces the adhesive layer; a protective structure is formed on the surface of the first pad, and the material of the protective structure is a conductive material; wherein, in the semiconductor structure, the first pad faces the adhesive layer, and the redistribution layer is electrically connected to the conductive material. In one embodiment, the one or more electrical components include a second chip, the second chip including a second pad; an insulating layer covering the second pad; and an opening formed on the insulating layer to expose the second pad; wherein, in the semiconductor structure, the redistribution layer is electrically connected to the second pad through the opening. In one embodiment, the one or more electrical components include at least one of a chip, an inductor, a resistor and a capacitor. A second aspect of an embodiment of the present application provides a semiconductor structure, which includes: one or more electrical components, at least one of which includes a body and a welding end protruding from the body; a plastic encapsulation layer, at least encapsulating the side of the electrical component; at least one conductive structure, corresponding one to the welding end, the conductive structure covers the surface of the corresponding welding end exposed from the plastic encapsulation layer and is welded to the welding end, and the material of the conductive structure is different from that of the welding end; a rewiring layer, located on the side of the conductive structure away from the electrical component, and electrically connected to the conductive structure. In one embodiment, the one or more electrical components include a first chip, the first chip includes a first pad, an insulating material layer located on one side of the first pad, and a protective structure in an opening of the insulating material layer, the material of the protective structure is a conductive material; the rewiring layer is electrically connected to the conductive material. In one embodiment, the one or more electrical components include a second chip, the second chip includes a second welding pad, an insulating material layer located on one side of the second welding pad, and an insulating layer, wherein the insulating layer covers the insulating material layer and fills the opening in the insulating material layer; and the redistribution layer is electrically connected to the second welding pad. In one embodiment, the semiconductor structure also includes a first insulating film layer covering the conductive structure, the first insulating film layer includes a plurality of first through holes, each of the first through holes includes a conductive portion, and the redistribution layer includes a plurality of trace structures, each of the trace structures is electrically connected to the conductive portion in the corresponding first through hole. In one embodiment, the semiconductor structure also includes a second insulating film layer covering the rewiring layer, the second insulating film layer includes a plurality of second through holes, each of the second through holes exposing a portion of the surface of a trace structure; and a conductive ball on the surface of each trace structure facing away from the plastic encapsulation layer is partially located in the second through hole of the second insulating film layer. The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application. FIG. 2 is a partial cross-sectional view of a first intermediate structure provided by an exemplary embodiment of the present application. FIG. 3 is a partial cross-sectional view of a second intermediate structure provided by an exemplary embodiment of the present application. FIG. 4 is a partial cross-sectional view of a third intermediate structure provided by an exemplary embodiment of the present application. FIG. 5 is a partial cross-sectional view of a fourth intermediate structure provided by an exemplary embodiment of the present application. FIG. 6 is a partial cross-sectional view of a fifth intermediate structure provided by an exemplary embodiment of the present application. FIG. 7 is a flow chart of forming a conductive structure on a surface exposed by a soldering terminal according to an exemplary embodiment of the present application. FIG. 8 is a partial cross-sectional view of a sixth intermediate structure provided by an exemplary embodiment of the present application. FIG. 9 is a partial cross-sectional view of a seventh intermediate structure provided by an exemplary embodiment of the present application. FIG. 10 is a partial cross-sectional view of welding a conductive film and a welding terminal provided by an exemplary embodiment of the present application. FIG. 11 is a partial cross-sectional view of an eighth intermediate structure provided by an exemplary embodiment of the present application. FIG. 12 is a partial cross-sectional view of a ninth intermediate structure provided by an exemplary embodiment of the present application. FIG. 13 is a partial cross-sectional view of a tenth intermediate structure provided by an exemplary embodiment of the present application. FIG. 14 is a partial cross-sectional view of an eleventh intermediate structure provided by an exemplary embodiment of the present application. FIG. 15 is a partial cross-sectional view of a twelfth intermediate structure provided by an exemplary embodiment of the present application. FIG. 16 is a partial cross-sectional view of a thirteenth intermediate structure provided by an exemplary embodiment of the present application. FIG. 17 is a partial cross-sectional view of a fourteenth intermediate structure provided by an exemplary embodiment of the present application. FIG. 18 is a cross-sectional view of a semiconductor structure provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims. The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items. It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining". Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The embodiment of the present application provides a method for manufacturing a semiconductor structure. Referring to FIG1 , the method for manufacturing a semiconductor structure includes the following steps 110 to 150 . In step 110, an adhesive layer is provided on one side of the carrier. In step 120, an electrical component is placed on the side of the adhesive layer facing away from the carrier. The number is one or more, and at least one of the electrical components includes a body and a welding end protruding from the body, the welding end faces the carrier and at least partially enters the bonding layer. In step 130, a plastic encapsulation layer is formed on the adhesive layer, and the plastic encapsulation layer at least encapsulates the side surface of the electrical component. In step 140 , the carrier board and the bonding layer are removed, and the portion of the soldering end that enters the bonding layer is exposed. In step 150, a rewiring layer is formed on a side of the electrical component where the soldering terminal is provided, and the rewiring layer is electrically connected to the soldering terminal. In the manufacturing method of the semiconductor structure provided by the embodiment of the present application, since at least one electrical component includes a body and a soldering end protruding from the body, after the electrical component is placed on the side of the adhesive layer away from the carrier, the soldering end protruding from the body at least partially enters the adhesive layer, and the adhesive layer can make the electrical component adhere to the carrier, and after the plastic sealing layer is formed, the part of the soldering end entering the adhesive layer will not be encapsulated by the plastic sealing layer, so after the adhesive layer and the carrier are removed, the part of the soldering end entering the adhesive layer is exposed, so that the wiring layer can contact the soldering end to realize the electrical connection between the two. In the embodiment of the present application, the carrier can be recycled after being removed, which helps to reduce the manufacturing cost of the semiconductor structure. The following is a detailed introduction to each step of the method for manufacturing a semiconductor structure provided in an embodiment of the present application. In step 110, an adhesive layer is provided on one side of the carrier. In one embodiment, the shape of the carrier plate can be circular, rectangular or other shapes. The material of the carrier plate can be, for example, stainless steel, polymer, etc., so that the carrier plate is not easily deformed. In one embodiment, the adhesive layer may be made of an easily peelable material so that the carrier can be peeled off later. For example, the adhesive layer may be made of a thermally releasable material that can lose its stickiness by heating. The adhesive layer has stickiness on both the side facing the carrier and the side facing away from the carrier. In step 120, an electrical component is placed on a side of the adhesive layer facing away from the carrier. The number of the electrical components is one or more, and at least one of the electrical components includes a body and a welding end protruding from the body, the welding end faces the carrier and at least partially enters the adhesive layer. Through step 120, a first intermediate structure as shown in FIG2 can be obtained. As shown in FIG2, a plurality of electrical components 30 can be provided on the side of the bonding layer 20 facing away from the carrier 10, and at least one of the plurality of electrical components 30 includes a body 302 and a welding end 301 protruding from the body 302, and at least a portion of the welding end 301 enters the bonding layer 20. The thickness of the portion of the welding end 301 entering the bonding layer 20 is less than the thickness of the bonding layer 20, so that the welding end 301 does not contact the carrier 10, and deformation of the welding end 301 caused by contact with the carrier 10 can be avoided. In one embodiment, the electrical component 30 includes at least one of a chip and a passive device, and the passive device includes at least one of an inductor, a resistor and a capacitor. In the embodiment shown in FIG2 , the electrical component 30 includes a first chip 33, a second chip 34, a third chip 31 and three passive devices (also referred to as passive components) 32. The third chip 31 and the three passive devices 32 are all provided with a soldering end 301 protruding from the body. In one embodiment, as shown in FIG. 2 , the third chip 31 is provided with a pad 311, an insulating material layer 312 and a conductive ball 313 located on one side of the pad 311. The insulating material layer 312 is provided with an opening for exposing the pad 311. The conductive ball 313 is located in the opening and is electrically connected to the pad 311 to lead out the pad 311. The end of the conductive ball 313 protruding from the insulating material layer 312 is the soldering end 301. The soldering end 301 of the third chip 31 partially enters the bonding layer 20. The passive component 32 includes a body 321 and electrodes 322 located on both sides of the body 321. The end of the electrode 322 facing the carrier 10 protrudes from the body 321. The end of the electrode 322 facing the carrier 10 and protruding from the body 321 is the soldering end 301. The soldering end 301 of the passive component 32 can fully enter the bonding layer 20. In one embodiment, the ratio of the thickness of the adhesive layer 20 to the thickness of the portion of the welding end 301 entering the adhesive layer 20 is greater than or equal to 2. This arrangement can ensure that the welding end 301 is better covered by the adhesive layer 20 after entering the adhesive layer 20, thereby preventing the welding end 301 from being covered by the subsequently formed plastic sealing layer; at the same time, it can also effectively prevent the welding end 301 from being deformed due to the contact between the welding end 301 and the carrier 10. In one embodiment, as shown in FIG. 2 , the first chip 34 is provided with a first pad 344, and after the step of placing the electrical component on the side of the adhesive layer away from the carrier, the first pad 344 faces the adhesive layer 20. The first chip 34 also includes an insulating material layer 341 located on one side of the first pad 344, and the insulating material layer 341 is provided with an opening 342 exposing the first pad 344. Before the step of placing the electrical component on the side of the adhesive layer away from the carrier, the method for manufacturing the semiconductor structure further includes: forming a protective structure 343 on the surface of the first pad 344, and the material of the protective structure 343 is a conductive material. The protective structure 343 is formed in the opening 342 of the insulating material layer 341, and the protective structure 343 can protect the first pad 344, and the first pad 344 can be led out through the protective structure 343. In one embodiment, as shown in FIG. 2 , the second chip 33 is provided with a second pad 334 and an insulating material layer 331 located on one side of the second pad 334, and the insulating material layer 331 is provided with an opening 336 exposing the second pad 334. Before placing the electrical component on the side of the adhesive layer away from the carrier, the method for manufacturing the semiconductor structure further includes: forming an insulating layer covering the second pad on the second chip. As shown in FIG. 2 , the insulating layer 333 covers the insulating material layer 331 and fills the opening 336 opened in the insulating material layer 331. The insulating layer 333 can protect the second pad 334. In one embodiment, the material of the welding end may be solder, such as tin, so that the welding end is easy to be welded with other structures. In step 130, a plastic encapsulation layer is formed on the adhesive layer, and the plastic encapsulation layer at least encapsulates the side surface of the electrical component. Step 130 can obtain the second intermediate structure shown in FIG3 . As shown in FIG2 , the plastic layer 40 encapsulates the side surfaces of each electrical component 30 and the surface facing away from the carrier 20 , and the portion of each soldering end 301 entering the adhesive layer 10 does not contact the plastic layer 40 . In one embodiment, before forming the plastic encapsulation layer 40, some pre-treatment steps, such as chemical cleaning, plasma cleaning, etc., can be performed to remove impurities on the surface of the electrical component 30 and the bonding layer 20, so that the plastic encapsulation layer 40 and the electrical component 30 and the bonding layer 20 can be more closely connected without delamination or cracking. In one embodiment, the material of the plastic encapsulation layer 40 may be a polymer resin, a resin composite material, a polymer composite material, etc. For example, the plastic encapsulation layer 40 may be a resin with a filler, wherein the filler may be an inorganic particle. The plastic encapsulation layer 40 may be formed by injection molding, compression molding, or transfer molding. In step 140 , the carrier board and the bonding layer are removed, and the portion of the soldering end that enters the bonding layer is exposed. The third intermediate structure shown in Fig. 4 can be obtained through step 140. As shown in Fig. 4, the portion of the welding end 301 entering the bonding layer 20 is exposed after the bonding layer 20 is removed. In one embodiment, when the adhesive layer 20 is a thermally separable material that can lose its viscosity by heating, the adhesive layer 20 and the carrier 10 can be removed by heating the second intermediate structure. In step 150, a rewiring layer is formed on a side of the electrical component where the soldering terminal is provided, and the rewiring layer is electrically connected to the soldering terminal. In one embodiment, before the step 150 of forming a rewiring layer on the side of the electrical component provided with a solder terminal, the method for preparing the semiconductor structure further includes: forming a conductive structure on the surface exposed by the solder terminal, the orthographic projection of the conductive structure on the plane where the surface of the plastic layer away from the solder terminal is located covers the orthographic projection of the solder terminal on the plane, and the material of the conductive structure is different from the material of the solder terminal. The orthographic projection of the conductive structure on the plane where the surface of the plastic layer away from the solder terminal is located covers the orthographic projection of the part of the solder terminal exposed from the plastic layer on the plane, which means that the orthographic projection of the conductive structure on the plane coincides with the orthographic projection of the part of the solder terminal exposed from the plastic layer on the plane, or the orthographic projection area of ​​the conductive structure on the plane is larger than the orthographic projection area of ​​the part of the solder terminal exposed from the plastic layer on the plane. When the material of the soldering terminal 301 is solder, it is difficult to directly form a rewiring layer on the soldering terminal 301 and the process is difficult to implement. By first forming a conductive structure with a material different from that of the soldering terminal on the surface of the soldering terminal, the subsequent formation of the rewiring layer is facilitated. In one embodiment, before forming the conductive structure on the surface exposed by the soldering end, the method for manufacturing the semiconductor structure further includes: mounting the third intermediate structure shown in FIG. 4 on a substrate, with the soldering end facing away from the substrate. Through this step, the fourth intermediate structure shown in FIG5 can be obtained. As shown in FIG5, the surface of the plastic encapsulation layer 40 away from the welding end 301 is attached to the substrate 52 through the adhesive material layer 51. The adhesive material layer 51 can be made of an easy-to-peel material so that the substrate can be peeled off later. For example, the adhesive material layer 51 can be made of a thermal separation material that can lose its viscosity by heating. The substrate 52 can support the third intermediate structure to facilitate the subsequent steps. In one embodiment, before the step of forming a conductive structure on the surface exposed by the soldering end, the method for manufacturing the semiconductor structure further comprises: disposing a soldering flux on the surface exposed by the soldering end. Through this step, a fifth intermediate structure as shown in FIG6 can be obtained. As shown in FIG6, the exposed surface of each welding end 301 is provided with soldering flux 61. The soldering flux 61 can completely cover the exposed surface of each welding end 301. The soldering flux can facilitate soldering the conductive film and the welding end in the subsequent steps. In some embodiments, soldering flux may be disposed on the exposed surface of the soldering terminal by screen printing. In one embodiment, as shown in FIG. 7 , the step of forming a conductive structure on the surface exposed by the soldering end may include the following steps 160 to 180 . In step 160, a conductive film is disposed on a side of the electrical component facing away from the body, and the conductive film covers the soldering flux. Through this step, the sixth intermediate structure shown in Figure 8 can be obtained. As shown in Figure 8, the conductive film 62 can cover the surface of the soldering flux 61 away from the substrate 52. Since the surface of the fifth intermediate structure facing the conductive film is uneven, there are gaps between the conductive film 62 and some areas of the surface of the fifth intermediate structure facing the conductive film 62. In step 170, the conductive film and the welding terminal are welded together. In one embodiment, before welding the conductive film and the welding end together, the method for manufacturing the semiconductor structure further comprises: using a vacuum adsorption method to make the conductive film adhere to the soldering flux on the surface of the welding end. Through this step, the seventh intermediate structure shown in FIG9 can be obtained. As shown in FIG9, each part of the conductive film 62 is in contact with the surface of the fifth intermediate structure facing the conductive film, and the conductive film 62 is in contact with the soldering flux 61 disposed on the exposed surface of the welding end 301. Such a configuration helps to achieve a better welding effect between the conductive film 62 and the welding end 301. In one embodiment, the thickness of the conductive film 62 is in the range of 10 μm to 35 μm. This configuration can prevent the conductive film 62 from being too thick, making it difficult for the conductive film 61 to deform and the exposed surface of the soldering end 301 to be aligned with the conductive film 62. The soldering flux 61 placed thereon has a poor bonding effect, thereby affecting the welding effect between the soldering end 301 and the conductive film 61, and can also prevent the conductive film 62 from being too thin and being prone to cracking. In some embodiments, the thickness of the conductive film 62 can be 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, etc. In one embodiment, the conductive film 62 may be made of copper, which can reduce the resistance of the conductive film 62 and have less impact on the performance of the semiconductor structure. In one embodiment, the step of welding the conductive film and the welding end together may include the following process: as shown in FIG10 , a pressure plate is arranged on the surface of the conductive film 61 away from the plastic sealing layer 40, and the pressure plate is heated to weld the conductive film 62 and the welding end 301. The high temperature and high pressure conditions can make the welding effect of the conductive film 62 and the welding end 301 better. After removing the pressure plate, an eighth intermediate structure as shown in FIG. 11 can be obtained. In step 180, the conductive film is patterned to obtain the conductive structure. In one embodiment, the step 180 of patterning the conductive film to obtain the conductive structure may include the following process: First, a photoresist layer is disposed on the surface of the conductive film facing away from the plastic sealing layer. Through this step, a ninth intermediate structure as shown in FIG12 can be obtained. As shown in FIG12 , the photoresist layer 64 covers the conductive film 62 . Subsequently, the photoresist layer is exposed and developed to obtain a plurality of photoresist structures. This step can obtain the tenth intermediate structure shown in FIG13 . As shown in FIG13 , each photoresist structure 641 is opposite to a soldering end 301 , and the orthographic projection of the photoresist structure 641 on the carrier 20 covers the orthographic projection of the corresponding soldering end 301 on the carrier 20 . Then, the conductive film is patterned using the photoresist layer as a shield to obtain a conductive structure. Through this step, the eleventh intermediate structure shown in FIG14 can be obtained. As shown in FIG14, the area of ​​the conductive film not covered by the photoresist structure 641 is etched away, and the area of ​​the conductive film covered by the photoresist structure 641 is retained, which is the conductive structure 621. The conductive structures 621 correspond to the welding terminals 301 one by one, and the orthographic projection of each conductive structure 621 on the plane where the surface of the plastic encapsulation layer 40 away from the welding terminal 301 is located covers the orthographic projection of the corresponding welding terminal 301 exposed from the plastic encapsulation layer 40 on the plane. Subsequently, the photoresist layer is removed. Through this step, the twelfth intermediate structure shown in FIG. 15 can be obtained. In one embodiment, a chemical reagent may be used to react with the photoresist layer to remove the photoresist layer. In the process of removing the photoresist layer, the protective structure 343 may prevent the chemical reagent from corroding the first pad 344 of the first chip 34, and the insulating layer 333 may prevent the chemical reagent from corroding the second pad 334 of the second chip 34. The material of the protective structure 343 may be nickel-gold or nickel-palladium-gold, so that the property of the protective structure 343 is relatively stable, and the protective effect on the first pad 344 of the first chip 34 is better. In one embodiment, the area of ​​the orthographic projection of the conductive structure 621 on the plane is larger than the area of ​​the orthographic projection of the corresponding portion of the soldering terminal 301 exposed from the plastic encapsulation layer 40 on the plane. In this way, the edge of the conductive structure 621 exceeds the portion of the corresponding soldering terminal 301 exposed from the plastic encapsulation layer 40, and the chemical reagent used can be better prevented from corroding the soldering terminal 301 during the process of removing the photoresist layer. In one embodiment, before step 150 of forming a rewiring layer on the side of the electrical component where the solder end is provided, and after forming a conductive structure on the surface where the solder end is exposed, the method for manufacturing the semiconductor structure may further include the following steps: forming a first insulating film layer covering the conductive structure, and forming a plurality of through holes on the first insulating film layer. In one embodiment, before the step 150 of forming a rewiring layer on the side of the electrical component where the solder terminal is provided, the method for manufacturing the semiconductor structure further includes: forming an opening on the insulating layer to expose the second solder pad. Through this step, a thirteenth intermediate structure as shown in FIG16 can be obtained. As shown in FIG16, the first insulating film layer 70 is provided with a plurality of through holes 71, each conductive structure 621 is partially exposed by a through hole 71, each protective structure 343 is partially exposed by a through hole 71, and each opening 335 of the insulating layer 333 is connected to a through hole 71. In one embodiment, the through hole 71 of the first insulating film layer 70 and the opening 335 of the insulating layer 333 may be formed simultaneously. In one embodiment, after the step 150 of forming a rewiring layer on the side of the electrical component where the soldering terminal is provided, a fourteenth intermediate structure as shown in FIG17 can be obtained. As shown in FIG17, the rewiring layer 82 is partially located on the side of the conductive structure 621 away from the plastic encapsulation layer 40, and is electrically connected to the conductive structure 621. The rewiring layer 82 includes a plurality of trace structures 821, each of which is electrically connected to the conductive portion 81 in the through hole 71, so that the soldering terminal 301 is electrically connected to the trace structure 821 through the conductive portion 81, the first soldering pad 344 is electrically connected to the trace structure 821 through the protective structure 343 and the conductive portion 81 in turn, and the second soldering pad 334 is electrically connected to the trace structure 821 through the conductive portion 81. In one embodiment, the conductive portion 81 and the redistribution layer 82 can be formed simultaneously in the same process step, which helps to simplify the manufacturing process of the semiconductor structure. In one embodiment, the material of the conductive structure 621 is the same as that of the rewiring layer 82 , which helps to improve the bonding force between the conductive structure 621 and the rewiring layer 82 , thereby improving the electrical connection effect between the rewiring layer 82 and the conductive structure 621 . In one embodiment, after the step 150 of forming a rewiring layer on the side of the electrical component where the solder terminal is provided, The method for manufacturing the semiconductor structure may further include the following process: First, a second insulating film layer covering the rewiring layer is formed, and through holes are opened on the second insulating film layer, each of which exposes a partial surface of the trace structure. Subsequently, a plurality of conductive balls are formed, each conductive ball is partially located in a through hole of the second insulating film layer and is electrically connected to the trace structure. After the above steps, the method for manufacturing the semiconductor structure further comprises: removing the substrate and cutting the obtained structure to obtain a plurality of semiconductor structures. The semiconductor structure can be as shown in FIG. 18 , where a plurality of through holes are provided on the second insulating film layer 90, each of which exposes a portion of the surface of a trace structure 821; a conductive ball 83 is formed on the surface of each trace structure 821 away from the plastic encapsulation layer 40, and a portion of the conductive ball 83 is located in the through hole of the second insulating film layer 90. The semiconductor structure can be soldered on the circuit board through the conductive ball 83, which facilitates the connection between the semiconductor structure and the circuit board. The material of the conductive ball 83 can be solder paste, metal tin or tin alloy. The embodiment of the present application also provides a semiconductor structure, as shown in FIG18 , the semiconductor structure includes an electrical component 30, a plastic encapsulation layer 40, a conductive structure 621 and a rewiring layer 82. The number of the electrical components may be one or more, and at least one of the electrical components 30 includes a body 302 and a welding end 301 protruding from the body 302. The plastic encapsulation layer 40 at least encapsulates the side of the electrical component 30. The conductive structure 621 corresponds to the welding end 301 one by one, and each conductive structure 621 covers the corresponding welding end 301 and exposes the surface of the plastic encapsulation layer 40 and is welded to the welding end 301. The material of the conductive structure 621 is different from that of the welding end 301. The rewiring layer 82 is partially located on the side of the conductive structure 621 away from the electrical component 30, and is electrically connected to the conductive structure 621. The embodiment of the semiconductor structure provided in the embodiment of the present application and the embodiment of the method for manufacturing the semiconductor structure belong to the same inventive concept, and the description of the relevant details and beneficial effects can be referred to each other, and will not be repeated here. It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements. Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptive changes of the present application, which variations, uses, or adaptive changes of the present application Or the adaptive changes follow the general principles of this application and include common knowledge or conventional technical means in the technical field that are not disclosed in this application. The description and examples are only regarded as exemplary, and the true scope and spirit of this application are pointed out by the following claims. It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for manufacturing a semiconductor structure, the method comprising: providing an adhesive layer on one side of the carrier plate; Placing one or more electrical components on a side of the adhesive layer away from the carrier, wherein at least one of the electrical components comprises a body and a welding end protruding from the body, the welding end faces the carrier and at least partially enters the adhesive layer; forming a plastic encapsulation layer on the bonding layer, wherein the plastic encapsulation layer at least encapsulates a side surface of the electrical component; The carrier board and the bonding layer are removed, and the portion of the welding end that enters the bonding layer is exposed; A rewiring layer is formed on one side of the electrical component where the soldering terminal is provided, and the rewiring layer is electrically connected to the soldering terminal. 2 . The method for manufacturing a semiconductor structure according to claim 1 , wherein a ratio of a thickness of the bonding layer to a thickness of a portion of the soldering end that enters the bonding layer is greater than or equal to 2. 3 .

3. The method for manufacturing a semiconductor structure according to claim 1 or 2, further comprising: forming a conductive structure on the surface exposed by the soldering end, The orthographic projection of the conductive structure on the plane where the surface of the plastic layer away from the welding end is located covers the orthographic projection of the portion of the welding end exposed from the plastic layer on the plane, and the material of the conductive structure is different from that of the welding end; The redistribution layer is at least partially located on a side of the conductive structure away from the electrical component and is electrically connected to the conductive structure.

4. The method for manufacturing a semiconductor structure according to claim 3, further comprising: Disposing soldering flux on the exposed surface of the soldering end; Wherein, forming the conductive structure on the surface exposed by the welding end includes: A conductive film is provided on one side of the electrical component where the soldering flux is provided, wherein the conductive film covers the soldering flux; Welding the conductive film and the welding end together; The conductive film is patterned to obtain the conductive structure.

5. According to the method for manufacturing a semiconductor structure according to claim 3 or 4, the conductive structure corresponds to the welding end one by one, and the area of ​​the orthographic projection of the conductive structure on the plane is larger than the area of ​​the orthographic projection of the corresponding portion of the welding end exposed from the plastic encapsulation layer on the plane.

6. The method for manufacturing a semiconductor structure according to claim 4 or 5, before welding the conductive film and the welding terminal together, the method for manufacturing a semiconductor structure further comprises: The conductive film is bonded to the soldering flux on the surface of the soldering end by vacuum adsorption. 7 . The method for manufacturing a semiconductor structure according to claim 4 , wherein the thickness of the conductive film is in the range of 10 μm to 35 μm. 8 . The method for manufacturing a semiconductor structure according to claim 3 , wherein a material of the conductive structure is the same as a material of the redistribution layer.

9. The method for manufacturing a semiconductor structure according to any one of claims 1 to 8, wherein the one or more electrical components include a first chip, and the first chip includes: A first welding pad; as well as A protective structure is formed on the surface of the first pad, wherein the material of the protective structure is a conductive material, Wherein, in the semiconductor structure, the first pad faces the bonding layer, and the redistribution layer is electrically connected to the conductive material.

10. The method for manufacturing a semiconductor structure according to any one of claims 1 to 9, wherein the one or more electrical components include a second chip, and the second chip includes: A second welding pad; an insulating layer covering the second pad; as well as an opening formed in the insulating layer to expose the second pad, Wherein, in the semiconductor structure, the redistribution layer is electrically connected to the second pad through the opening. 11 . The method for manufacturing a semiconductor structure according to claim 1 , wherein the one or more electrical components comprise at least one of a chip, an inductor, a resistor and a capacitor.

12. A semiconductor structure, comprising: One or more electrical components, at least one of the electrical components comprising a body and a welding terminal protruding from the body; A plastic encapsulation layer, encapsulating at least the side surfaces of the electrical component; at least one conductive structure corresponding to the welding end one by one, the conductive structure covers the surface of the corresponding welding end exposed from the plastic sealing layer and is welded to the welding end, and the material of the conductive structure is different from that of the welding end; The redistribution layer is located on a side of the conductive structure away from the electrical component and is electrically connected to the conductive structure.

13. The semiconductor structure according to claim 12, wherein the one or more electrical components include a first chip, the first chip includes a first pad, an insulating material layer located on one side of the first pad, and a protection structure in an opening of the insulating material layer, wherein the material of the protection structure is a conductive material; The redistribution layer is electrically connected to the conductive material.

14. The semiconductor structure according to claim 12 or 13, wherein the one or more electrical components include a second chip, the second chip includes a second pad, an insulating material layer located on one side of the second pad, and an insulating layer, wherein: The insulating layer covers the insulating material layer and fills the opening in the insulating material layer; The redistribution layer is electrically connected to the second pad.

15. The semiconductor structure according to any one of claims 12 to 14, further comprising a first insulating film layer covering the conductive structure, The first insulating film layer includes a plurality of first through holes, each of which includes a conductive portion. The rewiring layer includes a plurality of trace structures, each of which is electrically connected to a conductive portion in a corresponding first through hole.

16. The semiconductor structure according to claim 15, further comprising a second insulating film layer covering the redistribution layer, The second insulating film layer includes a plurality of second through holes, each of which exposes a portion of the surface of a trace structure; A conductive ball on a surface of each trace structure facing away from the plastic encapsulation layer is partially located in the second through hole of the second insulating film layer.

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