Assembly for an electronic computing device, and method for operating an assembly

Abstract

The invention relates to an assembly for an electronic computing device (10), comprising at least one microcontroller (12) and at least one I / O device (18, 20) communicating with the microcontroller (12), wherein an integrated circuit (14) is arranged between the microcontroller (12) and the I / O device (18, 20) and is designed to control the communication between the microcontroller (12) and the I / O device (18, 20). The invention also relates to a corresponding method for operating an assembly of this kind. The invention also relates to a method for operating an assembly (16).

Description

[0001] Description

[0002] Arrangement for an electronic computing device, and method for operating an arrangement

[0003] The invention relates to an arrangement for an electronic computing device, comprising at least one microcontroller and at least one input / output device that communicates with the microcontroller according to the applicable patent claim 1. Furthermore, the invention relates to a corresponding method for operating such an arrangement.

[0004] System developers want to prototype gateway devices as flexibly as possible, particularly devices that improve the connectivity of other devices, for example by connecting sensors or actuators to a network, or separating north and south bound communication, or similar. To achieve this, modularity can be offered at the PCB level. The user connects additional interface expansion modules to previously defined connectors. This gives rise to the following problems: The interfaces require different processing of their data and control signals, and certain timing guarantees and restrictions are difficult to implement in software. A microcontroller that controls the gateway device usually offers only a limited, often small, number of interfaces with predefined types.Often these interfaces are already reserved for other necessary applications, such as connecting flash memories or permanently installed Ethernet controllers. In order to keep the possible configuration flexible - every expansion module can be connected to any connector - it would have to be possible to route from every connector to every interface on the microcontroller. It is also often the case that expansion modules implement interfaces that have no equivalent on the microcontroller. The expansion modules should be automatically detected and configured to avoid sources of error and unnecessary work. In summary, a problem with the current state of the art is that expansion modules of as arbitrary a number, type and configuration as possible have to be connected to the microcontroller and set up automatically.

[0005] This modularity problem is usually solved at a higher level than the PCB level. For example, modules are connected that process the raw signals themselves, perhaps through their own microcontroller, and forward them to the main device, especially the electronic computing device, via a common interface. These signals are often also preprocessed before being forwarded to the microcontroller.

[0006] Other solutions, however, are simply not as flexible, but define in advance which signals are routed via a connector, for example, SRI and I2C. This makes the development of unanticipated expansion modules more difficult, as they may require conversion to the supported signals.

[0007] The object of the present invention is to provide an arrangement and a method by means of which input / output devices can be connected to an electronic computing device in a simplified manner.

[0008] This object is achieved by an arrangement and a method according to the independent patent claims. Advantageous embodiments are specified in the subclaims.

[0009] One aspect of the invention relates to an arrangement for an electronic computing device, comprising at least one microcontroller and at least one input / output device which communicates with the microcontroller.

[0010] It is provided that an integrated circuit is arranged between the microcontroller and the input / output device, which is designed to control communication between the microcontroller and the input / output device. In particular, an integrated circuit is thus proposed as a modular input / output coprocessor. In particular, the input / output device is also referred to as an input / output device.

[0011] In particular, the integrated circuit can be designed as a so-called embedded device. The integrated circuit, as well as the microcontroller, can be provided as part of the electronic computing device or as separate components.

[0012] In particular, the invention proposes that the integrated circuit act as an I / O coprocessor and decouple the microcontroller from the expansion modules. Automatic setup can be achieved through a combination of identification data and partial reconfiguration. Partial reconfiguration is a capability of integrated circuits in which only parts, particularly so-called partitions, of the integrated circuit are reconfigured, thus allowing new hardware functionality to be implemented. This is used here so that expansion modules can, for example, bring their own hardware implementations.

[0013] In particular, the idea is that the user connects expansion modules, which bring a so-called partial bitstream with which a pre-reserved partition of the integrated circuit is configured, thus partially reconfiguring the integrated circuit. The partial bitstream implements hardware functionality that handles decoding and encoding the raw data and control signals for the expansion module. The actual communication with the microcontroller, controlling the reconfiguration, and the like, are statically configured functionalities and are shared by all expansion modules and the microcontroller.In particular, the main difference compared to the state of the art is the use of the integrated circuit to extend and decouple the input / output interfaces of a microcontroller and in the use of partial reconfiguration, so that expansion modules bring their own partial configuration.

[0014] This has the particular advantage that expansion modules are largely decoupled from the input / output interfaces inherent in the microcontroller. This allows for much more flexibility in the design of expansion modules without requiring changes to the hardware of the base unit, especially the electronic computing device.

[0015] By using the integrated circuit, processing can be performed in hardware, which also increases flexibility, as hardware timing guarantees can be provided, especially for interfaces, which are simply not possible in software. The integrated circuit also allows the input voltages to be set by the pin, for example, at 1.8 volts or 3.3 volts.

[0016] The partial reconfiguration ensures that the data and control signals can be processed dedicatedly on the interface pins without the need for complex and expensive multiplex / switch / or even crossbar structures for routing.

[0017] The expansion modules themselves do not require a microcontroller or similar, which can reduce their complexity, size, and price. Yet they are capable of easily implementing functionality not anticipated in advance.

[0018] The strengths of an integrated circuit can be utilized here. The integrated circuit can be used for other activities in parallel. For example, various hardware accelerators can be implemented, for example, for data processing or security, or even simply the agitation of a microcontroller bus can be taken over. This can also minimize the number of integrated circuit devices required.

[0019] According to an advantageous embodiment, the integrated circuit is designed as a field-programmable gate array device. The field-programmable gate array (FPGA) is a type of integrated circuit. Unlike conventional integrated circuits, an FPGA can be programmed after manufacture to perform a specific function. This allows for simple communication between the input / output device and the microcontroller.

[0020] It has also proven advantageous for the integrated circuit to perform a partial reconfiguration of its own partition after connecting at least one input / output device. Partial reconfiguration is a capability of the FPGA in particular, where only parts, so-called partitions of the FPGA, are reconfigured, thus enabling the functional implementation of new hardware. This is used here so that the expansion modules can provide their own hardware implementation.

[0021] A further advantageous embodiment provides that a respective bitstream for a respective input / output device is provided for the integrated circuit. Thus, it can be provided that the partial reconfiguration can be carried out on the basis of the bitstream in the integrated circuit. Thus, the reconfiguration of the integrated circuit can be implemented in a simple manner.

[0022] It is also advantageous if the respective input / output device is provided with the respective bitstream. For example, the input / output device, which can also be referred to as an expansion module, can be equipped with a corresponding ROM memory that contains both the corresponding identification data, i.e. which module it actually is - which is also necessary for the software on the microcontroller, among other things - and the partial bitstream for the partial reconfiguration of the integrated circuit - i.e. the assigned expansion partition. This means that the partial reconfiguration can be carried out easily when the input / output device is connected.

[0023] Furthermore, it has proven advantageous if the respective bitstream is stored within a memory device of the integrated circuit. For example, the integrated circuit can also retain respective bitstreams and thus, upon connection of an input / output device, read the corresponding bitstream from the memory device, thus automatically performing the partial reconfiguration.

[0024] It is also advantageous if the respective bitstream is provided in a flash memory as the storage device. For example, the flash memory can be in the form of a USB stick or an SD card. This makes it possible, for example, to flexibly replace the flash memory, which also allows the corresponding bitstreams to be updated. Thus, the bitstream can be reliably provided for partial reconfiguration.

[0025] A further advantageous embodiment provides that the bitstream for downloading from a network is provided by means of the integrated circuit. For example, the integrated circuit can have a corresponding communications module that can communicate with a network, for example the Internet. After the input / output device has been identified, the bitstream can then be downloaded from the network. Furthermore, it is also possible, for example, for the electronic computing device to be connected to the network and for the integrated circuit to be able to download the corresponding bitstream via the microcontroller. The bitstream for partial reconfiguration can thus be reliably provided.

[0026] A further advantageous embodiment provides that the integrated circuit is designed to convert raw data from the input / output device for the microcontroller. In particular, it is thus provided that, for example, the integrated circuit converts the corresponding data for the microcontroller, so that the microcontroller receives preprocessed data and thus does not have to convert the raw data accordingly. The microcontroller can thus be equipped with a correspondingly lower computing capacity.

[0027] Furthermore, it has proven advantageous if the integrated circuit has a pin arrangement that is connected to all connectors of the integrated circuit. In particular, the integrated circuit thus has an external interface for partial reconfiguration, for example, depending on the manufacturer, as JTAG, ISAP, or others. This contains additional control signals for loading the partial bitstreams from the corresponding expansion modules. Accordingly, the pins of this interface are connected to all connectors.

[0028] It has also proven advantageous if the integrated circuit has at least one further pin arrangement, the further pin arrangement being designed for connection to the at least one input / output device. In particular, an expansion interface is thus provided on the integrated circuit, which in each case provides an expansion module and a certain number of pins and is connected to the corresponding external connector. The meaning of the pins is specific to each expansion module. In order to decode and encode these, a corresponding number of expansion partitions are reserved on the integrated circuit, which can be dynamically reconfigured using the special hardware module that converts the signals from the connected expansion modules into a common format.

[0029] It is further advantageous if an integrated circuit has at least two additional pin arrangements, wherein the two additional pin arrangements are homogeneously configured. In particular, the pin arrangements for the corresponding expansion modules / input / output devices are thus homogeneously configured, so that a large number of different input / output devices can be reliably connected.

[0030] A further aspect of the invention relates to a method for operating an arrangement according to the preceding aspect. In particular, a connection of at least one input / output device to the integrated circuit is detected by means of the integrated circuit. The respective input / output device is identified by means of the integrated circuit, and in the event that no bitstream is received for the respective input / output device, an extension description is generated by the integrated circuit and stored on the memory device. A bitstream is provided / received for the input / output device by means of the integrated circuit, and a partition of the integrated circuit is partially reconfigured as a function of the respectively received bitstream by means of the integrated circuit.

[0031] The extension description may contain information about the electronic components used in the respective input / output device, in particular their type designations, serial numbers, and / or information about the technical standards applied. The extension description may also contain information about which technical interface, in particular which protocol with which parameters, has been implemented.

[0032] According to an advantageous embodiment of the method, raw data from the input / output device are converted into data readable by the microcontroller by means of the integrated circuit.

[0033] Furthermore, an advantageous embodiment of the method provides that a new connection of an input / output device to an integrated circuit is communicated to the microcontroller via the integrated circuit. According to an advantageous embodiment of the method, at least one extension description stored on the memory device is read out by an external system, and a new firmware and / or bitstream for the integrated circuit is compiled using the extension description and then transferred to the integrated circuit.

[0034] This advantageously allows the computationally intensive process of code compilation to be outsourced to the external system and the integrated circuit can thus be a more cost-effective type with lower computing power and a smaller design.

[0035] The method presented is, in particular, a computer-implemented method. A further aspect of the invention therefore also relates to a computer program product with program code means which cause an electronic computing device and / or the integrated circuit to carry out a method according to the preceding aspect when the program code means are processed by the electronic computing device and / or the integrated circuit. Furthermore, the invention therefore also relates to a computer-readable storage medium with the computer program product.

[0036] Advantageous embodiments of the arrangement are also to be regarded as advantageous embodiments of the method.

[0037] The arrangement has the necessary features to enable the corresponding procedural step to be carried out.

[0038] For use cases or application situations that may arise during the method and are not explicitly described here, it may be provided that, in accordance with the method, an error message and / or a request for user feedback is issued and / or a default setting and / or a predetermined initial state is set. Regardless of the grammatical gender of a particular term, this includes persons with male, female, or other gender identities.

[0039] Further features of the invention emerge from the claims, the figures and the description of the figures. The features and combinations of features mentioned above in the description as well as the features and combinations of features mentioned below in the description of the figures and / or shown in the figures can be encompassed by the invention not only in the respectively specified combination, but also in other combinations. In particular, the invention can also encompass embodiments and combinations of features which do not have all the features of an originally formulated claim. Furthermore, the invention can encompass embodiments and combinations of features which go beyond the combinations of features set out in the references to the claims or deviate from them.

[0040] It shows:

[0041] FIG shows a schematic block diagram according to an embodiment of an arrangement;

[0042] The invention is explained in more detail below with reference to specific embodiments and associated schematic drawings. In the figures, identical or functionally equivalent elements may be provided with the same reference numerals.

[0043] The FIG shows a schematic block diagram according to an embodiment of an electronic computing device 10. In the present exemplary embodiment, the electronic computing device 10 has at least one microcontroller 12 and an integrated circuit 14, in particular in the form of an FPGA (field-programmable gate array).

[0044] In particular, the FIG shows an overall arrangement 16 for the electronic computing device 10, with at least the microcontroller 12 and at least one input / output device 18, 20 that communicates with the microcontroller 12. Provision is made here for the integrated circuit 14, which is designed to control the communication between the microcontroller 12 and the input / output device 18, 20, to be arranged between the microcontroller 12 and the input / output device 18, 20.

[0045] The figure further shows that, for example, the integrated circuit 14 can have a memory device 22 configured to store a bitstream. The memory device 22 can be configured, in particular, in the form of a flash memory, for example, in the form of an SD card.

[0046] The figure also shows that the integrated circuit 14 has a pin arrangement 24, wherein the pin arrangement 24 is connected to all connectors of the integrated circuit 14. Furthermore, the pin arrangement 24 is coupled in the present case to a so-called configuration module 26, 28 of the respective input / output device 18, 20. The figure also shows that the integrated circuit 14 has at least one further pin arrangement 30, 32, in the present case, in particular two further pin arrangements 30, 32, wherein the further pin arrangements 30, 32 are designed for connection to the at least one input / output device 18, 20. For example, a first further pin arrangement 30 can be coupled to a first connection module 34 of a first input / output device 18 and the second further pin arrangement 32 can be coupled to a second connection module 36 of a second input / output device 20.

[0047] In the present exemplary embodiment, it can be provided that the integrated circuit 14, in particular, has the two further pin arrangements 30, 32, wherein the two further pin arrangements 30, 32 are formed homogeneously.

[0048] Furthermore, the figure shows that, for example, the first input / output device 18 can have a first ROM memory 38 and the second input / output device 20 can have a second ROM memory 40. Furthermore, the first input / output device 18 has a first specific circuit 42 and the second input / output device 20 has a second specific circuit 44.

[0049] It is further shown that the integrated circuit 14 has, for example, a first extension partition 46 for the first further pin arrangement 30 and a second extension partition 48 for the second further pin arrangement 32.

[0050] Furthermore, the integrated circuit 14 has a so-called expansion handler and partial reconfigurator, which in this case has the reference numeral 50. Furthermore, the integrated circuit 14 has a microcontroller interface 52, which is designed to communicate with the microcontroller 12.

[0051] Furthermore, it can be provided that the integrated circuit 14 carries out a partial reconfiguration of its own partition after connection of the at least one input / output device 18, 20. Furthermore, it can be provided that a respective bitstream for a respective input / output device 18, 20 is provided for the integrated circuit 14. In this case, it can be provided that the respective input / output device 18, 20 is provided with the respective bitstream. Alternatively or additionally, the respective bitstream can be stored within the memory device 22 of the integrated circuit 14. Again alternatively or additionally, the bitstream can be made available for downloading from a network by means of the integrated circuit 14.

[0052] In particular, it can be provided that the integrated circuit 14 is designed to convert raw data of the input / output device 18, 20 for the microcontroller 12.

[0053] In particular, the FIG shows that through the use of the integrated circuit 14, in particular the FPGA, the microcontroller 12 is decoupled from the input / output devices 18, 20. The automatic setup is achieved by a combination of identification data and partial reconfiguration being carried out by means of the integrated circuit 14. Partial reconfiguration is the ability of an FPGA in which only parts, in particular so-called partitions, of the FPGA are reconfigured and thus new hardware functionality can be implemented. This is used so that the corresponding expansion modules, i.e. the input / output devices 18, 20, can bring their own hardware implementation.

[0054] The idea is that a user connects the input / output devices 18, 20, which bring a so-called partial bitstream with which a pre-reserved partition on the FPGA is configured and thus the FPGA is partially reconfigured. The partial bitstream implements hardware functionality that handles decoding and encoding the raw data and control signals for the input / output device 18, 20. The actual communication with the microcontroller 12, the control of the reconfiguration, and the like, are statically configured functionalities and are shared by all input / output devices 18, 20 and the microcontroller 12.

[0055] The FIG illustrates a specific example. The FIG shows, in particular, the relevant interfaces and components. On the FPGA, the pin arrangement 24 for partial reconfiguration is defined, depending on the manufacturer and specific FPGA model, for example via JTag or ISAP or others. This contains additional control signals for loading the partial bitstreams from the input / output devices 18, 20. Accordingly, the pins of this interface are connected to all connectors / other pin arrangements 30, 32.

[0056] In addition, there are several homogeneous external expansion interfaces, in particular the additional pin arrangements 30, 32, which each provide a certain number of pins to an input / output device 18, 20 and are connected to the corresponding external connector. The meaning of the pins is specific to each expansion module / input / output device 18, 20. To decode and encode these, a corresponding number of expansion partitions are reserved on the FPGA. These partitions can be dynamically reconfigured using special hardware modules that convert the signals from the connected input / output devices 18, 20 into a common format.

[0057] In the concrete example presented, the input / output devices 18, 20 are equipped with the ROM memory 38, 40, which contains both identification data, i.e. which module is involved, and the partial bitstream for the partial reconfiguration of the FPGA, i.e. the assigned expansion partition.

[0058] The following steps are carried out when booting the gateways or when plugging in an input / output device 18, 20. All input / output devices 18, 20 are run through, i.e. the following steps are repeated for all connectors. The identification of the input / output device 18, 20 is checked and passed on to the microcontroller 12, among other things, so that it can load any drivers or similar. Analogous to the partial bitstream, the ROM could also contain the software drivers. The so-called extension handler loads the partial bitstream, which is stored in the ROM memory 38, 40 of the input / output devices 18, 20, into the expansion partition reserved for the corresponding interfaces. This ensures that the newly configured functions can be used. The input / output device 18, 20 and the microcontroller 12 are informed that the extension is now set up.

[0059] Other implementations are also possible. For example, the partial bitstreams of all known input / output devices 18, 20 could be stored on the SD card, and the FPGA retrieves the necessary information based on the identification data of the actually connected input / output devices 18, 20. This solution, for example, is less flexible but less expensive. Overall, a variety of such trade-offs can be achieved through clever distribution of the individual components. List of reference symbols

[0060] 10 Electronic computing device

[0061] 12 microcontrollers

[0062] 14 integrated circuits

[0063] 16 Arrangement

[0064] 18 first input / output device

[0065] 20 second input / output device

[0066] 22 Storage device

[0067] 24 pin arrangement

[0068] 26 first configuration module

[0069] 28 second configuration module

[0070] 30 first further pin arrangement

[0071] 32 second additional pin arrangement

[0072] 34 first connection module

[0073] 36 second connection module

[0074] 38 first ROM memory

[0075] 40 second ROM memory

[0076] 42 first specific circuit

[0077] 44 second specific circuit

[0078] 46 first expansion partition

[0079] 48 second expansion partition

[0080] 50 Extension Handler and Partial Reconfigurator

[0081] 52 Microcontroller interface

Claims

Patent claims 1. Arrangement (16) for an electronic computing device (10), with at least one microcontroller (12) and at least one input / output device (18, 20) which communicates with the microcontroller (12), characterized in that an integrated circuit (14) is arranged between the microcontroller (12) and the input / output device (18, 20), which is designed to control communication between the microcontroller (12) and the input / output device (18, 20).

2. Arrangement (16) according to claim 1, characterized in that the integrated circuit (14) is designed as a field-programmable gate array device.

3. Arrangement (16) according to claim 1 or 2, characterized in that the integrated circuit (14) carries out a partial reconfiguration of its own partition after connection of the at least one input / output device (18, 20).

4. Arrangement (16) according to one of the preceding claims, characterized in that a respective bitstream for a respective input / output device (18, 20) is provided for the integrated circuit (14).

5. Arrangement (16) according to claim 4, characterized in that the respective input / output device (18, 20) is provided with the respective bitstream.

6. Arrangement (16) according to one of claims 4 or 5, characterized in that the respective bit stream is stored within a memory device (22) of the integrated circuit (14).

7. Arrangement (16) according to claim 6, characterized in that the respective bitstream is provided in a flash memory as storage device (22).

8. Arrangement (16) according to one of claims 4 to 7, characterized in that the bitstream for downloading from a network is provided by means of the integrated circuit (14).

9. Arrangement (16) according to one of the preceding claims, characterized in that the integrated circuit (16) is designed to convert raw data of the input / output device (18, 20) for the microcontroller (12).

10. Arrangement (16) according to one of the preceding claims, characterized in that the integrated circuit (14) has a pin arrangement (24) which is connected to all connectors of the integrated circuit (14).

11. Arrangement (16) according to one of the preceding claims, characterized in that the integrated circuit (14) has at least one further pin arrangement (30, 32), wherein the further pin arrangement (30, 32) is designed for connection to the at least one input / output device (18, 20).

12. Arrangement (16) according to claim 11, characterized in that the integrated circuit (14) has at least two further pin arrangements (30, 32), wherein the two further pin arrangements (30, 32) are formed homogeneously.

13. A method for operating an arrangement (16) according to one of claims 1 to 12, comprising the steps: - detecting a connection of at least one input / output device (18, 20) to the integrated circuit (14) by means of the integrated circuit (14); - identifying the respective input / output device (18, 20) by means of the integrated circuit (14); - receiving a bitstream for the respective input / output device (18, 20) by means of the integrated circuit (14), wherein, in the event that no bitstream is received for the respective input / output device, an extension description is generated by the integrated circuit (14) and stored on the memory device (22); and - Partially reconfiguring a partition of the integrated circuit (14) as a function of the respectively received bit stream by means of the integrated circuit (14).

14. The method according to claim 13, characterized in that raw data from the input / output device (18, 20) are converted by means of the integrated circuit (14) into data readable by the microcontroller (12), wherein a new connection of an input / output device (18, 20) to the integrated circuit (14) is communicated to the microcontroller (12) by means of the integrated circuit (14).

15. The method according to claim 13 or 14, characterized in that at least one extension description stored on the memory device (22) is read out by an external system and by means of the extension description a new firmware and / or bitstream for the integrated circuit (14) is compiled and then transferred to the integrated circuit (14).

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