Data processing device and data driving device

Abstract

Disclosed in an embodiment are a data processing device and a data driving device, the data processing devicecomprise: a first data mapping unit for converting original data into a plurality of data packets; and an encoder for inverting some bits of the plurality of data packets, wherein the encoder includes: a data comparison unit for comparing the most significant bit (MSB) of a first data packet and the least significant bit (LSB) of a second data packet, which neighbor each other from among the plurality of data packets; a code conversion unit for inverting the LSB of the second data packet if the MSB of the first data packet is the same as the LSB of the second data packet; and a bit generation unit for generating an indicator packet in which conversion information of the LSB of the second data packet is stored.

Description

Data processing devices and data driving devices The embodiment relates to a data processing device and a data driving device. A data processing device, such as a timing controller, can transmit signals to a source driver according to an interface protocol, and the receiver can obtain data corresponding to the received signal by processing the received signal. The source driver can extract or recover a clock from the received signal to operate in response to the clock. To this end, the source driver can include a clock-data recovery (CDR) circuit. In response to the clock extracted or recovered by the clock-data recovery circuit, the source driver can appropriately recover data corresponding to the received signal. In high-speed clock-embedded transmission systems, periodic clock embedding is required in the transmitted data for the clock-data recovery (CDR) circuit to easily recover the clock. Data run length refers to the number of consecutive identical values ​​in the transmitted data and is related to the maximum period without clock embedding. To ensure smooth clock recovery in a clock-data recovery (CDR) circuit, the maximum run length must be adjusted to remain constant. Therefore, a data coding technique that enables clock embedding at a constant cycle is required. One embodiment may provide a data processing device and a data driving device that encode data such that the maximum run length is constant. One embodiment can provide a coding technique with a high degree of freedom by setting the number of data packets and the number of data bits differently. The tasks of the present invention are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the description below. According to one aspect of the present invention, a data processing device comprises: a first data mapping unit that converts original data into a plurality of data packets; and an encoder that inverts some bits of the plurality of data packets, wherein the encoder comprises: a data comparison unit that compares a most significant bit (MSB) of an adjacent first data packet among the plurality of data packets with a least significant bit (LSB) of a second data packet; a code conversion unit that inverts the least significant bit of the second data packet when the most significant bit of the first data packet and the least significant bit of the second data packet are the same; and a bit generation unit that generates an indicator packet in which conversion information of the least significant bit of the second data packet is stored. The method may further include a data group generation unit that generates a plurality of data groups by inserting the indicator packet into the plurality of encoded data packets. Each of the above multiple data groups may have the same number of packets. In the above data group, the indicator packet has a plurality of bits, and the number of bits of the indicator packet may be equal to the number of data packets in the data group. The number of bits of the above indicator packet may be the same as the number of bits of the above data packet. In the above data group, the indicator packet has multiple bits, and the number of bits of the indicator packet may be different from the number of the multiple data packets. The data comparison unit may perform an XOR operation on the most significant bit (MSB) of the adjacent first data packet and the least significant bit (LSB) of the second data packet, and the code conversion unit may invert or not invert the least significant bit of the second data packet according to the result of the XOR operation. The bit generation unit can store the result of an XOR operation of the most significant bit (MSB) of the adjacent first data packet and the least significant bit (LSB) of the second data packet in the bit position of the indicator packet. The above indicator packet includes a least significant bit, a most significant bit, and storage bits positioned between the least significant bit and the most significant bit, wherein the most significant bit has a value that is an inverted value of the most significant bit of the data packet immediately before the indicator packet, and the most significant bit may have a value that is an inverted value of the least significant bit of the data packet immediately after the indicator packet. According to one aspect of the present invention, a data driving device comprises: a data receiving unit that receives a plurality of data groups including an indicator packet and a plurality of data packets; and a decoder that restores the data packets to original data, wherein the decoder comprises: an indicator packet storage unit that separates and stores the indicator packets; and inverts or non-inverts the least significant bits of the plurality of data packets according to conversion information of the least significant bits of each data packet stored in the indicator packet to restore the data to original data. The above decoder may include a second data mapping unit that restores clock information and data information from the restored original data. According to an embodiment, since the clock edge occurs at the boundary of the packet, the maximum run length can be secured at a constant level, making it easy to restore the clock and data. Additionally, the number of data packets and the number of bits can be freely changed, which increases the degree of freedom and enables high-speed transmission. The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims. Figure 1 is a conceptual diagram of a transmission and reception device according to one embodiment of the present invention. Figure 2 is a conceptual diagram of an encoder according to one embodiment of the present invention. Figure 3 is a conceptual diagram of a decoder according to one embodiment of the present invention. FIG. 4 is a diagram showing a data structure according to one embodiment of the present invention. FIG. 5 is a flowchart showing a data encoding step according to one embodiment of the present invention. Figure 6 is a diagram showing an original data packet. FIG. 7 is a diagram illustrating a data encoding method according to one embodiment of the present invention. FIG. 8 is a diagram showing an XOR operation table according to one embodiment of the present invention. FIG. 9 is a diagram showing encoded data according to one embodiment of the present invention. FIG. 10 is a diagram showing a decoding process according to one embodiment of the present invention. FIG. 11 is a diagram illustrating a data encoding method according to another embodiment of the present invention. FIG. 12 is a drawing showing a data encoding method according to another embodiment of the present invention. FIG. 13 and FIG. 14 are diagrams showing an encoding process by a data encoding method according to another embodiment of the present invention. Fig. 15 is a drawing showing a first modified example of Fig. 12. Fig. 16 is a drawing showing a second modified example of Fig. 12. FIG. 17 is a diagram showing a decoding process according to another embodiment of the present invention. The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. The embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the details depicted in the drawings. Throughout the specification, the same reference numerals designate substantially the same components. Furthermore, in describing the present invention, detailed descriptions of related known technologies will be omitted if they are deemed to unnecessarily obscure the gist of the present invention. The following embodiments can be partially or fully combined or combined with one another, enabling various technically diverse interconnections and operations. Each embodiment can be implemented independently of the other, or can be implemented together in a related manner. Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings. FIG. 1 is a conceptual diagram of a data transmission and reception device according to one embodiment of the present invention. FIG. 2 is a conceptual diagram of an encoder of a transmitter according to one embodiment of the present invention. FIG. 3 is a conceptual diagram of a decoder of a receiver according to one embodiment of the present invention. Referring to FIGS. 1 and 2, a transceiver according to an embodiment may include a transmitter (100) and a receiver (200). The transceiver may be a variety of display devices, such as a smartphone, a TV, or a display inside a vehicle, but embodiments of the present invention are not limited thereto. The transmitter (100) may include a variety of transmitters that encode and transmit data. For example, the transmitter (100) may be a data processing device, such as a timing controller, but embodiments of the present invention are not limited thereto. The receiver (200) may include various receivers that decode encoded data to restore the original data. For example, the receiver (200) may be a data-driven device such as a source driver, but embodiments of the present invention are not limited thereto. The transmitter (100) may include a first data mapping unit (110) that converts input data into a data packet, an encoder (120) that encodes data, and a transmission unit (130) that serially transmits the encoded data. The first data mapping unit (110) may be a transmission circuit (TX logic) that receives and stores original data in frame units, packetizes the data, and transmits it to an encoder. The first data mapping unit (110) may convert the original data into a packet having N bits. For example, the N bits may be a multiple of 2, a multiple of 3, or a multiple of 5, but embodiments of the present invention are not limited thereto. The bits of the packet may be predetermined in consideration of the maximum run length. If the maximum run length is 12UI, each packet may have 12 bits, but is not necessarily limited thereto. The first data mapping unit (110) can count the bits inputted continuously and convert them into a packet having N bits. The first data mapping unit (110) can include a counter (not shown). The first data mapping unit (110) can count the bits inputted according to a predetermined protocol and generate a packet having N bits. The encoder (120) may include a data comparison unit (121), a bit generation unit (122), a code conversion unit (123), and a data group generation unit (124). The data comparison unit (121) can compare the most significant bit (MSB) of the adjacent first data packet with the least significant bit (LSB) of the second data packet. The first data packet may be a previous data packet transmitted to the encoder immediately before, and the second data packet may be a current data packet, but embodiments of the present invention are not limited thereto. For example, the data comparison unit (121) may simultaneously input multiple data packets stored in the frame memory and compare bits at the packet boundaries. The data comparison unit (121) may output an inverted signal when the most significant bit of the first data packet and the least significant bit of the second data packet are the same, and may output a non-inverted signal when the most significant bit of the first data packet and the least significant bit of the second data packet are different. The fact that the bits are the same may mean that the bit values ​​have the same value of 0 or 1. In addition, the fact that the bits are different may mean that the bit values ​​have different values ​​of 0 or 1. The data comparison unit (121) can perform an exclusive OR (XOR) operation. The data comparison unit (121) can output an inverted signal 0 when the most significant bit of the first data packet and the least significant bit of the second data packet are both 0 or both 1. The data comparison unit (121) can output a non-inverted signal 1 when the most significant bit of the first data packet is 1 and the least significant bit of the second data packet is 0, or when the most significant bit of the first data packet is 0 and the least significant bit of the second data packet is 1. The data comparison unit (121) can include a logic operation circuit capable of an exclusive OR (XOR) operation. The bit generation unit (122) can generate an indicator packet and receive an inverted signal or a non-inverted signal output from the data comparison unit (121) to map the conversion information of the corresponding bit to the indicator packet. The conversion information may be an inverted signal or a non-inverted signal output from the data comparison unit (121). For example, if the conversion information is input as 1, the decoder (220) does not invert the corresponding bit, and if the conversion information is input as 0, the decoder (220) can invert the corresponding bit. The code conversion unit (123) can invert or non-invert the least significant bit of the data packet according to an inverted or non-inverted signal. However, embodiments of the present invention are not limited thereto. For example, the most significant bit of the first data packet may be compared with the least significant bit of the second data packet, and if the bits are the same, the most significant bit of the first data packet may be inverted. According to an embodiment, two neighboring data packets may be compared, and if the neighboring bits at the packet boundary have the same value, one of the neighboring bits may be inverted to generate a clock edge. Therefore, the least significant bit of a data packet may have a different value than the most significant bit of an adjacent data packet. In an embodiment, the bits at the boundary of each data packet have different values, so that a clock edge can be generated at the packet boundary. Therefore, the set maximum run length can be secured. For example, if the maximum run length set is 3UI, the bits of the first data packet are

[0100] and the bits of the second data packet are

[0000] In this case, since there are 6 consecutive 0s in two data packets, the maximum run length of 3UI may be exceeded. However, according to the embodiment, the least significant bit of the second data packet is inverted from 0 to 1, so the bit of the second data packet is

[1000] can be encoded. Therefore, the bits change at the boundary between the first data packet and the second data packet, generating a clock edge, so that the maximum run length can be satisfied. The data group generation unit (124) can generate a data group having N data packets by inserting one indicator packet into N-1 data packets. According to an embodiment, one data group can have N packets, and each data packet can have N bits. In other words, the number of data packets and the number of bits can be the same. Therefore, there is an advantage in that effective clock recovery is possible in the receiver (200). The encoder (120) may include a counter (125). The counter (125) counts each bit or packet to identify a boundary position between packets. However, the present invention is not limited thereto, and the counter may not be disposed in the encoder (120) but in the first data mapping unit (110). The first data mapping unit (110) may generate packets of the same bit using the counter. The encoder (120) may also identify a boundary position between packets based on the counting information of the first data mapping unit (110) without a separate counter. Referring to FIGS. 1 and 3, the receiver (200) may include a data receiving unit (210) that receives encoded data, a decoder (220) that converts the encoded data into original data, and a second data mapping unit (230) that restores clock and data from the original data. The decoder (220) may include an indicator packet storage unit (221) that extracts and stores indicator packets from encoded data, and a code restoration unit (222) that restores inverted bits of data packets. The indicator packet storage unit (221) may extract mapping data excluding the least significant bit and the most significant bit from the indicator packet. The code restoration unit (222) may convert or maintain the value of the least significant bit of each data packet based on the mapping data of the indicator packet. The decoder (220) may further include a counter (223) for counting bits or packets, but is not necessarily limited thereto. The decoder (220) may sequentially transmit data packets from which indicator packets are separated and bits are restored. The second data mapping unit (230) may include a clock-data recovery (CDR) circuit that restores the clock and data from the data packet. According to an embodiment, the encoder (120) can secure the maximum run length by inverting bits at the boundary of a data packet, and the decoder (220) can restore the inverted data to validly secure the original data. FIG. 4 is a diagram showing a data structure according to one embodiment of the present invention. Referring to FIG. 4, one data group may be composed of a total of N packets, including one indicator packet (IDP) and N-1 data packets (Packet 1 to Packet (n-1)). The data packet may be defined as effective data as RGB image data, but embodiments of the present invention are not limited thereto. The data packet may also include control data. The data group may be sequentially transmitted as a previous data group, a current data group, and a next data group. An indicator packet (IDP) may have N bits (HD1, I1 to I(n-1), and HD2). The least significant bit (LSB) and the most significant bit (MSB) of the indicator packet (IDP) may be a clock bit (CK), a guard bit, or a dummy bit. The conversion information (BI) of each data packet may be mapped between the least significant bit (LSB) and the most significant bit (MSB) of the indicator packet. In an embodiment, the least significant bit may be the bit closest to the previous packet within each packet, and the most significant bit may be the bit closest to the next packet within each packet, but embodiments of the present invention are not limited thereto. The least significant bit (LSB) of an indicator packet can be mapped to a different value than the most significant bit (B(n-1)) of the previous data packet. For example, if the last bit (B(n-1)) of the previous data group is 0, the least significant bit (LSB) of the indicator packet can be written as 1. For example, if the last bit (B(n-1)) of the previous data group is 1, the least significant bit (LSB) of the indicator packet can be written as 0. Therefore, a clock edge can be generated at the boundary between the previous data group and the current data group. The most significant bit (MSB) of the indicator packet can be matched by inverting the value of the least significant bit (B0) of the first data packet (Packet 1) within the current data group. For example, if the least significant bit (B0) of the first data packet within the current data group is 1, the most significant bit (MSB) of the indicator packet can be mapped to 0. For example, if the least significant bit (B0) of the first data packet (Packet 1) within the current data group is 0, the most significant bit (MSB) of the indicator packet can be mapped to 1. Therefore, since the clock edge occurs at the boundary between the indicator packet and the adjacent first data packet (Packet 1), the maximum run length can be satisfied. FIG. 5 is a flowchart illustrating a data encoding step according to one embodiment of the present invention. FIG. 6 is a diagram illustrating original data. FIG. 7 is a diagram illustrating a data encoding method according to one embodiment of the present invention. FIG. 8 is a diagram illustrating an encoding table according to one embodiment of the present invention. FIG. 9 is a diagram illustrating encoded data according to one embodiment of the present invention. Referring to FIG. 5, the data encoding method may include a step of comparing the most significant bit of an adjacent first data packet with the least significant bit of a second data packet (S110), a step of inverting the least significant bit of the second data packet based on the comparison result (S120), a step of mapping conversion information to generate an indicator packet (S130), and a step of inserting an indicator packet into an encoded data packet to generate a data group (S140). Each step will be described with reference to FIGS. 6 to 9. Referring to Figure 6, the original data can be converted into a packet having N bits. The original data may be scrambled data, but is not necessarily limited thereto. The original data may be RGB image data, but is not necessarily limited thereto, and may also include control data. Referring to FIGS. 7 and 8, the comparing step may perform an exclusive OR (XOR) operation on the most significant bit (MSB) of the first data packet and the least significant bit (LSB) of the second data packet. The data comparison unit (121) can output an inversion signal 0 when both the most significant bit (MSB) of the first data packet and the least significant bit (LSB) of the current data packet are 0 or 1. The data comparison unit (121) can output a non-inverted signal 1 when the most significant bit (MSB) of the first data packet and the least significant bit (LSB) of the second data packet have different bit values. For example, if the most significant bit (MSB) of the first data packet (Packet 1) is 1 and the least significant bit (LSB) of the second data packet is 1, the data comparison unit (121) can output an inversion signal 0 that inverts the least significant bit (LSB) of the second data packet because the bit values ​​are the same. The code conversion unit (123) can invert the least significant bit (LSB) of the second data packet and convert it to 0 (~B0) because the inversion signal 0 is output. The bit generation unit (122) can map the conversion information 0 to the I1 position of the indicator packet (~P2[B0]). Thereafter, the data comparison unit (121) can compare the most significant bit (MSB) of the second data packet and the least significant bit (LSB) of the third data packet, and output an inverted signal if the bit values ​​are the same. For example, the data comparison unit (121) can output a non-inverted signal 1 if the most significant bit (MSB) of the second data packet (Packet 2) is 1 and the least significant bit (LSB) of the third data packet (Packet 2) is 0 because the bit values ​​are different. The code conversion unit (123) can keep the least significant bit (LSB) of the third data packet (Packet 3) as is (B0) without inverting it according to the non-inverted signal 1. The bit generation unit (122) can map the conversion information 1 to the I2 position of the indicator packet (P3[B0]). Likewise, the data comparison unit (121) can sequentially compare the most significant bit (MSB) of the previous data packet and the least significant bit (LSB) of the current data packet to output an inverted signal or a non-inverted signal. The code conversion unit (123) can invert or non-invert the bit value of the least significant bit (LSB) of the current data packet according to an inverted or non-inverted signal. The bit generation unit (122) can sequentially map the conversion information (BI) to the corresponding bit position. The least significant bit (LSB) of the indicator packet (IDP) can be mapped to 1 by inverting the bit value 0 of the most significant bit (MSB) of the previous data packet, and the most significant bit (MSB) of the indicator packet (IDP) can be mapped to 0 by inverting the bit value 1 of the least significant bit (LSB) of the first data packet (Packet 1) of the current data group. The conversion information (BI) of the least significant bit (LSB) of the second to eleventh data packets (Packet 2 to Packet 11) can be sequentially mapped between the least significant bit (LSB) and most significant bit (MSB) of the indicator packet (IDP). According to an embodiment, the most significant bit (MSB) of the indicator packet is mapped to a different value from the least significant bit (LSB) of the first data packet (Packet 1), so that the least significant bit (LSB) of the first data packet (Packet 1) may not be encoded. In the data group, the least significant bits (LSBs) of the remaining 10 data packets, excluding the first data packet (Packet 1), may be inverted or maintained by an XOR operation. For example, a data group may be composed of a total of 12 packets, each including one indicator packet and 11 data packets. The indicator packet and the data packet may each be composed of 12 bits. Therefore, the total number of bits in the data group may be 144 bits. However, the present invention is not limited thereto. For example, a data group may be composed of 8 packets, each including one indicator packet and 7 data packets. If each packet is composed of 8 bits, the total number of bits in the data group may be 64 bits. According to an embodiment, since the number of packets and the number of bits in the packets are the same, the maximum run length can be maintained constant. Referring to Figure 9, since the bit values ​​of the encoded data are inverted at the packet boundary point (EP), a clock edge can be generated between each packet. Accordingly, the maximum run lengths (MRL0 to MRL11) can all be the same between each packet. This configuration offers the advantage of ensuring a regular run length, enabling optimized clock embedding. Furthermore, it improves bit rate with relatively small overhead. FIG. 10 is a diagram showing a decoding process according to one embodiment of the present invention. Referring to FIG. 10, the indicator packet and the data packet of the data group are separated, the indicator packet can be stored in the indicator packet storage unit (221), and the data packet can be stored in the code restoration unit (222). The decoder (220) can invert or not invert the least significant bit of the data packet according to the conversion information (BI) of the indicator packet. The conversion information (BI) can be an indicator bit mapped to a bit position. Since the bit information at position I1 in the conversion information (BI) is 0, the decoder can invert the least significant bit (LSB) of the second data packet (Packet 2) to 1. Since the bit information at position I2 in the conversion information (BI) is 1, the decoder can keep the least significant bit (LSB) of the third data packet (Packet 3) as 0 by not inverting it. Since the bit information at position I3 in the conversion information (BI) is 0, the decoder can invert the least significant bit (LSB) of the fourth data packet (Packet 4) to 0. Since the bit information at position I10 in the conversion information (BI) is 1, the decoder can invert the least significant bit (LSB) of the 11th data packet (Packet 11) and keep it 0. The restored data information can be restored identically to the original data of Fig. 5. According to the embodiment, since decoding is performed using the conversion information stored in the indicator packet, there is an advantage in that separate memory for decoding is not required. FIG. 11 is a diagram illustrating a data encoding method according to another embodiment of the present invention. Referring to Fig. 11, a data group may be composed of a total of N packets, including one indicator packet and N-1 data packets. A data packet may be defined as a valid data packet as RGB image data, but embodiments of the present invention are not limited thereto. A data packet may also include control data. The data groups may be sequentially arranged as a previous data group, a current data group, and a next data group. An indicator packet (IDP) can have N bits. The least significant bit of the indicator packet can be a clock bit (CK), a guard bit, or a dummy bit. After the least significant bit of the indicator packet, toggle information for each data packet can be sequentially mapped. The least significant bit (LSB) of an indicator packet can be mapped to a different value than the most significant bit (B(n-1)) of the previous data packet. For example, if the last bit (B(n-1)) of the previous data group is 0, the least significant bit (LSB) of the indicator packet can be set to 1. Therefore, a clock edge can be generated at the boundary between the previous data group and the current data group. According to an embodiment, the most significant bit of the indicator packet may not be written by inverting the value of the least significant bit (B0) of the first data packet (Packet 1) in the current data group. Instead, the least significant bit B0 of the first data packet (Packet 1) may be compared with the most significant bit I(n-1) of the indicator packet, and if the bits have the same value, the least significant bit B0 of the first data packet may be inverted and the conversion information may be mapped to the corresponding bit position (I1) in the indicator packet. Accordingly, after mapping the conversion information at the boundary of each data packet to the indicator packet, the last mapping bit may be compared with the least significant bit B0 of the first data packet (Packet 1). According to this configuration, the indicator packet includes a total of N bits, but the remaining bits except the least significant bit (LSB) can be bits to which conversion information is mapped. In addition, all the least significant bits of the data packet can be inverted or not inverted by an XOR operation. In FIGS. 4 and 7, the least significant bit of the first data packet is not XORed, but in this embodiment, there is a difference in that the least significant bit of the first data packet is also XORed. FIG. 12 is a diagram illustrating a data encoding method according to another embodiment of the present invention. FIG. 13 and FIG. 14 are diagrams illustrating a data structure according to another embodiment of the present invention. FIG. 15 is a diagram illustrating a first modified example of FIG. 12. FIG. 16 is a diagram illustrating a second modified example of FIG. 12. Referring to FIGS. 12 and 13, according to an embodiment, the number of packets in a data group may be different from the number of bits in the packets. For example, a first data group may be composed of M packets, and each packet may be composed of N bits. In this case, M and N may be the same or different natural numbers. For example, the number of packets may be greater than the number of bits, or the number of packets may be less than the number of bits. Alternatively, the number of packets and the number of bits may be the same. For example, the number of packets in a data group may be 2, and each packet may be composed of 10 bits. According to an embodiment, data coding rules can be established that set different packet counts and bit depths within a data group. Therefore, the optimal number of packets and bit depth can be adjusted based on various conditions, such as the type and size of the data. The data comparison unit (121) can output an inverted signal by performing an XOR operation on the most significant bit (B9) of the first data packet (Packet 1) and the least significant bit (B0) of the second data packet. The output inverted signal can be stored in the bit position (S) of the indicator packet. The indicator packet may be a clock bit (CK). According to an embodiment, there is an advantage in that data groups can be quickly created because only the boundaries of two packets are compared and encoded. In an embodiment, the technique may increase the maximum run length (MRL) by the number of bits in the indicator packet, unlike the data coding rules described above. For example, if an indicator packet has

[0000] bits and the immediately preceding data packet has [1000000000] bits, the run length may be increased by the number of bits in the indicator packet, since there are 11 consecutive 0s. Taking this into account, the number of bits may be appropriately adjusted. Referring to Fig. 14, the first data group may be composed of three data packets, and each data packet may be composed of eight bits. The data comparison unit (121) may compare bits at the boundary (B7 and B0) between the first data packet and the second data packet and at the boundary (B7 and B0) between the second data packet and the third data packet to output an inverted signal or a non-inverted signal. For example, in the case of RGB data, if each pixel data is 8 bits, the first data group can be composed of 3 data packets, and each data packet can be composed of 8 bits. In this case, the first data group can express RGB pixel data. Therefore, the encoder can generate data groups by generating only inverted signals at the boundaries of three data packets, enabling real-time encoding and offering the advantage of high-speed operation. Specifically, data can be compared at RGB data boundaries to generate inverted signals and mapped to clock bits (S1, S2). Consequently, the physical time required to map data can be shortened. Referring to FIG. 15, the least significant bit (LSB) of an indicator packet can be generated by inverting the last bit of the previous data group, and the most significant bit (MSB) of the indicator packet can be generated by inverting the least significant bit (LSB) of the first data packet (Packet 1) of the current data group. According to this configuration, since a clock edge occurs at the boundary between the indicator packet and the data packet, the run length due to the indicator bit can be improved. According to this configuration, the number of bits of a data packet and the number of bits of an indicator packet can be different. In addition, the number of data packets and the number of bits of a data packet can be different. Therefore, the number of data packets and the number of bits can be freely changed, which increases the degree of freedom and enables high-speed transmission. Referring to FIG. 16, dummy bits (D0 to D4) can be inserted into the indicator packet to match the number of bits in the indicator packet with the number of bits in the data packet. For example, both the indicator packet and the data packet can consist of 8 bits. Additionally, the least significant bit (LSB) of the indicator packet can be generated by inverting the last bit of the previous data group, and the most significant bit (MSB) of the indicator packet can be generated by inverting the least significant bit (LSB) of the first data packet (Packet 1) of the current data group. In this case, since the clock edge is generated at the boundary between the indicator packet and the data packet, the maximum run length can be secured. According to an embodiment, there is an advantage of having a constant run length while having freedom in the number of data packets and bit depth. According to an embodiment, adjacent bits at the boundary of an input packet can be inverted or not inverted by performing an XOR operation, and the conversion information can be mapped to an indicator packet and transmitted immediately. Therefore, the configuration of a separate counter or data group generation unit can be omitted. FIG. 17 is a diagram showing a decoding process according to another embodiment of the present invention. Referring to FIG. 17, the receiver (200) can extract conversion information from the clock domain of the input first data group, and invert or non-invert the least significant bit of the data packet according to the conversion information. For example, since the bit information at the S1 position in the mapping data is 0, the least significant bit of the second data packet can be inverted to 1, and since the bit information at the S1 position in the mapping data of the next first data group is 1, the least significant bit of the second data packet can be non-inverted to maintain 1. Since the content of the specification described in the problem to be solved, the means for solving the problem, and the effect described above does not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the specification. Although the embodiments have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be implemented without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but rather to illustrate it, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims

1. A first data mapping unit that generates multiple data packets; and An encoder for inverting some bits of the plurality of data packets, The above encoder, A data comparison unit that compares the most significant bit (MSB) of a first data packet and the least significant bit (LSB) of a second data packet among the plurality of data packets; A code conversion unit that inverts the least significant bit of the second data packet when the most significant bit of the first data packet and the least significant bit of the second data packet have the same value; and A data processing device comprising a bit generation unit that generates an indicator packet in which conversion information of the least significant bit of the second data packet is stored.

2. In paragraph 1, A data processing device in which the code conversion unit maintains the least significant bit of the second data packet when the most significant bit of the first data packet and the least significant bit of the second data packet have different values.

3. In paragraph 1, A data processing device further comprising a data group generation unit that generates a plurality of data groups by inserting the indicator packet into the plurality of data packets.

4. In paragraph 3, Each of the above multiple data groups has the same number of packets, A data processing device, wherein the number of bits of the above indicator packet is equal to the number of data packets in the above data group.

5. In paragraph 4, A data processing device, wherein the number of bits of the indicator packet is the same as the number of bits of the data packet.

6. In paragraph 3, In the above data group, the indicator packet has multiple bits, A data processing device, wherein the number of bits of the indicator packet is different from the number of the plurality of data packets.

7. In paragraph 1, The above data comparison unit performs an XOR operation on the most significant bit (MSB) of the adjacent first data packet and the least significant bit (LSB) of the second data packet, A data processing device in which the code conversion unit inverts or does not invert the least significant bit of the second data packet according to the result of the XOR operation.

8. In paragraph 7, A data processing device in which the bit generation unit stores the result of an XOR operation of the most significant bit (MSB) of the adjacent first data packet and the least significant bit (LSB) of the second data packet in an indicator packet.

9. In paragraph 8, The above indicator packet includes a least significant bit, a most significant bit, and storage bits positioned between the least significant bit and the most significant bit, The least significant bit of the above indicator packet has a value that is the inverted most significant bit of the data packet immediately preceding the above indicator packet, A data processing device, wherein the most significant bit of the above indicator packet has a value that is the inverted value of the least significant bit of the data packet immediately following the above indicator packet.

10. A data receiving unit that receives a plurality of data groups including an indicator packet and a plurality of data packets; and A decoder is included that restores the above data packet to the original data, The above decoder, An indicator packet storage unit for storing the above indicator packet; and A data driving device that restores the original data by inverting or non-inverting the least significant bit of the plurality of data packets according to the conversion information of the least significant bit of each data packet stored in the indicator packet.

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