Electronic device and control method therefor

Abstract

This electronic device comprises: a communication interface communicably connected to a wireless network; a memory for storing one or more instructions; and one or more processors communicably connected to the communication interface and the memory so as to control the electronic device. The one or more processors executes the one or more instructions to: identify a frame scan rate of a variable refresh rate (VRR) video signal; obtain a compressed video stream corresponding to the VRR video signal by inserting information about the identified frame scan rate into at least one of a tail region or a header region of a video stream; and control the communication interface to transmit the obtained compressed video stream to an external device through the wireless network.

Description

Electronic device and method of controlling the same

[0001] The present disclosure relates to an electronic device and a control method thereof, and more particularly, to an electronic device for processing VRR (Variable Refresh Rate) images and a control method thereof.

[0002] Advances in electronic technology have led to the development and proliferation of various types of electronic devices. In particular, the development and distribution of display devices (including but not limited to TVs and mobile devices) are rapidly progressing.

[0003] For example, a real-time video streaming service can be provided to a client using a variable refresh rate (VRR) video signal from a server, game console, etc. The client can receive the VRR video signal from a video processing device such as a set-top box or an OC (one connected) box and transmit it to a display device such as a TV and / or monitor (but not limited to).

[0004] One or more embodiments of the present disclosure provide an electronic device for processing VRR (Variable Refresh Rate) images and a method for controlling the same.

[0005] An electronic device according to one or more embodiments includes a communication interface communicatively connected to a wireless network, a memory storing one or more commands, and one or more processors communicatively connected to the communication interface and the memory to control the electronic device, wherein the one or more processors execute the one or more commands to identify a frame rate of a VRR (Variable Refresh Rate) video signal, insert information about the identified frame rate into at least one of a tail area or a header area of ​​a video stream, and obtain a compressed video stream corresponding to the VRR video signal, and transmit the obtained compressed video stream to an external device through the wireless network.

[0006] An electronic device according to one or more embodiments includes a communication interface communicatively connected to a wireless network, a memory storing one or more commands, and one or more processors communicatively connected to the communication interface and the memory to control the electronic device, wherein the one or more processors are configured to receive a compressed video stream corresponding to a variable refresh rate (VRR) video signal through the communication interface by executing the one or more commands, obtain frame refresh rate information included in at least one of a tail area or a header area of ​​the compressed video stream, and generate a first sync signal corresponding to a first video frame based on the obtained information on the frame refresh rate.

[0007] A method of controlling an electronic device according to one or more embodiments includes a step of identifying a frame refresh rate of a VRR (Variable Refresh Rate) video signal, a step of inserting information about the identified frame refresh rate into at least one of a tail area or a header area of ​​a video stream to obtain a compressed video stream corresponding to the VRR video signal, and a step of transmitting the compressed video stream to an external device through a wireless network.

[0008] A method of controlling an electronic device according to one or more embodiments comprises the steps of: receiving a compressed video stream corresponding to a VRR video signal via a wireless network; obtaining frame rate information included in at least one of a tail area or a header area of ​​the compressed video stream; and generating a first sync signal corresponding to a first video frame based on the obtained information about the frame rate.

[0009] Additional aspects may be partly described in the following description, and partly will be obvious from the description and / or may be learned by practice of the embodiments presented.

[0010] The above and other aspects, features and advantages of specific embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0011] FIG. 1 is a drawing for explaining an implementation example of an electronic system according to one embodiment of the present disclosure.

[0012] FIG. 2 is a block diagram showing the configuration of an electronic device (100) according to one or more embodiments.

[0013] FIG. 3 is a flowchart for explaining a method of controlling an electronic device (100) according to one or more embodiments.

[0014] FIG. 4 is a flowchart for explaining a method of controlling an electronic device (100) according to one or more embodiments.

[0015] FIG. 5A is a block diagram specifically illustrating the configuration of an electronic device (200) according to one or more embodiments.

[0016] FIG. 5b is a drawing for explaining a detailed configuration of an electronic device (200) according to one or more embodiments.

[0017] FIG. 6 is a flowchart for explaining a method of controlling an electronic device (200) according to one or more embodiments.

[0018] FIG. 7 is a flowchart for explaining a method of controlling an electronic device (200) according to one or more embodiments.

[0019] FIG. 8 is a diagram illustrating operations between a transmitting device and a receiving device according to one or more embodiments.

[0020] FIG. 9 is a diagram for explaining a Vsync signal processing method according to one or more embodiments.

[0021] FIG. 10 is a diagram for explaining a compressed video stream processing method of a transmitting device according to one or more embodiments.

[0022] FIG. 11 is a diagram for explaining a compressed video stream processing method of a receiving device according to one or more embodiments.

[0023] FIG. 12 is a drawing for detailing a Vsync restoration method according to one or more embodiments.

[0024] FIG. 13A is a diagram illustrating a method for restoring a Vsync signal based on information inserted into a tail area of ​​a stream according to one or more embodiments.

[0025] FIG. 13b is a diagram illustrating a method for restoring a Vsync signal based on information inserted into a header area of ​​a stream according to one or more embodiments.

[0026] The terms used in this specification are briefly described and various aspects of the present disclosure are described.

[0027] The terms used in the embodiments of this disclosure may vary depending on current widespread use, the emergence of new technologies, and other factors, taking into account the functions described herein. Furthermore, in certain cases, terms may be arbitrarily selected by the applicant, and their meanings will be described in detail in the relevant description of the disclosure. Therefore, the terms used in this disclosure should not be defined simply as names, but rather based on their meaning and the overall content of the disclosure.

[0028] In this disclosure, expressions such as “has,” “can have,” “includes,” or “may include” indicate the presence of a corresponding feature (e.g., a component such as a number, function, operation, or part), and do not exclude the presence of additional features.

[0029] In this disclosure, expressions such as “A or B,” “at least one of A and / or B,” or “one or more of A or / and B” can include all possible combinations of the listed items. For example, “A or B,” “at least one of A and B,” or “at least one of A or B” can all refer to cases where (1) only A is included, (2) only B is included, or (3) both A and B are included.

[0030] As used herein, the expressions “first,” “second,” “first,” or “second,” etc., may describe various components, regardless of order and / or importance, and are only used to distinguish one component from another, but do not limit the components.

[0031] When it is said that a component (e.g., a first component) is “operatively or communicatively coupled with / to” or “connected to” another component (e.g., a second component), it should be understood that the component may be directly coupled to the other component, or may be connected through another component (e.g., a third component).

[0032] The expression "configured to" as used in the present disclosure may be used interchangeably with, for example, "suitable for," "having the capacity to," "designed to," "adapted to," "made to," or "capable of." The term "configured to" may not necessarily mean only "specifically designed to" in terms of hardware.

[0033] In some contexts, the phrase "a device configured to" may mean that the device, in conjunction with other devices or components, is "capable of" performing A, B, and C. For example, the phrase "a processor configured (or set) to perform A, B, and C" may refer to a dedicated processor (e.g., an embedded processor) for performing those operations, or a general-purpose processor (e.g., a CPU or application processor) that can perform those operations by executing one or more software programs stored in a memory device.

[0034] Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, terms such as "comprise" or "consist of" are intended to indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but should be understood not to preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0035] In the embodiments, a "module" or "part" performs at least one function or operation and may be implemented as hardware or software, or as a combination of hardware and software. Furthermore, a plurality of "modules" or "parts" may be integrated into at least one module and implemented as at least one processor (not shown), excluding any "module" or "part" that needs to be implemented as specific hardware.

[0036] Meanwhile, the various elements and areas in the drawings are schematically drawn. Therefore, the technical concept of the present invention is not limited by the relative sizes and / or spacing drawn in the attached drawings.

[0037] An embodiment of the present disclosure will be described in more detail with reference to the attached drawings below.

[0038] Throughout this disclosure, references to "one embodiment," "an embodiment," "an exemplary embodiment," or similar language may indicate that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present solution. Thus, throughout this disclosure, the phrases "in one embodiment," "in an embodiment," "in an exemplary embodiment," and similar language may all refer to the same embodiment, but do not necessarily. The embodiments described herein are merely exemplary embodiments, and the present invention is not limited thereto and may be implemented in various forms.

[0039] It should be understood that the specific order or hierarchy of blocks in the disclosed process / flow diagram is merely an example of an exemplary approach. It should be understood that the specific order or hierarchy of blocks in the process / flow diagram may be rearranged according to design preference. Furthermore, some blocks may be combined or omitted. The appended claims present elements of various blocks in a sample order and are not intended to be limited to the specific order or hierarchy presented.

[0040] Embodiments of the present specification may be described and illustrated in terms of blocks that perform the described function or functions as illustrated in the drawings. These blocks, which may be referred to herein as units or modules, or may also be referred to as devices, logic, circuits, controllers, counters, comparators, generators, converters, etc., may be physically implemented by analog and / or digital circuits that include one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc.

[0041] In this disclosure, the articles "a" and "an" are intended to include one or more items, and can be used interchangeably with "one or more." If only one item is intended, the term "a" or similar language may be used. For example, the term "processor" can refer to a single processor or multiple processors. When a processor is described as performing an operation and the processor is also referred to as performing additional operations, the multiple operations can be performed by either a single processor or multiple processors, or a combination of both.

[0042] FIG. 1 is a drawing for explaining an implementation example of an electronic system according to one embodiment of the present disclosure.

[0043] According to FIG. 1, the electronic system may include a transmitting device (100), a receiving device (200), and a source device (300).

[0044] The source device (300) is a device that provides content or includes such a device, and can be implemented as a server, a game console, a personal computer (PC), etc. As an example, the transmission device (100) can provide a real-time video streaming service, and the real-time video streaming service can include a live broadcasting service, a cloud game service, a mirroring service, a video communication service, etc.

[0045] The transmitting device (100) can be implemented as a set-top box or an oc (one connected) box as shown in FIG. 1, but is not limited thereto, and can be applied to any device having image processing and communication functions.

[0046] The receiving device (200) can be implemented as a TV as shown in FIG. 1, but is not limited thereto, and can be applied to any device having communication and display functions, such as a monitor, a smart phone, a tablet PC, a notebook PC, a HMD (Head mounted Display), a NED (Near Eye Display), a LFD (large format display), a digital signage, a DID (Digital Information Display), a video wall, a projector display, etc.

[0047] The receiving device (200) can receive various compressed images and / or images of various resolutions. For example, the receiving device (200) can receive images in a compressed form such as MPEG (Moving Picture Experts Group) (e.g., MPEG-1 Audio Layer II (MP2), MPEG-4 Part 14 (MP4), multimedia content description interface (MP7), etc.), JPEG (joint photographic coding experts group), AVC (Advanced Video Coding), H.264, H.265, HEVC (High Efficiency Video Codec), etc. Alternatively or additionally, the electronic device (100) can receive any one of SD (Standard Definition), HD (High Definition), Full HD, Ultra HD, or higher resolution images.

[0048] For example, content provided from a source device (300) may include a VRR (Variable Refresh Rate) image or / and the image. In this case, the source device (300) outputs a VRR image signal using a Vsync (vertical synchronization) function at a frame rate that varies depending on the image processing speed (e.g., the image processing speed of a GPU (graphics processing unit)).

[0049] According to an example, the source device (300) and the transmitting device (100) can be connected to each other via wired communication to perform communication. For example, a VRR video signal can be transmitted from the source device (300) to the transmitting device (100) via wired communication, and in this case, the transmitting device (100) can receive Vsync corresponding to the VRR video signal from the source device (300) via wired communication.

[0050] According to an example, a transmitting device (100) and a receiving device (200) can communicate via a wireless network. For example, the transmitting device (100) can compress a VRR video signal received from a source device (300), insert necessary information into a header, and transmit it to the receiving device (200) via a wireless network. In this case, there is a problem that timing synchronization is difficult because a vertical synchronization signal (Vsync signal) is not transmitted from the transmitting device (100) to the source device (300) as the compressed video stream is transmitted via the wireless network.

[0051] Accordingly, in the following, various embodiments that can transmit information about Vsync for timing synchronization between a transmitter and a receiver when transmitting a VRR video signal through a wireless network will be described.

[0052] FIG. 2 is a block diagram showing the configuration of an electronic device (100) according to one or more embodiments.

[0053] According to an example, the electronic device (100) may be implemented as a transmitting device (100) illustrated in FIG. 1. For example, the electronic device (100) may be implemented as a set-top box or an oc (one connected) box, but is not limited thereto, and may be applied to any device having image processing and communication functions.

[0054] According to FIG. 2, the electronic device (100) includes a communication interface (110), a memory (120), and one or more processors (130).

[0055] It goes without saying that the communication interface (110) can be implemented as various interfaces depending on the implementation example of the electronic device (100). For example, the communication interface (110) can support wireless communication such as Bluetooth, Zigbee, wireless LAN (Local Area Network) (e.g., access point (AP)-based wireless network, Institute of Electrical and Electronics Engineers (IEEE) 802.11 (Wireless-Fidelity or Wi-Fi)), WAN (Wide Area Network), etc. However, it is not limited thereto, and wired communication such as Ethernet, HDMI (High-Definition Multimedia Interface), USB (Universal Serial Bus), MHL (Mobile High-Definition Link), AES / EBU (Audio Engineering Society / European Broadcasting Union), optical, coaxial, etc. can also be supported. For example, the communication interface (110) may communicate with other electronic devices, external servers, and / or remote control devices.

[0056] The memory (120) can store data required for implementation and / or operation of various embodiments. The memory (120) may be implemented in the form of memory embedded in the electronic device (100) or in the form of memory that can be detachably attached to the electronic device (100) depending on the purpose of data storage. For example, data for operating the electronic device (100) may be stored in a memory embedded in the electronic device (100), and data for expanding the functions of the electronic device (100) may be stored in a memory that can be detachably attached to the electronic device (100). Meanwhile, in the case of memory embedded in the electronic device (100), it may be implemented as at least one of volatile memory (e.g., dynamic RAM (DRAM), static RAM (SRAM), or synchronous dynamic RAM (SDRAM)), non-volatile memory (e.g., one time programmable ROM (OTPROM), programmable ROM (PROM), erasable and programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), mask ROM, flash ROM, flash memory (e.g., NAND flash or NOR flash), hard drive, or solid state drive (SSD). In addition, in the case of memory that can be attached or detached to the electronic device (100'), it may be implemented as at least one of memory cards (e.g., compact flash (CF), secure digital (SD), micro secure digital (Micro-SD), mini secure digital (Mini-SD), extreme digital (xD), multi-media card (MMC), etc.), external memory that can be connected to a USB port (e.g., USB memory), etc. It can be implemented in the form of.

[0057] One or more processors (130) control the overall operation of the electronic device (100). Specifically, one or more processors (130) may be connected to each component of the electronic device (100) to control the overall operation of the electronic device (100). For example, one or more processors (130) may be electrically connected to a communication interface (110) and a memory (120) to control the overall operation of the electronic device (100). The processor (130) may be composed of one or more processors.

[0058] One or more processors (130) may perform operations of the electronic device (100) according to various embodiments by executing at least one instruction stored in the memory (120).

[0059] The one or more processors (130) may include one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), an Accelerated Processing Unit (APU), a Many Integrated Core (MIC), a Digital Signal Processor (DSP), a Neural Processing Unit (NPU), a hardware accelerator, or a machine learning accelerator. The one or more processors (130) may control one or any combination of other components of the electronic device, and may perform operations related to communication or data processing. The one or more processors (130) may execute one or more programs or instructions stored in a memory. For example, the one or more processors may perform a method according to one or more embodiments of the present disclosure by executing one or more instructions stored in a memory.

[0060] When a method according to one or more embodiments of the present disclosure includes multiple operations, the multiple operations may be performed by one processor or by multiple processors. For example, when a first operation, a second operation, and a third operation are performed by a method according to one or more embodiments, the first operation, the second operation, and the third operation may all be performed by the first processor, or the first operation and the second operation may be performed by the first processor (e.g., a general-purpose processor) and the third operation may be performed by the second processor (e.g., an artificial intelligence-specific processor).

[0061] One or more processors (130) may be implemented as a single core processor including one core, or may be implemented as one or more multicore processors including multiple cores (e.g., homogeneous multicores or heterogeneous multicores). When one or more processors (130) are implemented as a multicore processor, each of the multiple cores included in the multicore processor may include an internal processor memory, such as a cache memory or an on-chip memory, and a common cache shared by the multiple cores may be included in the multicore processor. In addition, each of the multiple cores (or some of the multiple cores) included in the multicore processor may independently read and execute a program instruction for implementing a method according to one or more embodiments of the present disclosure, or all (or some) of the multiple cores may be linked to read and execute a program instruction for implementing a method according to one or more embodiments of the present disclosure.

[0062] When a method according to one or more embodiments of the present disclosure includes a plurality of operations, the plurality of operations may be performed by one core among the plurality of cores included in a multi-core processor, or may be performed by the plurality of cores. For example, when a first operation, a second operation, and a third operation are performed by a method according to one or more embodiments, the first operation, the second operation, and the third operation may all be performed by a first core included in the multi-core processor, or the first operation and the second operation may be performed by a first core included in the multi-core processor, and the third operation may be performed by a second core included in the multi-core processor.

[0063] In the embodiments of the present disclosure, a processor may mean a system on a chip (SoC) in which one or more processors and other electronic components are integrated, a single-core processor, a multi-core processor, or a core included in a single-core processor or a multi-core processor, wherein the core may be implemented as a CPU, a GPU, an APU, a MIC, a DSP, an NPU, a hardware accelerator, or a machine learning accelerator, but the embodiments of the present disclosure are not limited thereto. Hereinafter, for the convenience of explanation, one or more processors (130) will be referred to as a processor (130).

[0064] According to one embodiment, the processor (130) can identify a frame refresh rate of a VRR (Variable Refresh Rate) video signal. For example, the VRR video signal may be a video signal transmitted from the source device (300) illustrated in FIG. 1. For example, since the source device (300) and the electronic device (100) are connected by a wire, the frame refresh rate can be identified by receiving a sync signal, for example, a Vsync signal, from the source device (300). Here, the frame refresh rate refers to the monitor refresh rate, and is also called a vertical frequency or screen refresh rate. The unit of the refresh rate is expressed in hertz (hz), and hertz may mean how many screens (= frames) are displayed in 1 second. The frame rate of the GPU is referred to as a refresh rate or screen refresh rate. The unit of the frame rate is expressed in FPS (Frame Per Second), and FPS may mean how many frames (= screens) are created in 1 second.

[0065] A VRR (Variable Refresh Rate) video signal is a video whose frame rate varies depending on the video processing speed of the GPU, and the processor (130) can identify the frame refresh rate of the VRR video signal using the Vsync function.

[0066] Next, the processor (130) can insert information about the identified frame rate into at least one of a tail area or a header area of ​​the video stream to obtain a compressed video stream corresponding to the VRR video signal. For example, the processor (130) can generate a compressed video stream corresponding to the VRR video signal based on a compression method such as MPEG (Moving Picture Experts Group) (e.g., MP2, MP4, MP7, etc.), JPEG (joint photographic coding experts group), AVC (Advanced Video Coding), H.264, H.265, HEVC (High Efficiency Video Codec), etc.

[0067] The processor (130) may generate a compression packet corresponding to each video frame and include video information corresponding to each video frame in the header of each compression packet. For example, the video information may include information such as video size and compression ratio.

[0068] Additionally, the processor (130) may include VRR information in the header or tail area of ​​the compressed packet. For example, the VRR information may be frame refresh rate information. For example, the frame refresh rate information may be the interval between Vsync signals.

[0069] According to one example, the processor (130) may insert frame rate information of the first video frame into the tail area of ​​the first compressed video packet corresponding to the first video frame. For example, the processor (130) may insert interval information between the first Vsync signal corresponding to the first video frame and the second Vsync signal corresponding to the second video frame, which is the next video frame, into the tail area of ​​the first compressed video packet corresponding to the first video frame.

[0070] Additionally, the processor (130) may insert frame rate information of the first image frame into the header area of ​​the second compressed image packet corresponding to the second image frame, which is the next frame of the first image frame. For example, the processor (130) may insert interval information between the first Vsync signal corresponding to the first image frame and the second Vsync signal corresponding to the second image frame, which is the next image frame, into the header area of ​​the second compressed image packet.

[0071] For example, the processor (130) may operate a clock counter based on a Vsync signal of a first image frame included in a VRR image signal. In addition, the processor (130) may identify a frame refresh rate of the first image frame based on a counting value of the clock counter. In addition, the processor (130) may insert frame refresh rate information of the first image frame into a tail area of ​​a first compressed image packet, or insert frame refresh rate information of the first image frame into a header area of ​​a second compressed image packet.

[0072] Next, the processor (130) can control the communication interface (110) to transmit the acquired compressed image stream to an external device via a wireless network.

[0073] FIG. 3 is a flowchart for explaining a method of controlling an electronic device (100) according to one or more embodiments.

[0074] According to FIG. 3, the electronic device (100) can identify the frame refresh rate of the VRR video signal (S310). For example, the VRR video signal may be a video signal transmitted from the source device (300) to the electronic device (100). For example, since the source device (300) and the electronic device (100) are connected by a wire, the frame refresh rate can be identified by receiving a sync signal, for example, a Vsync signal, from the source device (300). The Vsync signal includes a signal or / and the corresponding signal used to match the starting point of scanning one field on the transmitting side and the receiving side, and can transmit a pulse signal of the opposite polarity to the video signal in the vertical erase section of the video signal.

[0075] The electronic device (100) can obtain a compressed video stream corresponding to a VRR video signal by inserting information about the identified frame injection rate into at least one of a tail area or a header area of ​​the video stream (S320).

[0076] The electronic device (100) can transmit the acquired compressed image stream to an external device via a wireless network (S330).

[0077] In Fig. 3, the order is mapped for all steps for convenience of explanation, but it is of course not necessarily limited to the order of steps that are not related to the order or can be performed in parallel.

[0078] FIG. 4 is a flowchart for explaining a method of controlling an electronic device (100) according to one or more embodiments.

[0079] According to FIG. 4, the electronic device (100) can receive a VRR video signal from an external source device via wired communication (S410). However, in some cases, the electronic device (100) can receive a VRR video signal from an external source via wireless communication.

[0080] The electronic device (100) can identify the frame rate of the VRR video signal (S420). For example, when receiving a VRR video signal from an external source device via wired communication, the electronic device can also receive a frame-by-frame Vsync signal included in the VRR video signal.

[0081] The electronic device (100) can insert frame rate information of the first frame into the tail area of ​​the first compressed video packet corresponding to the first video frame, or insert frame rate information of the first video frame into the header area of ​​the second compressed video packet corresponding to the second video frame, which is the next frame of the first video frame (S430).

[0082] The electronic device (100) can obtain a compressed video stream corresponding to the VRR video signal (S440).

[0083] The electronic device (100) can transmit the acquired compressed image stream to an external device via a wireless network (S450).

[0084] In Fig. 4, the order is mapped for all steps for convenience of explanation, but it is of course not necessarily limited to the order of steps that are not related to the order or can be performed in parallel.

[0085] FIG. 5A is a block diagram specifically illustrating the configuration of an electronic device (200) according to one or more embodiments.

[0086] According to an example, the electronic device (200) can be implemented as the receiving device (200) illustrated in FIG. 1. For example, the electronic device (200) can be implemented as a TV, but is not limited thereto, and can be applied to any device having communication and display functions, such as a monitor, a smart phone, a tablet PC, a notebook PC, a head mounted display (HMD), a near eye display (NED), a large format display (LFD), a digital signage, a digital information display (DID), a video wall, a projector display, etc.

[0087] According to FIG. 5A, the electronic device (200) includes a communication interface (210), a memory (220), and one or more processors (230). Implementation examples of the communication interface (210), the memory (220), and the one or more processors (230) are identical / similar to the communication interface (110), the memory (120), and the one or more processors (130) illustrated in FIG. 2, and may include additional functions not mentioned above. Therefore, the description of the electronic device (200) and its components described above with reference to FIG. 2 may be omitted for convenience.

[0088] According to one embodiment, when a compressed video stream corresponding to a VRR video signal is received through the communication interface (210), the processor (230) may obtain frame rate information included in at least one of a tail area or a header area of ​​the compressed video stream.

[0089] The processor (230) can generate a sync signal corresponding to the image frame based on information about the acquired frame injection rate.

[0090] For example, when a compressed video stream is received, the processor (230) may generate an initial sync signal and operate a clock counter. A clock counter is a component (or device) that counts the number of clock pulses while circulating a predetermined state transition sequence. Operating the clock counter may be an operation of resetting the clock counter to start counting, and may count the number of clock pulses according to an upward counting method. For example, the clock counter may include one or more of a binary counter, a ring counter, a Johnson counter, and a Gray code counter, which are distinguished according to the form of an output code.

[0091] According to an example, when the processor (230) obtains frame rate information of a first image frame included in a tail area of ​​a compressed image stream, the processor (230) can generate a sync signal corresponding to a second image frame, which is a frame following the first image frame, based on the counting value of the clock counter and the frame rate information of the first image frame.

[0092] For example, the processor (230) may obtain frame rate information included in a tail area of ​​each of a plurality of compressed video packets included in a compressed video stream. In this example, the tail area of ​​each of the plurality of compressed video packets may include frame rate information of a video frame corresponding to each of the plurality of compressed video packets.

[0093] For example, when the processor (230) obtains frame rate information of the first image frame included in the header area of ​​the compressed image stream, the processor (230) may generate a sync signal corresponding to the first image frame based on the counting value of the clock counter and information about the frame rate for the first image frame.

[0094] For example, the processor (230) may obtain frame rate information included in the header area of ​​each of the plurality of compressed video packets included in the compressed video stream. In this example, the header area of ​​each of the plurality of compressed video packets may include frame rate information of the previous frame of the video frame corresponding to each of the plurality of compressed video packets.

[0095] FIG. 5b is a drawing for explaining a detailed configuration of an electronic device (200) according to one or more embodiments.

[0096] According to FIG. 5b, the electronic device (200') may include a communication interface (210), a memory (220), one or more processors (230), a display (240), a user interface (250), a camera (260), a speaker (270), and a sensor (280). Among the configurations illustrated in FIG. 5b, a detailed description of configurations that overlap with those illustrated in FIG. 5a will be omitted.

[0097] The display (240) may be implemented as a display including a self-luminous element or a display including a non-luminous element and a backlight. For example, it may be implemented as various types of displays such as an LCD (Liquid Crystal Display), an OLED (Organic Light Emitting Diodes) display, an LED (Light Emitting Diodes), a micro LED, a Mini LED, a PDP (Plasma Display Panel), a QD (Quantum dot) display, a QLED (Quantum dot light-emitting diodes), etc. The display (240) may also include a driving circuit, a backlight unit, etc., which may be implemented in a form such as an a-si TFT, an LTPS (low temperature poly silicon) TFT, an OTFT (organic TFT), etc. According to an example, a touch sensor that detects a touch operation in the form of a touch film, a touch sheet, a touch pad, etc. may be disposed on the front of the display (240) so as to be implemented so as to detect various types of touch inputs. For example, the display (240) can detect various types of touch inputs, such as a touch input by a user's hand, a touch input by an input device such as a stylus pen, and a touch input by a specific electrostatic material. Here, the input device can be implemented as a pen-type input device that can be referred to by various terms such as an electronic pen, a stylus pen, an S-pen, etc. According to an example, the display (240) can be implemented as a flat display, a curved display, a flexible display that can be folded or / and rolled, etc. According to an example, the processor (230) can display an acquired output image through the display (240).

[0098] For example, the processor (230) may control the display (240) to output a video frame based on a video signal restored from a compressed video stream and a sync signal corresponding to the video frame. For example, the processor (230) may generate a Vsync signal based on an identified frame refresh rate and output a video frame based on the generated Vsync signal.

[0099] The user interface (250) may be implemented as a device such as a button, a touch pad, a mouse, and a keyboard, or as a touch screen that can also perform the display function and operation input function described above.

[0100] The camera (260) can be turned on and take pictures according to a preset event. The camera (260) can convert the captured image into an electrical signal and generate image data based on the converted signal. For example, the subject can be converted into an electrical image signal through a semiconductor optical element (CCD; Charge Coupled Device), and the converted image signal can be amplified and converted into a digital signal and then signal processed. For example, the camera (120) can be implemented as a general camera, a stereo camera, a depth camera, etc.

[0101] The speaker (270) may be configured and / or include components that output various audio data as well as various notification sounds or voice messages. The processor (230) may control the speaker (270) to output feedback or various notifications in audio format according to various embodiments of the present disclosure.

[0102] The sensor (280) may include various types of sensors and / or the like, such as a touch sensor, a proximity sensor, an acceleration sensor (or a gravity sensor), a geomagnetic sensor, a gyro sensor, a pressure sensor, a position sensor, a distance sensor, an illuminance sensor, etc.

[0103] In addition, the electronic device (200') is not limited to the configuration illustrated in FIG. 5b, and may include a microphone (not shown), a tuner (not shown), and a demodulator (not shown) depending on implementation examples and / or design constraints.

[0104] For example, a microphone (not shown) may be configured and / or include a device for receiving user voice or other sounds and converting them into audio data. However, according to another embodiment, the electronic device (200') may receive user voice input via an external device through a communication interface (210).

[0105] As another example, a tuner (not shown) can receive RF broadcast signals by tuning to a channel selected by a user or all previously stored channels among RF broadcast signals received through an antenna.

[0106] As another example, a demodulator (not shown) may receive a digital IF signal (DIF) converted from a tuner, demodulate it, and perform channel decoding, etc.

[0107] FIG. 6 is a flowchart for explaining a method of controlling an electronic device (200) according to one or more embodiments.

[0108] According to FIG. 6, the electronic device (200) can receive a compressed video stream corresponding to a VRR video signal via a wireless network (S610). For example, the electronic device (200) can receive a compressed video stream from an electronic device (100), for example, the transmitting device (100) of FIG. 1.

[0109] Next, the electronic device (200) can obtain frame rate information included in at least one of the tail area or header area of ​​the compressed video stream (S620). For example, the electronic device (200) can obtain a plurality of compressed video packets from the compressed video stream and obtain frame rate information included in at least one of the tail area or header area of ​​each of the plurality of compressed video packets.

[0110] Next, the electronic device (200) can generate a sync signal corresponding to the video frame based on the acquired frame refresh rate information (S630). For example, the electronic device (200) can generate the following Vsync signal based on the frame refresh rate.

[0111] Meanwhile, in Fig. 6, the order is mapped for all steps for convenience of explanation, but it is of course not necessarily limited to the order of steps that are not related to the order or can be performed in parallel.

[0112] FIG. 7 is a flowchart for explaining a method of controlling an electronic device (200) according to one or more embodiments.

[0113] According to FIG. 7, the electronic device (200) can receive a compressed video stream corresponding to a VRR video signal via a wireless network (S710).

[0114] Next, the electronic device (200) can generate an initial sync signal and operate a clock counter (S720).

[0115] When the electronic device (200) obtains frame rate information of the first image frame included in the tail area of ​​the compressed image stream (S730:Y), the electronic device (200) can generate a sync signal corresponding to the second image frame, which is the next frame of the first image frame, based on the counting value of the clock counter and the frame rate information of the first image frame (S740).

[0116] In one example, the electronic device (200) may obtain frame rate information included in the tail area of ​​each of a plurality of compressed video packets included in a compressed video stream. For example, the tail area of ​​each of the plurality of compressed video packets may include frame rate information of a video frame corresponding to each of the plurality of compressed video packets.

[0117] Alternatively or additionally, when the electronic device (200) obtains frame rate information of the first image frame included in the header area of ​​the compressed image stream (S750:Y), the electronic device can generate a sync signal corresponding to the first image frame based on the counting value of the clock counter and information about the frame rate for the first image frame.

[0118] According to an example, the electronic device (200) may obtain frame rate information included in the header area of ​​each of a plurality of compressed video packets included in a compressed video stream. For example, the header area of ​​each of the plurality of compressed video packets may include frame rate information of a previous frame of a video frame corresponding to each of the plurality of compressed video packets.

[0119] Meanwhile, in Fig. 7, the order is mapped for all steps for convenience of explanation, but it is of course not necessarily limited to the order of steps that are not related to the order or can be performed in parallel.

[0120] FIG. 8 is a diagram illustrating operations between a transmitting device and a receiving device according to one or more embodiments.

[0121] According to FIG. 8, a transmitting device (810) and a receiving device (820) can communicate via a wireless network. In one example, the transmitting device (810) can be implemented as an electronic device (100) illustrated in FIG. 2 and / or a device substantially similar thereto, and the receiving device (820) can be implemented as an electronic device (200, 200') illustrated in FIGS. 5A and 5B and / or a device similar thereto.

[0122] According to one example, the transmitting device (810) may include an image receiving module (811) and an image compression module (812). Each module may be implemented with at least one software, at least one hardware, and / or a combination thereof. For example, at least one of the image receiving module (811) and the image compression module (812) may be implemented to utilize a predefined algorithm, a predefined formula, and / or a learned artificial intelligence model. The image receiving module (811) and the image compression module (812) may be included within the electronic device (100), but may be distributed to at least one external device according to one example.

[0123] According to an example, the transmitting device (810) can receive a video signal from a source device (Fig. 1, 300) using the video receiving module (811). For example, the transmitting device (810) can receive a VRR video signal from the source device (300) via a wire. In this case, the transmitting device (810) can receive a Vsync corresponding to the VRR video signal from the source device (300) via a wire.

[0124] According to an example, the transmitting device (810) can compress the received video signal using the video compression module (812). For example, the transmitting device (810) can process (812-1) VRR information obtained based on the VRR video signal received from the source device (300), and compress (812-2) the video by inserting the video information and VRR information to generate a compressed video stream. For example, the video information can include information such as the video size, compression ratio, etc. For example, the VRR information can include Vsync interval information. For example, the transmitting device (810) can compress the video using a standard codec such as H.264 / 265, VP8 / 9, or AV1.

[0125] After this, the transmitting device (810) can transmit the compressed video stream to the receiving device (820) via a wireless network.

[0126] According to one example, the receiving device (820) may include an image restoration module (821) and an image output module (822). Here, each module may be implemented with at least one software, at least one hardware, and / or a combination thereof. For example, at least one of the image restoration module (821) and the output module (822) may be implemented to utilize a predefined algorithm, a predefined formula, and / or a learned artificial intelligence model. The image restoration module (821) and the image output module (822) may be included within the electronic device (100), but may be distributed to at least one external device according to one example.

[0127] According to an example, the receiving device (820) can restore (or decode) the compressed video stream received from the transmitting device (810) using the video restoration module (821). For example, the receiving device (820) can restore (821-1, 821-2) a Vsync signal and an image from the compressed video stream using the video restoration module (821). For example, the receiving device (820) can restore (821-1) a Vsync signal based on VRR information included in at least one of a header area or a tail area of ​​the compressed video stream. For example, the receiving device (820) can restore (821-2) an image based on image information included in a header area of ​​the compressed video stream.

[0128] For example, the receiving device (820) can store a compressed video stream transmitted in real time from the transmitting device (810) in a stream buffer (or receiving buffer) and restore the compressed video stream using the video restoration module (821). For example, the video restoration module (821) can be implemented as a decoder, and the decoder can be implemented in the form of a type of DSP (digital signal processor).

[0129] For example, the receiving device (820) may output a restored image based on a Vsync signal using the image output module (822). For example, the receiving device (820) may obtain a Vsync signal corresponding to each frame based on VRR information included in each compressed image packet included in a compressed image stream, and output a VRR frame based on the obtained Vsync signal.

[0130] FIG. 9 is a diagram for explaining a Vsync signal processing method according to one or more embodiments.

[0131] According to FIG. 9, the electronic device (100) can generate a compressed video stream based on a VRR video stream received from a source device (300) and transmit the generated compressed video stream to the electronic device (200). Hereinafter, for convenience of explanation, the electronic device (100) will be referred to as a transmitting device (100), and the electronic device (200) will be referred to as a receiving device (200).

[0132] The transmitting device (100) may obtain VRR information based on a Vsync signal corresponding to each frame included in a VRR video stream received from the source device (300), and generate a compressed video stream based on the VRR information and the video information. For example, the VRR information may include frame refresh rate information. For example, the frame refresh rate information may be an interval between Vsync signals. For example, the video information may include information such as a video size and a compression rate.

[0133] For example, the transmitting device (100) may generate a compressed video stream by inserting VRR information into a compressed video packet corresponding to each video frame. For example, the transmitting device (100) may insert VRR information into the header area or tail area of ​​each compressed video packet. However, for convenience of explanation, in FIG. 9, the case where VRR information is inserted into the tail area of ​​each compressed video packet is assumed and explained.

[0134] According to FIG. 9, the transmitting device (100) can insert frame refresh rate information (e.g., 120 Hz) of the first frame Frame (0) into the tail area of ​​the compressed video packet of the first frame Frame (0) corresponding to the first frame Frame (0). For example, the transmitting device (100) can insert interval information between the first Vsync signal corresponding to the first frame Frame (0) and the second Vsync signal corresponding to the second frame Frame (1), which is the next video frame, into the tail area of ​​the compressed video packet of the first frame Frame (0). In addition, the transmitting device (100) can insert frame refresh rate information (e.g., 120 Hz) of the second frame Frame (1) into the tail area of ​​the compressed video packet of the second frame Frame (1) corresponding to the second frame Frame (1). For example, the transmitting device (100) can insert interval information between a second Vsync signal corresponding to the second frame Frame (1) and a third Vsync signal corresponding to the third frame Frame (2), which is the next video frame, in the tail area of ​​the compressed video packet of the second frame Frame (1). In addition, the transmitting device (100) can insert frame scan rate information (e.g., 60 Hz) of the third frame Frame (2) into the tail area of ​​the compressed video packet of the third frame Frame (2). For example, the transmitting device (100) can insert interval information between a third Vsync signal corresponding to the third frame Frame (2) and a fourth Vsync signal corresponding to the fourth frame Frame (3), which is the next video frame, in the tail area of ​​the compressed video packet of the third frame Frame (2).

[0135] When a compressed video stream is received from a transmitting device (100), the receiving device (200) can restore a Vsync signal based on VRR information included in the compressed video stream and output a VRR video frame based on the Vsync signal.

[0136] For example, the receiving device (200) may obtain VRR information inserted into the tail area of ​​each compressed video packet and restore a Vsync signal corresponding to each video frame based on the obtained VRR information. In addition, the receiving device (200) may output each video frame based on the Vsync signal corresponding to each video frame.

[0137] According to FIG. 9, the receiving device (200) can obtain frame refresh rate information (e.g., 120 Hz) of the first frame Frame (0) included in the tail area of ​​the compressed video packet of the first frame Frame (0) corresponding to the first frame Frame (0). In this case, the receiving device (200) can generate a second Vsync signal of the second frame Frame (1), which is the next video frame, based on the frame refresh rate information (e.g., 120 Hz) of the first frame Frame (0), and output the second frame Frame (1). For example, the receiving device (200) can identify the output time of the second Vsync signal corresponding to the second frame Frame (1) by counting the time corresponding to 120 Hz from the time when the first Vsync signal is output after arbitrarily outputting the first Vsync signal, which is the first Vsync signal.

[0138] Next, the receiving device (200) can obtain frame refresh rate information (e.g., 120 Hz) of the second frame Frame (1) included in the tail area of ​​the compressed video packet of the second frame Frame (1) corresponding to the second frame Frame (1). In this case, the receiving device (200) can generate a third Vsync signal corresponding to the third frame Frame (2), which is the next video frame, based on the frame refresh rate information (e.g., 120 Hz) of the second frame Frame (1), and output the third frame Frame (2). For example, the receiving device (200) can identify the output time of the third Vsync signal corresponding to the third frame Frame (2) by counting the time corresponding to 120 Hz from the time when the second Vsync signal corresponding to the second frame Frame (1) is output.

[0139] Next, the receiving device (200) can obtain frame refresh rate information (e.g., 60 Hz) of the third frame Frame (2) included in the tail area of ​​the third frame Frame (2) compressed video packet corresponding to the third frame Frame (2). In this case, the receiving device (200) can generate a fourth Vsync signal corresponding to the fourth frame Frame (3), which is the next video frame, based on the frame refresh rate information (e.g., 60 Hz) of the third frame Frame (2), and output the fourth frame Frame (3). For example, the receiving device (200) can identify the output time of the fourth Vsync signal corresponding to the fourth frame Frame (3) by counting the time corresponding to 60 Hz from the time when the third Vsync signal corresponding to the third frame Frame (2) is output.

[0140] FIG. 10 is a diagram for explaining a compressed video stream processing method of a transmitting device according to one or more embodiments.

[0141] According to FIG. 10, the transmitting device (100) can generate a compressed video stream including compression information based on a video signal received from the source device (300) (S1010). For example, the transmitting device (100) can receive a video signal from the source device (300) via a wire. For example, the compression information can include video information such as the video size and compression ratio.

[0142] The transmitting device (100) can generate VRR information corresponding to the compressed video stream (S1020). For example, the transmitting device (100) can generate VRR information based on a Vsync signal included in an input video signal. For example, the VRR information can include frame refresh rate information. For example, the transmitting device (100) can obtain frame refresh rate information corresponding to each frame by counting the interval between Vsync signals received from the transmitting device (300).

[0143] For example, the transmitting device (100) can operate a clock counter based on a first Vsync signal included in a VRR video signal and obtain first frame refresh rate information corresponding to the first video frame based on the counted value until the second Vsync signal is received. For example, if the counted value from the time when the first Vsync signal is received until the second Vsync signal is received is 1 / 120 s (e.g., about 8.33 milliseconds), first frame refresh rate information of 120 Hz can be obtained. Then, when the second Vsync signal is received, the transmitting device (100) can reset and initialize the clock counter and obtain second frame refresh rate information corresponding to the second video frame based on the counted value until the third Vsync signal is received. For example, if the counted value from the time the second Vsync signal is received until the third Vsync signal is received is 1 / 120s, second frame refresh rate information of 120Hz can be obtained. Then, when the third Vsync signal is received, the transmitting device (100) can reset and initialize the clock counter and obtain third frame refresh rate information corresponding to the third image frame based on the counted value until the fourth Vsync signal is received. For example, if the counted value from the time the third Vsync signal is received until the fourth Vsync signal is received is 1 / 60s, third frame refresh rate information of 60Hz can be obtained.

[0144] The transmitting device (100) can insert VRR information into a compressed video stream (S1030). For example, the transmitting device (100) can insert first frame scan rate information corresponding to a first video frame into a tail area of ​​a first video compression packet corresponding to the first video frame. In addition, the transmitting device (100) can insert second frame scan rate information corresponding to a second video frame into a tail area of ​​a second video compression packet corresponding to the second video frame. In addition, the transmitting device (100) can insert third frame scan rate information corresponding to a third video frame into a tail area of ​​a third video compression packet corresponding to the third video frame.

[0145] The transmitting device (100) can transmit a compressed video stream to the receiving device (200) via a wireless network. For example, the transmitting device (100) can transmit a compressed video stream including a first compressed video packet, a second compressed video packet, a third compressed video packet, and so on, to the receiving device (200) via a wireless network.

[0146] Meanwhile, in Fig. 10, the order is mapped for all steps for convenience of explanation, but it is of course not necessarily limited to the order of steps that are not related to the order or can be performed in parallel.

[0147] FIG. 11 is a diagram for explaining a compressed video stream processing method of a receiving device according to one or more embodiments.

[0148] According to FIG. 11, the receiving device (200) can receive a compressed video stream from the transmitting device (100) via a wireless network (S1110). For example, the compressed video stream can include a plurality of compressed video packets compressed on a frame-by-frame basis.

[0149] Next, the receiving device (200) can extract compression information and VRR information from the stream header (S1120). For example, the compression information may include video information such as video size and compression ratio. For example, the VRR information may include frame refresh rate information. In one example, the compression information may be included in the header area of ​​each compressed video packet. For example, the VRR information may be included in the header area or tail area of ​​each compressed video packet.

[0150] Next, the receiving device (200) can restore the compressed image based on the compression information (S1130) and restore the output Vsync signal based on the VRR information (S1140). For example, the receiving device (200) can decode the compressed image packet based on image information such as the image size, compression ratio, etc. For example, the receiving device (200) can restore the output Vsync signal based on the frame scan rate information, for example, the interval information between Vsync signals.

[0151] For example, the receiving device (200) can arbitrarily output a first Vsync signal and operate a clock counter. If the first frame refresh rate information included in the first compressed video packet is acquired while counting by the clock counter is maintained, the receiving device (200) can output a second Vsync signal based on the first frame refresh rate information. For example, if the first frame refresh rate information is 120 Hz, the second Vsync signal can be output when the clock counting value becomes 1 / 120 s. Subsequently, the receiving device (200) can reset and initialize the clock counter when the second Vsync signal is output. If the second frame refresh rate information included in the second compressed video packet is acquired while counting by the clock counter is maintained, the receiving device (200) can output a third Vsync signal based on the second frame refresh rate information. For example, if the third frame refresh rate information is 120 Hz, the third Vsync signal can be output when the clock counting value becomes 1 / 120 s. Subsequently, the receiving device (200) can reset and initialize the clock counter when the third Vsync signal is output. If the third frame refresh rate information included in the third compressed video packet is acquired while counting by the clock counter is maintained, the receiving device (200) can output the fourth Vsync signal based on the second frame refresh rate information. For example, if the third frame refresh rate information is 60 Hz, the fourth Vsync signal can be output when the clock counting value becomes 1 / 60 s.

[0152] Next, the receiving device (200) can output a restored compressed image based on the output Vsync signal (S1150). For example, the receiving device (200) can output a decoded image stream in synchronization with the output Vsync signal.

[0153] Meanwhile, in Fig. 11, the order is mapped for all steps for convenience of explanation, but it is of course not necessarily limited to the order of steps that are not related to the order or can be performed in parallel.

[0154] FIG. 12 is a drawing for detailing a Vsync restoration method according to one or more embodiments.

[0155] According to FIG. 12, when a compressed video stream is received from a transmitting device (100), the receiving device (200) can generate an initial Vsync signal based on the reception time (S1210). For example, the receiving device (200) can generate an initial Vsync signal within a threshold time from the time when the compressed video stream is received. For example, when a specific content is selected according to a user command and a compressed video stream corresponding to the selected content is received, the receiving device (200) can generate an initial Vsync signal within a threshold time from the reception time.

[0156] Next, the receiving device (200) can operate an internal counter and increase a clock counter value (A) (S1220). For example, the receiving device (200) can start counting by operating the clock counter at the time when the first Vsync signal is generated and output. In addition, the receiving device (200) can reset and initialize the clock counter every time the next Vsync signal is output, thereby restarting counting.

[0157] Next, when the tail area or header area of ​​the compressed video stream is received (S1230:Y), the receiving device (200) can calculate and store a clock counter value (B) corresponding to the output time of the next Vsync signal based on the frame scan rate information included in the received tail area or header area (S1240). For example, when the tail area or header area of ​​each compressed video packet included in the compressed video stream is received, the receiving device (200) can calculate and store a clock counter value (B) corresponding to the output time of the next Vsync signal based on the frame scan rate information included in the received tail area or header area.

[0158] Next, the receiving device (200) can generate and output the next Vsync signal (S1260) if the clock counter value (A) counted by the internal counter and the clock counter value (B) calculated based on the frame scan rate information are the same (S1250:Y). For example, the receiving device (200) can compare the recounted clock counter value (A) and the clock counter value (B) calculated based on the newly received compressed video packet each time the Vsync signal is output, and if they are the same, generate and output the next Vsync signal.

[0159] Meanwhile, in Fig. 12, the order is mapped for all steps for convenience of explanation, but it is of course not necessarily limited to the order of steps that are not related to the order or can be performed in parallel.

[0160] FIG. 13A is a diagram illustrating a method for restoring a Vsync signal based on information inserted into a tail area of ​​a stream according to one or more embodiments.

[0161] In FIG. 13a, the upper area may correspond to an operation of generating and transmitting a compressed video stream in a transmitting device (100), and the lower area may correspond to an operation of receiving and processing a compressed video stream in a receiving device (200).

[0162] According to FIG. 13A, when a compressed video stream is received, the receiving device (200) may output the first Vsync signal (time t1) and start counting by operating a clock counter at that time. Subsequently, the receiving device (200) may decode the compressed video packet corresponding to the first frame Frame (0) and start displaying the screen of the first frame Frame (0). Subsequently, when the tail area of ​​the compressed video packet corresponding to the first frame Frame (0) is received (time t2), the receiving device (200) may output the next Vsync signal based on the frame refresh rate information included in the tail area (time t3). For example, the tail area of ​​the compressed video packet corresponding to the first frame Frame (0) may include the frame refresh rate information corresponding to the first frame Frame (0). For example, if the frame refresh rate information included in the tail area is 120 Hz, the receiving device (200) can output a Vsync signal corresponding to the second frame Frame (1) when the counting value of the clock counter becomes 1 / 120 s. The receiving device (200) can output a Vsync signal corresponding to the third frame Frame (2), the fourth frame Frame (3), ... Frame (n) in the same manner. N can be a positive integer greater than 0.

[0163] FIG. 13b is a diagram illustrating a method for restoring a Vsync signal based on information inserted into a header area of ​​a stream according to one or more embodiments.

[0164] In FIG. 13b, the upper area may correspond to an operation of generating and transmitting a compressed video stream in a transmitting device (100), and the lower area may correspond to an operation of receiving and processing multiple compressed streams in a receiving device (200).

[0165] According to FIG. 13A, when a compressed video stream is received, the receiving device (200) may output the first Vsync signal (time t1) and start counting by operating a clock counter at that time. Subsequently, the receiving device (200) may decode the compressed video packet corresponding to the first frame Frame (0) and start displaying the screen of the first frame Frame (0). Subsequently, when the header area of ​​the compressed video packet corresponding to the second frame Frame (1) is received (time t2), the receiving device (200) may output the next Vsync signal based on the frame refresh rate information included in the corresponding header area (time t3). For example, the header area of ​​the compressed video packet corresponding to the second frame Frame (1) may include frame refresh rate information corresponding to the first frame Frame (0). For example, if the frame refresh rate information included in the header area is 120 Hz, the receiving device (200) can output a Vsync signal corresponding to the second frame Frame (1) when the counting value of the clock counter becomes 1 / 120 s. The receiving device (200) can output a Vsync signal corresponding to the third frame Frame (2), the fourth frame Frame (3), ... Frame (n) in the same manner.

[0166] As described above, according to various embodiments, when a receiver receives a VRR video signal by communicating with a transmitter via a wireless network, the frame generation rate of the transmitter and the output rate of the receiver can be synchronized with low latency even when a Vsync signal is not received due to wireless network communication. Accordingly, VRR video signals can be transmitted and received in real time via a wireless network with low latency, thereby improving user convenience.

[0167] Meanwhile, the methods according to the various embodiments of the present disclosure described above can be implemented only with a software upgrade or a hardware upgrade for an existing electronic device.

[0168] Additionally, the various embodiments of the present disclosure described above can also be performed through an embedded server provided in an electronic device, or an external server of the electronic device.

[0169] Meanwhile, according to a temporary example of the present disclosure, the various embodiments described above can be implemented as software including instructions stored in a machine-readable storage medium that can be read by a machine (e.g., a computer). The device is a device that can call instructions stored from the storage medium and operate according to the called instructions, and may include an electronic device (e.g., electronic device (A)) according to the disclosed embodiments. When an instruction is executed by a processor, the processor can perform a function corresponding to the instruction directly or by using other components under the control of the processor. The instruction may include code generated or executed by a compiler or interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' means that the storage medium does not contain a signal and is tangible, but does not distinguish between data being stored semi-permanently or temporarily in the storage medium.

[0170] Furthermore, according to one embodiment of the present disclosure, the method according to the various embodiments described above may be provided as included in a computer program product. The computer program product may be traded as a product between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read-only memory (CD-ROM)) or online through an application store (e.g., Play Store™). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily generated in a storage medium, such as the memory of a manufacturer's server, an application store's server, or a relay server.

[0171] In addition, each of the components (e.g., modules or programs) according to the various embodiments described above may be composed of a single or multiple entities, and some of the corresponding sub-components described above may be omitted, or other sub-components may be further included in various embodiments. Alternatively or additionally, some components (e.g., modules or programs) may be integrated into a single entity, which may perform the same or similar functions as those performed by each of the corresponding components prior to integration. Operations performed by modules, programs or other components according to various embodiments may be executed sequentially, in parallel, iteratively or heuristically, or at least some operations may be executed in a different order, omitted, or other operations may be added.

[0172] While the present disclosure has been specifically illustrated and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the following claims.

Claims

1. In electronic devices, A communication interface connected to enable communication with a wireless network; A memory storing one or more instructions; and comprising one or more processors connected to the communication interface and the memory so as to be communicatively connected to control the electronic device; The one or more processors, by executing the one or more instructions, Identifies the frame refresh rate of the VRR (Variable Refresh Rate) video signal, Inserting information about the identified frame injection rate into at least one of a tail area or a header area of ​​a video stream to obtain a compressed video stream corresponding to the VRR video signal, An electronic device that transmits the compressed video stream obtained above to an external device via the wireless network.

2. In paragraph 1, The one or more processors, by executing the one or more instructions, Inserting frame rate information of the first video frame into at least one of a first tail area of ​​a first compressed video packet of the compressed video stream corresponding to the first video frame or a first header area of ​​a second compressed video packet of the compressed video stream corresponding to the second video frame, An electronic device wherein the second image frame is a frame following the first image frame in the VRR image signal.

3. In paragraph 2, The one or more processors, by executing the one or more instructions, A clock counter is operated based on the sync signal of the first video frame included in the above VRR video signal, An electronic device that identifies a frame rate of the first image frame based on a counting value of the clock counter.

4. In paragraph 1, The one or more processors, by executing the one or more instructions, Receives the VRR video signal from an external source device via wired communication, The above VRR video signal is an electronic device including a Vsync (vertical synchronization) signal, 5. In electronic devices, A communication interface connected to enable communication with a wireless network; A memory storing one or more instructions; and comprising one or more processors connected to the communication interface and the memory so as to be communicatively connected to control the electronic device; The one or more processors, by executing the one or more instructions, A compressed video stream corresponding to a VRR (variable refresh rate) video signal is received through the above communication interface, Obtaining frame injection rate information included in at least one of a tail area or a header area of ​​the compressed video stream, An electronic device that generates a first sync signal corresponding to a first image frame based on information about the acquired frame injection rate.

6. In paragraph 5, The one or more processors, by executing the one or more instructions, When the above compressed video stream is received, the first sync signal is generated and the clock counter is operated. When frame injection rate information of a first image frame included in a tail area of ​​the compressed image stream is acquired, a second sync signal corresponding to a second image frame is generated based on the counting value of the clock counter and the frame injection rate information of the first image frame. An electronic device wherein the second image frame is a frame following the first image frame.

7. In paragraph 5, The one or more processors, by executing the one or more instructions, When the above compressed video stream is received, the first sync signal is generated and the clock counter is operated. An electronic device that generates a second sync signal corresponding to the first image frame based on frame injection rate information of the first image frame obtained from a header area of ​​the compressed image stream and a counting value of the clock counter.

8. In paragraph 5, The one or more processors, by executing the one or more instructions, Obtaining frame injection rate information included in the tail area of ​​a plurality of compressed video packets included in the compressed video stream, Each tail area of ​​the above multiple compressed video packets is, An electronic device including frame rate information of a video frame corresponding to the plurality of compressed video packets.

9. In paragraph 5, The one or more processors, by executing the one or more instructions, Obtaining frame injection rate information included in the header area of ​​a plurality of compressed video packets included in the compressed video stream, Each header area of ​​the above multiple compressed video packets is: An electronic device, comprising frame injection rate information of a previous video frame of a video frame corresponding to the plurality of compressed video packets.

10. In paragraph 5, display; including more; The one or more processors, by executing the one or more instructions, An electronic device that controls the display to output the first image frame based on a video signal restored from the compressed video stream and the first sync signal corresponding to the first image frame.

11. In a method for controlling an electronic device, A step for identifying the frame refresh rate of a VRR (Variable Refresh Rate) video signal; A step of obtaining a compressed video stream corresponding to the VRR video signal by inserting information about the identified frame injection rate into at least one of a tail area or a header area of ​​the video stream; and A control method comprising the step of transmitting the compressed video stream to an external device via a wireless network.

12. In paragraph 11, The step of obtaining the above compressed video stream is: Inserting frame rate information of the first video frame into at least one of the tail area of ​​the first compressed video packet corresponding to the first video frame or the header area of ​​the second compressed video packet corresponding to the second video frame, A control method wherein the compressed video packet is a frame following the first video frame.

13. In paragraph 12, The step of obtaining the above compressed video stream is: A step of operating a clock counter based on a sync signal of a first image frame included in the above VRR image signal; and A control method, comprising: a step of identifying a frame injection rate of the first image frame based on a counting value of the clock counter.

14. In a method for controlling an electronic device, A step of receiving a compressed video stream corresponding to a VRR video signal via a wireless network; A step of obtaining frame injection rate information included in at least one of a tail area or a header area of ​​the compressed video stream; and A control method comprising: a step of generating a first sync signal corresponding to the first image frame based on information about the acquired frame injection rate.

15. In paragraph 14, The step of obtaining the above frame injection rate information is: A step of generating an initial sync signal and operating a clock counter when the above compressed video stream is received; and A step of obtaining frame injection rate information of a first image frame included in a tail area of ​​the compressed image stream; The step of generating the first sync signal is: A step of generating a second sync signal corresponding to a second image frame based on the counting value of the clock counter and the frame injection rate information of the first image frame is further included; A control method, wherein the second image frame is a frame following the first image frame.

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